Migrating from i.MX RT1060 to i.MX RT1170

Package

The i.MX RT1170 utilizes a 289-pin MAPBGA package due to its increased functionality, while the i.MX RT1060 uses a 196-pin MAPBGA package.

Pin Multiplexing

Refer to Table 3 for information on new pin multiplexing options on the i.MX RT1170.

Power Supply Changes

There are several changes in power supply between the i.MX RT1170 and RT1060. For detailed information, please refer to the Hardware Development Guide for the MIMXRT1170 Processor (Document MIMXRT1170HDUG) and the MIMXRT1170 EVK Board Hardware User's Guide (Document MIMXRT1170EVKHUG).

• The i.MX RT1170 has more power domains than the RT1060, notably the new NVCC_LPSR domain. This requires VDD_LPSR_DIG to be stable for 1 ms before powering up VDD_SOC_IN during the power-up sequence.
• The i.MX RT1170 uses the VDD_SNVS_DIG (1.8 V) domain's POR pin reset. If external pull-ups or external POR logic are added, the voltage level must be correct.
• The i.MX RT1170 has two internal DCDC outputs: one 1.0 V and one 1.8 V. The i.MX RT1060 has only one output.
• For automotive-grade i.MX RT1170 products, due to limited internal DCDC load capacity, an external PMIC is required for high-power operation. For the i.MX RT1060, internal DCDC can be used directly for various applications.

Clocking

Overview

The i.MX RT1170 features a completely redesigned clocking architecture, comprising three parts:

• Clock sources: Crystal/OSC/PLL/PLL_PFD
• Independent clock sources and divider settings for each root clock.
• Clock gating for enabling/disabling clocks.

For other important related information, such as the System Clocks Table (mapping IP clocks to system clock sources), Clock Tree (paths from clock sources to root clocks), Clock Sources List, Clock Roots List (available sources for each root clock), Clock Gate Table, and Clock Group (synchronous clocks), refer to the i.MX RT1170 Processor Reference Manual (Document IMXRT1170RM).

Crystal and PLL

Power Mode Management

Compared to the i.MX RT1060, the i.MX RT1170 adopts a new power management architecture. For more detailed information, please refer to the power mode management chapters in the i.MX RT1170 Processor Reference Manual (Document IMXRT1170RM) and the document RT1170 Clock and Low Power Features (Document AN13104).

DMA

Memory Map

This section highlights key memory map differences. For comprehensive details, consult the i.MX RT1170 Processor Reference Manual (Document IMXRT1170RM).

ECC

Refer to Table 7 for ECC feature comparison.

Image Processing and Display Interfaces

Graphics Accelerator (GPU2D)

The Graphics Accelerator (GPU2D) provides high-performance, low-power, and high-quality graphics acceleration. It supports raster and vector graphics processing common in embedded graphics scenarios. The SDK offers hardware and OS-independent APIs for GPU utilization.

• OpenVG 1.1 API Standard Vector Graphics Acceleration Interface: A royalty-free, cross-platform API maintained by the Khronos Group, providing hardware acceleration for vector graphics libraries like Flash and SVG, and enhancing human-machine interfaces and text rendering.
• VGLite Graphics API: Optimized for overall system resource usage, VGLite aims for maximum performance with minimal memory footprint. It supports a subset of Khronos OpenVG CTS features, including Porter-Duff compositing, gradient control, fast clear, arbitrary rotation, path fill rules, path rendering, and pattern path filling. The VGLite API categories include Initialization, Pixel Buffer Management, Matrix Control, Blit operations, Vector Path Control, and Drawing operations. SDK documentation provides detailed explanations.

LCDIFv2

LCDIFv2 is a new graphics processing and display IP on the i.MX RT1170 with the following features:

• Supports up to 8 layers of alpha blending.
• One Background (BG) layer for static background images.
• One Video Foreground (FG) layer.
• Six User Interface (UI) layers for icons, text, cursors, etc. UI layers are suitable for small images stored in OCRAM.
• Each layer supports color indexing (1/2/4/8 bpp) with independent Color Look-Up Tables (CLUTs) for conversion to 32-bit ARGB pixels.
• Each layer supports programmable screen pixel dimensions (width/height/stride), X/Y offsets, background color, embedded and global alpha blending, and color indexing (1/2/4/8 bpp).
• Encoding format support includes RGB565/ARGB1555/ARGB4444, RGB888/ARGB8888/ABGR8888, and YCbCr422 (supporting up to two layers of YCbCr interleaving).
• Supports parallel camera interface input and the following CSI-2 data formats: YUV422/RGB888/RGB666/RGB565/RGB555/RGB444.

Audio Peripherals

Asynchronous Sample Rate Converter (ASRC)

The Asynchronous Sample Rate Converter (ASRC) is a new IP on the i.MX RT1170 that converts the sampling rate of signals related to an input clock to signals related to a different output clock. ASRC supports up to 10 channels of parallel sample rate conversion with approximately -120dB THD+N and up to 3 pairs of sample rate processing. Input audio data can come from different sources with different sampling rates, and the output audio data can have different sampling rates, associated with the output clock, which is asynchronous to the input clock.

PDM MIC Interface

Compared to the i.MX RT1060, the i.MX RT1170 adds support for a 4-wire, 8-channel PDM D-MIC audio input. Key features include:

• Decimation Filter: Fixed filtering characteristics for audio applications, 24-bit signed filter output, dynamic range <140dB (0dBFS) for a 1 KHz tone. Features an internal clock divider for programmable PDM clock generation, independent enable control for all or partial channels, programmable decimation rate, programmable de-DC functionality, range adjustment, and FIFO with interrupt and DMA capabilities, storing 8 samples per FIFO.
• Hardware Voice Activity Detection (HWVAD): Supports interrupts and zero-crossing detection.

Low-Speed Peripherals

FlexIO

EMVSIM

The EMVSIM module is a new IP on the i.MX RT1170 compared to the i.MX RT1060. Key features include:

• Independent transmit/receive clock + independent register read/write interface clock.
• Bidirectional 16-byte FIFO for transmit and receive.
• Automatic NACK generation on parity error and receive FIFO overflow.
• Forward and reverse conventions.
• Retransmission based on smart card NACK requests, with programmable retransmission thresholds.
• Automatic detection of initial characters and data format settings for forward and reverse reception.
• NACK reception detection.
• Two general-purpose counters for software applications, with programmable counter clocks.
• FIFO supports DMA transfers, operating in interrupt or DMA mode.
• Programmable prescaler for card clock generation and baud rate divider for arbitrary F/D ratio transmission/reception ETU clock.
• Deep sleep and wake-up via smart card status detection interrupt.
• Automatic power-down of smart card detection port logic.
• Support for generating 8-bit LRC and 16-bit CRC for transmitted data, and checking checksums for received data.

Watchdog Timers

Refer to Table 9 for watchdog timer comparison.

Analog Peripherals

The RT1170 does not have a TSC (Touch Screen Controller). The RT1170's ADC peripheral is a newly designed LPADC, structurally different from the i.MX RT1060. Refer to the i.MX RT1170 Processor Reference Manual (Document IMXRT1170RM) for details. Table 10 compares its features with the i.MX RT1060.

Boot Process

Table 11 outlines the system boot differences between the i.MX RT1060 and i.MX RT1170.

Security

Table 12 details the main security differences between the i.MX RT1060 and i.MX RT1170.

For tamper-related applications, refer to How to use Tamper Function (Document AN13078).

Software Porting Considerations

The i.MX RT1170 software ecosystem is based on MCUXpresso SDK/IDE/Tools, similar to the i.MX RT1060. Refer to Table 13 for comparison.

For new features in the i.MX RT1170, such as clocking, power management modes, and new IPs, significant differences from the i.MX RT1060 may require code porting or even redesign for specific software modules. For IPs that are similar or identical between the i.MX RT1170 and i.MX RT1060, most code can be reused, but consider potential impacts from different SDK versions.

Reference Materials

• i.MX RT1170 Processor Reference Manual (Document IMXRT1170RM)
• i.MX RT1170 Crossover Processors Data Sheet for Consumer Products (Document IMXRT1170CEC)

Revision History

How To Reach Us

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Date of release: February 18, 2021

Document identifier: AN13106