Samsung LTM190EP01 TFT-LCD Module Product Information

General Description

Description

The LTM190EP01 is a color active matrix liquid crystal display (LCD) utilizing amorphous silicon TFT (Thin Film Transistor) as switching components. This 19.0-inch model features a resolution of 1280 x 1024 pixels and can display up to 16.7 million colors. It comprises a TFT LCD panel, a driver circuit, and a back light unit.

Features

• High contrast ratio and high aperture structure
• PVA (Plus Viewing Angle) mode for wide viewing angles
• High speed response (DCC Technology)
• SXGA (1280 x 1024 pixels) resolution
• Low power consumption
• Two dual CCFTs (Cold Cathode Fluorescent Tube)
• DE (Data Enable) only mode
• LVDS (Low Voltage Differential Signaling) interface (2pixel/clock)
• Compact Size Design
• RoHS and TCO'03 compliance

Applications

This module is suitable for workstation and desktop monitors, display terminals for AV application products, and monitors for industrial machines. For other applications, Samsung Electronics Co., LTD. should be contacted in advance.

General Information

Mechanical Information

Note (1): Mechanical tolerance is ± 0.5mm unless otherwise specified.

1. Absolute Maximum Ratings

Exceeding maximum ratings can cause malfunction or unrecoverable damage to the device.

Note (1): T_a = 25 ± 2 °C

Temperature and Relative Humidity Range:

• 90% RH Max. (T_a ≤ 39 °C)
• Maximum wet-bulb temperature at 39 °C or less. (T_a ≤ 39 °C)
• No condensation
• Shock: 11ms, sine wave, one time for ±X, ±Y, ±Z axis
• Vibration: 10-300 Hz, Sweep rate 10min, 30min for X,Y,Z axis

The operating range for temperature and relative humidity is defined by a polygon connecting points: (-25,5), (39,90), (50,50.4), (60,27.7). The storage range extends below this operating range.

2. Optical Characteristics

Measurements are conducted in a dark room using TOPCON RD-80S and SPECTRORADIOMETER SR-3, at T_a = 25 ± 2°C, V_DD=5V, f_v= 60Hz, f_DCLK=54MHz, I_L = 6.5mArms.

* C.G.L: Color Grayscale Linearity

Test Equipment Setup

Measurements should be executed in a stable, windless, and dark room, 30 minutes after back light stabilization at the given temperature. Measurements are taken at the center of the screen. Single lamp current: 6.5mA. Environment condition: T_a = 25 ± 2 °C.

The setup involves a photo detector (SR-3) positioned 40cm from the LCD Panel, and a Spectroradiometer (RD-80S) 50cm from the LCD Panel, both facing the center of the screen.

Definition of Test Point

The active area is divided into a 3x3 grid, with 9 test points. Point 5 is the center. Horizontal points are at 128, 640, 1152 pixels. Vertical points are at 102, 512, 922 pixels.

Definition of Contrast Ratio (C/R)

C/R is the ratio of maximum gray luminance (Gmax) to minimum gray luminance (Gmin) at the center point (point 5) of the panel. C/R = Gmax / Gmin. Gmax is luminance with all pixels white, Gmin is luminance with all pixels black.

Definition of 9 Points Brightness Uniformity

Brightness uniformity (B_uni) is calculated as: B_uni = 100 × (B_max - B_min) / B_max, where B_max is maximum brightness and B_min is minimum brightness.

Definition of Response Time

Gray to Gray Response Time involves measuring transitions between various gray levels (e.g., 31→63, 63→95, ..., 191→223 grays and vice versa). T_{G-G, avg} is the average response time between these grays.

Definition of Luminance of White

Luminance of white is measured at the center point (point 5).

Definition of Color Chromaticity

Color coordinates of Red, Green, Blue, and White are measured at the center point (point 5) according to CIE 1931 and CIE 1976 standards.

Definition of Viewing Angle

Viewing angle range is defined where the Contrast Ratio (CR) is greater than or equal to 10. The viewing angles (θ_L, θ_R, θ_U, θ_D) are measured from the center of the screen.

Color Grayscale Linearity

Test Image: 100% full white pattern with a test pattern consisting of squares (40mm x 40mm) filled with 255, 225, 195, 165, 135, and 105 gray steps, arranged at the center of the screen.

Test Method:

1. Move a 255 gray level square to the screen center and measure luminance and u' and v' coordinates.
2. Move a 225 gray square to the center and measure both luminance and coordinates, and so on for other gray levels.

Test Evaluation: Calculate Δu'v' = √((u'_A - u'_B)² + (v'_A - v'_B)²), where A and B are two gray levels with the largest color differences. The largest Δu' and Δv' from each of 6 pairs of u' and v' are used.

3. Electrical Characteristics

3.1 TFT LCD Module

The display data and timing signal connector must be connected. All measurements are at T_a = 25°C.

Note (1): Ripple voltage should be controlled under 10% of V_DD.

Differential Receiver Voltage Definitions:

The test circuit for differential receiver voltage definitions, propagation delay, and transition time uses input pulses with a frequency of 10MHz and rise/fall times of 1ns. Capacitance includes probe and fixture capacitance. The diagram shows R_IN+ and R_IN- inputs, V_ID (V_IA - V_IB), V_IC ((V_IA + V_IB)/2), and R_OUT.

LVDS Receiver DC parameters are measured under static and steady conditions.

LVDS Timing Diagram:

The LVDS Clock (RxCLKO/E) shows a period T, with V_DIFF=0V. LVDS Data (Rx +/-) also shows V_DIFF=0V. t_SKEW is the skew between LVDS clock and data. T is one period of LVDS clock. A skew of (-/+) 380psec means LVDS data goes before or after LVDS clock.

Definition of V_ID and V_CM using single-end signals:

Various voltage levels and ranges are illustrated for V_CM and |V_IDI| for typical application and different V_CM ranges.

Power Dissipation Check Patterns:

Measurements are taken at f_V=75Hz, f_DCLK = 54MHz, V_DD = 5.0V, DC Current. Patterns include a solid black screen, a solid white screen, and a dot pattern (a grid of alternating colored pixels).

Rush Current Measurement Condition:

The V_DD voltage rises from 10% to 100% over a time T_RUSH. Rush Current I_RUSH can be measured when T_RUSH is 470µs.

3.2 Back Light Unit

The back light unit is an edge-lighting type with two dual Cold Cathode Fluorescent Tubes (CCFTs). Characteristics are measured at T_a=25 ± 2°C.

Note (1): Specified values are for a single lamp.

Lamp current is measured with a current meter for high frequency. The back light unit block diagram shows an LCD Module connected to an INVERTER (SK1700A) with four lamp connections (HOT(PINK), COLD(WHITE), HOT(BLUE), COLD(BLACK)).

Lamp Frequency Interference: Lamp frequency that may interfere with horizontal synchronous frequency can cause line flow on the display. Lamp frequency should be detached from horizontal synchronous frequency and its harmonics to avoid interference.

Life Time: Defined as the time when lamp unit brightness becomes 50% or less of its original value at T_a = 25±2°C and I_L = 6.5mArms.

Inverter Design: A system inverter designed for better display performance, power efficiency, and lamp reliability helps increase lamp lifetime and reduce leakage current. Measurements should be done at typical lamp current. Asymmetry rate of the inverter waveform should be less than 10%. Distortion rate should be √2 with ±10% tolerance, ideally similar to a sine wave.

Inverter Shutdown Function: If an inverter has a shutdown function, it should maintain output for over 1 second even if the lamp connector is open, otherwise lamps may not turn on.

4. Block Diagram

4.1 TFT LCD Module

The TFT LCD Module block diagram illustrates the signal flow. LVDS pairs (#1 and #2) connect to the LVDS(Rx) and LVDS(Tx) inputs. RSDS(Tx) and RSDS signals are processed by a Timing Controller, which also receives +5.0V V_DD from a Power Circuit. The Timing Controller sends control signals (S1, S1280) to Source Driver ICs, which then drive the TFT-LCD (1280 x RGB x 1024 pixels).

4.2 Back Light Unit

The Back Light Unit (YEONHO 35001HS-02L or equivalent) consists of four CCFL lamps. Each lamp has two connections: HOT (Pink/Blue) and COLD (White/Black). These are typically connected to an inverter.

5. Input Terminal Pin Assignment

5.1 Input Signal & Power

The connector is UJU IS100-L300-C23 or equivalent. Pin numbers start from the right side of the PCB (Pin No. 30 to Pin No. 1).

* If the system already uses pins 25 and 26, they should be kept under GND level. The voltage applied to these pins should not exceed -200mV.

All GND pins should be connected together and to the LCD's metal chassis. All power input pins should be connected together. All NC pins should be separated from other signal or power lines.

5.2 LVDS Interface

Detailed pin assignments for Odd and Even Pixel Data for both 1st and 2nd pixel data, using DS90C383, DS90C385, and DS90C387 LVDS Transmitters, are provided in tables. These tables map device input pins (TXIN symbols) to their functions (Red, Green, Blue Odd/Even Pixel Data, LSB/MSB) and corresponding output signals (TXOUT) to LTM190EP interface terminals (CN1) and symbols (RXO/RXE).

5.3.3 Timing Diagrams of LVDS For Transmitting LVDS Receiver: Integrated T-CON

The timing diagrams illustrate the relationship between the LVDS Clock (RxCLKO/E) and various LVDS data signals (RxINO/E3, RxINO/E2, RxINO/E1, RxINO/E0). The clock signal has a period T, with V_DIFF=0V. Data signals show transitions relative to the clock, indicating data enable (DE), VSYNC, and HSYNC. Detailed timing parameters like T_CH, T_CL, T_DS, T_DH, T_ES are shown relative to DCLK and DISPLAY DATA, with voltage levels at 0.5 V_CC.

5.4 Back Light Unit Pin Assignment

Connector: Yeonho 35001HS-02L or equivalent. Mating Connector: SM02B-BHSS-1-TB or equivalent.

5.5 Input Signals, Basic Display Colors and Gray Scale of Each Color

A comprehensive table details the 8-bit data signals (R0-R7, G0-G7, B0-B7) for various basic display colors (BLACK, BLUE, GREEN, CYAN, RED, MAGENTA, YELLOW, WHITE) and different gray scale levels for Red, Green, and Blue. Input Signal: 0 = Low level voltage, 1 = High level voltage. Rn, Gn, Bn represent Red, Green, Blue Gray at level 'n'.

6. Interface Timing

6.1 Timing Parameters (DE only mode)

This product operates in DE (Data Enable) only mode, meaning Hsync & Vsync signals do not affect normal operation. Test Point: TTL control signal and CLK at LVDS Tx input terminal in system. Internal Vcc = 3.3V.

6.2 Timing Diagrams of Interface Signal (DE only mode)

The diagrams illustrate the vertical (T_V, T_VD, T_VB) and horizontal (T_H, T_HD, T_C) timing relationships for the DE only mode. They show the DCLK signal and the display data transitions relative to the clock, including setup and hold times (T_DS, T_DH, T_ES).

6.3 Power ON/OFF Sequence

To prevent latch-up or DC operation of the LCD Module, a specific power on/off sequence must be followed. The sequence involves V_DD and Back-Light timing (T1-T6).

• T1: V_DD rising time from 10% to 90% (300µs ≤ T1 ≤ 10ms)
• T2: Time from V_DD to valid data at power ON (0 ≤ T2 ≤ 50ms)
• T3: Time from valid data off to V_DD off at power Off (0 ≤ T3 ≤ 50ms)
• T4: V_DD off time for Windows restart (1s ≤ T4)
• T5: Time from valid data to B/L enable at power ON (500ms ≤ T5)
• T6: Time from valid data off to B/L disable at power Off (100ms ≤ T6)

Precautions:

• The external system's supply voltage for the Module input should match V_DD definition.
• Apply lamp voltage within the LCD operation range. Abnormal screens may appear if backlight turns on/off before LCD operation.
• When V_DD is off, input signals should be kept low or at high impedance.
• T4 should be measured after the Module is fully discharged.
• Interface signal should not be kept at high impedance when power is on.

6.4 VDD Power Dip Condition

For stable operation, if V_DD(typ.) x 80% ≤ V_CC ≤ V_DD(typ) x 90%, then the dip duration (T_d) should be less than 20ms. This condition applies to input voltage glitches.

7. Outline Dimension

The document includes a detailed technical drawing of the LTM190EP01 module, showing its overall dimensions (e.g., 396±0.5mm horizontal, 324±0.5mm vertical), active display area (376.32mm x 301.056mm), and bezel open dimensions. It also indicates user hole locations (e.g., 4-M3 User Holes) and their positions. Key notes on the drawing specify: 1. Backlight: 4 Cold Cathode Fluorescent Lamps. 2. I/F Connector Specification: FI-XB30SSL-HF15 or equivalent. 3. Lamp Connector/Wire Specification: 35001HS-02L or equivalent (2 PIN x 170mm). 4. User Mounting Torque Spec: Max 6 Kgf-cm. The total weight is approximately 2250g.

8. General Precautions

8.1 Handling

• Assemble the module firmly using all mounting holes; avoid twisting or bending.
• Disconnect the inverter from the power source before assembly or disassembly due to high voltages.
• Avoid strong mechanical shock or force to prevent damage to the module and CCFT backlight.
• Polarizer films are fragile; do not press or scratch the surface harder than a HB pencil lead.
• Immediately wipe off water droplets or oil to prevent staining or discoloration.
• Clean polarizer surface with absorbent cotton or soft cloth. Desirable cleaners include water, IPA (Isopropyl Alcohol), or Hexane. Avoid Ketone type materials (e.g., Acetone), Ethyl alcohol, Toluene, Ethyl acid, or Methyl chloride, as they may cause permanent damage.
• If liquid crystal material leaks, keep it away from eyes or mouth. In case of contact, wash thoroughly with soap.
• Protect the module from static discharge to prevent damage to CMOS Gate Array ICs.
• Use finger-stalls with soft gloves during inspection and assembly to keep the display clean.
• Do not disassemble the module.
• Do not pull or fold the lamp wire.
• Do not adjust the variable resistor on the module.
• Slowly peel off the polarizer protection film just before use to minimize electrostatic charge.
• Do not touch I/F connector pins directly with bare hands.

8.2 Storage

• Do not store the module in high temperature or high humidity for extended periods. Recommended storage conditions are 0 to 35 °C and less than 70% relative humidity.
• Do not store the TFT-LCD Module in direct sunlight or fluorescent light; store in a dark place.

8.3 Operation

• Do not connect or disconnect the module while it is powered on.
• Power supply should always be turned on/off according to the specified
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