Samsung LTM190EP01 TFT-LCD Product Information

General Description

Description

The LTM190EP01 is a color active matrix liquid crystal display (LCD) utilizing amorphous silicon TFT (Thin Film Transistor) as switching components. This 19.0-inch model consists of a TFT LCD panel, a driver circuit, and a back light unit, offering a resolution of 1280 x 1024 pixels and capable of displaying up to 16.7 million colors.

Features

• High contrast ratio, high aperture structure
• PVA (Plus Viewing Angle) mode
• Wide Viewing Angle
• High speed response (DCC Technology)
• SXGA (1280 x 1024 pixels) resolution
• Low power consumption
• 2 dual CCFTs (Cold Cathode Fluorescent Tube)
• DE (Data Enable) only mode
• LVDS (Low Voltage Differential Signaling) interface (2pixel/clock)
• Compact Size Design
• RoHS, TCO'03 compliance

Applications

• Workstation & desktop monitors
• Display terminals for AV application products
• Monitors for industrial machine

* If the module is used for applications other than those listed above, contact Samsung Electronics Co., LTD. (SEC) in advance.

General Information

Mechanical Information

Note (1) Mechanical tolerance is ± 0.5mm unless otherwise specified.

1. Absolute Maximum Ratings

Exceeding maximum ratings can cause malfunction or unrecoverable damage to the device.

Note (1) Ta= 25 ± 2 °C

Temperature and Relative Humidity Range:

1. Temperature and relative humidity range are defined as follows:
   • 90% RH Max. (Ta ≤ 39 °C)
   • Maximum wet-bulb temperature at 39 °C or less. (Ta ≤ 39 °C)
   • No condensation

   The operating range for relative humidity and temperature is depicted graphically, showing a region where humidity decreases with increasing temperature, from approximately (39°C, 90%RH) to (50°C, 50.4%RH) and (60°C, 27.7%RH). The storage range extends from (-25°C, 5%RH) to (60°C, 5%RH).

2. 11ms, sine wave, one time for ±X, ±Y, ±Z axis.
3. 10-300 Hz, Sweep rate 10min, 30min for X,Y,Z axis.

2. Optical Characteristics

Optical characteristics are measured in a dark room or equivalent using TOPCON RD-80S and SPECTRORADIOMETER SR-3 equipment. Test conditions: Ta = 25 ± 2°C, VDD=5V, fv= 60Hz, fDCLK=54MHz, IL = 6.5mArms.

* C.G.L: Color Grayscale Linearity (continued on next page)

Note (1) Test Equipment Setup: Measurement should be executed in a stable, windless, and dark room 30 minutes after lighting the backlight for stabilization. Measurement is taken at the center of the screen. Single lamp current: 6.5mA. Environment condition: Ta = 25 ± 2 °C. The setup involves a photo detector (SR-3) positioned 40cm from the LCD panel, and a spectroradiometer (RD-80S) 50cm from the panel, both focused on the center of the screen.

Note (2) Definition of Test Point: The active area is divided into a 3x3 grid of test points. Point 1 is at (1152, 922), Point 2 at (640, 922), Point 3 at (128, 922), Point 4 at (1152, 512), Point 5 at (640, 512), Point 6 at (128, 512), Point 7 at (1152, 102), Point 8 at (640, 102), and Point 9 at (128, 102). Point 5 is the center test point.

Note (3) Definition of Contrast Ratio (C/R): Ratio of gray max (Gmax) & gray min (Gmin) at the center point (Point 5) of the panel. CR = Gmax / Gmin, where Gmax is luminance with all pixels white, and Gmin is luminance with all pixels black.

Note (4) Definition of 9 points brightness uniformity: Buni = 100 × (Bmax - Bmin) / Bmax, where Bmax is maximum brightness and Bmin is minimum brightness.

Note (5) Definition of Response time: Gray to Gray Response Time involves measuring transitions between various gray levels (e.g., 31→63, 63→95, 95→127, 127→159, 159→191, 191→223 grays and vice versa). T_{G-G, avg} is the average response time between these grays. The response time graph shows the luminance percentage (100%, 90%, 10%, 0%) over time for transitions between different gray levels (e.g., 95 gray to 127 gray, 96 gray to 128 gray).

Note (6) Definition of Luminance of White: Luminance of white is measured at the center point (Point 5).

Note (7) Definition of Color Chromaticity (CIE 1931, CIE1976): Color coordinates of Red, Green, Blue & White are measured at the center point (Point 5).

Note (8) Definition of Viewing Angle: Viewing angle range is defined where Contrast Ratio (CR) ≥ 10. The viewing angle diagram illustrates the horizontal (θ_L, θ_R) and vertical (θ_U, θ_D) viewing angles relative to the display surface.

Note (9) Color Grayscale Linearity: Test image is a 100% full white pattern with a test pattern of squares. Test pattern consists of 40mm x 40mm squares filled with 255, 225, 195, 165, 135, and 105 gray steps, arranged at the center of the screen. Test method involves moving a 255 gray level square to the center to measure luminance and u' and v' coordinates, then repeating for a 225 gray square. Test evaluation calculates Δu'v' = √((u'_A - u'_B)² + (v'_A - v'_B)²), where A and B are two gray levels with the largest color differences among 6 pairs of u' and v'.

3. Electrical Characteristics

3.1 TFT LCD Module

The connector for display data & timing signal should be connected. (Ta = 25°C)

Note (1) The ripple voltage should be controlled under 10% of V_DD.

Note (2) Differential receiver voltage definitions and propagation delay and transition time test circuit: All input pulses have frequency = 10MHz, t_r or t_e=1ns. C_L includes all probe and fixture capacitance. The circuit shows differential inputs (R_IN+, R_IN-) with input voltages V_IA and V_IB, and a common mode voltage V_IC = (V_IA - V_IB)/2. The output is R_OUT.

Note (3) LVDS Receiver DC parameters are measured under static and steady conditions, which may not reflect performance in the end application. The LVDS Clock (V_DIFF=0V) and LVDS Data (RX +/-) signals are shown with a period T and skew t_SKEW. t_SKEW is the skew between LVDS clock & LVDS data. T is one period time of LVDS clock. (-/+) of 380psec means LVDS data goes before or after LVDS clock.

Note (4) Definition of V_ID and V_CM using single-end signals: Waveforms illustrate V_CM and |V_IDI| for typical application (V_CM=1.25V, |V_IDI|=350mV), V_CM range with minimum |V_IDI| (V_CM=100mV to 2.3V, |V_IDI|=200mV), and V_CM range with minimum |V_IDI| (V_CM=300mV to 2.1V, |V_IDI|=600mV).

Note (5) f_V=75Hz, f_DCLK = 54MHz, V_DD = 5.0V, DC Current.

Note (6) Power dissipation check pattern (LCD Module only): Illustrated patterns include a solid black pattern, a solid white pattern, and a dot pattern (a grid of alternating black and white pixels, with a magnified view showing RGB subpixels).

Note (7) Measurement Condition: The Rush Current I_RUSH can be measured when T_RUSH is 470µs. The V_DD waveform shows a rise from 10% to 90% over T_RUSH=470µs.

3.2 Back Light Unit

The back light unit is an edge-lighting type with 2 dual Cold Cathode Fluorescent Tubes (CCFTs). Characteristics of the two dual lamps are shown below. (Ta=25 ± 2°C)

Note (1) Specified values are for a single lamp. Lamp current is measured with a current meter for high frequency. The block diagram of the back light unit shows the LCD Module connected to an INVERTER (SK1700A). The inverter has four outputs for the CCFTs: HOT(PINK) and COLD(WHITE) for the first lamp, and HOT(BLUE) and COLD(BLACK) for the second lamp. There are two sets of these connections, indicating two dual CCFTs.

Note (2) Lamp frequency that may produce interference with horizontal synchronous frequency can cause line flow on the display. Therefore, lamp frequency should be detached from the horizontal synchronous frequency and its harmonics as far as possible to avoid interference.

Note (3) Life time (Hr) is defined as the time when brightness of a lamp unit itself becomes 50% or less than its original value at Ta = 25±2°C and I_L = 6.5mArms.

Note (4) Designing a system inverter for better display performance, power efficiency, and lamp reliability helps increase lamp lifetime and reduce leakage current. The measurement should be done at typical lamp current. The asymmetry rate of the inverter waveform should be less than 10%. The distortion rate of the waveform should be √2 with ±10% tolerance. Inverter output waveform should be similar to an ideal sine wave. The waveform diagram illustrates the peak current (I_p), negative peak current (I_-p), and RMS current (I_rms), defining asymmetry rate as (|I_p - I_-p| / I_rms) × 100 and distortion rate as |I_p / I_rms| or |I_-p / I_rms|.

Note (5) If an inverter has a shutdown function, it should keep its output for over 1 second even if the lamp connector is open. Otherwise, the lamps may not turn on.

4. Block Diagram

4.1 TFT LCD Module

The block diagram for the TFT LCD Module shows the following components and connections: LVDS pair #1 and LVDS pair #2 connect to the CN1 (30pin) connector. From CN1, signals go to the Timing Controller. The Timing Controller outputs RSDS signals to the Source Driver ICs. The Source Driver ICs receive control signals (S1, S1280) and drive the TFT-LCD panel (1280 x RGB x 1024 pixels). A Power Circuit provides +5.0V (V_DD) to the Timing Controller.

4.2 Back Light Unit (YEONHO 35001HS-02L or equivalent)

The back light unit consists of four CCFL lamps. Each lamp has two terminals: HOT (e.g., PINK, BLUE) and COLD (e.g., WHITE, BLACK). The diagram shows four LAMP(CCFL) units, each with a HOT and COLD connection, indicating a total of four lamps. These lamps are connected to the inverter.

5. Input Terminal Pin Assignment

5.1 Input Signal & Power (Connector : UJU IS100-L300-C23 or equivalent)

* If the system already uses pins 25 and 26, they should be kept under GND level. The voltage applied to those pins should not exceed -200mV.

Connector Diagram: The PCB connector has 30 pins, with Pin No. 1 on the right side and Pin No. 30 on the left side, as viewed from the front. This corresponds to the UJU IS100-L300-C23 or equivalent connector.

1. All GND pins should be connected together and also connected to the LCD's metal chassis.
2. All power input pins should be connected together.
3. All NC pins should be separated from other signal or power.

5.2 LVDS Interface

5.2.1 Odd Pixel Data (1st pixel data) - 1st LVDS Transmitter (DS90C383, DS90C385) Signal Interface

5.2.2 Even Pixel Data (2nd pixel data) - 2nd LVDS Transmitter (DS90C383, DS90C385) Signal Interface

5.3 LVDS Interface(2)

5.3.1 Odd Pixel Data (1st pixel data) - LVDS Transmitter (DS90C387) Signal Interface

5.3.2 Even Pixel Data (2nd pixel data) - LVDS Transmitter (DS90C387) Signal Interface

5.3.3 Timing Diagrams of LVDS For Transmitting LVDS Receiver : Integrated T-CON

The timing diagrams illustrate the relationship between RxCLKO/E, RxINO/E3, RxINO/E2, RxINO/E1, and RxINO/E0 signals. RxCLKO/E shows a clock signal with period T, transitioning between V_DIFF=0V. The data signals (RxINO/E0 to RxINO/E3) show pixel data (Red, Green, Blue) and control signals (DE, VSYNC, HSYNC) transmitted across previous, current (1 cycle), and next cycles. A detailed view of the clock (D_CLK) and display data (DISPLAY DATA) shows timing parameters like T_CH, T_CL, T_DS, T_DH, and T_ES, all relative to 0.5 V_CC levels.

5.4 Back Light Unit Pin Assignment

5.5 Input Signals, Basic Display Colors and Gray Scale of Each Color

This table defines the 8-bit data signals for various basic display colors and gray scales for Red, Green, and Blue channels. Each color channel (Red, Green, Blue) uses 8 bits (R0-R7, G0-G7, B0-B7) to represent intensity. '0' indicates a low level voltage, and '1' indicates a high level voltage.

Note (1) Definition of Gray: R_n: Red Gray, G_n: Green Gray, B_n: Blue Gray (n = Gray level). Input Signal: 0 = Low level voltage, 1 = High level voltage.

6. Interface Timing

6.1 Timing Parameters (DE only mode)

Note (1) This product is DE only mode. The input of Hsync & Vsync signal does not affect normal operation.

Note (2) Test Point: TTL control signal and CLK at LVDS Tx input terminal in system.

Note (3) Internal Vcc = 3.3V.

6.2 Timing Diagrams of interface Signal (DE only mode)

The timing diagrams illustrate the relationships between various signals in DE only mode. The vertical timing (T_V) shows the active display period (T_VD) and the vertical blanking period (T_VB). The horizontal timing (T_H) shows the active display period (T_HD) and the horizontal blanking period. A detailed view of the D_CLK signal shows its period T_C, and the high (T_CH) and low (T_CL) times. The DISPLAY DATA signal shows the data setup time (T_DS), data hold time (T_DH), and data enable setup time (T_ES) relative to the D_CLK transitions. All signal levels are referenced to 0.5 V_CC.

6.3 Power ON/OFF Sequence

To prevent latch-up or DC operation of the LCD Module, the power on/off sequence should follow the diagram below.

The power sequence diagram illustrates the timing relationships between Power Supply (V_DD), Signals, and Back-Light. V_DD rises from 0V to 0.9 V_DD, with T1 being the rising time (10% to 90%, 300µs ≤ T1 ≤ 10ms). Signals become valid after V_DD rises (0 ≤ T2 ≤ 50ms). Power Off sequence shows V_DD dropping, with T3 being the time from valid data off to V_DD off (0 ≤ T3 ≤ 50ms). T4 is the V_DD off time for Windows restart (1sec ≤ T4). The Back-Light (Recommended) turns on after valid data (500ms ≤ T5 ≤ 1sec) and turns off after valid data off (100ms ≤ T6 ≤ 1sec).

• The supply voltage of the external system for the Module input should be the same as the definition of V_DD.
• Apply the lamp voltage within the LCD operation range. If the backlight turns on before LCD operation or turns off before LCD operation, the display may momentarily show an abnormal screen.
• In case of V_DD = off level, keep input signals low or maintain high impedance.
• T4 should be measured after the Module has been fully discharged between power off and on periods.
• Interface signal should not be kept at high impedance when the power is on.

6.4 VDD Power Dip Condition

The V_DD power dip condition diagram shows V_DD dropping from 90% to 80% of its typical value, then recovering. The duration of this dip is T_d. For stable operation of an LCD Module, if V_DD(typ.) × 80% ≤ V_CC ≤ V_DD(typ) × 90%, then T_d should be less than 20ms. These conditions are for input voltage glitches.

7. Outline Dimension

The outline dimension diagram provides detailed mechanical specifications for the LTM190EP01 module. Key dimensions include: 396 ± 0.5mm (overall horizontal size), 324 ± 0.5mm (overall vertical size), and 17.0mm (depth). The active display area is 376.32mm (H) x 301.056mm (V). The bezel open dimensions are 380.2mm (H) x 305mm (V). There are four M3 user holes for mounting, with specific locations and distances from edges and center. The diagram also shows various internal components and their relative positions, including the LCD panel, TFT-LCD module, and the location of the inverter. The weight is approximately 2,250g for the LCD module only. Mechanical tolerance is ± 0.5mm unless otherwise specified. The backlight consists of 4 Cold Cathode Fluorescent Lamps. The I/F connector specification is FI-XB30SSL-HF15 or equivalent. The lamp connector/wire specification is Yeonho 35001HS-02L or equivalent (2 PIN x 170mm). User mounting torque specification is a maximum of 6 Kgf-cm.

8. General Precautions

8.1 Handling

• When assembling the module, attach it firmly to the system using all mounting holes. Avoid twisting and bending the module.
• The inverter uses high voltages; disconnect it from the power source before assembly or disassembly.
• Avoid strong mechanical shock or force to the module, as it may cause damage or improper operation of the module and CCFT backlight.
• Polarizer films are fragile and easily damaged. Do not press or scratch the surface harder than an HB pencil lead.
• Wipe off water droplets or oil immediately to prevent staining or discoloration.
• Clean the polarizer surface with absorbent cotton or a soft cloth if dirty.
• Use water, IPA (Isopropyl Alcohol), or Hexane as cleaners. Do not use Ketone type materials (e.g., Acetone), Ethyl alcohol, Toluene, Ethyl acid, or Methyl chloride, as they may cause permanent damage to the polarizer.
• If liquid crystal material leaks from the panel, keep it away from eyes or mouth. In case of contact with hands, legs, or clothes, wash thoroughly with soap.
• Protect the Module from static electricity to prevent damage to the CMOS Gate Array IC.
• Use finger-stalls with soft gloves during incoming inspection and assembly to keep the display clean.
• Do not disassemble the Module.
• Do not pull or fold the lamp wire.
• Do not adjust the variable resistor located on the Module.
• Slowly peel off the protection film for the polarizer just before use to minimize electrostatic charge.
• Do not touch the pins of the I/F connector directly with bare hands.

8.2 Storage

• Do not leave the Module in high temperature or high humidity for extended periods. Store the Module with temperature from 0 to 35 °C and relative humidity less than 70%.
• Do not store the TFT-LCD Module in direct sunlight.
• Store the Module in a dark place. Avoid applying sunlight or fluorescent light during storage.

8.3 Operation

• Do not connect or disconnect the Module while in the "Power On" condition.
• Power supply should always be turned on/off according to the "Power on/off sequence" described in item 6.3.
• The module has high frequency circuits. System manufacturers should implement sufficient suppression for electromagnetic interference. Grounding and shielding methods are important to minimize interference.
• The cable between the backlight connector and its inverter power supply should be connected directly with minimized length. A longer cable may cause lower lamp luminance (CCFT) and require higher startup voltage (V_S).

8.4 Operation Condition Guide

• The LCD product should be operated under normal conditions. Normal conditions are defined as:
  • Temperature: 20 ± 15 °C
  • Humidity: 65 ± 20%
  • Display pattern: continually changing pattern (Not stationary)
• If the product will be used in extreme conditions (e.g., high temperature, humidity, specific display patterns, or extended operation time), it is strongly recommended to contact SEC for Application engineering advice. Otherwise, reliability and function may not be guaranteed. Extreme conditions are commonly found at airports, transit stations, banks, stock markets, and controlling systems.

8.5 Others

• An Ultra-violet ray filter is necessary for outdoor operation.
• Avoid condensation of water, as it may result in improper operation or disconnection of electrodes.
• Do not exceed the absolute maximum rating values (supply voltage variation, input voltage variation, variation in part contents, and environmental temperature). Exceeding these may damage the Module.
• If the Module displays the same pattern for a long period, image "sticking" may occur. To avoid this, use a screen saver.
• The Module has circuitry PCBs on the rear side and should be handled carefully to avoid stress.
• Contact SEC in advance if the same pattern will be displayed for a long time.