MPC5777C MCAL4.3 Dual Core Project Implementation

2.1. Dual core memory section

Flash_rsvd1 is used to store RCW, and flash_memory is used by core 0. Modify the link file to allocate flash_memory1 to store the core 1 startup code and fix the vector reset address as 0x00ED0000. This address also needs to be configured in EB tresos.

Note: This linker command file is to be used with the MPC5777C device only.

MEMORY {
/* 5777C Flash 8.0 MB 0x00800000 0x00FFFFFF */
 flash_rsvdl : ORIGIN = 0x00800000, LENGTH = 0x20
 /*flash_memory : ORIGIN = 0x00800020, LENGTH = 0x7CFFE0*/
 flash_memory : ORIGIN = 0x00800020, LENGTH = 0x6CFFE0
 flash_memoryl : ORIGIN = 0x00ED0000, LENGTH = 0x100000
 flash_vec : ORIGIN = 0x00FD0000, LENGTH = 0x010000
 flash_vec_corel : ORIGIN = 0x00FE0000, LENGTH = 0x010000
 flash_rsvd2 : ORIGIN = , LENGTH = 0
}

Figure 1. Memory for two core

The following figure shows the allocated stack for core 0, starting from address 0x4003EBC0. The core 1 stack address starts from 0x4003FBC0 and has a length of 4k.

/* 5777C SRAM 512 KB : 0x40000000 0x4007FFFF */
 ram_rsvdl : ORIGIN = 0x20000000, LENGTH = 0
 int_sram : ORIGIN = 0x40000000, LENGTH = 0x3EB60
 res_ram : ORIGIN = 0x4003EB60, LENGTH = 0x60
 iram_stack : ORIGIN = 0x4003EBCO, LENGTH = 0x1000
 iram_stack_corel : ORIGIN = 0x4003FBCO, LENGTH = 0x1000
 int_timers : ORIGIN = 0x40040BC0, LENGTH = 0x0340
 int_results : ORIGIN = 0x40040F00, LENGTH = 0x0100
 int_sram_no_cacheable : ORIGIN = 0x40041000, LENGTH = 0x3F000
 ram_rsvd2 : ORIGIN = , LENGTH = 0

Figure 2. Stack for core1

The following figure shows the allocated new section for core 1:

• .text1: section for core 1 startup code
• .isrvectbl_core1: section for core 1 interrupt vector table
• .isrvectbl_core_corel: section for core1 core vector table (IVOR)
• _IV_ADDR_core1: gets the flash_vec_corel address
• _SP_INIT_core1: gets iram_stack_corel address

.textl : > flash_memoryl
.isrvectbl_corel : ALIGN (0x10000) : > flash_vec
.isrvectbl_core_corel : ALIGN (0x10000) : > flash_vec_corel
_IV_ADDR_corel = MEMADDR(flash_vec);
_IV_ADDR_corel = MEMADDR(flash_vec_corel);
_SP_INIT_corel = ADDR(iram_stack_corel) + SIZEOF(iram_stack_corel);
_SP_END_corel = ADDR(iram_stack_corel);
STACK_SIZE_corel = SIZEOF(iram_stack_corel);

Figure 3. Allocated new section for core 1

2.2. Dual core startup file

To place the startup code into its own section, use the GHS compiler keywords to set the core 1 startup code to the text1 section.

#pragma ghs section text=".textl"
void StartupCode_corel(void)
{
 ASM_KEYWORD (".globl _start1");
 ASM_KEYWORD (".globl startl");
 ASM_KEYWORD (".align 4");
 ASM_KEYWORD ("_start1:");
 ASM_KEYWORD ("start1:");
}
#pragma ghs section

Figure 4. Startup code for core 1

The following figure shows the IVPR register that needs to be initialized to the address of the interrupt vector table and exception vector handler. These handler addresses are provided as configuration parameters in link setting.

/* Initialize IVPR register to address of Interrupt Vector Table */
ASM_KEYWORD (" e_lis r5, IV_ADDR_corel@h ");
ASM_KEYWORD ("e_or2i r5, IV_ADDR_corel@l ");
ASM_KEYWORD (" mtIVPR r5");
ASM_KEYWORD ("se_mr r0, r31 ");

ASM_KEYWORD (" e_lis r5, IVORO_Handler_corel@h ");
ASM_KEYWORD (" e_or2i r5, IVORO_Handler_corel@l ");
ASM_KEYWORD("mtspr 400, r5 ");

ASM_KEYWORD (" e_lis r5, IVOR1_Handler_corel@h ");
ASM_KEYWORD (" e_or2i r5, IVOR1_Handler_corel@l ");
ASM_KEYWORD("mtspr 401, r5 ");

ASM_KEYWORD (" e_lis r5, IVOR2_Handler_corel@h ");
ASM_KEYWORD (" e_or2i r5, IVOR2_Handler_corel@l ");
ASM_KEYWORD("mtspr 402, r5 ");

ASM_KEYWORD (" e_lis r5, IVOR3_Handler_corel@h ");
ASM_KEYWORD (" e_or2i r5, IVOR3_Handler_corel@l ");
ASM_KEYWORD("mtspr 403, r5 ");

ASM_KEYWORD (" e_lis r5, IVOR4_Handler_corel@h ");
ASM_KEYWORD (" e_or2i r5, IVOR4_Handler_corel@l ");
ASM_KEYWORD("mtspr 404, r5 ");

Figure 5. Interrupt vector and exception handler initialization

The machine check and exception for core 1 should be enabled as shown in the following figure.

/* define MSR mask to enable Machine Check and Exception / IRQ */
ASM_KEYWORD(".equ MSR_Mask1, 0x00009000 ");
ASM_KEYWORD(" mfmsr r5 ");
ASM_KEYWORD (" e_lis r6, MSR_Mask1@h ");
ASM_KEYWORD (" e_or2i r6, MSR_Mask1@l ");
ASM_KEYWORD(" se_or r5, r6 ");
ASM_KEYWORD(" mtmsr r5 ");
ASM_KEYWORD (" se_isync");

Figure 6. Machine check and exception for core 1

Start-up code should initialize the user stack pointer for core 1, as shown in the following figure.

/*
* Autosar Guidance 3 The start-up code shall initialize the
* user stack pointer. The user stack pointer base address and
* the stack size are provided as configuration parameter or
* linker/locator setting.
*/
ASM_KEYWORD(" e_lis r1, SP_INIT_corel@h");
ASM_KEYWORD(" e_or2i r1, SP_INIT_corel@l");

Figure 7. Stack initialization for core 1

4.1. Compiling GHS

The test hardware is the MPC5777C EVB. Compiler GHS version is compiler 2019.5.4 (it is recommended to update to the latest version). EB tresos version is 25.1, and the MCAL package version is MPC5777C MCAL4.3 1.0.0.

Open the build folder as shown in the following figure.

Figure 10. Sample code build folder

The launch.bat file contains configuration for TRESOS_DIR, MAKE_DIR, GHS_DIR, and PLUGINS_DIR. It also specifies the TRESOS_WORKSPACE_DIR.

To build the sample, execute the following command to run launch.bat:

C:\Windows\System32\cmd.exe

C:\Work_Material\software\vds-mpc5777c-mcal4.3\vds-mpc5777c-mca14.3\MPC5777C_MCAL4_3_RTM_1_0_0_Sample_Application\eclipse\plugins\PlatformIntegration_TS_T2D41M10IORO\build\launch.bat

Figure 12. Build command

The object files and linker output file (PlatformIntegration.elf) will be generated in the /bin subdirectory. Open the cmm folder and run the smp_demo.cmm script using LAUTERBACH debugger and debug the sample application code.