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Intel Agilex General-purpose I/O and LVDS SERDES User Guide This user guide provides comprehensive details on the Intel Agilex general-purpose I/O (GPIO) and LVDS SERDES interfaces. It covers features, functional descriptions, implementation guidelines, and restrictions for these I/O systems within Intel Agilex devices. Updated for Intel Quartus Prime Design Suite 20.3. |
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OCT Intel® FPGA IP User Guide This user guide provides detailed information on the OCT Intel FPGA IP, including its features, functional description, parameter settings, signals, and QSF assignments. It supports Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX devices, offering dynamic on-chip termination for improved signal integrity. The guide also covers IP migration from older ALTOCT IP cores and design example generation. |
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Intel® FPGA Design Flow for Xilinx® Users: A Comprehensive Guide This application note guides Xilinx designers in migrating their FPGA designs to Intel® Quartus® Prime Pro Edition software, covering technology comparison, tool equivalencies, and detailed conversion steps for primitives, IP cores, and constraints. |
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Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook A comprehensive technical handbook detailing the core fabric, logic array blocks (LABs), adaptive logic modules (ALMs), embedded memory blocks, DSP blocks, clock networks, PLLs, and I/O features of the Intel® Cyclone® 10 GX FPGA family. It serves as a guide for engineers and designers. |
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JESD204C Intel Stratix 10 FPGA IP Design Example User Guide This user guide provides the features, usage guidelines, and detailed description about the design examples for the JESD204C Intel FPGA IP using Intel Stratix 10 devices. It covers system components, clock and reset signals, design example signals, control registers, and hardware testing procedures. |
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5G Polar Intel FPGA IP User Guide | Intel FPGA Technology This user guide provides comprehensive technical details for the 5G Polar Intel® FPGA IP. It covers features, 3GPP 5G NR compliance, installation, design, simulation, and functional descriptions for wireless applications. |
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Intel Stratix 10 E-tile Hard IP Design Examples: Ethernet, CPRI PHY, and Dynamic Reconfiguration User Guide This user guide provides detailed information and examples for implementing Ethernet, CPRI PHY, and Dynamic Reconfiguration using the E-tile Hard IP on Intel Stratix 10 devices. It covers design generation, simulation, compilation, and hardware testing for various configurations. |
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Intel® FPGA IP GPIO User Guide for Arria® 10 and Cyclone® 10 GX Devices This user guide details the Intel® FPGA IP GPIO core, covering its features, data paths, interface signals, parameter settings, and timing for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices. It includes migration guidelines and design examples for FPGA developers. |