ATE Solutions

Overview of the V93K HSIO System

Advantest and MultiLane offer a single platform solution which leverages the best capabilities and qualities of both companies. These two established test equipment companies have developed a highly integrated solution that brings these high-frequency resources very close to the device under test (DUT) and significantly enhances signal integrity and test accuracy.

Figure 1: Diagram illustrating the V93K HSIO System, showing connections between the Device Under Test (DUT) board, instrument backplane, twinning test head extension, and components like MultiLane instruments and Advantest systems, along with power and cooling.

Key Features

• Very short distance from DUT to high-speed instruments
• High-speed instruments controlled via Smartest APIs, in line with V93000 tester resource control
• Direct Docking to device handlers and wafer probers
• High-speed BERT testing (56Gbps NRZ, 112Gbps PAM4)
• Multi-Channel Digital Sampling Scope
• Widest bandwidth ATE resident DSO in the industry
• Leading edge signal equalization uses scope's capability to measure S21
• Long list of interactive test tools
• Easy movement of capabilities between bench and ATE
• MultiLane Experience and Support

Benefits

• Supports testing of leading-edge interfaces
• DSO brings a wealth of new test capabilities to the V93000 test platform.
• 50GHz BW consistent with the needs of this high-end digital market.
• BERTs and SCOPEs compensate for cable and DUT board traces.
• Tried-and-true tools to speed debug & bring-up effort.
• Use ATE DUT board on bench & bench type tools on ATE
• Years of experience with high-speed communications testing

Instruments Integration in V93000

The V93000 provides customers with fully integrated capabilities to improve the testing of their products and speed their time to market.

Figure 2: Exploded view of instrument integration within the V93K system, detailing the arrangement of up to four instrument cassettes, MultiLane backplanes, and the HSIO card cage, connecting to a twinning DUT board with multiple cavities for signal routing.

Figure 3: System block diagram of the V93K integration, depicting the flow of power, clock signals, and data between PS1600 power supplies, 93K modules, the family board, MultiLane BERT and Scope modules, and the DUT board within a twinning frame.

Instruments Specs

Below are the specifications for the MultiLane instruments that have been seamlessly integrated into Advantest's V93000 ATE tester and can be controlled by Advantest's SmarTest software platform, and by MultiLane assigned GUIs.

AT4025-50: 50 GHz Electrical DSO

Key Features

• Up to 100 MHz sampling rate
• Less than 5 seconds TDECQ on a SSPRQ pattern
• Fast pattern capture and DSP thanks to an FPGA-based architecture.
• An extensive library of built-in DSP filters such as Bessel-Thomson, CTLE, DFE, FFE, de-embedding and component emulation, all available free of charge in the standard GUI.
• User-writable calibration constants
• Can be calibrated up to the DUT to include losses of test fixtures and cables.
• Built-in standard masks library
• A complete set of APIs and multiple SmarTest sample code to speed up integration.

Figure 4: Graph showing NRZ sample measurements, displaying signal amplitude over time.

Figure 6: Graph showing Total Harmonic Distortion (THD) levels.

AT4039D: 4-Lane BERT 28 GBd PAM4/NRZ

Programmable Pattern Generator Features

• High-speed clock out to 3 GHz
• Gray coding, polarity inversion
• PRBS 7, 9, 13, 15, 23, 31, 58
• PRBS 13Q, 15Q, 31Q
• Up to 1500 mVppd voltage swing
• Patterns are generated algorithmically
• Custom patterns: 64 bits can be repeated up to 255 times and repeated as needed

Error Detection Features

• FFE Equalizers
• > 13 dB equalization with FFE+CTLE
• PAM4 eye balance tuning
• Eye contour and PAM level histogram
• PRBS 7, 9, 13, 15, 23 & 31 checker
• Automatic PRBS detection
• Clock-data recover
• BER counters

Figure 5: Block diagram of the AT4039D, illustrating the signal path from reference clock input, through the pattern generator (PPG) with various pattern options, to the transmitter (TX PAM NRZ), and the receiver (RX PAM NRZ) with error detection features like FEC emulator and detector.

AT4039E: 4-Lane BERT 56 GBd PAM4/NRZ

PPG Features

• High-speed clock out to 7 GHz
• Real FEC and Gray coding
• PRBS 7, 9, 13, 15, 23, 31, 58
• PRBS 13Q, 31Q
• Up to 800 mVppd voltage swing
• Patterns are generated algorithmically
• Custom patterns: 64 bits can be repeated up to 255 times and repeated as needed

ED Features

• FFE Equalizers with reflection cancellation and DFE
• PAM4 eye balance tuning
• Eye contour and PAM level histogram
• PRBS 7, 9, 13, 15, 23 & 31 checker
• Automatic PRBS detection
• Clock-data recover
• BER counters

Figure 7: Histogram illustrating PAM eye measurements, showing the distribution of signal levels.

Figure 8: Graph displaying Bit Error Rate (BER) curves for four channels, plotted against acquisition time or a similar metric.

AT4039EML: 4-Lane SE BERT 56 GBd PAM4/NRZ w/EML Driver

PPG Features

• High-speed clock out to 7 GHz
• Real FEC and Gray coding
• PRBS 7, 9, 13, 15, 23, 31, 58
• PRBS 13Q, 31Q
• Up to 1800 mVppd voltage swing
• Single-ended high swing output for EML driving

ED Features

• FFE Equalizers with reflection cancellation and DFE
• PAM4 eye balance tuning
• Eye contour and PAM level histogram
• PRBS 7, 9, 13, 15, 23 & 31 checker

Figure 9: Photograph of four HSIO MultiLane cassettes installed within a twinning frame, directly connected to an Advantest V93K test head.

AT4079B: 8-Lane 1 – 28 GBd PAM4/NRZ

Key Features

• Low cost, instrument-grade BERT optimized for high speed data analysis of 100G/200G/400G transceivers.
• The wide range of bitrate coverage allows phy testing for Ethernet, HDMI 2, USB 3.1, PCIe, Fiber-Channel and others.
• Ability to tune the bit rate in very fine steps to facilitate finding the locking margin.
• FEC support.
• Supports PRBS13Q/15Q/31Q and user-defined patterns.
• API library, sample code and Python wrapper

ATE Applications

• Diff-Diff TIA/Driver test
• SE-Diff TIA/Driver
• Diff-Diff and SE-Diff TIA/Driver with CDR
• ASIC with high-speed IO

SE and Diff TIA measurements: Eye captures allow to visualize non-linearities and imbalances.

Figure 10: Photograph of the twinning frame enclosure and its assembly, showcasing the integration of MultiLane cassettes.

AT4039B-JIT: 4-Lane BERT 28 GBd NRZ Jitter Injection

Key Features

• Bitrate coverage 1 – 30 Gbps continuous
• Sinusoidal Jitter Modulation to 100 ps
• Phase skew adjustment to +/- 50 ps
• Random jitter injection
• Random interference injection
• Error insertion
• User defined pattern generation
• Supports all standard PRBS patterns

Figure 11: Graph representing Eye/Pattern Measurements, likely showing signal quality metrics.

Figure 12: Graph plotting Sample TIA S-Parameters against Bandwidth (BW), indicating the frequency response characteristics.

AT93000-CALKIT

• Calkit has load board form factor
• It contains all the cables and brackets for quick mount
• Simply undock load board and mount calkit instead
• No need to touch the ML cassettes
• Quick connect to external calibration reference
• ML4035 cabling de-embedded

Figure 13: Photograph demonstrating a fully automated calibration procedure, likely involving the AT93000-CALKIT.

Software Integration

• ML Shared Libraries for RHEL5 and RHEL7
• Supports Multisite Testing
• SMARTEST sample code available
• High throughput features
• Co-development MultiLane & Advantest

Figure 14: Screenshot of a Signal Analyzer interface, displaying waveform data and analysis results.

Figure 15: Diagram illustrating the SmarTest Integration Model, showing the interaction between user test programs, MultiLane API libraries, SmarTest software, and hardware components like PCs, Ethernet routers, and power supplies.

Ordering Information

Contact Information

North America

48521 Warm Springs Blvd. Suite 310
Fremont, CA 94539
USA
+1 510 573 6388

Worldwide

Houmal Technology Park
Askarieh Main Road
Houmal, Lebanon
+961 81 794 455

Asia

14F-5/ Rm.5, 14F., No 295
Sec.2, Guangfu Rd. East Dist.,
Hsinchu City 300, Taiwan (R.O.C)
+886 3 5744 591