AR2002 Service Manual

Specifications

Frequency ranges: 25.000-550.000MHz & 800.000-1300.000MHz

Modes of operation: Narrow FM, Wide FM & AM

Frequency readout: Complete to .5 KHz on LCD screen

Number of memory channels: 20 channels with mode, step & lockout information

Frequency selection: Keyboard entry & rotary up/down tuning

Channel steps: 5 KHz, 12.5 KHz & 25 KHz

Frequency stability: Within +/-10 PPM at 25°C and +/-50 PPM between -10°C and +60°C

Sensitivity:

• Narrow FM: 0.35 uV for 12 dB SINAD
• Wide FM: 1.0 uV for 12 dB SINAD
• AM: 1.0 uV for 10 dB S/N

Selectivity:

Intermediate frequencies:

• 750 MHz for range 25-550 MHz
• 45.03 MHz, 455 KHz for NFM/AM modes
• 5.5 MHz for WFM

Scan rate: 5 channel per second

Search speed: 10 second per megahertz by 25 KHz step

Scan delay: 2.5 seconds

Audio power output: 1 watt at 10% maximum distortion

Power requirement: DC 12 to 16 volts, 0.6 ampere maximum

Dimensions: 80 mm High x 138 mm Wide x 200 mm Deep

Weight: 1.1 Kgs. (less rod antenna & AC adaptor)

Standard accessories: AC adaptor, DC cable, Rod antenna & Operator's manual

Optional accessories: Mobil mounting bracket/model MM-1, Outdoor antenna with 10 meter coaxial cable with connectors/model DA300, Computer interface RS232C with cable/connectors/model "RC PACK"

Theory of Operation

General

The AR2002 receiver offers high-performance monitoring and surveillance across a wide frequency range of 25-550 MHz and 800-1300 MHz. Its versatility is enhanced by reception modes including AM, NFM, and WFM, making it suitable for various applications such as general off-air monitoring, spot frequency monitoring/measurement, selective multi-frequency analysis, spectrum surveillance, and detection of unwanted transmissions.

The receiver covers two frequency ranges with selectable increments of 5 KHz, 12.5 KHz, or 25 KHz, allowing any reception mode to be used at any frequency or channel spacing. Typical sensitivity for NFM is better than 0.3 uV for 12 dB SINAD, maintained across the tuning range.

Control can be managed via a professional keyboard and a front panel tuning control for conventional rotary tuning, or through an external control interface on the rear panel. Twenty memory channels are available, storing frequency and mode information, which can be recalled manually or scanned automatically for unattended monitoring. The entire frequency coverage can be scanned in 5, 12.5, or 25 KHz steps. A search facility between two user-programmed limits is also included, with options for high-to-low or low-to-high searching. Two search speeds are available.

A delay function can be activated to manage slight pauses between transmissions in two-way simplex conversations. Memory channel 1 can be set as a priority frequency, monitored at 2-second intervals.

Front panel information is displayed on a liquid crystal display (LCD), showing frequency, mode, memory channel number, frequency increment, delay status, channel lockout, and more. A bar-type signal strength meter aids in comparative measurements and direction finding. A crystal-controlled real-time clock is also integrated and displayed on the LCD.

The AR2002 requires 12-14 V DC at 0.3-0.5 A. A suitable mains adaptor and power lead for battery operation are included.

The AR2002 is a triple conversion super-heterodyne receiver. For the 25-550 MHz range, it uses a 750 MHz first IF. For the 800-1300 MHz range, it is a double conversion super-heterodyne receiver with a 45.03 MHz first IF.

Signal Path Circuits

Signals from the antenna pass through an attenuator circuit and then enter the RF amplifier (IC-1) via a bandpass filter for the 25-550 MHz range, or IC-9 via a high-pass filter for the 800-1300 MHz range. Diode protection is provided at the input of each RF amplifier stage.

Amplified signals are mixed in the first mixer with the 1st local oscillator frequency to produce a 750 MHz 1st IF for the low range (25-550 MHz) and a 45.03 MHz 1st IF for the high range (800-1300 MHz). In the low range, the output signal of the 1st mixer passes through a 750 MHz bandpass filter, is amplified by two stages of IF amplifiers with AGC, and then mixed in the 2nd mixer with a 2nd local oscillator frequency of 704.97 MHz to produce a 45.03 MHz 2nd IF frequency.

In the high range, the output signal of the 1st mixer bypasses the 1st IF amplifier and 2nd mixer to enter the 45.03 MHz bandpass filter.

The 2nd IF signal (1st IF for the high range) is switched to further IF stages for WFM IF or NFM/AM IF. In WFM IF, the 45.03 MHz signal passes through a bandpass filter, is amplified, and converted to a 5.5 MHz 3rd IF by a 39.53 MHz oscillator. It is then amplified and FM detected, followed by de-emphasis and an audio gate.

In NFM/AM IF, the 45.03 MHz signal passes through monolithic crystal filters centered on 45.0275 MHz (+/-8 KHz, 83 dB bandwidth), is amplified, and converted to a 455 KHz 3rd IF by a 44.575 or 44.570 MHz crystal oscillator, depending on the channel step (0/12.3 KHz or 5 KHz). The 455 KHz 3rd IF signal passes through a ceramic filter centered on 455 KHz, and is then switched to further IF amplifiers/detectors for NFM or AM. The detected signal is gated in an audio gate circuit and amplified by an audio power amplifier to 1 watt.

Main Unit

The main unit board includes RF amplifiers, 1st and 2nd mixers, 2nd local oscillator, bandpass filters, WFM IF circuit, NFM/AM IF circuit, audio power amplifier, squelch circuit, and power control circuits. The RF amplifiers provide flat response, low noise figure, and low intermodulation distortion for signals from 25 to 550 MHz and 800 to 1300 MHz.

The 1st mixer (D30) is a passive double-balanced mixer using 4 diodes in a ring configuration for a high intercept point. The IF amplifier (Q31) acts as an impedance matcher and amplifier. The bandpass filter uses triple helical resonators for +/-2 MHz at 35 dB and +/-40 MHz at 65 dB.

The IF amplifier (Q1) is a Ga-As FET high-gain amplifier that compensates for helical resonator insertion loss and has gain automatically controlled by the Q2 AGC controller along with Q31. The 2nd mixer is an active mixer using bipolar transistor Q3. The 704.97 MHz 2nd local oscillator frequency is generated by a 46.998 MHz quartz crystal oscillator and a multiplier stage (x15).

Q13 is a power amplifier for 704.97 MHz, with its output passing through double helical resonators. In WFM mode, D2 conducts, and the signal passes through a bandpass filter (T-15, 16, 17) and is amplified by Q14, 15, then enters IC-5 (MC3357P). IC-5 converts the signal to a 5.5 MHz 3rd IF using its internal 39.53 MHz oscillator, amplifies it, and discriminates it to audio frequency with ceramic filters CF3 and discriminator CF4.

In NFM/AM mode, D3 conducts, and the signal passes through monolithic crystal filters, is amplified by Q4, 5 (with AGC control), and enters IC-4 (MC3357P). IC-4 converts the signal to 455 KHz using its internal 44.575 or 44.570 MHz crystal oscillator and amplifies/discriminates it to audio frequency with ceramic filter CF1 and discriminator CF2. IC-2 is a capacitor/resistor network for the MC3357P circuit.

The squelch circuit operates in NFM, AM, and WFM modes. IC-3 (NIS-112) amplifies and detects AM/AGC. Q36 acts as a buffer amplifier for AGC, supplying AGC voltage to Q31, 2, 4, and 5. Q6 inhibits 3rd local oscillation in WFM mode. Q7 switches the quartz crystal oscillator for proper frequency based on the 0/5 KHz signal from the CPU (uPD7503). The mode switch, consisting of transistors Q22 through Q27, selects and controls AM (Q18), NFM (Q21), and WFM (Q20) preamplifiers.

Audio level output for each mode is equalized within +/-6dB tolerance. The audio gate circuit uses IC-6 (TC4066) and transistors Q28, 29 (2SC2785), controlled by the squelch signal from IC-4 or the PLL lock signal from the PLL unit.

The audio power amplifier IC-8 (uPD2002) provides sufficient power output for the internal 8-ohm speaker, and the specified power output can be achieved with a 4-ohm external speaker. The power supply circuit provides 6V and 10V outputs. IC-7 (uA78M06) regulates the 6V output, and a 10V regulator is formed by transistors Q32 through Q35. These regulators also function as effective ripple and noise filters.

PLL Unit

This unit is a Phase Lock Loop (PLL) oscillator controlled by the CPU/LCD unit, providing carrier frequencies from 754.97 to 1300 MHz to the 1st mixer. Two versions of the PLL unit exist: one for serial numbers up to 1500, and a newer version for serial numbers above 1500.

For AR2002 serial numbers up to 1500:

• IC-1 (NIS-118) oscillates at 377.5-490MHz, and IC-3 (NIS-116) doubles the frequency to 755-980MHz.
• IC-2 (NIS-119) oscillates at 490-650MHz, and IC-5 (NIS-117) doubles the frequency to 980-1300MHz.
• IC-1 and IC-2 are voltage-controlled oscillators (VCOs), while IC-3 and IC-5 are bandpass filters.
• Doubled carrier is buffered by Q5 or Q6, then amplified by Q7, 8, and a power amplifier to an output level of 1 milliwatt.
• VCO outputs via Q1, 3 are buffered by Q2, 4 and pass through IC-4 (NIS-115) low-pass filter.
• IC-12 (uPC1651) wideband amplifier boosts the carrier to a sufficient level to drive IC-6 (uPB566) prescaler.
• IC-6 (uPB566) is a dual modulus prescaler that forms pulse swallow counters in combination with PLL IC-7 (uPD2833C).
• Reference frequency is controlled by quartz crystal oscillator Q9 at 3.200 MHz and divided by 128 or 512 in IC-7's internal fixed divider for 25 KHz or 6.25 KHz, respectively.
• IC-9 (TC5026) divides 25 KHz by 5 for 5 KHz.
• IC-8 switches between 5 KHz or 6.25 KHz based on the 5K/12.5K step signal from the CPU.
• The output signal from the internal tri-state phase detector enters a low-pass filter (Q13, 14, 15) which produces the VCO control voltage (VCV) in the 220-volt range.
• IC-11 (TCA-720) is a DC-DC converter for 30 volts.
• The lock detector circuit (Q10, 11, 12, 16) transfers the PLL lock signal to the CPU to confirm PLL lock completion at each frequency.
• Q20 acts as a compensator when lock fails initially due to noise mixing in data.
• The VCO switch circuit (Q17, 18, 19) selects the VCO based on control signals from the CPU (VCO SW).
• A backup circuit uses IC-10 (uA78L62) to back up the CPU when DC supply is connected. When DC supply is removed, super capacitor C58 (1 Farad) backs up the CPU until its voltage drops to 3 volts (approximately one week).

For AR2002 serial numbers more than 1500:

• IC-1 (NIS-130) is a voltage-controlled oscillator that directly oscillates the 754.97-1300MHz frequency carrier.
• The VCO output carrier passes through a low-pass filter (L1, L2, C7-11), is buffered and amplified by Q1-4 transistors to an output level of 1 milliwatt.
• The VCO output carrier is also buffered by Q5 transistor and amplified by IC-2 (uPC1651G) wideband amplifier to drive IC-3 (NIS-131) prescaler, which divides the carrier by 1/2.
• The divided carrier (377.485-650MHz) is applied to IC-4 (uPB566) dual modulus counter, which functions as a pulse swallow counter in combination with PLL IC-5 (uPD2833C).
• Reference frequency is controlled by quartz crystal oscillator Q6 at 6.400 MHz and divided by 128 or 1024 in IC-5's internal fixed divider for 50 KHz or 6.25 KHz, respectively.
• IC-7 (uPD4510BG) divides 50 KHz by 10 for 5 KHz.
• IC-6 (uPD4011BG) switches between 5 KHz or 6.25 KHz based on the 5/12.5 KHz step signal from the CPU.
• The output signal from the internal tri-state phase detector enters a low-pass filter (Q7-9) which produces the VCO control voltage. D1 rectifies this to obtain a DC 30-volt supply source for the VCV voltage.
• The lock detector circuit (Q10-13) transfers the PLL lock signal to the CPU to confirm PLL lock completion at each frequency.
• A backup circuit uses IC-8 (uA78L05) to back up the CPU when DC supply is connected. When DC supply is removed, super capacitor C62 (0.47 Farad) backs up the CPU until its voltage drops to 3 volts (approximately one week).

CPU/LCD Unit

This unit comprises the CPU, keyboard, LCD display, and S-meter circuit. The CPU (uPD7503G) is a 4-bit microprocessor with an ALU, ROM, RAM, I/O ports, serial interface, programmable counter, and LCD controller/driver. It features 4096x8 bit ROM, 224x4 bit RAM, direct LCD drive, low voltage data maintenance, RC oscillator for system clock, crystal oscillator, single power supply, and low current drain.

The CPU accepts 4 control signal inputs and outputs 6 control signals, driving the LCD screen. The inputs are: squelch signal from IC-4 (MC3357P pin 14) on the main unit, PLL lock signal from the PLL unit, 6V signal from IC-7 (uA7806) on the main unit, and key lock signal from the CPU/LCD unit.

The CPU outputs include: mode switching signals (AM, NFM, WFM) to the main unit; VCO switching signal (high/low) to the PLL unit (for serial numbers less than 1500); alarm signal for beep tone to the audio amplifier in the main unit; 5 KHz switching signal (0/5 KHz) in NFM/AM mode to the 3rd oscillator in the main unit; step switching signal (5/12.5 KHz) to IC-6 (TC4011) in the PLL unit; and PLL data signals (clock (CK), data (DATA), and strobe (STB)) to IC-7 (uPD2833C) via a 17-bit binary serial input.

The LCD screen displays frequency, channel number, mode, priority, delay, scan, lockout, search, steps, and real time. The bar-type 'S' meter uses LEDs (Green/Red) and IC-2 (TA7612AP) S-meter driver, with Q8 transistor as an AGC inverter. A rotary shaft encoder is provided for manual up/down control.

Maintenance

Cover Removal

To remove the covers: Unscrew the two screws near the rubber feet on the bottom of the AR2002 and the two screws on the back of the lower cabinet. Remove the lower cabinet. Then, remove the two screws on the back of the upper cabinet, lift the back wall of the upper cabinet upwards, and pull backward to remove it.

Test Equipment Required

The following test equipment is recommended for maintenance:

1. DC voltmeter
2. AC voltmeter
3. Oscilloscope with 10 MHz response
4. Frequency counter with 1350 MHz response
5. Signal generator with range of 455 KHz to 1300 MHz
6. Spectrum analyzer with 1350 MHz response
7. Tracking generator or sweep generator with 50 MHz response
8. DC power supply with 12 V 500 mA capacity
9. Special RF probe for spectrum analyzer and frequency counter (recommended probe involves soldering two short pins to a BNC female connector)

Alignment and Calibration

New receivers are pre-aligned and tested before shipment. If realignment is necessary:

1. Clock time base oscillator: On the CPU/LCD unit board, locate test point TP-1 and trimmer capacitor TC-1. Set the receiver to 100.000 MHz (flashing CH condition). Connect a frequency counter to TP-1 and carefully adjust TC-1 to obtain exactly 512.000 Hz. Clock accuracy depends on this alignment (approx. 20 seconds/month tolerance).
2. DC 10V alignment: On the main unit board, measure DC voltage at pin 5 of IC-8 (uPC2002). Adjust variable resistor VR3 near the RF input connector to get 10V.
3. Reference oscillator alignment: On the PLL unit board, find the RF output connector (RCA type) and trimmer capacitor TC-1. Set the receiver to 550.000 MHz. Connect a frequency counter probe to the back terminal of the RCA connector and adjust TC-1 to get exactly 1300.000 MHz (+/-500 Hz allowed at ambient temperature).
4. 2nd IF alignment: Locate R15 (220 K ohm) near T8 and R32 (2.2 K ohm) at pin 3 of IC-4 (MC3357P). Use a short jumper wire to connect the emitter of Q36 to the +6V line, disabling AGC on Q36. Connect the output of a tracking/sweep generator to the base of Q3 (2SC3355) (2nd mixer) and the input of a spectrum analyzer to pin 16 of IC-4 (MC3357P). Set the receiver in AM or NFM mode at any frequency. Use a -40dBm output from the generator and a 0dBm input range with 10 KHz/division on the spectrum analyzer. Adjust T4 and T8 for the highest and flattest curve. Remove the spectrum analyzer connection from pin 16 of IC-4 and connect it to pin 16 of IC-5 (MC3357P). Set the receiver in WFM mode and change the spectrum analyzer dispersion to 50 KHz/division. Adjust T15, T16, T17, and T18 for the highest possible curve.
5. 2nd oscillator alignment: Connect the spectrum analyzer probe to the base of Q12 (2SC3355) and adjust T10, T11, T12 for a peak at 234.99 MHz. Change the probe connection to the base of Q3 (2SC3355) and adjust T12 again, T13, and T14 for a peak at 704.97 MHz. Connect a frequency counter probe to the base of Q3 (2SC3355) and adjust T3 for exactly 704.970 MHz.
6. 1st IF alignment: Connect a signal generator output (225.105 MHz, 1 KHz 60% AM, -80dBm) to the receiver input. Connect a DC voltmeter across R15 (220 K ohm at T8 corner) and ground. Connect an AC voltmeter and oscilloscope in parallel to the speaker terminal. Set the receiver to 225.105 MHz in AM mode, adjust volume for proper distortion-free indication on the oscilloscope. Adjust T2 and T3 for minimum indication on the DC voltmeter. If AGC voltage drops below 3V, decrease the signal generator output and readjust T2 and T3 until no further improvement occurs.
7. RF amplifier alignment: Use the same settings as the 1st IF alignment, but set the signal generator and receiver to 25.105 MHz. Adjust T1 for minimum indication on the DC voltmeter. Check sensitivity within +/-2 dB at any frequency for both ranges (25-550 MHz and 800-1300 MHz).

Troubleshooting

1. Defective on one of three receiving modes:

• Check voltage at pins 3 and 4 of J-4 connector on the MAIN UNIT board (near IC-7 uA7806 regulator) for proper voltage on the selected mode.
• Check voltage at W3 (orange jumper wire) for AM, W4 (grey jumper wire) for NFM, and pin 4 of IC-5 (MC3357P) for WFM.
• Check the detected output from each detector using an oscilloscope.

2. No sound except beep tone when keying in any mode:

• Check voltage at D10 and D11 for Q28 (2SC2785) conduction.
• Check the wiring for the volume control.
• Check for leakage in C9 (1uF) on the CPU/LCD unit that might be muting IC-8 (uPC2002) in the main unit.

3. Low sensitivity:

• Check for defective IC-1 (MC5800) or IC-9 (MC5805) based on the frequency range.
• Verify the frequency and output level of the 1st oscillator (PLL UNIT).
• Verify the frequency and output level of the 2nd oscillator (704.97MHz).

4. No sound, fixed display, or only channel number display without frequency:

• This issue is typically caused by PLL unlock. Try grounding the PLL UNLOCK line and check if the display changes. Then, set the receiver to scan mode and check for data from the CPU appearing on pins 1 (STB), 6 (DATA), and 7 (CK) of IC-5 (uPD2833C) on the PLL board.
• Check the voltages of the 30V line and VCV line at specific frequencies:
  • 25.03MHz: 29V, 3.2V
  • 273.70MHz: 34V, 10.9V
  • 550.00MHz: 41V, 23.4V
• If the VCV line voltage is very low, check if 5KHz or 6.25KHz appears on pin 2 of IC-5 (uPD2833C).
• If the VCV line voltage is sufficiently high, check the RF signal on pin 2 of IC-4 (uPB566) using a spectrum analyzer or RF voltmeter.
• Check for a defective VCO IC-1 by connecting a spectrum analyzer to see if it oscillates randomly or parasitically.

5. Unlock on special frequencies or random frequencies:

• Check for 5KHz or 6.25KHz on pin 2 of IC-5 (uPD2833C).
• Check the waveform on pin 5 of IC-5 (uPD2833C) at the relevant frequencies.
• Check for a defective IC-5 (uPD2833C).

6. No receive on 5KHz up or down:

• Check the 3rd oscillator on the main unit to ensure the quartz crystal unit is properly switched.
• Check for a defective quartz crystal unit (44.570 MHz) for 5KHz operation.

7. Acoustic coupling:

• In NFM mode: Ensure the VCO IC-1 in the shield case is secured properly with adhesive tape. Check the crystal X-1 (46.998 MHz) in the 2nd oscillator. Verify screw tightness for all printed circuit board mountings. Check solder joints at the four corners of the separating shield plate between the main and PLL units.
• In AM mode: Check the vibrating helical resonators. Check the connections of RF coaxial cables.

AR2002 Block Diagram

The AR2002 utilizes a block diagram that illustrates the interconnection of the CPU/LCD Unit, Main Unit, and PLL Unit. The Main Unit contains RF amplifiers, mixers, IF stages, and audio output. The PLL Unit generates the necessary local oscillator frequencies for tuning across the receiver's bands. The CPU/LCD Unit manages user interface, control signals, and display functions.

[Diagrams for Block Diagram, Main Unit Component Location, Component Side, Solder Foil Side, PLL Unit Component Location, Component Side, Solder Foil Side, CPU/LCD Unit Component Location, Component Side, Solder Foil Side are referenced but not displayed here.]

Component Lists

Main Unit Parts List

PLL Unit Parts List

CPU/LCD Unit Parts List

Miscellaneous Parts List

[Diagrams for component pin connections and physical dimensions are referenced but not displayed here.]

Birdie List

Complex receivers can experience internally generated signals called "BIRDIES" that interfere with reception. The following is a partial list of frequencies where birdies may occur in the AR2002:

Additionally, interference from external sources like TV stations, other receivers, and man-made noise can affect reception. This interference varies by location and may sometimes be mitigated by increasing the squelch action (turning the squelch control knob counterclockwise).

PLL Board Installation

[Diagram illustrating PLL Board Installation is referenced but not displayed here.]

Schematic Diagrams

Schematic diagrams for the AR2002, including the PLL Unit (for serial numbers 1500 UP) and the overall AR2002 schematic, are provided for detailed circuit analysis.

[Diagrams for PLL Unit Schematic Diagram and AR2002 Schematic Diagram are referenced but not displayed here.]