AN0002.1: EFM32 and EFR32 Wireless Gecko Series 1 Hardware Design Considerations

Key Points

• Decoupling capacitors are crucial for ensuring the integrity of the device's power supplies.
• The debug interface consists of two communication pins: SWCLK (clock) and SWDIO (data in/out).
• External clock sources must be connected correctly for proper operation.

1. Device Compatibility

This application note supports multiple device families, with some functionality varying by device.

EFM32 Series 1 consists of:

• EFM32 Jade Gecko (EFM32JG1/EFM32JG12)
• EFM32 Pearl Gecko (EFM32PG1/EFM32PG12)
• EFM32 Giant Gecko (EFM32GG11)
• EFM32 Tiny Gecko (EFM32TG11)

EFR32 Wireless Gecko Series 1 consists of:

• EFR32 Blue Gecko (EFR32BG1/EFR32BG12/EFR32BG13)
• EFR32 Flex Gecko (EFR32FG1/EFR32FG12/EFR32FG13/EFR32FG14)
• EFR32 Mighty Gecko (EFR32MG1/EFR32MG12/EFR32MG13)

2. Power Supply Overview

2.1 Introduction

Although EFM32 and EFR32 Wireless Gecko Series 1 devices have low average current consumption, proper decoupling is critical. Digital circuits draw current in short pulses corresponding to clock edges. Simultaneous I/O switching can cause transient current pulses of several hundred mA for nanoseconds, necessitating decoupling capacitors to supplement current during these short transients and reduce noise.

2.2 Decoupling Capacitors

Decoupling capacitors minimize the current loop between the supply, MCU, and ground for high-frequency transients. They should be placed as close as possible to power supply pins, ground pins, and PCB ground planes. External decoupling capacitors should be rated for the operating environment's temperature range, such as X5R ceramic capacitors for -55 to +85 °C or -55 to +125 °C. For regulator output capacitors, pay attention to temperature and bias voltage characteristics, as capacitance can decrease significantly, potentially causing output instability.

2.3 Power Supply Requirements

System designers must ensure that voltage requirements and dependencies between power supply pins are met. Refer to the device datasheet for absolute maximum ratings and system voltage constraints.

EFM32 Series 1 Power Supply Requirements:

• VREGVDD = AVDD (Must be the highest voltage in the system)
• VREGVDD >= DVDD
• VREGVDD >= IOVDD
• DVDD >= DECOUPLE

EFR32 Wireless Gecko Series 1 Power Supply Requirements:

• VREGVDD = AVDD (Must be the highest voltage in the system)
• VREGVDD >= DVDD
• VREGVDD >= PAVDD (For 2.4GHz or Dual band devices, PAVDD refers to the device pin. For sub-GHz devices, PAVDD refers to the external power amplifier supply)
• VREGVDD >= RFVDD
• VREGVDD >= IOVDD
• DVDD >= DECOUPLE

2.3.1 Power Supply Pin Overview

The table below provides an overview of available power supply pins. Note that not all pins exist on all devices.

2.4 DECOUPLE

All EFM32 and EFR32 Wireless Gecko Series 1 devices have an internal linear regulator for core and digital logic. The DECOUPLE pin is the output of this Digital LDO and requires a 1 µF capacitor. System designers must carefully consider capacitor characteristics over temperature and bias voltage, as capacitance reduction can lead to output instability.

2.4.1 EFM32xG1 and EFR32xG1 DECOUPLE Pin

On these devices, DVDD is the input supply to the Digital LDO, and DECOUPLE is the output. A diagram illustrates this configuration, showing the main supply connected to DVDD via a 0.1 µF capacitor, and DVDD feeding the Digital LDO, whose output is DECOUPLE, connected to Digital Logic and a 1 µF capacitor.

2.4.2 EFM32xG11/12 and EFR32xG12/13/14 DECOUPLE Pin

On these devices, the Digital LDO input is either AVDD (default) or DVDD. DECOUPLE is the output. When powered from AVDD, the Digital LDO current is limited to 20 mA. Firmware should configure EMU_PWRCTRL_REGPWRSEL to power the LDO from DVDD after startup. A diagram shows this configuration, including the option to select AVDD or DVDD as the input via REGPWRSEL.

2.5 IOVDD

The IOVDD pin(s) provide decoupling for GPIO pins. A 0.1 µF capacitor per IOVDD pin is recommended, along with a 10 µF bulk capacitor. The bulk capacitor can be reduced if other large capacitors are present on the same supply. A diagram illustrates this decoupling scheme.

Note: IOVDD should not be supplied from the DC-DC converter on EFM32xG11/12 and EFR32xG12/13/14 devices. At reset, the DC-DC converter defaults to an unconfigured state, potentially preventing bootloader communication without IOVDD power.

2.6 AVDD

Analog peripheral performance depends on AVDD quality. A simpler decoupling scheme is acceptable for less demanding applications, while robust decoupling and filtering are needed for high-quality analog performance. The number of AVDD pins varies by device and package.

2.6.1 AVDD Standard Decoupling

A standard approach includes one 10 µF bulk capacitor (CAVDD) and one 10 nF capacitor per AVDD pin. A diagram illustrates this configuration.

2.6.2 AVDD Improved Decoupling

An improved approach adds a ferrite bead and a 1 Ω resistor for additional filtering and isolation. A diagram shows this enhanced setup. The document also lists recommended ferrite bead part numbers from Würth Electronics and Murata, detailing impedance, current rating, DCR, temperature range, and package size.

2.7 USB (VREGI & VREGO)

Some devices integrate a USB controller and a 3.3V LDO. Decoupling, signaling, and control signals are discussed in Section 6 (USB).

2.8 DC-DC

Onboard DC-DC converters improve power efficiency but introduce switching noise requiring additional filtering. Configurations are described for when the DC-DC converter is unused, and when it is used to power DVDD (and potentially RFVDD and PAVDD on EFR32 devices). Detailed diagrams and notes on capacitor selection (e.g., 4.7 µF vs 1.0 µF for CDCDC) are provided.

2.9 Radio (RFVDD & PAVDD) -- EFR32 Wireless Gecko Series 1

Radio power supplies (PAVDD and RFVDD) can be powered from the integrated DC-DC converter (for improved efficiency, up to 13 dBm transmit power) or the main supply (less efficient, supports > 13 dBm transmit power).

2.9.1 RFVDD and PAVDD -- Powered from DC-DC

This configuration is for lowest power operation. Maximum transmit power is limited to 13 dBm. A diagram shows decoupling components for 2.4 GHz and sub-GHz applications, including tables for decoupling values and recommended inductors.

2.9.2 RFVDD and PAVDD -- Powered from Main Supply

Used when greater than 13 dBm transmit power is required. PAVDD connects to the main supply, while RFVDD can use either the main supply or DC-DC output. A diagram illustrates this setup, with a table for decoupling values.

3. Example Power Supply Configurations

This section illustrates typical configurations for EFM32 and EFR32 Wireless Gecko Series 1 devices.

3.1 EFM32 and EFR32 Wireless Gecko Series 1 Configuration after POR

3.1.1 EFM32xG1 and EFR32xG1 Startup Configuration

During power-on reset (POR), these devices boot in a safe startup configuration with the DC-DC converter's bypass switch on (VREGVDD to DVDD) and analog blocks powered from AVDD. Firmware can reconfigure the device post-startup. A diagram shows this configuration.

3.1.2 EFM32xG11/12 and EFR32xG12/13/14 Unconfigured Configuration

Upon POR or entry into EM4 Shutoff, these devices enter a safe state with the DC-DC converter's bypass switch off. The internal digital LDO is powered from AVDD (limited to 20 mA); firmware should switch it to DVDD using REGPWRSEL=1. Analog blocks are powered from AVDD. A diagram illustrates this configuration.

3.2 EFR32 Wireless Gecko Series 1--No DC-DC, 2.4 GHz, <= 13 dBm Example

For space- or cost-sensitive applications where power efficiency is less critical, the DC-DC converter can be unused. In this setup, the converter is off, bypass switch is off, DVDD is externally powered (typically from the main supply), and powers the digital LDO. RFVDD, PAVDD, IOVDD, and AVDD connect to the main supply. VREGSW is disconnected. Diagrams show configurations for EFR32xG1 and EFR32xG12/13/14 devices.

3.3 EFR32 Wireless Gecko Series 1--DC-DC, 2.4 GHz, ≤ 13 dBm Example

This configuration uses the DC-DC converter to maximize power savings. The DC-DC output (VDCDC) powers DVDD (and thus the digital LDO), RFVDD, and PAVDD. AVDD and IOVDD are connected to the main supply. Diagrams illustrate this for EFR32xG1 and EFR32xG12/13/14 devices. Notes discuss the CDCDC capacitor value (4.7 µF recommended).

3.4 EFR32 Wireless Gecko Series 1--DC-DC, 2.4 GHz, > 13 dBm Example

For high power (>13 dBm) radio output, PAVDD connects to the main supply. The DC-DC converter can continue to power DVDD and RFVDD. Diagrams illustrate this for EFR32xG1 and EFR32xG12/13/14 devices.

3.5 EFM32 Series 1--DC-DC Example

This configuration uses the DC-DC converter to power DVDD. AVDD and IOVDD are connected to the main supply. Diagrams illustrate this for EFM32xG1 and EFM32xG11/12 devices. Notes discuss the CDCDC capacitor value.

4. Debug Interface and External Reset Pin

4.1 Serial Wire Debug

The Serial Wire Debug (SWD) interface uses SWCLK (clock) and SWDIO (data in/out) pins, optionally SWO (serial wire output) for trace. Connections to a standard ARM 20-pin debug header are shown. The Vtarget pin provides a reference voltage, not power. PF2 is the default location for SWO.

4.2 JTAG Debug

EFM32 and EFR32 Wireless Gecko Series 1 devices optionally support JTAG debug using TCLK, TDI, TDO, and TMS pins. The JTAG implementation does not support boundary scan testing but can operate in pass-through mode. Connections to an ARM 20-pin debug header are shown. The Vtarget pin provides a reference voltage, not power.

4.3 External Reset Pin (RESETn)

Processors are reset by driving the RESETn pin low. An internal pull-up holds the pin high. A low-pass filter prevents noise glitches. The internal pull-up ensures reset release. Care must be taken when the device is unpowered to avoid back-powering other devices via an external pull-up on RESETn.

5. External Clock Sources

5.1 Introduction

Devices support external clock sources (oscillators, crystals, ceramic resonators) for high and low frequency clocks, in addition to internal RC oscillators. Refer to AN0016.2: Oscillator Design Considerations for more details.

5.2 Low Frequency Clock Sources

An external low-frequency clock can be supplied from a crystal/ceramic resonator or an external clock source (e.g., TCXO, VCXO). The crystal/resonator connects across the LFXTAL_N and LFXTAL_P pins. On Series 1 devices, on-chip load capacitors are used, tuned via software. External clock signals should meet specific frequency, aging, stability, and signal level requirements. A diagram shows the connection for low-frequency external clocks.

5.3 High Frequency Clock Sources

High-frequency clocks can be sourced from a crystal/ceramic resonator or an external square/sine wave source. Crystals connect across the HFXTAL_N and HFXTAL_P pins. On Series 1 devices, on-chip load capacitors are used. The frequency range is typically 38-40 MHz, but consult the datasheet for specific device ranges. A table details high-frequency external clock input options for various devices, indicating pin limitations and clock type selection. A diagram shows the connection for high-frequency external clocks.

6. USB

Some EFM32 Series 1 devices integrate a USB controller and a 3.3V LDO. Total capacitance on VUSB should not exceed 10 µF. Consult AN0046: USB Hardware Design Guide for detailed guidance.

6.1 USB Self-Powered

In this configuration, an external 1.8V to 3.8V supply powers the system, while the internal 3.3V regulator powers the USB PHY (3.0V to 3.6V required). VREGI may be left floating. A diagram illustrates this setup.

6.2 USB Bus-Powered

The USB 5V supply powers the internal 3.3V regulator, which in turn supplies the USB PHY and the EFM32 Series 1. VREGI may be left floating. A diagram illustrates this setup.

6.3 USB Dual-Powered

This configuration allows switching between a battery/external supply (on VREGI) and the USB 5V supply (on VBUS) for the 3.3V LDO. Firmware selects the higher of the two inputs. VREGI and VBUS inputs are pulled down if unused. A diagram illustrates this setup.

6.4 USB Host

A typical host configuration uses an external 5V step-up regulator. The internal 3.3V LDO is unused, and VREGO is driven by an external 3.0V to 3.6V source. VBUS is used for 5V detection. VREGI may be left floating. Minimum USB 5V decoupling capacitance is 120 µF. A diagram illustrates this setup.

7. Backup Power Domain

7.1 Overview

Giant Gecko and Tiny Gecko devices can be partly powered by a backup battery. This powers a dedicated domain including the RTCC and its 128 bytes of retention registers, and the CRYOTIMER. Upon main power loss, the system enters EM4 Hibernate and switches to the backup supply. Power supply relationship requirements (e.g., IOVDD <= AVDD) must be maintained.

7.2 Connections

The backup domain interface has three pins: BU_VIN (backup supply input), BU_VOUT (output to external devices), and BU_STAT (status indicator). These pins share GPIO functionality and require specific configuration. Allowable backup sources include batteries and supercapacitors. External circuitry can be connected to BU_VOUT. It is imperative that such circuits are electrically isolated from the rest of the system when not in backup mode to prevent back-powering and rapid depletion of the backup supply. A diagram illustrates the backup power domain connections.

8. Revision History

This section lists revisions and changes made to the document:

• Revision 1.53 (December, 2019): Added reference to AN958; corrected typos.
• Revision 1.52 (August, 2018): Updated USB_DP/DM series resistance.
• Revision 1.51 (May, 2018): Clarified PAVDD pin function for 2.4 GHz amplifier.
• Revision 1.50 (January, 2018): Removed EFM32JG13/PG13 compatibility; reworded decoupling capacitor note.
• Revision 1.49 (September, 2017): Added references to EFR32xG14, EFM32TG11; added backup domain section; revised High Frequency External Clocks section.
• Revision 1.48 (June, 2017): Added reference to EFM32GG11; added VBUS to overview; renamed USB pins; added USB section.
• Revision 1.47 (January, 2017): Split application note; updated content for G11/G12/G13/G14 devices; changed default DCDC capacitor to 4.7 µF; added note on capacitor characteristics.

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