EFR32 Series 2 Layout Design Guide for Optimal RF Performance

Introduction

The purpose of this application note is to help users design Printed Circuit Boards (PCBs) for the EFR32 Wireless Gecko Portfolio using design practices that allow for good Radio Frequency (RF) performance.

Key related application notes include:

AN930.2: EFR32 Series 2 2.4 GHz Matching Guide (for matching principles)
AN0918.2: Series 1 to Wireless Gecko Series 2 Compatibility and Migration Guide
AN0948: Power Configurations and DC-DC
AN0955: CRYPTO
AN958: Debugging and Programming Interfaces for Custom Designs (for connector interface details)

Silicon Labs' MCU and Wireless Starter Kits, along with Simplicity Studio, offer a powerful development and debug environment. For custom hardware designs, Silicon Labs recommends including debugging and programming interface connectors to leverage these capabilities.

The power configurations of EFR32 devices are detailed in AN0002.2: EFR32 Wireless Gecko Series 2 Hardware Design Considerations. RF performance is significantly influenced by PCB layout and matching network design. For optimal results, Silicon Labs recommends adhering to the PCB layout design guidelines presented in the following sections.

KEY POINTS

Provides a reference schematic and PCB layout
Lists and describes all main design principles
Provides a summary checklist of all design principles

1. Device Compatibility

This application note supports the following devices:

EFR32 Series 2:

EFR32 Mighty Gecko (EFR32MG21)
EFR32 Blue Gecko (EFR32BG21)

2. Design Recommendations When Using EFR32 Series 2 Wireless MCUs

Extensive testing has been conducted using reference designs provided by Silicon Labs. It is recommended that designers utilize these reference designs as-is to minimize detuning effects caused by parasitics or poor component placement and PCB routing. EFR32 reference design files are accessible within Simplicity Studio under the Kit Documentation tab.

The compact RF part of the designs (excluding the 50 Ω single-ended antenna) is highlighted by a blue frame. It is strongly advised to replicate this framed RF layout to prevent detuning effects. The figure below illustrates this framed compact RF part.

Figure 2.1. Top Layer of the BRD4180A Radio Board (Left Side) and Assembly Drawing of the RF Part (Right Side). This figure shows the physical layout of the RF components on a PCB, with a specific section highlighted, and a separate diagram detailing the assembly of the RF components.

The layout of the MCU VDD filtering capacitors should also be closely followed from the reference design. If deviations are necessary due to PCB size or shape limitations, the layout design rules described in subsequent sections should be applied.

2.1 Matching Network Types for the 2.4 GHz EFR32 Series 2 Wireless MCU

The 2.4 GHz EFR32 Series 2 wireless MCU can deliver a maximum of +20 dBm power. All 2.4 GHz EFR32 Series 2 reference designs employ a parallel-C series-L ladder structured matching network. For low-power applications (≤10 dBm), a 3-element C-L-C network is sufficient, while high-power solutions (>10 dBm) require a 5-element match.

The antenna and radio interface schematic for the 10 dBm BRD4181A Radio Board is shown below.

Figure 2.2. Schematic of the RF Section for the 10 dBm BRD4181A Radio Board (Matching Network is Highlighted). This schematic depicts the RF circuitry, including the EFR32 MCU, crystal, and matching components, with the matching network emphasized.

The antenna and radio interface schematic for the 20 dBm BRD4180A Radio Board is shown below.

Figure 2.3. Schematic of the RF Section for the 20 dBm BRD4180A Radio Board (Matching Network is Highlighted). This schematic illustrates the RF circuitry for a higher-power board, also highlighting the matching network.

The increased TX output power of EFR32 devices is associated with a higher level of harmonic signals. Regulatory standards (e.g., FCC, ETSI, ARIB) mandate the attenuation of harmonic signals below specific power levels. Consequently, more extensive low-pass filtering is generally required for RF radio boards using EFR32 devices designed for higher output power.

All 2.4 GHz EFR32 Series 2 radio boards feature a 50 Ω Inverted-F Antenna (IFA) connected to the 50 Ω output of the matching network for radiated performance measurements. Conducted measurements can be performed using an U.FL connector.

An additional component (L3) is present near the antenna, which is not part of the primary matching network. For custom designs, it is recommended to include this series element for additional harmonic suppression, with a default value of 0 Ω.

The IFA PCB antenna on these boards is optimized for 50 Ω impedance without an external discrete antenna matching network. For flexibility, a 3-element pi-structure antenna matching network between L3 and the antenna is recommended for custom designs.

Note: If both RF pins (RF2G4_IO1 and RF2G4_IO2) are utilized, their matches can couple and detune each other. The ideal scenario is for only one pin to be populated.

Further details on EFR32 Series 2 2.4 GHz matching network principles can be found in application note AN930.2: EFR32 Series 2 2.4GHz Matching.

3. Guidelines for Layout Design When Using EFR32 Series 2 Wireless MCUs

General guidelines for designing RF-related layouts for good RF performance include:

PCB Layers: For custom designs, match the number of PCB layers to the reference design. If layer count must differ, ensure the distance between the top and first inner layers is similar to the reference design, as this distance affects parasitic capacitance to ground. Deviations may require fine-tuning component values.
Ground Plane: Utilize continuous and unified ground plane metallization, especially on the top and bottom layers. Avoid separating ground planes, particularly between the matching network ground and the RFIC GND pins/exposed pad.
Grounding Vias: Employ as many grounding vias as possible, especially near GND pins, to minimize series parasitic inductance between ground pours and GND pins across layers.
Stitching Vias: Use a series of GND stitching vias along PCB edges and internal GND metal pouring edges. The maximum distance between vias should be less than lambda/10 of the 10th harmonic (typically 40-50 mil on reference boards) to reduce PCB radiation at higher harmonics caused by fringing fields.
Inner Layers: For designs with more than two layers, route most traces (including digital traces) on inner layers. Ensure large, continuous GND pours on the top and bottom layers.
Transmission Lines: Avoid long and/or thin transmission lines for RF components to prevent detuning effects from distributed parasitic inductance. Shorten interconnection lines to reduce parallel parasitic capacitance to ground, though this may increase coupling between discretes.
Tapered Lines: Use tapered transmission lines with varying widths (different impedance) to minimize internal reflections.
Loops and Wires: Avoid loops and long wires to prevent resonances and unwanted radiation, especially at harmonics.
VDD Filtering: Always ensure good VDD filtering with bypass capacitors, ideally with self-resonance close to the operating frequency. The capacitor filtering the highest frequency should be closest to the VDD pins. Filter fundamental frequency, crystal/clock frequency, and its harmonics (up to the 3rd) to avoid up-converted spurs.
Crystal Grounding: Connect the crystal case to ground using multiple vias to prevent radiation from ungrounded parts. Avoid leaving any metal unconnected or floating. Do not route supply traces close to or beneath the crystal or parallel to crystal signal traces.
GPIO Routing: Avoid routing GPIO lines close to or beneath RF lines, antennas, or crystals, or parallel to crystal signals. Use the lowest slew rate possible on GPIO lines to minimize crosstalk.
VDD Traces: Keep VDD traces as short as possible. Simplify VDD routing and use large, continuous GND pours with many stitching vias. Avoid star topology for VDD traces.
Silkscreen: Avoid placing silkscreen near the antenna, as it can slightly affect the antenna's dielectric environment.

3.1 Layout for the 2.4 GHz EFR32 Series 2 Wireless MCU Based on BRD4180A 20 dBm Radio Board

The layout design concepts presented here are based on the 20 dBm BRD4180A Radio Board. These principles apply to both 5-element and 3-element matching networks.

The layout structure for the RF part of the BRD4180A Radio Board is shown below.

Figure 3.1. Layout of the RF Section for the BRD4180A Radio Board (Top Layer). This diagram displays the physical arrangement of the EFR32 IC, RF crystal, 5-element matching network, and RFVDD/PAVDD filtering components on the top layer of the PCB.

3.1.1 Layout Design Guidelines for the 2.4 GHz EFR32 Series 2 Wireless MCU

C1 Capacitor Placement: Place the C1 capacitor as close as possible to the corresponding TX/RX pin (RF2G4_IO1 or RF2G4_IO2) of the EFR32 IC to minimize series parasitic inductance and prevent detuning.
Component Proximity: Position neighboring matching network components closely together to minimize PCB parasitic capacitance to ground and series parasitic inductances between components.
Capacitor Orientation: While rotating harmonic filtering capacitors on opposite sides of the transmission line can improve harmonic performance in some cases, validation for EFR32 Series 2 showed this increases harmonic levels. Therefore, connect nearby shunt capacitors in the matching network to the same side of the transmission line.
Shunt Capacitor Grounding: Connect shunt capacitors in the matching network directly to the Layer 2 ground plane using ground vias. Avoid connecting ground pins to the common ground metal on the Top Layer for optimal harmonic performance.
Trace Thickness: Thicken traces near GND pins of capacitors to enhance grounding effects in thermal straps, minimizing series parasitic inductances.
Unused RF Pins: The 2.4 GHz EFR32 Series 2 chip has two equivalent single-ended TX/RX inputs. If only one is used, connect the other directly to the exposed pad ground. Do not connect the unused pin to the common top layer ground to avoid increasing harmonic levels.
RFGND Pin: For better harmonic performance, connect pin 11 (RFGND) directly to the exposed pad ground, not to the common top layer ground.
GND Separation: Maintain at least 0.3 mm separation between traces/pads and the adjacent GND pour in the matching network area to minimize parasitic capacitance and reduce detuning.
Series Inductor Placement: Place series matching/filtering inductors one after another or perpendicular to each other to reduce coupling between stages.

The figure below demonstrates these layout design recommendations on the BRD4180A Radio Board.

Figure 3.2. Matching Network Layout Guidelines on BRD4180A (Top Layer). This diagram highlights key layout practices, including component proximity, capacitor placement relative to TX/RX pins, connection of capacitors to the ground layer, and grounding of unused RF pins.

VDD Bypass Capacitors: Keep lower-value VDD bypass capacitors (~pF values) as close as possible to the VDD pins (RFVDD, PAVDD, AVDD, DVDD, IOVDD).
Ground Connection for VDD Filtering: Ensure good ground connection for all VDD filtering capacitors by using vias close to their ground pins. The GND return path from these vias to the RFIC paddle's GND vias should be unobstructed, allowing a clear pathway through the GND plane.
Exposed Pad Vias: The exposed pad footprint for the EFR32's paddle should incorporate as many vias as possible to ensure robust grounding and heat sink capability. Reference designs typically use 9 vias, each 10 mil in diameter.
RF Crystal Placement: Position the RF crystal as close as possible to the HFXTAL_I and HFXTAL_O pins of the EFR32 IC to minimize parasitic capacitances from wiring and potential frequency offsets.
RF Crystal Grounding: Connect the ground pins of the RF crystal directly to the first inner layer ground plane using ground vias. Avoid connecting them to the common ground metal on the Top Layer.

The figure below demonstrates these layout design recommendations on the BRD4180A Radio Board.

Figure 3.3. VDD filtering, RF Crystal and Exposed Pad Ground Layout Guidelines on BRD4180A (Top Layer, Inner Layer 1). This figure illustrates optimal placement and grounding for VDD filtering capacitors, the RF crystal, and the exposed pad, emphasizing connections to the ground plane and inner layers.

RF Ground: To achieve good RF ground, use large, continuous GND metallization on the top layer in the RF section. Ideally, this should extend across the entire PCB. Ensure RF voltage potentials are equal across the GND area for effective VDD filtering. Fill gaps in GND metal and connect top and bottom layers with vias.
Inner Layer Ground: The area beneath the RF chip and matching network on the first inner layer should be filled with continuous ground metal to provide a good ground reference and a low-impedance return path to the RF chip's ground. Avoid routing wires in this region to prevent coupling effects with the matching network. Ensure the GND return path between the matching network's GND vias and the RFIC paddle's GND vias is unobstructed.
Isolating Ground Metal: Use isolating ground metal between the crystal and RFVDD traces to prevent detuning effects on the crystal from nearby power supplies and to prevent leakage of crystal/clock signals and their harmonics to supply lines.

Figure 3.4. Ground connection Layout Guidelines on BRD4180A (Top Layer, Inner Layer 1). This diagram shows ground connection strategies, including continuous GND beneath the matching network and isolating ground metal between the crystal and RFVDD traces.

Grounding Vias at Edges: Use as many parallel grounding vias as possible at GND metal edges, particularly at the PCB edge and along VDD traces, to reduce harmonic radiation caused by fringing fields.

Figure 3.5. GND Vias at PCB Edges on BRD4180A Radio Board. This illustration highlights the placement of GND vias at the PCB edges for improved grounding and reduced harmonic radiation.

Shielding Cap: If necessary, a shielding cap can be used to shield harmonic radiations from the PCB, covering all RF-related components except the antenna.
Ideal Layer Consistency (for PCBs > 2 layers):
- Top layer: Maximize continuous solid GND metallization with many vias.
- First inner layer: Use continuous, unified GND metallization beneath the RF part; route wires beneath non-RF parts if needed.
- All other inner layers: Route as many supply and digital traces as possible.
- Bottom layer: Use unified GND metal; route traces only if necessary.

The following figure illustrates layer consistency on the BRD4180A Radio Board layout.

Figure 3.6. Layer Consistency on BRD4180A Radio Board. This figure visually compares the layout of the Top, Inner 1, Inner 2, and Bottom layers of the BRD4180A Radio Board, showing the distribution of GND planes and traces.

Trace Routing: Route supply and digital traces on inner layers for boards with more than two layers.
Supply Line Placement: Avoid placing supply lines close to the PCB edge.
50 Ω Lines: To reduce sensitivity to PCB thickness variations, use 50 Ω grounded coplanar lines for connecting the antenna or U.FL connector to the matching network. This also reduces radiation and coupling effects. A general rule is to use 50 Ω transmission lines where the RF trace length exceeds λ/16 at the fundamental frequency.

3.2 Transmission Line Considerations

Interconnections between components are not considered transmission lines if their lengths are much shorter than the wavelength, making their impedances less critical. For these connections, the trace width should match the pad width of the components to prevent reflections at pad-trace transitions and minimize parasitic capacitances to ground. Examples of trace dimensions are provided in the table below.

Use numerous vias near coplanar lines to minimize radiation.

The figure below demonstrates 50 Ω grounded coplanar lines on the Dual-band Reference Radio Board layout.

Figure 3.7. 50 Ω Grounded Coplanar Lines on BRD4180A Radio Board. This image shows the layout of 50 Ω coplanar lines connecting the PA matching to the antenna matching and to the U.FL connector.

Table 3.1. Parameters for 50 Ω Grounded Coplanar Lines
Lines	Parameters
f	2.4 GHz
T	0.018-0.035 mm
er	4.6
H	0.3 mm
G	0.25 mm
W	0.45 mm

Note:

Characteristic impedance is not highly sensitive to the gap value; a gap between 0.25 mm and 0.4 mm typically yields 47-53 Ω impedance.
Different impedance calculators may produce slightly different results.
H represents the distance between the top and the first inner layer.

Figure 3.8. Grounded Coplanar Line Parameters. This diagram illustrates the physical dimensions (H, G, W) related to grounded coplanar line parameters.

4. Checklists

4.1 Main Layout Design Principles

Is the number of PCB layers the same as in the reference design? Or, at a minimum, is the distance between the top and first inner layers similar?
Are the neighboring matching network components placed as close to each other as possible?
Is the trace width (near) the same as the pad width for connecting nearby components?
Are the series matching/filtering inductors placed one after another or perpendicular to each other?
Is the RF crystal placed as close to the XTAL pins of the EFR32 IC as possible?
Does ground metal exist between the crystal and the RFVDD feed?
Are the smallest value VDD filtering capacitors kept as close as possible to the VDD pins (RFVDD, PAVDD, AVDD, DVDD, IOVDD) of the EFR32?
Do the ground pins of the shunt capacitors use multiple vias close to these pins?
Does the exposed pad footprint use multiple vias?
Is there at least 0.3 mm separation between the traces/pads and the GND metal in the matching area?
Is wiring and routing avoided on the first inner (GND) layer between the grounding vias of VDD filtering capacitors and the exposed pad of the EFR32 IC?

(Refer to figures on pages 11 and 12 for visual examples of these principles.)

Are supply and digital traces routed on inner layers? Or, at a minimum, are supply lines surrounded by ground metal with many GND vias if routed on the top or bottom layers?
Is placing supply or digital lines close to the PCB edge avoided?
Is large, continuous GND metallization added to at least the RF sections, using as many GND vias as possible?
Are the GND metal edges closed by "stitching vias" where possible, with a via distance less than λ/10 of the highest (usually 10th) critical harmonic frequency?
Are 50 Ω grounded coplanar lines used for RF traces longer than λ/16 at the fundamental frequency?
Are there vias at the ground metallization near the 50 Ω transmission lines?

(Refer to figures on pages 12 and 13 for visual examples of these principles.)

4.2 Additional Concerns for the Matching Network

Is the first matching network component (C1) placed as close to the corresponding TX/RX pin as possible?
Are the nearby harmonic filtering capacitors connected to ground planes on the same sides of the transmission line?
Are shunt capacitors in the matching network connected directly to the first inner layer (common ground)? Is connecting the ground pins to the common ground metal on the Top Layer avoided?
Are the unused TX/RX pin and RFGND pin connected directly to the exposed pad ground? Is connecting those to the common top layer ground avoided?
Is the area on the first inner layer beneath the RF chip and the matching network filled with continuous GND metal, and was wiring and routing avoided in this region?

(Refer to figures on page 13 for visual examples of these principles.)

5. Revision History

Revision 0.1

March, 2019

Initial release.

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Silicon Labs provides documentation intended to be accurate and up-to-date for its products. Characterization data, modules, peripherals, memory sizes, and addresses are specific to each device, and typical parameters may vary. Application examples are for illustrative purposes only. Silicon Labs reserves the right to make changes to product information without notice and does not guarantee completeness or accuracy. Firmware updates may occur during manufacturing for security or reliability, without altering specifications or performance. Silicon Labs is not liable for consequences arising from the use of this document. This document does not grant licenses for integrated circuits. Products are not authorized for use in FDA Class III devices, applications requiring FDA premarket approval, or Life Support Systems without written consent. Life Support Systems are defined as products or systems intended to support or sustain life/health, where failure could result in significant injury or death. Silicon Labs products are not authorized for military applications or for use in weapons of mass destruction (nuclear, biological, chemical weapons, or missiles). Silicon Labs disclaims all warranties and is not responsible for injuries or damages related to unauthorized applications.

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AN928.2: EFR32 Series 2 Layout Design Guide