Versal ACAP AIE-ML Architecture Manual: A Comprehensive Guide

Introduction to Versal ACAP

Versal^® adaptive compute acceleration platforms (ACAPs) integrate Scalar Engines, Adaptable Engines, and Intelligent Engines with advanced memory and interfacing technologies. Built on TSMC 7 nm FinFET process technology, Versal ACAPs offer a unique combination of software programmability and domain-specific hardware acceleration, catering to the rapid pace of innovation across various markets.

The architecture features a heterogeneous mix of processing units, including Arm^® Cortex^®-A72 and Cortex-R5F processors, alongside specialized AI Engines optimized for machine learning inference and signal processing. The AIE-ML series specifically targets AI performance per watt for real-time systems, enhancing applications in areas like automated driving, industrial automation, and aerospace.

For more information on the Versal architecture, visit Xilinx Versal Documentation.

AIE-ML Architecture Overview

The AIE-ML array is a core component of the Versal ACAP, comprising a two-dimensional array of AIE-ML tiles, AIE-ML memory tiles, and specialized interface tiles. Each AIE-ML tile features a VLIW SIMD vector processor, integrated memory, and robust interconnects for streaming, configuration, and debugging.

Memory tiles provide high-density, high-bandwidth memory to offload processing logic, crucial for machine learning workloads. The AIE-ML array interface facilitates communication with the rest of the Versal device via the Network on Chip (NoC) or directly with Programmable Logic (PL).

Key Features and Capabilities

AIE-ML Tile Features: Includes a VLIW SIMD vector processor, 64 KB data memory, streaming interconnect, DMA, hardware synchronization primitives, and debug/trace/profile functionality.
AIE-ML Memory Tile Features: Offers 512 KB of memory, supporting advanced DMA capabilities and AXI4-Stream interconnects.
Performance: AIE-ML array targets up to 1 GHz clock speed for the -1L speed grade devices, with specific clock domains for NoC and PL interfaces.
Memory Error Handling: Implements ECC and parity protection for program and data memory to ensure data integrity.

Document Navigation

This manual is structured to guide users through different design processes, including System and Solution Planning and AI Engine Development. Key chapters cover the AIE-ML tile architecture, array interface, processor functionality, memory tile architecture, and configuration/boot sequences.

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Introduction to Versal ACAP

AIE-ML Architecture Overview

Key Features and Capabilities

Document Navigation

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