Allegro MicroSystems | Innovation with Purpose
Datasheet for Allegro MicroSystems models including: A4409, Allegro, Allegro MicroSystems, buck regulator, buck-boost regulator, pre-regulator, LDO, window watchdog timer, NPOR, automotive, AEC-Q100, power management IC, voltage regulator
A4409: Buck or Buck-Boost Pre-Regulator w/ Synchronous Buck
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DocumentDocumentA4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR FEATURES AND BENEFITS · Automotive AEC-Q100 qualified · VIN operating range from 3 to 36 V, with 40 V maximum · Buck or buck-boost pre-regulator (VREG) · Adjustable PWM switching frequency: 250 kHz to 2.4 MHz · PWM frequency can be synchronized to external clock · Two 5 V internal LDO regulators with foldback short- circuit protection · Power-on reset (NPOR) with fixed delay of 22.5 ms · Programmable window watchdog timer with a fixed activation delay of 30 ms · Active low, watchdog timer enable/disable pin (WDENn) · Dual bandgaps for increased reliability: BG1 for VREG, 5V0, and VCP reference BG2 for V5 reference, and VREG, 5V0, and VCP fault detection · Ignition-enable input (ENBAT) · Frequency dithering helps reduce EMI/EMC · Undervoltage protection for all output rails · Pin-to-pin and pin-to-ground tolerant at every pin · Thermal shutdown protection · -40°C to 150°C junction temperature range DESCRIPTION The A4409 is a power management IC that uses a buck or buck-boost pre-regulator to efficiently convert automotive battery voltages into a tightly regulated intermediate voltage, complete with control, diagnostics, and protections. The output of the pre-regulator supplies a 5 V, 300 mAMIN LDO and a 5 V, 200 mAMIN LDO. Designed to supply CAN or microprocessor power supplies in high-temperature environments, the A4409 is ideal for underhood applications. Enable-input to the A4409 is compatible to a high-voltage battery level (ENBAT). Diagnostic outputs from the A4409 include a power-on-reset output (NPOR) with a fixed 22.5 ms typical delay. Dual bandgaps, one for regulation and one for fault checking, improve long-term reliability of a system designed around the A4409. The A4409 contains a window watchdog timer that can be programmed to accept a wide range of clock frequencies (WDADJ). The watchdog timer has a fixed 30 ms activation delay to accommodate processor startup. The watchdog timer has an enable/disable pin (active low, WDENn) to facilitate initial factory programming or field reflash programming. Continued on next page... PACKAGE: 20-Pin eTSSOP (suffix LP) Not to scale APPLICATIONS Provides system power for (microcontroller/DSP, CAN, sensors, etc.) in automototive control modules, such as: · Electronic power steering (EPS) · Transmission control units (TCU) · Advanced braking systems (ABS) · Emissions control modules · Other automotive applications A4409-DS, Rev. 9 MCO-0000318 6.6 V (VREG) Buck-Boost Pre-Regulator 5 V LDO (V5) with Foldback Protection 5 V LDO (5V0) with Foldback Protection Bandgap 1 Bandgap 2 Charge Pump Thermal Shutdown (TSD) NPOR Output Programmable Window Watchdog Timer with Activation Delay A4409 Simplified Block Diagram April 6, 2022 A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR DESCRIPTION (continued) Protection features include dual control loop for pre-regulator rail. In case of a shorted output, all linear regulators feature foldback overcurrent protection. The switching regulator includes pulseby-pulse current limit, hiccup mode short-circuit protection, LX short-circuit protection, missing asynchronous diode protection, and thermal shutdown. The A4409 is supplied in a low-profile (1.2 mm maximum height), 20-lead eTSSOP package (suffix "LP") with exposed thermal pad. SELECTION GUIDE Part Number A4409KLPTR-T Temp. Range 40°C to 150°C [1] Contact Allegro for additional packing options. Package 20-pin eTSSOP with thermal pad Packing [1] 4000 pieces per 13-in. reel Lead Frame 100% Matte Tin ABSOLUTE MAXIMUM RATINGS[2] Characteristic Symbol VIN pin VIN ENBAT pin VENBAT IENBAT Notes With current limiting resistor [3] LX pin VCP, CP1, and CP2 pins All other pins Junction Temperature Storage Temperature Range VLX VVCP, VCPx t < 250 ns t < 50 ns TJ TS Rating Unit -0.3 to 40 V -0.3 to 8 V -13 to 40 V ±75 mA -0.3 to VIN + 0.3 V -1.5 V VIN + 3 V -0.3 to 50 V -0.3 to 7.5 V -40 to 150 °C -55 to 150 °C [2] Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. [3] The higher ENBAT ratings (13 V and 40 V) are measured at node "A" in the following circuit configuration: Node "A" 450 VENBAT + - ENBAT A4409 GND THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information Characteristic Symbol Test Conditions [4] Value Junction-to-Ambient Thermal Resistance RJC eTSSOP-20 (LP) Package 32 Unit °C/W [4] Additional thermal information available on the Allegro website. 2 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR Table of Contents Features and Benefits 1 Description 1 Applications 1 Package 1 Simplified Block Diagram 1 Selection Guide 2 Absolute Maximum Ratings 2 Thermal Characteristics 2 Functional Block Diagram 4 Pinout Diagram and Terminal List Table 5 Electrical Characteristics 6 General Specification 6 Buck and Buck-Boost Pre-Regulator Specifications 7 Linear Regulator (LDO) Specifications 9 Control Inputs 10 Diagnostic Outputs 11 Window Watchdog Timer (WWDT) 13 Timing Diagrams 17 Design and Component Selection 21 Setting Up the Pre-Regulator 21 Soft Start and Startup 21 Charge Pump Capacitors 21 PWM Switching Frequency 21 Pre-Regulator Output Inductor (L1) 21 Pre-Regulator Output Capacitors 22 Ceramic Input Capacitors 22 Buck-Boost Asynchronous Diode (D1) 23 Boost MOSFET (Q1) 23 Boost Diode (D2) 23 Pre-Regulator Compensation Components 23 Linear Regulators 24 Internal Bias (VCC) 24 Signal Pins (NPOR, ENBAT) 24 Watchdog (WDENn, WDIN, WDADJ) 24 PCB Layout Guidelines 27 Pin ESD Structures 29 Package Outline Drawings 30 3 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR VBAT 1 µF 2.2 µF VCP CP1 CP2 DIN VIN VREG 0.1 µF 0603 50-100 µF 50 V KEY_SW 2 × 4.7 µF 50 V 1210 1 µF 10 pF EN VCC COMP 17.4 k SYNC (optional) 3.3 nF 100 nA FSET/SYNC 8.66 k BG1 BG2 BG1_UV BG1 VCP UV/OV CHARGE 0.1 µA PUMP LDO BG2_UV BG2 BG1 BG2 OSC2 CLK1MHz OSC1 CLK @ fOSC COMP BG2 BG1 VREG ON VCP UV BUCK-BOOST PRE-REGULATOR (VREG) WITH HICCUP MODE STOP PWM VREG_OV FB2 FB1 75 m LX CONNECT LG TO VCC FOR BUCK ONLY MODE LG BG1_UV BG2_UV VIN_UV MASTER IC POR SS OK SOFT START tSS VCP OV TSD 5V0 *D1MISSING * indicates a *ILX(LIM) latched fault FOLDBACK VREG VLDO NPOR MPOR NPOR CLK1MHz NPOR TIMING ON EN MPOR 5V0 UV VREG_OK STARTUP / SHUTDOWN SEQUENCE WDSTART WDFAULT 5V0 UV *D1MISSING *ILX(LIM) VREG ON LDOs ON BG1 BG2 LDOs ON 5V LDO 5V0 FOLDBACK 5V LDO V5 BG2 5V0 UV 5V0 UV DEGLITCH td(FILT) 5V0 3.3 k 0.1 µF CLKIN WDENn 13 k tWDTO(SLOW) = 4 ms tWDTO(FAST) = 0.5 ms ENBAT 650 k + 3.3 VTYP 2.6 VTYP DEGLITCH ON td(ENBAT,FILT) FALLING EN DELAY td(off)LDO WDADJ WDIN WDENn WD OSC WDCLK WDENn = 0 or OPEN enables WD 60 k WDSTART WINDOW WATCHDOG TIMER (WWDT) CLK1MHz ONE SHOT tWD(FAULT) WDFAULT A4409 GND PGND Functional Block Diagram / Typical Schematic Buck-Boost Mode (fOSC = 2 MHz) L1 6.8 µH 60 mTYP REMOVE D2 AND Q1 FOR BUCK ONLY MODE D2 6.6 V 250 mA D1 Q1 4 × 10 µF 16 V / X7R / 1206 2 k 1 2.2 µF 2.2 µF 5 V 300 mA 2.2 µF 5 V 200 mA 4 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR PINOUT DIAGRAM AND TERMINAL LIST TABLE VCP 1 VIN 2 ENBAT 3 GND 4 VCC 5 COMP 6 FSET/SYNC 7 NPOR 8 WDENn 9 WDIN 10 PAD 20 CP2 19 CP1 18 LX 17 PGND 16 LG 15 VREG 14 VLDO 13 WDADJ 12 V5 11 5V0 Package LP, 20-Pin eTSSOP Pinout Diagram Terminal List Table Number Name Function 1 VCP Charge pump reservoir capacitor 2 VIN Input voltage 3 ENBAT Ignition-enable input from the key/switch through a 1 k resistor 4 GND Ground 5 VCC Internal voltage regulator bypass capacitor pin 6 COMP Error amplifier compensation network pin for the buck-boost pre-regulator 7 FSET/ Frequency setting and synchronization input SYNC 8 NPOR Active low, open-drain regulator fault detection output 9 WDENn Watchdog enable pin: Open/Low WD is enabled, High WD is disabled 10 WDIN Watchdog refresh input (rising edge triggered) from a microcontroller or DSP 11 5V0 5 V, 300 mA regulator output 12 V5 5 V, 200 mA regulator output 13 WDADJ The watchdog window time is programmed by connecting RADJ from this pin to ground 14 VLDO Input for the LDOs 15 VREG Feedback pin for VREG output, connect to VREG converter output capacitors 16 LG Boost gate drive output for the buck-boost pre-regulator 17 PGND Power ground 18 LX Switching node for the buck-boost pre-regulator 19 CP1 Charge pump capacitor connection 20 CP2 Charge pump capacitor connection PAD 5 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR ELECTRICAL CHARACTERISTICS GENERAL SPECIFICATIONS [1]: Valid at 3 V VIN 36 V in buck-boost mode and VIN having first reached VIN(START), 40°C TA = TJ 150°C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit GENERAL SPECIFICATIONS Operating Input Voltage After VIN > VIN(START), VENBAT 4 V, buck-boost pre-regulator 3 13.5 36 V VIN After VIN > VIN(START), VENBAT 4 V, buck preregulator 5.5 13.5 36 V VIN UVLO Start VIN(START) VIN rising - - 5 V VIN UVLO Stop VIN(STOP) VIN falling, when in buck-boost mode - - 2.9 V Supply Quiescent Current [1] IQ VIN = 13.5 V, VENBAT 4 V, no load on VREG 10 mA IQ(SLEEP) VIN = 13.5 V, VENBAT 2 V, no load on VREG 10 µA PWM SWITCHING FREQUENCY AND DITHERING Switching Frequency Frequency Divide By 2 Start [2] Frequency Divide By 2 Stop [2] Frequency Dithering VIN Dithering START Threshold VIN Dithering STOP Threshold VIN Dithering Hysteresis CHARGE PUMP (VCP) fOSC VIN(FREQ/2,START) VIN(FREQ/2,STOP) fOSC VIN(DITHER,ON) VIN(DITHER,OFF) VIN(DITHER,HYS) RFSET = 8.66 k RFSET = 57.6 k VIN rising, frequency = fOSC / 2 VIN falling, frequency = fOSC / 2 As a percent of fOSC Low range, VIN rising High range, VIN falling Low range, VIN falling High range, VIN rising 1.8 2 2.2 MHz 343 400 457 kHz 18 19 20 V 17 18 19 V ±12 % 9 9.5 10 V 17 18 19 V 8.5 9 9.5 V 18 19 20 V 500 mV Output Voltage Switching Frequency VCC OUTPUT VVCP fSW(CP) VVCP VIN 4.1 6.6 V 65 kHz Output Voltage THERMAL PROTECTION VVCC VVREG = 6.6 V 4.6 V Thermal Shutdown Threshold [2] Thermal Shutdown Hysteresis [2] TTSD THYS TJ rising 160 170 180 °C 20 °C [1] Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization, not production tested. 6 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR ELECTRICAL CHARACTERISTICS BUCK AND BUCK-BOOST PRE-REGULATOR SPECIFICATIONS [1]: Valid at 3 V VIN 36 V in buck-boost mode and VIN having first reached VIN(START), 40°C TA = TJ 150°C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit OUTPUT VOLTAGE SPECIFICATIONS Pre-Regulator Output Voltage VREG Regulating VVREG Pre-Regulator Output Voltage VLDO Regulating VVLDO(REG) PULSE WIDTH MODULATION (PWM) VIN = 13.5 V, ENBAT = 1, 0.1 A IVREG 1 A VREG pin open, measured at VLDO pin, VIN = 13.5 V, ENBAT = 1, 0.1 A IVREG 1 A 6.47 6.6 6.7 V 5.88 6 6.12 V PWM Ramp Offset LX Rising Slew Rate [2] LX Falling Slew Rate [2] Buck Minimum On-Time [2] Buck Minimum Off-Time Buck Maximum Duty Cycle Boost Minimum On-Time Boost Maximum Duty Cycle COMP to LX Current Gain Slope Compensation [2] INTERNAL MOSFET VPWMOFFSET SRLX(RISE) SRLX(FALL) tON(BUCK,MIN) tOFF(BUCK,MIN) DBUCK(MAX) tON(BOOST,MIN) DBOOST(MAX) gm(POWER) SE VCOMP for 0% duty cycle VIN = 13.5 V, 10% to 90%, IVREG = 1 A VIN = 13.5 V, 10% to 90%, IVREG = 1 A VIN = 3.5 V fOSC = 2 MHz fOSC = 400 kHz 400 mV 1.7 V/ns 1.5 V/ns 85 160 ns 0 ns 100 % 60 120 ns 70 % 4.5 A/V 3.84 4.8 5.76 A/µs 0.76 0.96 1.16 A/µs MOSFET On Resistance MOSFET Leakage ERROR AMPLIFIER RDS(on) IFET(LEAK) VIN = 13.5 V, TJ = 40°C [2], IDS = 0.1 A VIN = 13.5 V, TJ = 25°C [2], IDS = 0.1 A VIN = 13.5 V, TJ = 150°C, IDS = 0.1 A VENBAT 2 V, VLX = 0 V, VIN = 13.5 V, -40°C TJ 85°C [2] VENBAT 2 V, VLX = 0 V, VIN = 13.5 V, -40°C TJ 125°C [2] VENBAT 2 V, VLX = 0 V, VIN = 13.5 V, -40°C TJ 150°C 60 75 m 80 100 m 140 170 m 10 µA 100 µA 50 150 µA Open Loop Voltage Gain Transconductance Output Current Maximum Output Voltage Minimum Output Voltage COMP Pull-Down Resistance AVOL gm(EA) IO(EA) VO(EA,MAX) VO(EA,MIN) RCOMP HICCUP = 1 or FAULT = 1 or IC disabled 65 dB 550 750 950 µA/V ±75 µA 1.3 1.7 2.1 V 200 mV 1 k [1] Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization, not production tested. 7 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR ELECTRICAL CHARACTERISTICS BUCK AND BUCK-BOOST PRE-REGULATOR SPECIFICATIONS (continued) [1]: Valid at 3 V VIN 36 V in buck-boost mode and VIN having first reached VIN(START), 40°C TA = TJ 150°C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit BOOST MOSFET (LG) GATE DRIVER LG High Output Voltage LG Low Output Voltage LG Source Current [1] LG Sink Current [1] LG Leakage Current [2] SOFT START VLG(ON) VLG(OFF) ILG(ON) ILG(OFF) ILG(LEAK) VIN = 7 V, VVREG = 6.35 V VIN = 13.5 V, VVREG = 6.85 V VIN = 7 V, VVREG = 6.35 V, VLG = 1 V VIN = 13.5 V, VVREG = 6.85 V, VLG = 1 V VIN = 13.5 V, VVREG = 6.6 V, VLG = 3 V 4.6 6.35 V 0.2 0.4 V 500 mA 500 mA 10 µA SS Ramp Time HICCUP MODE tSS(ramp) 1 ms Hiccup OCP PWM Counts VVREG < 2.4 V (typical), VCOMP = VO(EA,MAX) 15 PWM cycles tHIC(OCP) VVREG > 2.4 V (typical), VCOMP = VO(EA,MAX) 60 PWM cycles Hiccup Mode Recovery Time trec(HIC) LX switching stops to LX switching starts, during VREG overcurrent 2 ms CURRENT PROTECTIONS Pulse-by-Pulse Current Limit ILIM LX Short-Circuit Current Limit ILIM(LX) MISSING ASYNCHRONOUS DIODE (D1) PROTECTION 3.6 4.1 4.6 A 6 7 A Detection Level VD(OPEN) Time Filtering [2] tD(OPEN) SWITCHING FREQUENCY DURING SOFT START AND OVERLOAD -1.5 -1.3 -0.9 V 50 250 ns SS PWM Frequency Foldback PWM Frequency Foldback During Overload [2] fSW(SS) fSW(OL) 0 V VVREG 2.4 V, VCOMP < VO(EA,MAX) 2.4 V < VVREG 3.3 V, VCOMP < VO(EA,MAX) VVREG > 3.3 V, VCOMP < VO(EA,MAX) 0 V VVREG 2.4 V, VCOMP = VO(EA,MAX) 2.4 V < VVREG 3.3 V, VCOMP = VO(EA,MAX) VVREG > 3.3 V, VCOMP = VO(EA,MAX) fOSC / 4 fOSC / 2 fOSC fOSC / 8 fOSC / 4 fOSC / 2 [1] Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization, not production tested. 8 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR ELECTRICAL CHARACTERISTICS LINEAR REGULATOR (LDO) SPECIFICATIONS [1]: Valid at 3 V VIN 36 V in buck-boost mode and VIN having first reached VIN(START), 40°C TA = TJ 150°C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit V5 LINEAR REGULATOR V5 Accuracy and Load Regulation VV5 V5 Dropout VV5(DROPOUT) V5 Output Capacitance Range [2] CV5(OUT) V5 OVERCURRENT PROTECTION 10 mA IV5 200 mA, VVREG = 5.4 V IV5 = 200 mA, VVLDO = 4.91 V 4.9 5 4.75 1 5.1 V V 22 µF V5 Current Limit [1] V5 Foldback Current [1] V5 STARTUP IV5(LIM) IV5(FB) VV5 = 5 V VV5 = 0 V -230 -325 mA -80 -120 -160 mA V5 Startup Time [2] 5V0 LINEAR REGULATOR tV5(START) CV5 2.9 µF, load = 25 ±5% (200 mA) 0.24 1 ms 5V0 Accuracy and Load Regulation V5V0 5V0 Dropout V5V0(DROPOUT) 5V0 Output Capacitance Range [2] C5V0(OUT) 5V0 OVERCURRENT PROTECTION 10 mA I5V0 300 mA, VVREG = 5.4 V I5V0 = 300 mA, VVLDO = 4.91 V 4.9 5 4.75 1 5.1 V V 22 µF 5V0 Current Limit [1] 5V0 Foldback Current [1] 5V0 STARTUP I5V0(LIM) I5V0(FB) V5V0 = 5 V V5V0 = 0 V -345 -485 mA -100 -165 -230 mA 5V0 Startup Time [2] t5V0(START) C5V0 2.9 µF, load = 20 ±5% (250 mA) 0.24 1 ms [1] Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization, not production tested. 9 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR ELECTRICAL CHARACTERISTICS CONTROL INPUTS [1]: Valid at 3 V VIN 36 V in buck-boost mode and VIN having first reached VIN(START), 40°C TA = TJ 150°C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit IGNITION-ENABLE (ENBAT) INPUT ENBAT Thresholds ENBAT Hysteresis ENBAT Bias Current [1] ENBAT Resistance ENBAT DEGLITCH VENBAT(H) VENBAT(L) VENBAT(HYS) IIB(ENBAT) RENBAT VENBAT rising VENBAT falling VENBAT(H) VENBAT(L) TJ = 25°C [2], VENBAT = 3.51 V TJ = 150°C, VENBAT = 3.51 V 2.8 3.2 3.5 V 2.1 2.5 2.8 V 700 mV 28 45 µA 35 60 µA 650 k Enable Filter/Deglitch Time ENBAT SHUTDOWN DELAY td(ENBAT,FILT) 10 15 20 µs LDO Shutdown Delay td(off)LDO Measure td(off)LDO from the falling edge of ENBAT to the time when all LDOs begin to decay 15 50 100 µs FSET/SYNC INPUT FSET/SYNC Pin Voltage VFSET/SYNC No external SYNC signal 800 mV FSET/SYNC Open Circuit (Undercurrent) Detection Time tFSET/SYNC(UC) PWM switching frequency becomes 900 kHz upon detection 3 µs FSET/SYNC Short-Circuit (Overcurrent) Detection Time tFSET/SYNC(OC) PWM switching frequency becomes 900 kHz disabled upon detection 3 µs Sync. High Threshold Sync. Low Threshold Sync. Input Duty Cycle Sync. Input Pulse Width Sync. Input Transition Times [2] VSYNC(H) VSYNC(L) DSYNC tPW(SYNC) tT(SYNC) VSYNC rising VSYNC falling 2 V 0.5 V 80 % 200 ns 10 15 ns [1] Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization, not production tested. 10 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR ELECTRICAL CHARACTERISTICS DIAGNOSTIC OUTPUTS [1]: Valid at 3 V VIN 36 V in buck-boost mode and VIN having first reached VIN(START), 40°C TA = TJ 150°C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit NPOR UNDERVOLTAGE PROTECTION THRESHOLDS 5V0 Undervoltage Thresholds V5V0(UV,H) V5V0(UV,L) 5V0 Undervoltage Hysteresis V5V0(UV,HYS) NPOR TURN-ON AND TURN-OFF DELAYS V5V0 rising V5V0 falling V5V0(UV,H) V5V0(UV,L) 4.665 V 4.5 4.625 4.75 V 20 40 60 mV NPOR Turn-On Delay NPOR Turn-Off Propagation Delay NPOR OUTPUT VOLTAGES td(on)NPOR td(off)NPOR ENBAT low to NPOR low, measured after ENBAT deglitch time td(ENBAT,FILT) 18 22.5 27 ms 3 µs NPOR Output Low Voltage VNPOR(L) NPOR Leakage Current [1] INPOR(LEAK) NPOR UNDERVOLTAGE FILTERING/DEGLITCH ENBAT high, VIN 2.5 V, INPOR = 4 mA ENBAT high, VIN = 1.5 V, INPOR = 2 mA VNPOR = 3.3 V 150 400 mV 800 mV 2 µA NPOR Undervoltage Filter/Deglitch Times td(NPOR,FILT) Applies to undervoltage of the 5V0 voltage 10 15 20 µs [1] Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). 11 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR ELECTRICAL CHARACTERISTICS DIAGNOSTIC OUTPUTS (continued) [1]: Valid at 3 V VIN 36 V in buck-boost mode and VIN having first reached VIN(START), 40°C TA = TJ 150°C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit VREG, VCP, AND BG THRESHOLDS VREG Overvoltage Threshold VREG Overvoltage Hysteresis VREG Undervoltage Thresholds VREG Undervoltage Hysteresis VCP Overvoltage Threshold VCP Undervoltage Thresholds VCP Undervoltage Hysteresis BG1 and BG2 Undervoltage Thresholds [2] VVREG(OV,H) VVREG(OV,HYS) VVREG(UV,H) VVREG(UV,L) VVREG(UV,HYS) VVCP(OV,H) VVCP(UV,H) VVCP(UV,L) VVCP(UV,HYS) VVREG rising, PWM disabled VVREG rising VVREG falling VVREG(UV,H) VVREG(UV,L) VVCP rising, PWM disabled VVCP rising, PWM enabled VVCP falling, PWM disabled VVCP(UV,H) VVCP(UV,L) VBGx(UV) BG1 or BG2 rising 6.8 6.93 7.18 V 100 mV 4.16 4.41 4.64 V 4.3 V 100 mV 11 12.5 14 V 3 3.2 3.4 V 2.7 V 500 mV 1 1.05 1.1 V UNDERVOLTAGE AND OVERVOLTAGE FILTERING/DEGLITCH Undervoltage Filter/Deglitch Time Overvoltage Response Time [2] td(UV,FILT) td(OV,FILT) 10 15 20 µs 1 µs [1] Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization, not production tested. 12 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR ELECTRICAL CHARACTERISTICS WINDOW WATCHDOG TIMER (WWDT) [1]: Valid at 3 V VIN 36 V in buck-boost mode and VIN having first reached VIN(START), 40°C TA = TJ 150°C, unless otherwise specified. Characteristic Symbol Test Conditions Min. Typ. Max. Unit WD ENABLE INPUT (WDENn) WDENn Voltage Thresholds VWDENn(L) VWDENn(H) WDENn Input Resistance RWDENn WDIN VOLTAGE THRESHOLDS AND CURRENT WDIN Input Voltage Thresholds VWDIN(L) VWDIN(H) WDIN Input Current [1] IWDIN WDIN TIMING SPECIFICATIONS WDIN Frequency fWDIN WDIN Duty Cycle DWDIN Watchdog Activation Delay tWD(START) WD PROGRAMMING VWDENn falling, WWDT enabled VWDENn rising, WWDT disabled VWDIN falling, WDADJ pulled low by RADJ VWDIN rising, WDADJ charging VWDIN = 5 V 0.8 V 2 V 60 k 0.8 V 2 V -10 ±1 10 µA 750 Hz 20 50 80 % 24 30 36 ms WD Timeout FAST Range [2] WD Timeout SLOW Range [2] WD Timeout, FAST Clock WD Timeout, SLOW Clock WD ONE-SHOT TIME tWDTO(FAST) tWDTO(SLOW) tWDTO(FASTCLK) tWDTO(SLOWCLK) RADJ = 13 k RADJ = 324 k RADJ = 13 k RADJ = 324 k 0.5 12.5 ms 4 100 ms 0.4 0.5 0.6 ms 10 12.5 15 ms 3.2 4 4.8 ms 80 100 120 ms WD Pulse Time After WD Fault tWD(FAULT) 1.6 2 2.4 ms [1] Negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). [2] Ensured by design and characterization, not production tested. 13 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR TIME Table 1: Startup and Shutdown Logic (signal names consistent with Functional Block Diagram) ENBAT A4409 Status Signals MPOR VREG UV 5V0_UV Supply Control (0=OFF, 1=ON) VREG ON LDOs ON A4409 MODE X 1 X X 0 0 RESET 0 0 1 1 0 0 OFF 1 0 1 1 1 0 STARTUP 1 0 0 1 1 0 1 0 0 1 1 1 1 0 0 0 1 1 RUN 0 0 0 0 1 1 50 µs DELAY 0 0 0 0 1 0 SHUTDOWN 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 OFF X = DON'T CARE MPOR = BG1_UV or BG2_UV or VIN_UV or TSD or VCP_UV or VCP_OV or D1MISSING (latched) + ILIM(LX) (latched) 14 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR Table 2: Summary of Fault Mode Operation FAULT TYPE and CONDITION A4409 RESPONSE TO FAULT 5V0 undervoltage 5V0 overcurrent V5 undervoltage V5 overcurrent VREG pin open circuit VREG shorted to ground, VVREG < 2.4 V, VCOMP EAVO(MAX) VREG overcurrent, VVREG < 2.4 V, VCOMP = EAVO(MAX) VREG overcurrent, VVREG > 2.4 V, VCOMP = EAVO(MAX) VREG asynchronous diode (D1) missing Asynchronous diode (D1) short circuited or LX shorted to ground FSET/SYNC pin open circuit FSET/SYNC pin shorted to ground Closed loop control will try to raise the voltage but may be constrained by the foldback or pulse-bypulse current limit Foldback current limit will reduce the output voltage Closed loop control will try to raise the voltage but may be constrained by the foldback current limit Foldback current limit will reduce the output voltage VLDO pin will take over regulation, power dissipation in IC will increase Continue to PWM but turn off LX when the highside MOSFET current exceeds ILIM Enters hiccup mode after 15 OCP faults Enters hiccup mode after 60 OCP faults Results in an MPOR after 1 detection, so all regulators are off Results in an MPOR after the high-side MOSFET current exceeds ILIM,LX, so all regulators are off Oscillator frequency becomes default frequency 900 kHz Oscillator frequency becomes default frequency 900 kHz Charge pump (VCP) overvoltage Results in an MPOR, so all regulators are shut off Charge pump (VCP) undervoltage Results in an MPOR, so all regulators are shut off VCP pin open circuit VCP pin shorted to ground Results in VCP_UV and an MPOR, so all regulators are shut off Results in high current from the charge pump and (intentional) fusing of an internal trace. Also results in an MPOR, so all regulators are shut off COMP shorted high CP1 or CP2 pin open circuit CP1 pin shorted to ground VREGOV,H will trip, so all regulators are shut off Results in VCP_UV and an MPOR, so all regulators are shut off Results in VCP_UV and an MPOR, so all regulators are shut off NPOR Low Transitions low if 5V0 < V5V0(UV,L) Not affected Not affected Not affected Depends on 5V0 Depends on 5V0 Depends on 5V0 Low Low Not affected Not affected Depends on 5V0 Depends on 5V0 Depends on 5V0 Depends on 5V0 Depends on 5V0 Depends on 5V0 Depends on 5V0 LATCHED FAULT? NO RESET METHOD or CORRECTION Decrease the load NO Decrease the load NO Decrease the load NO Decrease the load NO Connect the VREG pin NO Remove the short circuit NO Decrease the load NO YES YES NO NO NO NO NO NO YES NO NO Decrease the load Place D1 then cycle ENBAT or VIN Remove the short then cycle ENBAT or VIN Connect the FSET/SYNC pin Remove the short circuit Check VCP/CP1/CP2 pins and components, then cycle ENBAT or VIN Check VCP/CP1/CP2 pins and components Connect the VCP pin Remove the short circuit and replace the A4409 Remove the high level from the COMP pin then cycle ENBAT or VIN Connect the CP1 or CP2 pins Remove the short circuit Continued on next page... 15 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR Table 2: Summary of Fault Mode Operation (continued) FAULT TYPE and CONDITION A4409 RESPONSE TO FAULT CP2 pin shorted to ground Results in high current from the charge pump and (intentional) fusing of an internal trace. Also results in an MPOR, so all regulators are shut off. BG1 or BG2 undervoltage Results in an MPOR, so all regulators are shut off BG1 or BG2 overvoltage VIN undervoltage Thermal shutdown WDADJ pin shorted to ground or open circuit If BG1 is too high, 5V0 will appear to be overvoltage, because BG2 is good. If BG2 is too high, 5V0 will appear to be undervoltage, because BG1 is good. Results in an MPOR, so all regulators are shut off Results in an MPOR, so all regulators are shut off A WDADJ fault only affects the NPOR output. The remainder of the A4409 operates normally. NPOR LATCHED FAULT? RESET METHOD or CORRECTION Depends on 5V0 NO Remove the short circuit and replace the A4409 Depends on 5V0 NO Raise VIN or wait for BGs to power up Low NO Replace the A4409 Depends on 5V0 NO Raise VIN Depends on 5V0 NO Let the A4409 cool Low NO Remove the short circuit or connect the pin 16 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR VIN ENBAT > VIN(START, MAX) COMP fOSC / 2 fOSC / 4 LX tSS tSS(DLY) VREG VVREG(UV,H) 3.3 V 2.4 V V5V0(UV,H) 5V0 V5 5V0 > V5V0(UV,H) NPOR t d(on)NPOR TIMING DIAGRAMS (not to scale) t < t d(ENBAT,FILT) t d(ENBAT,FILT) SHUTDOWN SEQUENCE MUST FINISH BEFORE RE-START IS ACKNOWLEDGED fOSC V5V0(UV,L) t d(off)LDO 5V0 < V5V0(UV,L) t d(off)NPOR Figure 1: Startup and Shutdown Sequence 17 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR 13.5 V VIN ENBAT Decay rate of the VIN pin will depend on the total input capacitance and loads. VIN PIN: ~6.7 V @ 25°C COMP fOSC / 2 fOSC / 4 LX tSS(ramp) VREG VVREG(UV,H) 3.3 V 2.4 V tSS(DLY) V5V0(UV,H) V5V0(UV,L) 5.0V fOSC ~5.6 V @ 25ºC 100% Duty Cycle Dropout will depend on output load 5V NPOR td(on)NPOR Figure 2: Input Undervoltage Timing, when VIN > VIN(STOP) VVCC > VVCC(STOP) fOSC 18 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR 13.5 V VIN ENBAT VIN PIN: ~ 6.7 V @ 25ºC Decay rate of the VIN pin will depend on the total input capacitance and loads. MPOR VIN < VIN(STOP) COMP fOSC / 2 fOSC / 4 100% Duty Cycle fOSC fOSC LX VREG tSS VVREG(UV,H) 3.3 V 2.4 V ~5.6 V @ 25ºC td(SS) V5V0(UV,H) V5V0(UV,L) 5.0V 5V NPOR td(on)NPOR t d(NPOR,FILT) t d(on)NPOR Figure 3: Input Undervoltage Timing, when VIN < VIN(STOP) 19 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR VREG EN_HIC* HIC* COMP VO(EA,MAX) 15× OCP* OCP LX trec(HIC) 15× OCP 15× OCP Figure 4: VREG Short Circuit to Ground Hiccup Operation * Signal is internal to A4409 fOSC fOSC/8 fOSC/4 fOSC/8 fOSC/42 fOSC/8 fOSC/4 fOSC/8 20 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR DESIGN AND COMPONENT SELECTION Setting Up the Pre-Regulator This section describes component selection for the A4409 preregulator, including charge-pump circuit, inductor, diodes, boost MOSFET, and input and output capactors. This section also covers loop compensation. Soft Start and Startup The A4409 includes an internal soft start ramp to allow for controlled voltage ramp of the output. The soft start time is typically 1 ms. As the output voltage is rising from 0 V to its final value during soft start, the duty cycle demand can be quite small. To reduce the impact of a small duty cycle, the A4409 will vary the switching frequency based on the output voltage, VREG. For example, if VREG is less than 2.4 V, the switching frequency will be one quarter its programmed value. During soft start, as VREG rises, the switching frequency will step up to its final programmed value. The switching frequency is also reduced if the A4409 COMP voltage reaches its maximum value, i.e. maximum duty cycle is demanded. During this frequency foldback state, the duty cycle to the boost MOSFET is also reduced. This puts higher demand on the buck stage. This can occur during startup if very slow input voltage rise times are used. The A4409 requires a minimum of 5 V on VIN to ensure startup. However, if the A4409 is configured as a buck boost and the VIN rise rate is slower than 1 V/ms, this startup voltage may be as high as 6 V. Charge Pump Capacitors The charge pump requires two capacitors: a 2.2 µF capacitor connected from pin VCP to pin VIN, and a 1 µF capacitor connected between pins CP1 and CP2. These capacitors should be high quality ceramic capacitors, such as X7R, with a voltage rating of at least 50 V. PWM Switching Frequency When the PWM switching frequency is chosen, the designer should be aware of the minimum controllable on-time, tON(MIN), of the A4409. If the system's required on-time is less than the A4409's minimum controllable on-time, then switch-node jitter will occur and the output voltage will have increased ripple or oscillations. The PWM switching frequency should be calculated using equation 1, where tON(BUCK,MIN) is the minimum controllable on-time of the A4409 (160 ns typical), and VIN(MAX) is the maximum required operational input voltage (not the peak surge voltage). 6.6 V f < OSC t × V ON(BUCK,MIN) IN(MAX) (1) If the A4409's synchronization function is used, then the base oscillator frequency should be chosen such that jitter will not result at the maximum synchronized switching frequency according to equation 1. RFSET can be estimated using equation 2 below. RFSET = 1 0.0455 × fOSC 1.98 (k) (2) where fOSC is in MHz. Pre-Regulator Output Inductor (L1) For peak current mode control, it is well known that the system will become unstable when the duty cycle is above 50% without adequate slope compensation (SE). However, the slope compensation in the A4409 is a fixed value based on the oscillator fre- quency (fOSC). Therefore, it is important to calculate an inductor value so the falling slope of the inductor current (SF) will work well with the A4409's slope compensation. Equation 3 can be used to calculate a range of values for the output inductor for buck or buck-boost. ( VREG + SE VF ) L1 2 × ( VREG + VF ) SE (3) where VF is the asynchronous diode forward voltage, fOSC is the programmed oscillator frequency in kHz, and SE slope compensation can be calculated from equation 4 and is in amperes per microsecond (A/µs). The resultant inductor value will be in microhenries (µH). SE = 0.0024 × fOSC (4) If equation 3 yields an inductor value that is not a standard value, then the next closest available value should be used. The final inductor value should allow for 10%-20% of initial tolerance and 20%-30% of inductor saturation. The inductor should not saturate given the peak operating current during overload. Equation 5 calculates the current. In equation 5, VIN(MAX) is the maximum continuous input voltage, such as 16 V, 21 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR and VF is the asynchronous diodes forward voltage. IPEAK = 4.6 A SE × ( VREG + VF ) 0.9 × fOSC × ( VIN(MAX)+VF ) (5) After an inductor is chosen, it should be tested during output overload and short-circuit conditions. The inductor current should be monitored using a current probe. A good design should ensure the inductor or the regulator is not damaged when the output is shorted to ground at maximum input voltage and the highest expected ambient temperature. Inductor ripple current can be calculated using equation 6 for buck mode and equation 7 for buck-boost mode. IL1 = ( VIN VREG ) × VREG fSW × L1× VIN (6) IB / B = VIN × DBOOST fSW × L1 (7) Pre-Regulator Output Capacitors The output capacitors filter the output voltage to provide an acceptable level of ripple voltage, and they store energy to help maintain voltage regulation during a load transient. The voltage rating of the output capacitors must support the output voltage with sufficient design margin. The output voltage ripple (VOUT ) is a function of the output capacitors parameters: CO, ESRCO, ESLCO. VOUT = IL1× ESRCO + VIN VREG L1 × ESLCO + 8× IL1 fSW× CO (8) The type of output capacitors will determine which terms of equation 8 are dominant. For ceramic output capacitors, the ESRCO and ESLCO are virtually zero, so the output voltage ripple will be dominated by the third term of equation 8. VREG = IL1 (9) 8× fSW × CO To reduce the voltage ripple of a design using ceramic output capacitors, simply increase the total capacitance, reduce the inductor current ripple (i.e. increase the inductor value), or increase the switching frequency. The transient response of the regulator depends on the number and type of output capacitors. In general, minimizing the ESR of the output capacitance will result in a better transient response. The ESR can be minimized by simply adding more capacitors in parallel or by using higher quality capacitors. At the instant of a fast load transient (di/dt), the output voltage will change by the amount di VREG = ILOAD × ESRCO + dt ESLCO (10) After the load transient occurs, the output voltage will deviate from its nominal value for a short time. This time will depend on the system bandwidth, the output inductor value, and output capacitance. Eventually, the error amplifier will bring the output voltage back to its nominal value. The speed at which the error amplifier will bring the output voltage back to its setpoint will depend mainly on the closed-loop bandwidth of the system. A higher bandwidth usually results in a shorter time to return to the nominal voltage. However, it may be more difficult to obtain acceptable gain and phase margins in a a higher bandwidth system. Selection of the compensation components (RZ, CZ, CP) are discussed in more detail in the Compensation Components section of this datasheet. Ceramic Input Capacitors The ceramic input capacitor or capacitors must limit the voltage ripple at the VIN pin to a relatively low voltage during maximum load. Equation 11 can be used to calculate the minimum input capacitance, CIN I × VREG(MAX) 0.25 0.9× fSW× 50 mV (11) where IVREG(MAX) is the maximum current from the pre-regulator, IVREG(MAX) ILINEAR + IAUX + 20 mA (12) where ILINEAR is the sum of all internal linear regulators output currents, and IAUX is any extra current drawn from the VREG output to power other devices external to the A4409. A good design should consider the dc-bias effect on a ceramic capacitor-- as the applied voltage approaches the rated value, the capacitance value decreases. An X7R type capacitor should be the primary choice due to its stability with both dc bias and temperature variation. For all ceramic capacitors, the dc-bias effect is even more pronounced on smaller case sizes, so a good design will use the largest affordable case size. Also for improved noise performance, it is recommended to add smaller-sized capacitors close to the A4409 VIN pin and the D1 anode. Use a 0.1 µF, 0603 capacitor. 22 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR Buck-Boost Asynchronous Diode (D1) The highest peak current in the asynchronous diode (D1) occurs during overload and is limited by the A4409. Equation 5 can be used to calculate this current. The highest average current in the asynchronous diode occurs when VIN is at its maximum, DBOOST = 0%, and DBUCK = minimum (10%), IAVG = 0.9 × IVREG(MAX) (13) where IVREG(MAX) is calculated using equation 12. Boost MOSFET (Q1) The RMS current in the boost MOSFET (Q1) occurs when VIN is at its minimum and both the buck and boost operate at their maximum duty cycles (approximately 64% and 58%, respectively), [( ) ] IQ1(RMS) = DBOOST × IPEAK - IB / B 2 2 + IB / B 12 (14) where IPEAK and IB/B are derived using equations 5 and 7, respectively. Boost Diode (D2) In buck mode, this diode will simply conduct the output current. However, in buck-boost mode, the peak currents in this diode may increase significantly. The A4409 limits the peak current to the value calculated using equation 5. The average current is simply the output current. Pre-Regulator Compensation Components (RZ, CZ, CP) Although the A4409 can operate in buck-boost mode at low input voltages, it can still be considered a buck converter when looking at the control loop. The following equations can be used to calculate the compensation components. First, the target crossover frequency for the final system must be selected. Although the A4409 can switch at over 2 MHz, the crossover will be governed by the required phase margin. Since a type II compensation scheme is used, there are limits to the amount of phase that can be added. Therefore, a crossover fre- quency, fC, of around 40 kHz is selected. The total system phase will drop off at higher crossover frequencies. The RZ selection is based on the gain required at the crossover frequency, and can be calculated by the following simplified equation: RZ = 13.36 × × fC × CO g × g m(POWER) m(EA) (15) The series capacitor, CZ, along with the resistor, RZ, set the location of the compensation zero. This zero should be placed no lower than ¼ of the crossover frequency and should be kept to minimum value. Equation 18 can be used to estimate this capacitor value. 4 CZ > 2 × RZ× fC (16) Determine if the second compensation capacitor (CP) is required. It is required if the ESR zero of the output capacitor is located at less than half of the switching frequency or the following rela- tionship is valid: 1 < fSW (17) 2 × CO × ESRCO 2 If this is the case, then add the second compensation capacitor (CP) to set the pole fP3 at the location of the ESR zero. Determine the CP value by the equation: CP = COUT × ESR RZ (18) Finally, take a look at the combined bode plot of both the controlto-output and the compensated error amp-- see the red curves shown in Figure 5. Careful examination of this plot shows that the magnitude and phase of the entire system are simply the sum of the error amp response (blue) and the control-to-output response (green). As shown in Figure 5, the bandwidth of this system (fC) is 25.2 kHz, the phase margin is 52.5 degrees, and the gain margin is 22 dB. These values are theoretical; actual measured values may be different. Some fine-tuning of the final compensation components may be necessary in the lab. 23 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR 60 180 50 135 40 90 PM = 52.5° 30 45 20 0 Gain - dB Phase - ° 10 -45 fC = 25.2 kHz 0 -90 -10 -20 -30 -40 100 GM = 22 dB Total Gain Total Phase 1000 C to O Gain C to O Phase E/A Gain E/A Phase 10000 Frequency - Hz 100000 -135 -180 -225 -270 1000000 Figure 5: Bode plot of the complete system (red curve) RZ = 6.19 k, CZ = 4.7 nF, CP = 10 pF LO = 33 µH, CO = 4 × 10 µF ceramic Linear Regulators The two linear regulators only require a ceramic capacitor to ensure stable operation. The capacitor can be any value between 1 µF and 22 µF. A 2.2 µF or 4.7 µF capacitor per regulator is recommended. Internal Bias (VCC) The internal bias voltage should be decoupled at the VCC pin using a 1 µF, 25 V X7R ceramic capacitor. It is not recommended to use this pin as a source. Watchdog (WDENn, WDIN, WDADJ) The A4409 window watchdog circuit monitors an external clock applied to the WDIN pin. This clock should be generated by the microcontroller or DSP. The time between rising edges of the clock must fall within an acceptable "window" or a watchdog fault will be generated. A watchdog fault will set NPOR for tWD(FAULT) (typically 2 ms). A watchdog fault will occur if the time between rising edges is either too short (a FAST fault) or too long (a SLOW fault). The watchdog time "window" is programmable via the WDADJ pin according to the following equations: RADJ = 3.24 × tWDTO(SLOW) tWDTO(FAST) = tWDTO(SLOW) / 8 where tWDTO(SLOW) is the nominal watchdog timeout (in ms) and RADJ is the required external resistor value (in k) from the WDADJ pin to ground. Typical watchdog operation under FAST and SLOW fault conditions are shown in Figure 7 and Figure 8. The watchdog is enabled if two conditions are met: 1. the WDENn pin is a logic low, and 2. all regulators (5V0 and V5) have been above their undervoltage thresholds for at least 30 msTYP (tWD(START)). After startup, if no clock edges are detected at WDIN for at least tWD(START) + tWDTO(SLOW), the A4409 will set NPOR low for tWD(FAULT) and reset its counters. This process will repeat until the system recovers and clock edges are applied to WDIN. A timing diagram for the "missing clock" situation is shown in Figure 9. Figure 10 shows the WDFAULT signal during a fast clock fault. Signal Pins (NPOR, ENBAT) The NPOR signal is an open drain output and requires an external pull-up resistor. It is recommended to pull NPOR up to the 5V0 rail, so when the A4409 is disabled, NPOR will not be high. The ENBAT is a high-voltage input pin. It does require a currentlimiting resistor when connected to voltages greater than 8 V. There are limitations on this resistor value based on ENBAT sink current, ENBAT enable threshold, and input voltage operating conditions. Minimum ENBAT resistor is 450 . If ENBAT must ensure A4409 is enabled down to the minimum operating voltage, then a resistor less than 3.37 k is recommended. 24 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR CLKIN WDENn RADJ = 64.9 k for tWDTO(SLOW) = 20 ms WDADJ WDIN WDENn WD OSC WDCLK WDENn = 0 or OPEN enables WD 60 k WDSTART WINDOW WATCHDOG TIMER (WWDT) CLK1MHz ONE SHOT tWD(FAULT) WDFAULT Figure 6: Watchdog Block Diagram NPOR WDSTART* WDIN W DFAULT* tWD(START) tWDTO(FAST) tWDTO(SLOW) set set to to 5 ms (±1 ms) 40 ms (±8 ms) 6 ms < T < 32 ms T < 4 ms tWD(START) tWD(FAULT) Figure 7: Window Watchdog Timer FAST Fault, T = WDIN period * Signal is internal to A4409 NPOR WDSTART* WDIN W DFAULT* tWD(START) tWDTO(FAST) tWDTO(SLOW) set set to to 5 ms (±1 ms) 40 ms (±t 8 ms) 6 ms < T < 32 ms T > 48 ms tWD(START) tWD(FAULT) Figure 8: Window Watchdog Timer SLOW Fault, T = WDIN period * signal is internal to A4409 25 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR NPOR WDSTART* td(on)NPOR tWD(START) tWDTO(SLOW) tWD(START) tWDTO(SLOW) tWD(START) WDIN W DFAULT* STARTUP tWD(FAULT) tWD(FAULT) Figure 9: Window Watchdog Timer operation during slow clock fault, WDIN stuck low or high * signal is internal to A4409 NPOR W DSTART* WDIN W DFAULT* STARTUP tWDTO(FAST) td(on)NPOR tWD(START) tWDTO(FAST) tWD(START) tWDTO(FAST) tWD(START) tWDTO(FAST) tWD(START) tWD(FAULT) tWD(FAULT) tWD(FAULT) Figure 10: Window Watchdog Timer operation during fast clock fault * signal is internal to A4409 tWD(FAULT) 26 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR PCB LAYOUT GUIDELINES Good layout of the power components and high di/dt loops is critical to proper operation of the A4409. It also helps to reduce EMI generation. The first loop to consider is the buck regulator input loop. This consists of the input capacitors C3, C4, and C5, pins 2 and 18 of the A4409, and the diode D2. Figure 11 shows this loop in red. C6 C7 L1 C3 C4 C5 2.2 µF 1 µF 4.7 µF 0.1 µF 100 pF D2 GND 2 U1 VIN 3 ENBAT 1 19 VCP CP1 A4409LP 20 CP2 LX 18 GND Figure 11: Buck High di/dt Loop An example of how these components may be placed is shown below. Ensure that these components and connecting traces are on the same side of the PCB. Also ensure the enclosed area within the loop is as small as possible. The switch node trace connected to LX should be as short and as wide as possible to ensure the lowest possible impedance. If the A4409 is configured as a buck-boost, then the boost output loop needs to be considered. This is made up of the boost MOSFET Q1, boost diode D7, and output capacitors C30 and C8. The boost switch node (L1, Q1 drain, and D7 anode) should be as short and as wide as possible to ensure the lowest possible impedance. L1 D7 C30 C8 Q1 180 pF 10 µF GND Figure 13: Boost Output Loop Layout below shows the boost high di/dt loop. Figure 12 Figure 14: Boost High di/dt Loop 27 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR Also if configured for buck-boost mode, then care must be taken with the gate drive trace. The turn-on pulse is from C17 through A4409 pin 16 to Q1 gate and source back to C17. The turn-off pulse is from Q1 gate to A4409 pin 16 back to Q1 source through the ground. Other sensitive nodes to keep small are the FSET/SYNC to R3, the COMP pin to C15 and C16, and WDADJ pin to RADJ. Figure 15 Figure 16 28 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR PIN ESD STRUCTURES PIN 8 V Figure 17: VCC, COMP, FSET/SYNC, NPOR, WDENn, WDIN, 5V0, V5, WDADJ, VLDO, VREG, LG GND PGND Figure 18: GND, PGND 8 V 40 V CP1 CP2 VCP Figure 19: VCP, CP1, CP2 VIN 40 V LX Figure 20: VIN, LX 40 V ENBAT Figure 21: ENBAT 29 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR PACKAGE OUTLINE DRAWING For Reference Only Not for Tooling Use (Reference JEDEC MO-153ACT; Allegro DWG-0000379, Rev. 3) NOT TO SCALE Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 6.50 ±0.10 4.20 20 0.45 0.65 8° 20 0° 0.20 1.70 0.09 C 3.00 4.40 ±0.10 6.40 ±0.20 A 1.00 REF 3.00 6.10 12 20X 0.10 C 0.30 0.19 0.65 BSC 0.25 BSC 1.20 MAX C SEATING PLANE 0.15 0.025 0.60 ±0.15 SEATING PLANE GAUGE PLANE A Terminal #1 mark area B Reference land pattern layout (reference IPC7351 SOP65P640X110-21M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) C Exposed thermal pad (bottom surface) D Branding scale and appearance at supplier discretion Figure 22: Package LP, 20-Pin eTSSOP 12 4.20 B PCB Layout Reference View XXXXXXX Date Code Lot Number 1 D Standard Branding Reference View Line 1, 2, 3 = 8 characters Line 1: Part Number Line 2: Logo A, 4 digit Date Code Line 3: Characters 5, 6, 7, 8 of Assembly Lot Number 30 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com A4409 Adjustable Frequency Buck or Buck-Boost Pre-Regulator with 2 LDOs, Window Watchdog Timer, and NPOR Revision History Number 1 2 3 4 5 6 7 8 9 Date October 5, 2015 December 14, 2015 March 31, 2016 June 27, 2016 August 26, 2016 October 2, 2017 October 12, 2018 October 21, 2019 March 19, 2021 April 6, 2022 Description Initial Release Updated 5V0 Undervoltage Thresholds and Hysteresis in Electrical Characteristics table (page 10). Corrected NPOR Turn-Off Propagation Delay test condition (page 10); Corrected Watchdog Activation Delay symbol (page 12); Added "WDADJ Pin Shorted to Ground or Open Circuit" to Summary of Fault Mode Operation table (page 15); Corrected Figure 1 (page 16); Corrected Figure 3 (page 18); Removed "Window Watchdog Timer Operation During RADJ Fault" figure (page 25); Corrected PCB layout guidelines (page 27). Updated Pin ESD Structures (page 28). Corrected Figures 1, 2, and 3 (pages 16-18). Added Table of Contents (page 3); Added Switching Frequency During Soft Start and Overload section to Electrical Characteristics table (page 8); Updated Figures 1, 2, 3, and 4 (pages 17-20); Added Soft Start and Startup section to Design and Component Selection (page 21). Minor editorial updates. Minor editorial updates. Updated Equation 4 (page 21) Updated package drawing (page 30) Copyright 2022, Allegro MicroSystems. Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro's product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. Copies of this document are considered uncontrolled documents. For the latest version of this document, visit our website: www.allegromicro.com 31 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com
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