Transcend microSD C10I Card Series
Description
Transcend industrial-grade microSD cards offer greater design flexibility and cost savings. Despite their compact size, these cards provide excellent temperature flexibility from -40°C to 85°C. Manufactured with high-quality controllers and MLC flash chips, they deliver superior shock and vibration resistance and low power consumption, bringing the performance and reliability advantages of industrial memory cards to small form factor devices.
Features
- Manufactured with Industrial spec NAND Flash memory
- Operating Temperature: -40°C to 85°C
- Compatible with SD Specification Ver. 3.01
- Supports Speed Class Specification up to Class 10
- Built-in ECC and Wear leveling
- Support ESD IEC 61000-4-2
- Read Retry function
- Support S.M.A.R.T. function
Architecture
The microSD card architecture comprises a Card Interface Controller, a Memory Core Interface, and a Memory Core. The interface driver handles communication via DAT0-DAT2, CMD, CLK, and CD/DAT3 signals, with a 'Power on detection' mechanism.
Pin Definition
The microSD card features 8 pins with defined functions in both SD Mode and SPI Mode.
| Pin No. | Name | SD Mode Description | SPI Mode Name | SPI Mode Description |
|---|---|---|---|---|
| 1 | DAT2 | Data Line [Bit2] | RSV | Reserved |
| 2 | CD/DAT3 | Card Detect / Data Line [Bit3] | CS | Chip Select |
| 3 | CMD | Command / Response | DI | Data In |
| 4 | VDD | Supply voltage | VDD | Supply voltage |
| 5 | CLK | Clock | SCLK | Clock |
| 6 | VSS | Supply voltage ground | VSS | Supply voltage ground |
| 7 | DAT0 | Data Line [Bit0] | DO | Data out |
| 8 | DAT1 | Data Line [Bit1] | RSV | Reserved |
Diagram shows pin numbering from 1 to 8 on the microSD card connector.
Specifications
Physical Specification
| Parameter | Value |
|---|---|
| Form Factor | microSD |
| SD specification | SD3.01 |
| Dimensions (mm) | Length: 11.00 ± 0.1, Width: 15.00 ± 0.1, Height: 0.7 ± 0.1 |
Performance
| Model P/N | Sequential Read* | Sequential Write* | Random Read (4KB)* | Random Write (4KB)* |
|---|---|---|---|---|
| TS8GUSDC10I | 24 | 16 | 3.5 | 0.5 |
| TS16GUSDC10I | 24 | 16 | 3.5 | 0.5 |
| TS32GUSDC10I | 24 | 17 | 3.5 | 0.5 |
| TS64GUSDC10I | 24 | 22 | 3.7 | 0.5 |
Note: Maximum transfer speed recorded at 25°C, 4GB DRAM, Windows 7 with Transcend RDF5, benchmark utility Crystal DiskMark, copying a 1000MB file. Unit: MB/s.
Endurance
| Model | TeraBytes Written (T.B.) |
|---|---|
| TS8GUSDC10I | 15 |
| TS16GUSDC10I | 30 |
| TS32GUSDC10I | 60 |
| TS64GUSDC10I | 120 |
*TBW is based on Transcend internal standard. 1 TeraByte = 1,000,000,000,000 bytes.
Bus Mode / Power Consumption
| Mode | Operation | Value (Max.) |
|---|---|---|
| Default Mode (25MHz) | Read | 100mA |
| Write | 100mA | |
| Idle | 0.5mA | |
| Default Mode (25MHz,XPC=1) | Read | 150mA |
| Write | 150mA | |
| Idle | 0.5mA | |
| High Speed mode (50MHz) | Read | 200mA |
| Write | 200mA | |
| Idle | 0.5mA |
Note: Power consumption is referred to Section 6.6.3 of the SDA Physical Layer Specification, Version 3.01.
Environmental Specifications
| Parameter | Value |
|---|---|
| Operating Temperature | -40°C to 85°C |
| Storage Temperature | -40°C to 85°C |
| Durability | 10,000 mating cycles |
| Drop test | 1.5m free fall |
| Regulator | CE/FCC/BSMI |
Product Description
1. Features
1.1 Lock Function
Supports password-protected locking and unlocking of SD devices using the LOCK/UNLOCK command (CMD42) available in SD command sets.
1.2 Built-in ECC Engine
In the event of errors, the combined data allows for the recovery of the original data. The number of errors that can be recovered depends on the algorithm used.
1.3 Wear-leveling
This function ensures data is not tied to a single physical area, extending the card's life expectancy.
1.4 Read Retry
Allows the read voltage to be dynamically adjusted to decrease or eliminate read errors.
1.5 Early Move
Provides a mechanism to avoid read disturbance. Built-in ECC detects and corrects data bit errors. If error bits reach the default threshold, data is moved to another good block, and the original block is erased to prevent uncorrect errors.
1.6 S.M.A.R.T. function
Transcend Industrial SD Cards support the S.M.A.R.T. command (CMD56), allowing users to read the health information of the SD card. Transcend also offers innovative S.M.A.R.T. features for more efficient status evaluation.
Bus Topology
The SD Memory Card system supports two communication protocols: SD and SPI. The host system selects the mode, and the card detects the requested mode upon reset, expecting all subsequent communication in that mode.
2.1 SD Bus
For detailed information, refer to Section 3.5.1 of the SDA Physical Layer Specification, Version 3.01.
2.2 SPI Bus
For detailed information, refer to Section 3.5.2 of the SDA Physical Layer Specification, Version 3.01.
SD Card Register Information
3.1 OCR Register
The OCR register stores the VDD voltage profile of the card. Refer to Section 5.1 of the SDA Physical Layer Specification, Version 3.01 for more details.
3.2 CID Register
The Card Identification (CID) register is 128 bits wide and contains card identification information used during the identification phase. Each flash card has a unique identification number. The CID register structure includes:
- MID: 8-bit binary number identifying the card manufacturer, controlled by SD-3C, LLC.
- OID: 2-character ASCII string identifying the card OEM and/or contents, controlled by SD-3C, LLC.
- PNM: 5-character ASCII string for the product name, customizable by Transcend.
- PRV: Product revision, composed of two BCD digits representing "n.m" (e.g., "6.2" is 0110 0010).
- PSN: 32-bit binary number for the Serial Number, customizable by Transcend.
- MDT: Manufacturing date, composed of hexadecimal digits for year and month.
- CRC: CRC7 checksum (7 bits).
CSD Register
The CSD register describes fields and data types for standard and High Capacity SD Memory Cards. CSD Version 1.0 applies to Standard Capacity cards, while CSD Version 2.0 applies to High Capacity cards. Cell Type is coded as R (readable), W(1) (writable once), or W (multiple writable).
3.3.1 CSD Register Structure
| CSD_STRUCTURE | CSD Structure version | Card capacity |
|---|---|---|
| 0 | CSD Version1.0 | Standard Capacity |
| 1 | CSD Version2.0 | High Capacity and Extended Capacity |
| 2-3 | reserved | reserved |
3.3.2 CSD Register Structure (CSD Version 1.0)
| Name | Field | Width | Cell Type | CSD-slice |
|---|---|---|---|---|
| CSD structure | CSD_STRUCTURE | 2 | R | [127:126] |
| reserved | - | 6 | R | [125:120] |
| data read access-time-1 | TAAC | 8 | R | [119:112] |
| data read access-time-2 in CLK cycles (NSAC*100) | NSAC | 8 | R | [111:104] |
| max. data transfer rate | TRAN_SPEED | 8 | R | [103:96] |
| card command classes | CCC | 12 | R | [95:84] |
| max. read data block length | READ_BL_LEN | 4 | R | [83:80] |
| partial blocks for read allowed | READ_BL_PARTIAL | 1 | R | [79:79] |
| write block misalignment | WRITE_BLK_MISALIGN | 1 | R | [78:78] |
| read block misalignment | READ_BLK_MISALIGN | 1 | R | [77:77] |
| DSR implemented | DSR_IMP | 1 | R | [76:76] |
| reserved | - | 2 | R | [75:74] |
| device size | C_SIZE | 12 | R | [73:62] |
| max. read current @VDD min | VDD_R_CURR_MIN | 3 | R | [61:59] |
| max. read current @VDD max | VDD_R_CURR_MAX | 3 | R | [58:56] |
| max. write current @VDD min | VDD_W_CURR_MIN | 3 | R | [55:53] |
| max. write current @VDD max | VDD_W_CURR_MAX | 3 | R | [52:50] |
3.3.3 CSD Register (CSD Version 2.0)
| Name | Field | Width | Value | Cell Type | CSD-slice |
|---|---|---|---|---|---|
| CSD structure | CSD_STRUCTURE | 2 | 01b | R | [127:126] |
| reserved | - | 6 | 00 0000b | R | [125:120] |
| data read access-time | (TAAC) | 8 | 0Eh | R | [119:112] |
| data read access-time in CLK cycles (NSAC*100) | (NSAC) | 8 | 00h | R | [111:104] |
| max. data transfer rate | (TRAN SPEED) | 8 | 32h or 5Ah | R | [103:96] |
| card command classes | CCC | 12 | 01x110110101b | R | [95:84] |
| max. read data block length | (READ_BL_LEN) | 4 | 9 | R | [83:80] |
| partial blocks for read allowed | (READ_BL_PARTIAL) | 1 | 0 | R | [79:79] |
| write block misalignment | (WRITE BLK MISALIGN) | 1 | 10 | R | [78:78] |
| read block misalignment | (READ_BLK_MISALIGN) | 1 | 10 | R | [77:77] |
| DSR implemented | DSR IMP | 1 | X | R | [76:76] |
| reserved | - | 6 | 00 0000b | R | [75:70] |
| device size | C_SIZE | 22 | 00 xxxxh | R | [69:48] |
| erase single block enable | (ERASE BLK EN) | 1 | 0 | R | [47:47] |
| erase sector size | (SECTOR_SIZE) | 7 | 7Fh | R | [45:39] |
| write protect group size | (WP_GRP_SIZE) | 7 | 0000000b | R | [38:32] |
| write protect group enable | (WP GRP ENABLE) | 1 | 0 | R | [31:31] |
| reserved | - | 2 | 00b | R | [30:29] |
| write speed factor | (R2W_FACTOR) | 3 | 010b | R | [28:26] |
| max. write data block length | (WRITE BL LEN) | 4 | 9 | R | [25:22] |
| partial blocks for write allowed | (WRITE_BL_PARTIAL) | 1 | 0 | R | [21:21] |
| reserved | - | 5 | 00000b | R | [20:16] |
| File format group | (FILE FORMAT GRP) | 1 | 0 | R/W(1) | [15:15] |
| copy flag (OTP) | COPY | 1 | X | R/W(1) | [14:14] |
| permanent write protection | PERM_WRITE_PROTECT | 1 | X | R/W(1) | [13:13] |
| temporary write protection | TMP_WRITE_PROTECT | 1 | X | R/W | [12:12] |
| File format | (FILE_FORMAT) | 2 | 00b | R | [11:10] |
| reserved | - | 2 | 00b | R | [9:8] |
| CRC | CRC | 7 | xxxxxxxb | R/W | [7:1] |
| not used, always '1' | - | 1 | 1 | - | [0:0] |
RCA Register
3.4 RCA Register
The writable 16-bit relative card address register holds the card address published during the card identification phase. Refer to Section 5.4 in the SDA Physical Layer Specification, Version 3.01 for more information.
SCR Register
3.5 SCR Register
In addition to the CSD register, the SD CARD configuration Register (SCR) provides information on special features configured into the SD memory card. Refer to Section 5.6 in the SDA Physical Layer Specification, Version 3.01 for more information.
SSR Register
3.6 SSR Register
The SD status register contains status bits related to proprietary features and potential future application-specific usage. The SD Status structure is described in Section 4.10.2 in the SDA Physical Layer Specification, Version 3.01.
Order Information
| Capacity | Transcend Part Number |
|---|---|
| 8GB | TS8GUSDC10I |
| 16GB | TS16GUSDC10I |
| 32GB | TS32GUSDC10I |
The technical information provided is based on industry standard data and has been tested for reliability. However, Transcend makes no warranty, expressed or implied, regarding its accuracy and assumes no liability for its use. Transcend reserves the right to change specifications without prior notice. Due to the complexity and variety of industrial applications, it is strongly recommended to contact Transcend or its authorized resellers for compatibility confirmation for special applications and environments.
Contact Information
TAIWAN: E-mail: sales-tw@transcend-info.com
USA (Los Angeles, Maryland, Miami, Silicon Valley): E-mail: sales-us@transcend-info.com
GERMANY: E-mail: sales-de@transcend-info.com
THE NETHERLANDS: E-mail: sales-nl@transcend-info.com
United Kingdom: E-mail: sales-uk@transcend-info.com
JAPAN: E-mail: sales-jp@transcend-info.com
KOREA: E-mail: sales-kr@transcend-info.com
CHINA: E-mail: sales@transcendchina.com
HONG KONG: E-mail: sales-hk@transcend-info.com
Revision History
| Version | Date | Note |
|---|---|---|
| 1.0 | 2016/05/23 | The 1st edition |
| 1.1 | 2016/08/01 | Support CMD56 (S.M.A.R.T. function) |
| 1.2 | 2016/10/05 | Revised CMD56 (S.M.A.R.T. function) Revise pin definition of SPI mode |
| 1.3 | 2018/09/27 | Remove TS64GUSDC10I. |
| 1.4 | 2019/07/03 | Add TS64GUSDC10I |
| 1.5 | 2019/10/28 | Update Performance |
| 1.6 | 2020/04/08 | Update S.M.A.R.T. function |
