IGLOO FPGA Fabric User's Guide

Device Architecture

Device Architecture

Advanced Flash Switch: Unlike SRAM FPGAs, low power flash devices use a live-at-power-up ISP flash switch as their programming element. Flash cells are distributed throughout the device to provide nonvolatile, reconfigurable programming to connect signal lines to the appropriate VersaTile inputs and outputs. In the flash switch, two transistors share the floating gate, which stores the programming information. One is the sensing transistor, used for writing and verification of the floating gate voltage. The other is the switching transistor, used to connect or separate routing nets, or to configure VersaTile logic, and also to erase the floating gate. Dedicated high-performance lines are connected as required using the flash switch for fast, low-skew, global signal distribution throughout the device core, enabling maximum core utilization. The use of flash switch technology also removes the possibility of firm errors common in SRAM-based FPGAs.

FPGA Array Architecture Support

FPGA Array Architecture Support

The flash FPGAs listed in Table 1-1 support the architecture features described in this document.

Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information.

IGLOO Terminology

In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 1-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated.

ProASIC3 Terminology

In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 1-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated.

To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio.

Device Overview

Device Overview

Low power flash devices consist of multiple distinct programmable architectural features:

• FPGA fabric/core (VersaTiles)
• Routing and clock resources (VersaNets)
• FlashROM
• Dedicated SRAM and/or FIFO
  • 30 k gate and smaller device densities do not support SRAM or FIFO.
  • Automotive devices do not support FIFO operation.
• I/O structures
• Flash*Freeze technology and low power modes

I/O State of Newly Shipped Devices

I/O State of Newly Shipped Devices

Devices are shipped from the factory with a test design. The power-on switch for VCC is OFF by default, so I/Os are tristated by default, meaning they are not actively driven and float. The exact value cannot be guaranteed when floating. If there is concern regarding the exact state of unused I/Os, weak pull-up/pull-down should be added to control and stabilize their state.

Core Architecture

Array Coordinates

Array Coordinates

During place-and-route operations in Microsemi Designer software, array coordinates can be set for constraints. Tables 1-2, 1-3, and 1-4 provide array coordinates for core cells and memory blocks for various IGLOO and ProASIC3 devices. The array coordinates are measured from the lower left (0, 0). I/O and cell coordinates are used for placement constraints; the Designer ChipPlanner tool provides I/O location coordinates. Figure 1-9 illustrates array coordinates for a 600 k gate device.

Routing Architecture

Routing Architecture

The routing structure of low power flash devices uses a four-level hierarchy: ultra-fast local resources, efficient long-line resources, high-speed very-long-line resources, and VersaNet global networks. Ultra-fast local resources connect a VersaTile to its eight surrounding neighbors. Efficient long-line resources provide routing for longer distances and higher fanout, spanning one, two, or four VersaTiles. High-speed, very-long-line resources span the entire device with minimal delay. VersaNet global networks are low-skew, high-fanout nets accessible from external pins or internal logic, typically used for clocks, resets, and other high-fanout nets requiring minimum skew.

Related Documents

Related Documents

User's Guides

• Designer User's Guide: http://www.microsemi.com/soc/documents/designer_ug.pdf

List of Changes

List of Changes

The following table lists critical changes that were made in each revision of the chapter.

Flash*Freeze Technology and Low Power Modes

Microsemi IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3L, and Radiation-Tolerant (RT) ProASIC3 FPGAs with Flash*Freeze technology are designed for demanding power and area challenges in portable electronics. These devices offer lower power consumption in static and dynamic modes than other FPGAs or CPLDs. They provide various power-saving modes for ultra-low system power. Low Power Active capability (static idle) allows for ultra-low power consumption while the device is operational, retaining SRAM, registers, I/Os, and logic functions. Flash*Freeze technology provides an ultra-low power static mode that retains all SRAM and register information with rapid recovery to Active mode. IGLOO nano and IGLOO PLUS devices can also retain I/O states. This mechanism allows quick entry and exit from Flash*Freeze mode (within 1 s) by activating the Flash*Freeze (FF) pin, while power supplies remain stable. I/Os and clocks can toggle without impacting device power consumption. While in Flash*Freeze mode, the device retains core register states and SRAM information. Power consumption can be as low as 5 W for IGLOO devices and 2 W for IGLOO nano devices. Microsemi offers a state management IP core to assist with clock gating and data management before entering Flash*Freeze mode.

Flash Families Support the Flash*Freeze Feature

The low power flash FPGAs listed in Table 2-1 support the Flash*Freeze feature.

Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information.

IGLOO Terminology

In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 2-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated.

ProASIC3 Terminology

In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 2-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated.

To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio.

Low Power Modes Overview

Table 2-2 summarizes the low power modes that achieve power consumption reduction when the FPGA or system is idle.

* External clocks can be left toggling while the device is in Flash*Freeze mode. Clocks generated by the embedded PLL will be turned off automatically.

Static (Idle) Mode

Static (Idle) Mode

In Static (Idle) mode, no clock inputs are switching, and only static power is consumed. This mode is achieved by switching off incoming clocks, reducing power consumption. I/Os draw minimal leakage current. Embedded SRAM, I/Os, and registers retain their values, allowing the device to enter and exit this mode by switching clocks on or off. If the embedded PLL is used as the clock source, Static (Idle) mode can be entered by pulling the PLL POWERDOWN pin LOW (active Low), which turns off the PLL.

Flash*Freeze Mode

Flash*Freeze Mode

IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3L, and RT ProASIC3 FPGAs offer an ultra-low static power mode that reduces power consumption while preserving the state of registers, SRAM, and I/O states (IGLOO nano and IGLOO PLUS only) without switching off power supplies, inputs, or input clocks. Flash*Freeze technology enables switching to Flash*Freeze mode within 1 s, simplifying low power design. The Flash*Freeze (FF) pin (active Low) is a dedicated pin for direct entry/exit, or it can be routed internally to the FPGA core and state management IP for application-controlled transitions. If the FF pin is not used, it can serve as a regular I/O. The FF pin has a built-in glitch filter and optional Schmitt trigger (not available for all devices) to prevent accidental entry/exit. There are two usage types:

Flash*Freeze Type 1: Control by Dedicated Flash*Freeze Pin

Flash*Freeze type 1 is for systems where the device will be reset upon exiting Flash*Freeze mode, or data and clock are managed externally. The device enters Flash*Freeze mode 1 s after the FF pin is asserted (active Low) and returns to normal operation when the FF pin is deasserted (High). FF pin assertion/deassertion is the sole condition for entry/exit. In Libero System-on-Chip (SoC) software v8.2 and earlier, this mode is enabled in Compile options. From Libero software v8.3 onwards, an INBUF_FF I/O macro must be instantiated to identify the Flash*Freeze input. Microsemi recommends this new implementation.

Flash*Freeze Type 2: Control by Dedicated Flash*Freeze Pin and Internal Logic

The device enters Flash*Freeze mode by activating the FF pin along with Microsemi's Flash*Freeze management IP core or user-defined control logic within the FPGA core. This allows important activities before entering Flash*Freeze mode, such as transitioning to a safe state or completing critical events. Designers are encouraged to use the Flash*Freeze Management IP for clean entry/exit. The device enters Flash*Freeze mode when the FF pin is asserted (active Low) and the User Low Static ICC (ULSICC) macro input signal (LSICC) is asserted (High). Both conditions are required. The ULSICC macro needs to be instantiated by the user. The LSICC signal controls entry into Flash*Freeze mode. After exiting Flash*Freeze mode by deasserting the FF pin, the LSICC signal must be deasserted by the user design to prevent re-entry.

Table 2-3 details the assertion and deassertion values for the FF pin and LSICC signal.

Notes: 1. The Flash*Freeze (FF) pin is an active-Low signal, and LSICC is an active-High signal. 2. The LSICC signal is used only in Flash*Freeze mode type 2.

Table 2-4 summarizes Flash*Freeze mode implementations.

Note: Refer to Table 2-3 on page 26 for Flash*Freeze pin and LSICC signal assertion and deassertion values.

IGLOO, ProASIC3L, and RT ProASIC3 I/O State in Flash*Freeze Mode

In IGLOO and ProASIC3L devices, I/Os become tristated in Flash*Freeze mode. If weak pull-up or pull-down is used, I/Os maintain the configured status. Table 2-5 shows I/O pad state based on configuration and buffer type.

* Internal core logic driven by this input/global buffer will be tied High as long as the device is in Flash*Freeze mode.

IGLOO nano and IGLOO PLUS I/O State in Flash*Freeze Mode

In IGLOO nano and IGLOO PLUS devices, users can configure I/Os during Flash*Freeze mode in multiple ways: 1. Hold the previous state. 2. Set I/O pad to weak pull-up or pull-down. 3. Tristate I/O pads. Configuration is done per pin via the I/O Attribute Editor or a PDC constraint file. The output hold feature retains the last registered state. Input hold feature retains the last valid input pad state. Table 2-6 shows I/O pad state based on configuration and buffer type.

Notes: 1. Internal core logic driven by this input buffer will be set to the value this I/O had when entering Flash*Freeze mode. 2. Internal core logic driven by this input buffer will be tied High as long as the device is in Flash*Freeze mode. 3. For bidirectional buffers: Internal core logic driven by the input portion of the bidirectional buffer will be set to the hold state.

Flash*Freeze Mode Device Behavior

Flash*Freeze Mode Device Behavior

Entering Flash*Freeze Mode

• Devices enter Flash*Freeze mode when power supplies are stable. If powering up while FF pin is asserted (Type 1) or both FF and LSICC are asserted (Type 2), the device enters Flash*Freeze mode within 5 s after activation levels are reached.
• If already powered up, entry is within 1 s after FF pin assertion (Type 1) or both FF and LSICC assertion (Type 2). Exit is within 1 s after FF pin deassertion.
• PLLs: Entering Flash*Freeze mode automatically powers down the PLL. Output clocks stop toggling within 1 s, and I/Os transition to their specified Flash*Freeze state. The user design must ensure safe entry.
• I/Os and Globals: Inputs, globals, and PLLs enter their Flash*Freeze state asynchronously, potentially causing glitches or narrow pulses. I/O banks do not deactivate simultaneously. Inputs and globals tie High internally (except with hold state on nano/PLUS devices). Asynchronous input-to-output paths may glitch; use latches to prevent this.
• For Type 2, ensure the LSICC signal remains asserted High to reliably enter Flash*Freeze mode.

During Flash*Freeze Mode

• PLLs are off.
• I/O pads are configured per tables.
• Inputs and clocks can toggle with minimal power consumption if weak pull-up/down is not selected.
• Toggling signals charge/discharge package pin capacitance.
• IGLOO/ProASIC3L outputs are tristated unless configured with weak pull-up/down. Core output is High.
• IGLOO nano/IGLOO PLUS output behavior depends on user configuration.
• JTAG is active but operations are disabled. TCK should be static to avoid dynamic power consumption.
• FF pin must be asserted to stay in Flash*Freeze mode and is used to exit when deasserted.

Exiting Flash*Freeze Mode

• Inputs and globals exit their Flash*Freeze state asynchronously, potentially causing glitches.
• I/O banks activate asynchronously.
• Inputs and globals no longer tie High internally.
• Output hold state transitions are asynchronously controlled by the output signal for clean exit.
• PLLs require maximum acquisition time after exiting.

Flash*Freeze Pin Locations

Refer to device datasheets for Flash*Freeze pin location, which is independent of the device, allowing board-level consistency.

Sleep and Shutdown Modes

Sleep and Shutdown Modes

Sleep Mode

IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3L, and RT ProASIC3 FPGAs support Sleep mode when functionality is not required. VCC (core voltage), VJTAG, and VPUMP are grounded, turning off the FPGA core to reduce power. Driven inputs do not pull up internal power planes, limiting current draw to leakage. Table 2-7 shows power supply status in Sleep mode.

Refer to the "Power-Up/-Down Behavior" section on page 33 for more information.

Shutdown Mode

Shutdown mode is supported for IGLOO nano, IGLOO PLUS, and specific IGLOO/e devices (AGL015, AGL030, AGLE600, AGLE3000, A3PE3000L). It turns off all power supplies when the device is not needed. Cold-sparing and hot-insertion features allow power-down without system shutdown. The live-at-power-up feature enables operation after voltage activation.

Using Sleep and Shutdown Modes in the System

Using Sleep and Shutdown Modes in the System

Microprocessors can control power FETs or voltage regulator shutdown pins to manage power supplies for the device. Figure 2-6 shows microprocessor control via a power FET. Figure 2-7 shows control via a voltage regulator's shutdown pin.

Power-Up/-Down Behavior

All IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3L, and RT ProASIC3 I/Os are tristated before power-up and remain tristated until the last voltage supply (VCC or VCCI) reaches its activation level. During power-down, I/Os become tristated once the first power supply (VCC or VCCI) drops below its deactivation voltage. Figure 2-8 shows a timing diagram for VCC power supply ramp-up/down.

Context Save and Restore in Sleep or Shutdown Mode

In Sleep or Shutdown mode, SRAM, I/O, and register contents are lost without external measures. A serial EEPROM can save and restore device contents. Microcontrollers can manage this by reading data from the FPGA before powering down and loading it back after power-up.

Flash*Freeze Design Guide

Flash*Freeze Design Guide

This section guides designers in creating reliable designs using Flash*Freeze modes optimally. It covers selecting the right mode, design solutions for clocks, set/reset, I/Os, JTAG, and ULSICC, and details Microsemi's Flash*Freeze Management IP. Additional power conservation techniques are also discussed.

Selecting the Right Flash*Freeze Mode

Both Flash*Freeze modes retain register and SRAM content and set I/Os to a predetermined configuration. Type 2 mode offers an opportunity to wait for a second signal (internal or external) before activation, allowing for clean management of clocks and data, and performing housekeeping functions. Type 1 is suited for applications where entry is solely dependent on the FF pin, no internal housekeeping is needed, and the device is reset upon exit or external state saving is performed. Type 2 is recommended for most designs, especially when state saving is required and incoming data is not externally guaranteed valid.

Design Solutions

Clocks: Microsemi recommends synchronous design with Flash*Freeze management IP for clean clock gating. During entry/exit, external clocks may tie High internally or float; use weak pull-up if floating. Clock gating filters unwanted narrow pulses. Gating clocks LOW improves static power of RAM blocks. Drive FF port of RAM blocks with Flash*Freeze_Enabled signal.

Set/Reset: Use active low set/reset at the top-level port. A self-reset circuit can be implemented using an active High set/reset input pin with an internal pull-up.

I/Os: Release undriven inputs only after the device enters Flash*Freeze mode. Asynchronous input-to-output paths may glitch; use latches with management IP to gate these paths.

JTAG: TCK should be static during Flash*Freeze mode to prevent dynamic power consumption.

ULSICC: The ULSICC macro accesses the Flash*Freeze Technology block. The LSICC input must remain asserted High for reliable entry into Flash*Freeze mode.

Flash*Freeze Management IP: This IP offers a robust RTL block for clean clock gating and housekeeping before entering/exiting Flash*Freeze mode. It comprises the Flash*Freeze FSM, clock gating (filter) block, and ULSICC macro.

Flash*Freeze Management FSM: A state machine that controls clock gating, ULSICC, and housekeeping. It asserts WAIT_HOUSEKEEPING for user logic to perform shutdown processes and Flash_Freeze_Enabled when the device enters Flash*Freeze mode.

Clock Gating Block: Initiated by the FSM, this circuit gates clocks in less than two cycles using flip-flops, latches, and AND gates.

Design Flow: For Libero IDE v8.3+, Flash*Freeze type 1 uses INBUF_FF. Type 2 uses the Flash*Freeze management IP, which includes INBUF_FF and ULSICC. Manual instantiation is also possible.

INBUF_FF: A special input buffer macro that forces the top-level port to the dedicated FF pin, enabling Flash*Freeze mode. Only one INBUF_FF can be instantiated per device.

ULSICC: Enables core access to Flash*Freeze Technology for mode control. Requires INBUF_FF for Type 2 mode. If not instantiated, LSICC port is tied High.

Flash*Freeze Management IP: Configured via Libero/SmartGen core generator. Includes clock gating, ULSICC macro, and INBUF_FF. Clock gating adds skew; analyze setup/hold times carefully.

Power Analysis: SmartPower tool estimates static and dynamic power consumption, providing detailed reports and battery life estimates based on operational modes.

Additional Power Conservation Techniques: Use minimum I/O banks, tie unused power supplies to ground, leave unused I/O ports floating, use lowest voltage I/O standard, lowest drive strength, and slowest slew rate. Deselect unused RAM blocks. Gate clocks LOW. Drive FF port of RAM blocks with Flash*Freeze_Enabled. Drive inputs to full voltage levels. Avoid pull-ups/downs on I/Os. Minimize I/O usage across devices.

Conclusion

Conclusion

Microsemi IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3L, and RT ProASIC3 families achieve ultra-low power consumption via enhanced nonvolatile flash-based technology. Flash*Freeze, Static (Idle), Sleep, and Shutdown modes further reduce power, making them ideal for power-sensitive, battery-operated applications.

Related Documents

Related Documents

Application Notes

• Embedded SRAM Initialization Using External Serial EEPROM: http://www.microsemi.com/soc/documents/EmbeddedSRAMInit_AN.pdf

List of Changes

List of Changes

The following table lists critical changes that were made in each revision of the chapter.

Introduction

IGLOO, Fusion, and ProASIC3 FPGA devices feature a powerful, low-delay VersaNet global network and extensive support for multiple clock domains. This includes Clock Conditioning Circuits (CCCs), phase-locked loops (PLLs), and a comprehensive global clock distribution network called a VersaNet global network. Each logical element (VersaTile) input and output port accesses these global networks, which can distribute low-skew clock signals or high-fanout nets. These segmented networks contain spines (vertical branches) and ribs that reach all VersaTiles within their region, allowing flexible creation of low-skew local clock networks. This document details VersaNet global networks and their assignment in a design flow. PLL details are in the "Clock Conditioning Circuits" section. This chapter covers the global architecture and usage of these networks.

Global Architecture

Low power flash devices offer powerful and flexible control of circuit timing via global circuitry. Each chip has up to six CCCs, some with PLLs. IGLOOe, ProASIC3EL, and ProASIC3E devices have six PLLs per device (except PQ208 package with 2 PLLs). IGLOO, IGLOO nano, IGLOO PLUS, ProASIC3, and ProASIC3L devices have a PLL core in the west CCC (except 10 k through 30 k devices). Fusion devices also have a PLL core in the west CCC; larger Fusion devices (AFS600, AFS1500) have PLLs in both west and east CCCs. Each PLL includes delay lines, phase shifters, and clock multipliers/dividers. CCCs contain circuitry for selecting and interconnecting inputs to the VersaNet global network. East and west CCCs access three chip global lines each, totaling six. Corner CCCs access three quadrant global lines each (except 10 k-30 k devices). Nano 10 k, 15 k, 20 k devices support four VersaNet global resources; 30 k devices support six. 10 k-30 k devices use simplified CCCs called CCC-GLs. The VersaNet global network allows routing external or gated internal clocks using fast, low-skew resources for high-fanout nets, including clocks. It enables creation of low-skew local clock networks using spines for up to 252 internal/external clocks or high-fanout nets, significantly improving design performance.

Global Resource Support in Flash-Based Devices

The flash FPGAs listed in Table 3-1 support the global resources and functions described in this document.

Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information.

IGLOO Terminology

In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO products as listed in Table 3-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated.

ProASIC3 Terminology

In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 3-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated.

To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio.

VersaNet Global Network Distribution

Low power flash architecture offers powerful, low-delay VersaNet global networks accessing VersaTiles, SRAM, and I/O tiles. Each device has a chip global network with six global lines (except nano 10 k, 15 k, 20 k devices) distributed from the array center. Devices (except 10 k-30 k gate) have four quadrant global networks, each with three quadrant global net resources, driving signals only within their quadrant. Each VersaTile accesses nine global line resources (three quadrant, six chip-wide), totaling 18 globals per device (3x4 regional + 6 global). Figure 3-1 shows the VersaNet global network overview for devices 60 k and above. Figures 3-2 and 3-3 show simplified networks. VersaNet networks are segmented with spines, global ribs, and multiplexers (MUXes), driven from the center or north/south sides. MUX trees access spines, which use clock ribs to reach VersaTiles. These networks provide fast, low-skew routing for high-fanout nets like clocks, enabling low-skew local clock networks using spines for up to 252 internal/external clocks or nets, improving design performance.

Chip and Quadrant Global I/Os

Chip and Quadrant Global I/Os

Naming of Global I/Os

In low power flash devices, global I/Os access clock conditioning circuitry and have direct access to the global network. They can also function as regular I/Os. The naming convention Gmn/IOuxwByVz indicates a global input pin (Gmn) and a regular I/O pin (IOuxwByVz). Figure 3-4 illustrates global input pin connections, showing 54 global pins accessing 18 global networks in ProASIC3E families.

Figure 3-5 shows detailed global input connections for the northwest quadrant, illustrating global input pins (GAA0-GAA2) connected to MUXes for CLKA, CLKB, CLKC, feeding into a CCC. Each global buffer and PLL reference clock can be driven by dedicated single-ended I/Os, differential I/Os (not for nano devices), or the FPGA core.

Figure 3-6 shows nine global inputs for location A connected to the top left quadrant global network via CCC, with MUXes for CLKA, CLKB, CLKC.

Since each bank can have different I/O standards, choose the correct global I/O. 54 global pins access 18 global networks. For single-ended and voltage-referenced standards, any of three available I/Os can access the global network. For differential standards (LVDS, LVPECL), specific I/O macros must be used. Unassigned global I/Os can be regular I/Os. GF and GC pins are for chip global networks; GA, GB, GD, GE are for quadrant global networks. Tables 3-2 and 3-3 list chip and quadrant global pin names.

Note: Only one of the I/Os can be directly connected to a quadrant at a time.

Note: Only one of the I/Os can be directly connected to a quadrant at a time.

Unused Global I/O Configuration

Unused clock inputs behave like unused Pro I/Os. Microsemi Designer software automatically configures unused global pins as inputs with pull-up resistors if not used as regular I/Os.

I/O Banks and Global I/O Standards

Any I/O or internal logic can drive the global network. Only global macros at global pins use hardwired connections. Global signal assignment to I/O banks is similar to regular I/O assignment, with pin placement location being the only constraint. Global signals compatible with VCCI and VREF standards can be assigned to the same bank.

Spine Architecture

Low power flash device architecture segments VersaNet global networks into spines (vertical branches) and ribs, reaching all VersaTiles within a region. Nine spines per vertical column exist in global networks, divided into quadrant global networks (three spines) and chip global networks (six spines). Spine access is via dedicated global network MUX trees. Spine drivers are in the die center. Quadrant spines are driven from user I/Os or internal signals on north/south sides. Driving spines in quadrant networks significantly impacts system performance for high-fanout inputs. Access to top quadrant spine regions is from the top, bottom from the bottom. The A3PE3000 device has 28 clock trees, each with nine spines, enabling mapping of up to 252 different clocks.

Note: *Clock trees that are located at far left and far right will support more VersaTiles.

Spine Access

Spines, identified as Tn or Bn (n indicating horizontal location), are vertical branches of the global network tree. Chip global networks have six spines per tree, quadrant global networks have three. Spine segments (top/bottom) have the same height. Signals assigned only to top/bottom spines cannot access the middle two rows. Quadrant spines do not cross the die middle. Each spine and its ribs cover a region (scope). Spines are accessed by MUX trees, driven by global networks or user nets. Spine drivers are in the die center. Quadrant spines can be driven from user I/Os or internal signals on north/south sides. Driving spines in quadrant networks impacts performance. Access to top quadrant spine regions is from the top, bottom from the bottom. A3PE3000 has 28 clock trees, each with nine spines, allowing up to 252 clocks.

A spine is a local clock network accessed by dedicated global MUX architecture. MUXes define spine driving signals. Chip global spine MUXes are in the die middle; quadrant spine MUXes are on north/south sides. Driving T1 and B1 quadrant spines from the same signal is not recommended.

Using Clock Aggregation

Clock aggregation allows balanced clock trees for improved skew. Physical regions are defined left-to-right, shifting by one spine. Chip global networks offer three types of aggregation: driving up to four, two, or one adjacent spine. Quadrant spines also offer three types: driving up to four, two, or one adjacent spine via I/Os or local resources. A3PE600/AFS600 have twelve spine locations (T1-T6, B1-B6). Table 3-7 shows spine aggregation options.

Quadrant spine aggregation can cross quadrants (e.g., T1:T4) but not top-to-bottom (T1:B1 is illegal). Clock aggregation is hardwired; using buffers for non-adjacent spines may add skew.

Design Recommendations

Design Recommendations

Global Macros and I/O Standards

Larger low power flash devices have six chip and four quadrant global networks. Clock macros (CLKBUF, CLKBUF_x, CLKINT, CLKDLY) are used for assigning signals to these networks. Table 3-8 lists clock macros. Use I/O-standard-specific macros (CLKBUF_x) for direct assignment; changing standards later requires MVN or PDC. CLKBUF defaults to LVTTL. Table 3-9 lists I/O standards for CLKBUF.

Note: IGLOO nano and ProASIC nano devices do not support differential inputs.

Notes: 1. Supported in only the IGLOOe, ProASIC3E, AFS600, and AFS1500 devices 2. By default, the CLKBUF macro uses the 3.3 V LVTTL I/O technology.

VHDL Example for CLKBUF_LVCMOS25 instantiation:

component clkbuf_lvcmos25 port (pad : in std_logic; y : out std_logic); end component; u2 : clkbuf_lvcmos25 port map (pad => ext_clk, y => int_clk);

Verilog Example for CLKBUF_LVCMOS25 instantiation:

module design (______); input _____; output ______; clkbuf_lvcmos25 u2 (.y(int_clk), .pad(ext_clk); endmodule

Global Macro and Placement Selections

Low power flash devices offer three global input pad locations to connect to CCCs or global/quadrant networks. For 60K gate devices and above, single-ended I/O standards allow choosing one of three global input pads; other locations act as regular I/Os. Differential I/O standards pair inputs. Internal clock signals can also feed the global network. A multiplexer tree selects the input. Global I/O pads can also be regular I/Os.

Hardwired I/O Clock Source

Hardwired I/Os are global input pins directly connected to the multiplexer tree accessing global buffers. These pins have designated locations (Gmn, where m is position, n is MUX/pin number). This provides less delay. Figure 3-11 illustrates connections. CLKBUF macro inputs can be placed at nine dedicated global input pin locations (GmA0-GmA2, GmB0-GmB2, GmC0-GmC2). Placement determines chip vs. quadrant global usage (Figure 3-12, 3-13).

External I/O or Local signal as Clock Source

External I/Os (IOuxwByVz) can access the global network via internal routing using the CLKINT macro. Alternatively, PDC can promote signals from external I/Os or internal signals to the global network, but this may cause logic replication. Figure 3-14 shows CLKINT macro usage.

Using Global Macros in Synplicity

Synplify synthesis tool automatically inserts global buffers for high-fanout nets. By default, it inserts six global macros (CLKBUF or CLKINT), honoring user instantiations. A PLL uses 1-3 buffers. Synplify's global counting rule applies to CLKBUF, CLKINT, CLKDLY, and PLLs. The `syn_global_buffers` attribute limits the number of inserted globals. `syn_global_minfanout` promotes only high-fanout signals. Note that only six signals can be assigned to chip global networks; others must use quadrant networks.

Global Promotion and Demotion Using PDC

HDL source files or schematics are preferred for defining global signal assignments using clock macro instantiation. This prevents synthesis tool replication. PDC can promote signals to global networks or demote global macros to regular ones. `assign_global_clock -net netname` promotes a regular net to a chip global clock, inserting CLKINT. `assign_local_clock -net netname -type quadrant UR|UL|LR|LL` promotes to a quadrant clock. `unassign_global_clock -net netname` demotes global signals, changing CLKBUF_x to INBUF_x and removing CLKINT. Demotion is recommended only for small-fanout nets due to potential timing/routability issues.

Spine Assignment

Global networks can be segmented into spines (local clock networks). PDC or MVN can assign signals to spines using `assign_local_clock -net netname -type [quadrant|chip] Tn|Bn|Tn:Bm`. Designer demotes clock nets driven by macros before spine assignment. PLL or CLKDLY macro nets cannot be assigned to local clocks. Designer legalizes shared instances during Compile; MVN does not. Figure 3-16 illustrates PDC spine assignment for shared instances.

The number of shared instances can be controlled via Designer's Compile Option dialog box (Figure 3-17).

Designer Flow for Global Assignment

Global management is crucial during synthesis and place-and-route. Synplify defaults to six global buffers; quadrant assignment requires manual PDC or increased Synplify globals. Designer v6.2+ supports automatic quadrant global assignment. Steps for layout and timing improvement:

1. Run Compile, check Compile report for global information (Device Utilization, Net Report).
2. Promote high-fanout signals to global using compile options (e.g., "Promote regular nets whose fanout is greater than") or PDC. Figure 3-18 shows the Globals Management GUI.
3. Demote global nets with low fanout using compile options or PDC to free up global networks.
4. Use local clock networks (spines) for low-skew, non-chip-wide signals via PDC.
5. Assign I/O buffers using MVN if I/O assignment is fixed. Do not place multiple CLKBUF macros on the same three sets of global pins. Click "Commit" in MVN for pre-layout checks.
6. Run Compile with "Keep existing physical constraints" to verify MVN assignments.
7. Run Layout and check timing.

Simple Design Example

Example: A3PE600-PQ208 device with six shift registers, two PLLs, a global reset (ACLR), an enable (EN_ALL), and three external clock domains (QCLK1, QCLK2, QCLK3). PQ208 has two PLLs accessing chip global networks. Global reset/enable need chip globals due to fanout. Two remaining clocks (QCLK1, QCLK2) are assigned to quadrant globals via PDC.

Step 1: Run Synthesis; check device utilization report (e.g., 1536 DFN1E1C1, 278 INBUF, 10 CLKBUF).

Step 2: Run Compile; report shows 8 globals used (5 auto-promoted, 3 essential). Designer will promote more and assign two to quadrant globals.

Step 3 (optional): Assign QCLK1_c to quadrant UL and QCLK2_c to quadrant LL using PDC.

Step 4: Re-run Compile with PDC; report shows QCLK1_c and QCLK2_c assigned to quadrant resources.

Step 5: Run Layout.

Global Management in PLL Design

Use dedicated global pins to drive PLL reference clock inputs for reduced delay and distortion. Low power flash devices allow other signals to connect to reference clock inputs. Each PLL is associated with three global networks. Limitations: using a PLL with only primary output leaves two free global networks; using three globals associated with a PLL location prevents PLL use there; YB/YC outputs occupy a global even if not used for global networks.

Using Spines of Occupied Global Networks

When a signal is assigned to a global network, flash switches program MUX select lines to drive spines. If a global net is restricted from a spine's scope, its MUX drivers can be used for other signals. Example: Limit CLK1_c to the left half of the chip and use the right side for CLK2_c via PDC (Figure 3-20).

Conclusion

IGLOO, Fusion, and ProASIC3 devices offer 18 global networks (6 chip, 12 quadrant), segmentable into local low-skew spines. These spines support high-fanout signals, enabling up to 252 clocks in an A3PE3000 device. This document details the global network architecture and assignment methodologies.

Related Documents

User's Guides

• IGLOO, ProASIC3, SmartFusion, and Fusion Macro Library Guide: http://www.microsemi.com/soc/documents/pa3_libguide_ug.pdf

List of Changes

List of Changes

The following table lists critical changes that were made in each revision of the chapter.

Introduction

This document outlines Clock Conditioning Circuit (CCC) features, PLL core specifications, functional descriptions, software configuration, usage, board-level considerations, and other aspects of clock conditioning circuits and global networks in low power flash devices and mixed signal FPGAs.

Overview of Clock Conditioning Circuitry

In Fusion, IGLOO, and ProASIC3 devices, CCCs implement frequency division, multiplication, phase shifting, and delay operations. CCCs are located at six chip positions: four corners and the middle of east/west sides. Each CCC contains a PLL core, three phase selectors, six programmable delays, one fixed delay, and a dynamic shift register for reconfiguration. Figure 4-1 shows a simplified block diagram of CCC building blocks.

Each CCC can implement up to three independent global buffers (with or without programmable delay) or a PLL function with up to three global outputs. Unused PLL outputs can serve as independent global buffers, up to three per CCC.

CCC Programming

CCC blocks are fully configurable via flash configuration bits or an asynchronous shift register interface, allowing dynamic parameter changes during operation. Configuration data is stored in flash memory during device programming or written to the shift register during operation, enabling dynamic reconfiguration without core reprogramming. The shift register uses a simple serial interface. Refer to "UJTAG Applications" or the "Using Global Resources in Actel Fusion Devices" application note.

Global Resources

Low power flash and mixed signal devices provide three global routing networks (GLA, GLB, GLC) per CCC location. Global I/O locations can be chosen from three possibilities via a multiplexer tree. CCCs can be used before signals connect to global networks. CCCs at corners drive quadrant global networks; CCCs on east/west sides drive chip global networks. Quadrant networks span a quarter of the device; chip networks span the entire device. Refer to "Global Resources in Low Power Flash Devices" section for more details.

A global buffer can be placed in any of the three global locations (CLKA-GLA, CLKB-GLB, CLKC-GLC) of a CCC. A PLL macro uses CLKA for its reference clock and GLA, optionally GLB/GLC, for global outputs. PLLs can also drive YB/YC core outputs. GLB/GLC cannot be reused if YB/YC are used.

Each global buffer and PLL reference clock can be driven by: 3 dedicated single-ended I/Os, 2 dedicated differential I/Os (not for nano devices), or the FPGA core.

CCC Support in Microsemi's Flash Devices

The flash FPGAs listed in Table 4-1 support the CCC feature.

Note: *The device names link to the appropriate datasheet, including product brief, DC and switching characteristics, and packaging information.

IGLOO Terminology

In documentation, the terms IGLOO series and IGLOO devices refer to all of the IGLOO devices as listed in Table 4-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated.

ProASIC3 Terminology

In documentation, the terms ProASIC3 series and ProASIC3 devices refer to all of the ProASIC3 devices as listed in Table 4-1. Where the information applies to only one product line or limited devices, these exclusions will be explicitly stated.

To further understand the differences between the IGLOO and ProASIC3 devices, refer to the Industry's Lowest Power FPGAs Portfolio.

Global Buffers with No Programmable Delays

Global/quadrant networks can be accessed directly from global I/O buffers, bypassing CCCs (dotted lines in Figure 4-1). Internal signals use the global/quadrant networks via the routed clock input of the multiplexer tree. Specific CLKBUF macros support various single-ended I/O inputs and differential I/O standards (CLKBUF_LVDS/LVPECL) for direct connection to global/quadrant networks. Nano devices do not support differential inputs. For internal signals, the CLKINT macro connects to the network's MUX tree routed clock input. CLKBUF, CLKBUF_LVPECL/LVDS, and CLKINT macros are used for direct connection (Figure 4-2). CLKBUF and CLKBUF_LVPECL/LVDS macros are composite, including an I/O macro driving a global buffer with hardwired connection. CLKINT provides a global buffer driven internally by the FPGA core. CLKBUF macros are detailed in the Macro Library Guide.

Global Buffer with Programmable Delay

Clocks needing adjustment can use programmable delay cores before connecting to global/quadrant networks. Up to 18 CCC global buffers per device can be instantiated (three per CCC, six CCCs per device). Each CCC has a programmable delay element for each global network (up to three). Users utilize these features via corresponding macros (Figure 4-3).

The CLKDLY macro delays clock inputs using a programmable delay element, providing phase shift. It can be driven by an INBUF* macro for a composite macro with hardwired connection. Many INBUF macros support various I/O standards. The CLKDLY macro can be driven directly from the FPGA core or via routed I/O using the PLLINT macro. SmartGen tool allows visual configuration of delay and input source selection, automatically instantiating PLLINT when needed.

CLKDLY Macro Signal Descriptions

The CLKDLY macro has one input (CLK) and one output (GL).

CLKDLY Macro Usage

When CLKDLY is used in a CCC, programmable delay elements connect clocks to the global network. The PLL can be bypassed in CCCs with PLLs, using only the programmable delay. CCCs without PLLs also use CLKDLY for programmable delay. Delay elements are the same for PLL and CLKDLY. CCCs with PLLs can use programmable delay elements (Type 2) for global networks A, B, C, bypassing the PLL. CCCs without PLLs contain only programmable delay blocks (Type 2).

Global Buffers with PLL Function

Clocks requiring frequency synthesis or adjustments can use the PLL core before connecting to global/quadrant networks. Up to 18 CCC global buffers can be instantiated per device. Each PLL core generates up to three global/quadrant clocks; a clock delay element provides one. The PLL macro supports this functionality (Figure 4-4).

The PLL macro generates five derived clocks (three independent) from a single reference clock, plus power-down input and lock output. Configuration settings are managed via SmartGen. Figure 4-6 illustrates clock output options and delay elements.

PLL Macro Signal Descriptions

The PLL macro supports two inputs (CLKA, EXTFB, POWERDOWN) and up to six outputs (GLA, GLB, YB, GLC, YC, LOCK).

Input Clock

PLL reference clock inputs (CLKA) can come from global input pins, regular I/O pins, or internally from the core. Fusion families can also use embedded RC or crystal oscillators.

Global Output Clocks

GLA (Primary), GLB (Secondary 1), and GLC (Secondary 2) are outputs of Global Multiplexers 1, 2, and 3, driving high-speed global/quadrant networks. Each global multiplexer block includes input routing, output multiplexer, and delay elements.

Core Output Clocks

YB and YC are Core Outputs, driving internal logic without using global network resources, useful for conserving globals. They are identical to GLB and GLC, respectively, but with higher selectable final output delay. SmartGen configures these outputs and can enable them with or without Global Output Clocks.

PLL Macro Block Diagram

The PLL supports three distinct output frequencies from one input clock. GLB and GLC can route to B and C global networks or device core (YB, YC). Five delay elements support phase control on all five outputs. Feedback loop delays advance the clock relative to the reference. PLL reference clock can be driven by INBUF* macro (hardwired connection to global I/O), directly from FPGA core, or via routed I/O using PLLINT macro. During power-up, PLL outputs toggle around VCO frequency (40 MHz to 250 MHz) until CLKA is constant. POWERDOWN signal can prevent this. SmartGen derives internal divider ratios based on user-specified frequencies.

SmartGen allows selection of delay and phase shift values for reference clock (CLKA) and derived clocks (GLA, GLB, GLC, YB, YC). It also selects input clock source and automatically instantiates PLLINT when needed.

Global Input Selections

Low power flash devices offer three global input pad locations to connect to CCCs or global/quadrant networks. Figures 4-7 and 4-8 show global input structures for 30 k gate devices and below, and 60 k gate devices and above, respectively. For 60 k+ devices, single-ended I/O standards allow choosing one of three global input pads; others act as regular I/Os. Differential I/O standards pair inputs. Internal clock signals can also feed the global network or CCCs. A multiplexer tree selects the input. Global I/O pads can also be regular I/Os.

Each global buffer and PLL reference clock can be driven by: 3 dedicated single-ended I/Os, 2 dedicated differential I/Os (not for nano devices), or the FPGA core. I/O types supported for globals vary by device size: LVDS sources on 250 k+ gate devices (nano devices do not support differential inputs). 60 k/125 k gate devices support single-ended sources only. 15 k/30 k gate devices support inputs for CCC only and lack PLLs. Nano devices: 10 k, 15 k, 20 k support CLKBUF and CLKINT only (no PLLs). 60 k, 125 k, 250 k support one PLL in the middle left CCC; corner CCCs support CLKBUF, CLKINT, CLKDLY. Fusion devices (AFS600, AFS1500) support all I/O standards; AFS090/AFS250 support single-ended and differential.

Clock Sources for PLL and CLKDLY Macros

Input reference clocks (CLKA for PLL, CLK for CLKDLY) access CCCs via multiplexer trees. Sources include: Hardwired I/O, External I/O, Core Logic, RC Oscillator (Fusion only), Crystal Oscillator (Fusion only). SmartGen macro builder is recommended for creating PLL and CLKDLY macros.

Hardwired I/O Clock Source

Hardwired I/Os are global input pins directly connected to the multiplexer tree accessing CCC global buffers. They have designated locations (Gmn). This provides less delay. Figure 4-9 illustrates connections for 60 k+ gate devices, showing CLKBUF/CLKDLY inputs at nine global pin locations. For PLL macros, clock input connects only to GmA0, GmA1, or GmA2.

External I/O Clock Source

External I/Os (regular I/O pins) access CCCs via internal routing using INBUF options. Assign input to any IOuxwByVz location. Figure 4-11 briefly explains external I/O usage. This option offers flexibility but requires additional file metadata.