User Guide for intel models including: AN 775 Generating Initial I O Timing Data, AN 775, Generating Initial I O Timing Data, Initial I O Timing Data, Timing Data
Centre de développement FPGA : guides de l’utilisateur Intel Agilex...
Ressources de conception du centre de développement Intel Cyclone 10...
Intel Stratix 10 FPGA Developer Design Center Resources | Intel
File Info : application/pdf, 9 Pages, 450.49KB
DocumentDocumentAN 775: Generating Initial I/O Timing Data for Intel FPGAs Updated for Intel® Quartus® Prime Design Suite: 19.3 Online Version Send Feedback AN-775 ID: 683103 Version: 2019.12.08 Contents Contents 1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs........................................... 3 1.1. Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device.................................... 4 1.2. Step 2: Define I/O Standard and Pin Locations ......................................................... 5 1.3. Step 3: Specify Device Operating Conditions............................................................. 6 1.4. Step 4: View I/O Timing in Datasheet Report............................................................ 6 1.5. Scripted I/O Timing Data Generation........................................................................8 1.6. AN 775: Generating Initial I/O Timing Data Document Revision History.........................9 AN 775: Generating Initial I/O Timing Data: for Intel FPGAs 2 Send Feedback 683103 | 2019.12.08 Send Feedback 1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs You can generate initial I/O timing data for Intel FPGA devices using the Intel® Quartus® Prime software GUI or Tcl commands. Initial I/O timing data is useful for early pin planning and PCB design. You can generate initial timing data for the following relevant timing parameters to adjust the design timing budget when considering I/O standards and pin placement. Table 1. I/O Timing Parameters Timing Parameter Description Input setup time (tSU) Input hold time (tH) Figure 1. tSU and tH Timing Parameters Input Data Delay micro tSU micro tH Input Clock Delay tSU = input pin to input register data delay + input register micro setup time - input pin to input register clock delay Clock to output delay (tCO) tH = - input pin to input register data delay + input register micro hold time + input pin to input register clock delay Figure 2. tCO Timing Parameters Datain Clock Output Register micro tCO Output Clock Pad to Output Register Delay Output Register to Output Pin Delay tCO = + clock pad to output register delay + output register clock-to-output delay + output register to output pin delay Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered 1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs 683103 | 2019.12.08 Figure 3. Generating initial I/O timing information includes the following steps: · Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device on page 4 · Step 2: Define I/O Standard and Pin Locations on page 5 · Step 3: Specify Device Operating Conditions on page 6 · Step 4: View I/O Timing in Datasheet Report on page 6 I/O Timing Data Generation Flow Create Simple Flip-flop Design Define I/O Standard and Pin Location Compile Design Update Timing Netlist Set Operating Conditions Yes Test Another Standard No or Pin Location? End View Timing Parameters in Datasheet Report 1.1. Step 1: Synthesize a Flip-flop for the Target Intel FPGA Device Follow these steps to define and synthesize the minimum flip-flop logic to generate initial I/O timing data: 1. Create a new project in Intel Quartus Prime Pro Edition software version 19.3. 2. Click Assignments Device, specify your target device Family and a Target device. For example, select the AGFA014R24 Intel AgilexTM FPGA. 3. Click File New and create a Block Diagram/Schematic File. 4. To add components to the schematic, click the Symbol Tool button. Figure 4. Insert Pins and Wires in Block Editor Insert Symbols Insert Wires, Buses, Conduits AN 775: Generating Initial I/O Timing Data: for Intel FPGAs 4 Send Feedback 1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs 683103 | 2019.12.08 Figure 5. 5. Under Name, type DFF, and then click OK. Click in the Block Editor to insert the DFF symbol. 6. Repeat 4 on page 4 through 5 on page 5 to add an Input_data input pin, Clock input pin, and Output_data output pin. 7. To connect the pins to the DFF, click the Orthogonal Node Tool button, and then draw wire lines between the pin and DFF symbol. DFF with Pin Connections 8. To synthesize the DFF, click Processing Start Start Analysis & Synthesis. Synthesis generates the minimum design netlist required to obtain I/O timing Data. 1.2. Step 2: Define I/O Standard and Pin Locations The specific pin locations and I/O standard you assign to the device pins impacts the timing parameter values. Follow these steps to assign the pin I/O standard and location constraints: 1. Click Assignments Pin Planner. 2. Assign pin location and I/O standard constraints according to your design specifications. Enter the Node Name, Direction, Location, and I/O Standard values for the pins in the design in the All Pins spreadsheet. Alternatively, drag node names into the Pin Planner package view. Figure 6. Pin Locations and I/O Standards Assignments in Pin Planner 3. To compile the design, click Processing Start Compilation. The Compiler generates I/O timing information during full compilation. Send Feedback AN 775: Generating Initial I/O Timing Data: for Intel FPGAs 5 1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs 683103 | 2019.12.08 Related Information · I/O Standards Definition · Managing Device I/O Pins 1.3. Step 3: Specify Device Operating Conditions Follow these steps to update the timing netlist and set operating conditions for timing analysis following full compilation: 1. Click Tools Timing Analyzer. 2. In the Task pane, double-click Update Timing Netlist. The timing netlist updates with full compilation timing information that accounts for the pin constraints you make. Figure 7. Task Pane in the Timing Analyzer Figure 8. 3. Under Set Operating Conditions, select one of the available timing models, such as Slow vid3 100C Model or Fast vid3 100C Model. Set Operating Conditions in the Timing Analyzer Select Operating Condition 1.4. Step 4: View I/O Timing in Datasheet Report Generate the Datasheet Report in the Timing Analyzer to view the timing parameter values. 1. In the Timing Analyzer, click Reports Datasheet Report Datasheet. 2. Click OK. AN 775: Generating Initial I/O Timing Data: for Intel FPGAs 6 Send Feedback 1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs 683103 | 2019.12.08 Figure 9. Datasheet Report in Timing Analyzer Timing Parameters The Setup Times, Hold Times, and Clock to Output Times reports appear under the Datasheet Report folder in the Report pane. 3. Click each report to view the Rise and Fall parameter values. 4. For a conservative timing approach, specify the maximum absolute value. Example 1. Determining I/O Timing Parameters from the Datasheet Report In the following example Setup Times report, the fall time is greater than the rise time, therefore tSU=tfall. Figure 10. Setup Times Report 7.237 7.394 Figure 11. In the following example Hold Times report, the absolute value of the fall time is greater than the absolute value of the rise time, therefore tH=tfall. Hold Times Report -4.518 -4.618 Figure 12. In the following example Clock to Output Times report, the absolute value of the fall time is greater than the absolute value of the rise time, therefore tCO=tfall. Clock to Output Times Report 6.765 6.772 Related Information · Timing Analyzer Quick-Start Tutorial Send Feedback AN 775: Generating Initial I/O Timing Data: for Intel FPGAs 7 1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs 683103 | 2019.12.08 · Intel Quartus Prime Pro Edition User Guide: Timing Analyzer · How To Video: Introduction to Timing Analyzer 1.5. Scripted I/O Timing Data Generation You can use a Tcl script to generate I/O timing information with or without using the Intel Quartus Prime software user interface. The scripted approach generates textbased I/O timing parameter data for supported I/O standards. Note: The scripted method is available only for Linux* platforms. Follow these steps to generate I/O timing information reflecting multiple I/O standards for Intel Agilex, Intel Stratix® 10, and Intel Arria® 10 devices: 1. Download the appropriate Intel Quartus Prime project archive file for your target device family: · Intel Agilex devices--https://www.intel.com/content/dam/www/ programmable/us/en/others/literature/an/io_timing_agilex_latest.qar · Intel Stratix 10 devices--https://www.intel.com/content/dam/www/ programmable/us/en/others/literature/an/io_timing_stratix10.qar · Intel Arria 10 devices--https://www.intel.com/content/dam/www/ programmable/us/en/others/literature/an/io_timing_arria10.qar 2. To restore the .qar project archive, launch the Intel Quartus Prime Pro Edition software and click Project Restore Archived Project. Alternatively, run the following command line equivalent without launching the GUI: quartus_sh --restore <archive file> The io_timing_<device>_restored directory now contains the qdb subfolder and various files. 3. To run the script with the Intel Quartus Prime Timing Analyzer, run the following command: quartus_sta t <device>.tcl Wait for completion. The script execution may require 8 hours or more because each change on I/O standard or pin location requires design recompilation. 4. To view the timing parameter values, open the generated text files in timing_files, with names such as timing_tsuthtco_<device>_<speed>_<IO_standard>.txt. Related Information · Command Line Scripting · ::QUARTUS::STA Tcl Package AN 775: Generating Initial I/O Timing Data: for Intel FPGAs 8 Send Feedback 1. AN 775: Generating Initial I/O Timing Data for Intel FPGAs 683103 | 2019.12.08 1.6. AN 775: Generating Initial I/O Timing Data Document Revision History Document Version 2019.12.08 2016.10.31 Intel Quartus Prime Version 19.3 16.1 Changes · Revised title to reflect content. · Added support for Intel Stratix 10 and Intel Agilex FPGAs. · Added step numbers to flow. · Added timing parameter diagrams. · Updated screenshots to reflect latest version. · Updated links to related documents. · Applied latest product naming and style conventions. · First public release. Send Feedback AN 775: Generating Initial I/O Timing Data: for Intel FPGAs 9