CMOSTEK CMT2119B: High Power Sub-1G RF Transmitter

Features

• Frequency range: 127 - 1020 MHz
• Modulation: OOK, (G)FSK, and (G)MSK
• Data rate: 0.5 - 300 kbps
• Voltage range: 1.8 - 3.6 V
• Transmitting current: 23 mA @ +13 dBm (433.92 MHz, FSK), 72 mA @ +20 dBm (433.92 MHz, FSK)
• Support auto Tx mode
• Low sleep current: 300 nA (deep sleep), 800 nA (automatic operating)
• 3-wire SPI interface
• Support for direct mode and packet mode
• Configurable packet processor and 64-byte FIFO
• Codec supports non-return-to-zero, Manchester, and data whitening functions
• Support for forward error correction
• 16-pin QFN3x3 packaging

Applications

• Home security and building automation
• ISM band data communication
• Industrial monitoring and control
• Remote control and security system
• Remote key entry
• Wireless sensor node
• Tag reader

Description

The CMT2119B is an OOK and (G)FSK based high-performance RF transmitter with a transmitting power up to +20 dBm, suitable for 127-1020 MHz band wireless applications. It is part of the CMOSTEK NextGenRF™ product family. With high integration density and simplified peripheral designs, it delivers up to +20 dBm power, enhancing application link performance. It supports multiple packet formats and codecs, offering flexibility for various application requirements. Key features include a 64-byte Tx FIFO, rich GPIO and interrupt configuration, auto Tx operation mode, low voltage detection, power-on reset, low-frequency clock output, and manual fast frequency hopping. Operating from a 1.8-3.6 V supply, it consumes 23 mA for +13 dBm and 77 mA for +20 dBm output power.

Ordering Information

[1]. E refers to extended Industrial product rating, which supports temperature range from -40 to +85 °C. Q refers to the package type QFN16. R refers to tape and tray type, and the minimum order quantity (MOQ) is 3,000 pieces.

For more product information, please visit www.cmostek.com. For sales or pricing, contact sales@cmostek.com.

Electrical Specifications

1.1 Recommended Operating Conditions

1.2 Absolute Maximum Ratings

Notes:

[1]. Exceeding the Absolute Maximum Ratings may cause permanent damage. This value is a pressure rating and does not imply functional impact under this condition, but prolonged exposure may affect reliability.

[2]. The CMT2119B is a high-performance RF IC. Operation and assembly require good ESD protection.

Caution! ESD sensitive device. Handle with care to prevent performance degradation or loss of functionality.

1.3 Power Consumption

1.4 Transmitter

1.5 Settling Time

1.6 RF Frequency Synthesizer

1.7 Low Battery Detection

1.8 Crystals

Notes:

[1]. For CMT2119B, an external reference clock can be used to drive the XI pin directly through a coupling capacitor. The peak-to-peak level of the external reference clock is required between 0.3 and 0.7 V.

[2]. It involves: (1) initial tolerance, (2) crystal loading, (3) aging, and (4) temperature changing. The acceptable crystal frequency tolerance is subject to the bandwidth of the receiver and the RF tolerance between the receiver and its paired transmitter.

[3]. This parameter is largely related to the crystal.

1.9 Low-frequency Oscillator

Notes:

[1]. During the PUP phase, the low-frequency oscillator is calibrated automatically to the crystal oscillator frequency and the calibration is performed periodically.

[2]. The frequency drifts with the temperature change after calibration.

[3]. The frequency drifts with the supply voltage change after calibration.

1.10 Digital Interface

1.11 Typical Parameter Chart

1.11.1 Tx Power and Supply Voltage Correlation

The charts show Tx Power (dBm) versus Supply Voltage (V) for different output power levels (+20 dBm and +13 dBm) at 434 MHz and 868 MHz, indicating how output power varies with supply voltage.

1.11.2 Tx Phase Noise

The charts display phase noise (dBm) versus frequency offset (MHz) for 433.92 MHz and 868 MHz operation, showing the noise floor at different offsets from the carrier frequency.

Pin Description

The CMT2119B is a 16-pin device. The pin configuration is shown in the diagram below. The table details the function of each pin.

Pin Arrangement Diagram

A diagram shows the physical layout of the 16 pins, numbered 1 to 17 (with pin 17 being GND). Key pins include PA, AVDD, AGND, DGND, DVDD, SPI interface pins (SCLK, SDIO, CSB, FCSB), crystal interface pins (XI, XO), and GPIO pins (GPIO1, GPIO2, GPIO3).

Pin Description Table

Notes:

[1]. INT1 and INT2 refer to RF interrupts. DCLK (TX) refers to modulated data rate synchronous clock, which is switched automatically upon Tx mode switching.

[2]. DIN is the external modulation data input port in the direct mode. Only the GPIO1 pin has this function.

Typical Application Schematic

The document provides a typical application schematic showing the CMT2119B integrated into a circuit with external components like a crystal oscillator (Y1), capacitors (C1-C10), inductors (L1-L6), and an SMA connector for RF output. The Bill of Materials (BOM) lists the specific components and their values for different frequency bands (433 MHz, 868 MHz, 915 MHz).

Function Description

4.1 Transmitter

The CMT2119B transmitter operates in the 127-1020 MHz range, supporting OOK, (G)FSK, and (G)MSK modulation. It utilizes a fractional frequency synthesizer for carrier generation and an efficient single-ended power amplifier (PA) for transmission. The output power is configurable from -10 dBm to +20 dBm in 1 dB steps. A PA slow-and-drop mechanism is included to mitigate spectral components caused by rapid PA output changes. Users can design a PA matching network for optimal efficiency. The transmitter supports both direct mode (data input via DIN pin) and packet mode (data preloaded into FIFO).

4.2 Assisting Modules

4.2.1 Crystal Oscillator

Provides a reference clock for the phase-locked loop and digital circuits. Requires an external crystal (e.g., 26 MHz) and load capacitors. An external clock source can also be used.

4.2.2 Sleep Timer

An integrated timer driven by a 32 kHz low-power oscillator (LPOSC) wakes the chip periodically from sleep. The sleep time is configurable. The LPOSC frequency is calibrated automatically to maintain accuracy.

4.2.3 Low Battery Detection

Supports low battery detection. When the detected power supply voltage falls below a preset threshold, the chip can enter a low voltage state, awaiting MCU commands.

4.2.4 Fast Frequency Hopping

Enables multi-channel operation by configuring base frequency and offsets, allowing channel switching by changing FH_CHANNEL registers.

Chip Operation

5.1 SPI Interface

The chip communicates via a 4-wire SPI interface (CSB, FCSB, SCLK, SDIO) with a maximum speed of 5 MHz. Data is transferred MSB first. SPI register access is controlled by CSB, while FIFO access uses FCSB. Timing diagrams illustrate register reading and writing procedures.

5.2 FIFO

A 64-byte FIFO is available for data buffering. It can be cleared or restored via SPI commands. FIFO depth can be configured to 32 or 64 bytes. Interrupts are provided for FIFO status (not empty, threshold, full).

5.3 Operating State, Timing and Power Consumption

5.3.1 Startup Timing

Upon power-up, the chip requires time for POR release, crystal start-up, and settling before operating. Calibration of modules follows, after which the chip enters SLEEP mode, awaiting initialization.

5.3.2 Operating State

The CMT2119B supports five operating states: IDLE, SLEEP, STBY, TFS, and TX. SLEEP offers the lowest power consumption. STBY enables the crystal and LDO for faster transitions. TFS and TX states activate more modules for transmission. State transition diagrams illustrate the flow between these states.

5.4 GPIO and Interrupt

The chip features 3 GPIO pins configurable as inputs/outputs (DIN, CLKO, INT1, INT2, DCLK). Two interrupt ports (INT1, INT2) can be mapped to various internal events like TX completion, FIFO status, or state changes. Interrupt polarity can be configured.

Packet Handler

6.1 Packet Format

The CMT2119B supports flexible packet formats: variable packet with length before Node ID, variable packet with length after Node ID, and fixed packet. Each format includes Preamble, Sync Word, Node ID, Length (optional), Data, and CRC fields.

6.2 Data Mode

Supports two data input modes: Direct Mode (data sent directly via DIN pin, FIFO not used) and Packet Mode (data buffered in FIFO, supporting all packet formats).

Automatic Operating Mode

The CMT2119B offers three automatic operating modes to save power by managing the Tx function: Automatically exit Tx, Automatically wake up from SLEEP and exit Tx, and Fully automatic Tx. These modes manage transitions between SLEEP and active Tx states based on pre-configured parameters.

User Registers

The chip's functionality is controlled via various register banks, including CMT Bank, System Bank, Frequency Bank, Data Rate Bank, Baseband Bank, TX Bank, and Control Banks 1 & 2. These banks manage configuration, timing, data rates, packet formats, operating states, and interrupts. Access to Control Bank 2 is restricted in SLEEP state.

Packaging Information

The CMT2119B is available in a 16-pin QFN 3x3 mm package. Detailed dimensions for the package are provided.

Top Marking

The top marking includes the model number (119B), internal tracing codes, and date code (YWW), indicating the year and working week of manufacture.

Related Documents

Refer to the following documents for more information: AN167 (Quick Start Guide) and AN168 (Schematic and PCB Layout Design Guide).

Revise History

The document history tracks revisions, including modifications to GPIO pin descriptions and clarifications on data input methods.

Contacts

CMOSTEK Microelectronics Co., Ltd. Shenzhen Branch provides sales and support. Contact details including address, telephone, email, and website are listed.