Manuals+

Broadcom AS20-M42M-Pxx Series

Absolute Magnetic Encoder SPI 4-Wire Option

Software Specification

1 General Specification of SPI 4-Wire Serial Communication

This section details the general specifications for the SPI 4-Wire serial communication used by the AS20 encoder series.

Item Specification Note
Transmission Type Serial Peripheral Interface (SPI)
Communication Type Single-ended
Synchronization Type Synchronous
Communication Baud Rate Up to 10.0 Mb/s
Transmission Error Checking 6/16 bit CRC 6-bit CRC equation: G(X) = X6 + X1 + 1
16-bit CRC equation: G(X) = X16 + X15 + X12 + X7 + X6 + X4 + X3 + 1

2 General Format Definition of Transmission Frames between Host and Encoder

2.1 Overview of Communications

A one-to-one serial communication is established between the client encoder and the host (e.g., a servo driver). The communications use a single-ended transmission format compliant with the SPI electrical standard. The encoder performs operations based on command requests from the host.

Figure 1: General Transmission Frames Format for SPI 4-Wire Communications

This figure illustrates the timing relationships between SPI signals during data transmission. Key signals include:

  • SPI NCS (Chip Select): Controls the active state of the encoder.
  • SPI CLK (Clock): Synchronizes data transfer.
  • SPI MOSI (Master Out Slave In): Data from the host to the encoder.
  • SPI MISO (Master In Slave Out): Data from the encoder to the host.

Timing parameters such as tC1 (clock cycle time), tL1 (clock low duration), tL2 (clock high duration), tS1 (setup time for NCS), tH1 (hold time for NCS), tW1 (wait time for NCS), tH2 (hold time for MOSI), tS2 (setup time for MOSI), tP1 (MISO propagation delay), and tP2 (MISO high-impedance propagation delay) are defined with minimum and maximum values in nanoseconds (ns).

NOTE:

  • When NCS = 1, MISO is in a high-impedance state to support Multi-encoder Bus Mode.
  • During the first eight clocks, MISO echoes the Operation command from MOSI to support Multi-encoder Mode.
  • The communication supports SPI Mode 0 and SPI Mode 3.
Table 2: SPI 4-Wire Timing Specification
Symbol Description Min. Max. Unit
tC1Permissible clock cycle time100--ns
tL1Clock signal low-level duration50--ns
tL2Clock signal high-level duration50--ns
tS1Setup time: NCS low before SCLK, low to high50--ns
tH1Hold time: NCS low after SCLK, low to high80--ns
tW1Wait time: Between NCS low to high, and NCS high to low200--ns
tH2Hold time: MOSI stable after SCLK, low to high15--ns
tS2Setup time: MOSI stable before SCLK, low to high15--ns
tP1Propagation delay: MISO stable after SCLK, high to low35--ns
tP2Propagation delay: MISO hi impedance after NCS, low to high--35ns

2.2 Encoder Read-Out Frame Sets Format and Timing

Figure 2: Register Read Operation Diagram

This diagram shows the sequence of signals for a register read operation. The MOSI line carries the Operation Command (OC) and Address (ADR), while the MISO line returns the data, including error and CRC information.

Table 3: SPI 4-Wire Operation Commands
Operation Command (OC) Description Ports CLK Bits
Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Byte 8 Byte 9 Byte 10
0xB0 Activate (1 encoder) MOSI B0 100000 RA0 PA0
MISO B0 001000
Activate (2 encoders) MOSI B0 1000 RA0 PA0 RA1 PA1
MISO B0 000010
0xA6 Position Read MOSI A6
MISO A6 Position Data + nError + nWarning + CRC/Position Data + nError + nWarning +nSequence + CRC
0x81 Register Read (Continuous) MOSI 81 ADDRESS(ADDR) 0x00 DATA 1 DATA 2 ...
MISO 81 ADDRESS(ADDR) 0x00 DATA 1 DATA 2 ...
0xCF Register Write (Continuous) MOSI CF ADDRESS(ADDR) DATA 1 DATA 2
MISO CF ADDRESS(ADDR) DATA 1 DATA 2
0x9C Read Status MOSI 9C 0x00 ERR [7:0] ERR [15:8] ERR [23:16] ERR [31:24] WARN [7:0] WARN [15:8] WARN [23:16] WARN [31:24]
MISO 9C 0x00 ERR [7:0] ERR [15:8] ERR [23:16] ERR [31:24] WARN [7:0] WARN [15:8] WARN [23:16] WARN [31:24]
0xD9 Write Command MOSI D9 COMMAND
MISO D9 COMMAND
0x97 Register Read (Single) MOSI 97 ADDRESS(ADDR)
MISO 97 ADDRESS(ADDR)
0xAD Register Status/Data MOSI AD STATUS
MISO AD DATA
0xD2 Register Write (Single) MOSI D2 ADDRESS(ADDR)
MISO D2 ADDRESS(ADDR)

2.2.1 Memory Read Command

The Operation command (OC) 0x81h is used for continuous memory register reads. It is initiated by sending the OC and the starting address. Data is transmitted on MISO, followed by subsequent addresses and data as long as the clock signal is active. The OC 0x97h followed by 0xADh performs a single data read from any register address.

2.2.2 Memory Write Command

The Operation command (OC) 0xCFh is for continuous memory register writes. The OC 0xD2h followed by 0xADh performs a single data write to any register address and retrieves the written data. Continuous writes to external EEPROM are not recommended.

2.2.3 Memory Read Status Command (Single – STATUS Description)

The Operation command (OC) 0xAD provides status descriptions. Table 4 details the status bits:

Table 4: Status Bits Description
BitNameDescription
7Error/SC_ENInvalid Operation command, specific command enable
6:3--Reserved
2FailData request failed
1BusyEncoder busy
0ValidData valid

NOTE: If the last OC received is 0xD9, STATUS bit-7 indicates the operation status.

2.2.4 SPI 4-Wire Specific Command

Sending OC 0xD9 followed by a specific code executes special tasks. Reading back status via 0xAD confirms operation completion (0x00), error (0xFF), or in-progress status. For overwritten operations (e.g., 0x97h register read), OC 0x00 (NOP) resets the status buffer for 0xAD.

Table 5: Specific Command
CodeNameDescription
0x00<NOP_OK><Return-code: last operation succeeded>
0x10REBOOTReset, equivalent to power-cycle the encoder
0x18MT_RESYNCRe-synchronization of the MT device.
0x19MT_RESETClear the FeRAM Value
0x20SCLEARClear the System Alarm and Warning registers
0x80MTST_PRESETSet current position as MT=0, ST=0
0x81MT_PRESETSet current position as MT=0
0xFF<NOP_FAIL><Return-code: last operation failed>

2.2.5 Error or Warning Readout and Descriptions

Use OC 0x9C to read error or warning bits. Table 12 provides details on separating error and warning bits.

Table 6: Alarm or Error Bits Description
BitsAlarmsAlarms Definition
31:30, 27, 25:22, 18:17, 14:13, 10, 8:6, 3:0Reserved0: Default.
28MT Sync ErrorDetects wrong MT counting during MT synchronization upon the Startup operation or MT Sync Retry operation.
1: Incorrect MT synchronization.
0: MT synchronization is correct.
26Multi-turn ErrIndicates bit jump occurs in the multi-turn value. Compare the MT delta for every 12.8 µs; the delta is > ±1 rev.
1: Bit jump occurs.
0: No bit jump occurs.
21XC ErrorIndicates an MT encoder miscount by comparing the MT encoder counter to the MT SW counter.
1: EHMT; miscount or XCERR value overflow.
1: BBMT/Gear; miscount.
0: No MT miscount.
20Speed MT WarningDetects rotation speed greater than 30,000 rpm for MT synchronization.
1: Rotation speed exceeds the limit detected.
0: No over speed detected.
19FeRAM CRC ErrorIndicates a multi-turn block FeRAM communication CRC error.
1: Multi-turn FeRAM CRC error.
0: No CRC error.
16FeRAM Register ErrorDetects an FeRAM error reading MT hardware.
1: Error in FeRAM reading.
0: No error in the MT position reading.
15Chip ReadyIndicates the encoder status.
1: Encoder is ready for normal operation (no fault status).
0: Encoder has abnormality due to other alarm bit(s) triggered.
12TempErrIndicates the temperature is above the upper limit.
1: Temperature above setting limit.
0: Temperature below setting limit.
11Memory ErrIndicates if loading internal and external EEPROM content upon encoder power up is successful.
1: Failure loading internal EEPROM and external EEPROM memory data.
0: Success loading external internal EEPROM and external EEPROM memory data.
9STErrChecks the integrity of ST position. Mcode = absolute code.
1: Mcode jump, MLS-INC mismatch, or MLSErr flag.
0: INC and Mcode function as normal.
5Mag HiDetects an error in the magnetic field sensing.
1: Magnetic field strength is too strong.
0: Magnetic field strength is optimum for normal operation.
4Mag LoDetects an error in the magnetic field sensing.
1: Magnetic field strength is too weak.
0: Magnetic field strength is optimum for normal operation.

2.2.6 Position Read

The Operation command (OC) 0xA6 is used to read absolute position data. For nError (nE) and nWarning (nW) CRC selections, refer to Table 13. Position latch occurs at the first rising clock. nError and nWarning are set to 0 if any error bits are triggered. The sequence counter (Seq Cnt) tracks position reads, incrementing up to 63 before resetting to 0. Single-turn (ST-bit) and multi-turn (MT-bit) values are continuous.

Table 7: Multi-turn + Single-turn Position Read
Operation Command (OC) Description Ports 1 byte <MT-bit> <ST-bit> 2 bits 6 bits 2 bytes
0xA6 Position Read MOSI A6(8b) MT Pos ST Pos nE nW CRC (6b)
Format = Basic MISO A6(8b) MT Pos ST Pos nE nW CRC (6b)
Format = Extended MISO A6(8b) MT Pos ST Pos nE nW Seq Cnt (6b) CRC (16b)

2.2.7 Enable Encoders

The Operation command (OC) 0xB0 activates encoders in a bus mode. Register Data Access (RAx) accesses memory registers, and Position Data Access (PAx) accesses position data. '1' indicates enable, '0' indicates disable.

Table 8: Encoder Activation
OC Description Ports Bit
0123456789101112131415
0xB0 Activate (1 encoder) MOSI B0 1 0 0 0 0 0 RA0 PA0
MISO B0 0 0 1 0 0 0 0 0
Activate (2 encoders) MOSI B0 1 0 0 0 RA0 PA0 RA1 PA1
MISO B0 0 0 0 0 1 0 0 0

Figure 3: Bus-Type Connection for Multi Encoders

This diagram illustrates a bus-type connection for multiple encoders. An SPI Host is connected to multiple SPI Clients (e.g., Encoder-1, Encoder-2) using the SPI communication lines (CLK, NCS, MOSI, MISO).

Table 9: Encoder Data Output Arrangement
OC Description Ports 1 byte <Pos> 2 bits 6 bits 2 bytes <Pos> 2 bits 6 bits 2 bytes
0xA6 Position Read MOSI A6 (8b) MT+ST Pos nE nW CRC (6b) MT+ST Pos nE nW CRC (16b)
format = Basic MISO A6 (8b) MT+ST Pos nE nW CRC (6b) MT+ST Pos nE nW CRC (16b)
format = Extended MISO A6 (8b) MT+ST Pos nE nW Seq Cnt (6b) CRC (16b) MT+ST Pos nE nW Seq Cnt (6b) CRC (16b)

3 Encoder Memory Area

3.1 User Area

The AS20 supports 8 Kb of user register area stored in non-volatile memory. Available pages for user access are listed in Table 10.

Table 10: User Memory Area with 8 Kb
Page [decimal]Address [hex]Remarks
0 to 40x00 to 0x7EUser area
11 to 130x00 to 0x7EUser area
Page Selection0x7F

NOTE:

  • Eight pages with 127 addresses each are allocated for user access.
  • Active page numbers are specified in address 0x7F; page changes are made by writing to 0x7F. Default page after power-on is Page 0.
  • Allow a 18 ms delay after changing the page value.
  • Typical EEPROM read time is 200 µs (minimum).
  • Typical EEPROM write time is 6 ms (minimum).

3.2 Encoder System Area

Register pages are reserved for system areas, protected against accidental writing. Memory data is kept in non-volatile memory.

Table 11: Encoder System Memory Area
Page [decimal]Address [hex]Remarks
5 to 80x00 to 0x7ESystem area
Page Selection0x7F

NOTE: Pages 9 and 10 are volatile memory addresses for encoder system use.

4 Encoder Configuration

4.1 Error and Warning Setting

To enable or disable errors/warnings using Operation command (OC) 0x9C, set the respective bit to 1 (enable) or 0 (disable).

Table 12: Error and Warning Bit Configuration Addresses
Page Address [hex] Bit Initialize Value
7654321076543210
7 SPI4W Warning Mask [31:24] 8'h00
28 SPI4W Warning Mask [23:16] 8'h10
29 SPI4W Warning Mask [15:8] 8'h10
2A SPI4W Warning Mask [7:0] 8'h30
2B SPI4W Error Mask [31:24] 8'h14
2C SPI4W Error Mask [23:16] 8'h29
2D SPI4W Error Mask [15:8] 8'h0A
2E SPI4W Error Mask [7:0] 8'h00
2F SPI4W Alarm Enable [31:24] 8'h14
30 SPI4W Alarm Enable [23:16] 8'h39
31 SPI4W Alarm Enable [15:8] 8'h1A
32 SPI4W Alarm Enable [7:0] 8'h30
33 SPI4W Alarm Latch Enable [31:24] 8'h14
34 SPI4W Alarm Latch Enable [23:16] 8'h29
35 SPI4W Alarm Latch Enable [15:8] 8'h0A
36 SPI4W Alarm Latch Enable [7:0] 8'h00
37

4.2 Cyclic Redundancy Check (CRC) Setting

Table 13: CRC Settings
Page [hex] Address Bit Default Value Description
7654321076543210
7 22 SPI4W_Ext_EN 8'h00 6-bit CRC: 0
16-bit CRC: 1
26 SPI4W CRC [15:8] 8'h00 CRC initial value
27 SPI4W CRC [7:0] 8'h00

4.3 Encoder Memory Map for Calibration and Special Functions

This section details the volatile memory map for calibration and special functions.

Table 14: General Volatile Memory Map (Page 9, 0x09)
No. Item Address Bits
76543210
1 Unlock Memory 0x00 Unlock Memory by Writing 0xAB
2 Program Memory 0x01 Program Memory by Writing 0xC0
3 Clear Alarm/ Position 0x02 Alarm Clear ST Zero Reset MT Zero Reset
4 Calibration 0x04 OT_ Direction-2 OT_Without_ Accuracy OT Direction-1
5 Reset 0x0B Perform Hard Reset by Writing 0xA7
6 Alarm/ Warning [31:24] 0x24 N/A N/A N/A MT Sync Error N/A MT Error N/A N/A
7 Alarm/ Warning [23:16] 0x25 N/A N/A XCErr Speed MT Warning FeRAM CRC Err N/A N/A Feram ECC A/B Reg Err
8 Alarm/ Warning [15:8] 0x26 Chip Ready Reserved N/A Temp_ Err Memory Err N/A ST Err N/A
9 Alarm/ Warning [7:0] 0x27 N/A N/A Mag Hi Mag Lo N/A N/A N/A N/A
10 Calibration Status 0x28 Mem_ Busy N/A Internal Mem_Pass Internal Mem_Fail Zero_ Done Zero_ Err OT_Cal_ Done OT_Cal Err

NOTE:

  • The Memory Program command is required for system area memory to be effective upon power cycle, applicable for changes to internal memory Pages 5 to 8.
  • Perform the Memory Program command for changes to any affected bank before moving to other non-volatile memory banks.
  • Changes will be lost after a power cycle without a Memory Program command.

4.4 Counting Direction

This section describes the register bit for counting direction selection.

Table 15: Register Bit for Counting Direction Selection
Page [Decimal] Address [hex] Bit Default Value
76543210
7 20 NA Counting Direction N/A 8'h40

With the default setting, position data counts up when rotating in the counterclockwise direction, as viewed from the top of the encoder.

Figure 4: Default Counting Direction

This illustration shows an encoder with an arrow indicating that counterclockwise rotation (viewed from the top) results in counting up.

4.5 Zero Reset

Encoder zero-reset data is accessed by reading addresses in Table 16.

Table 16: User Zero-Reset Registers
Page Address [hex] Bit
76543210
7 0E MT_ZR[38:32]
0F MT_ZR[31:24]
10 MT_ZR[23:16]
11 MT_ZR[15:8]
12 MT_ZR[7:0]
13 ST_ZR[17:10]
14 ST_ZR[9:2]
15 ST_ZR[1:0] 6'b000000

For SPI protocol, zero reset options are described in Table 5. The MT position value depends on ST zero registers. The MT reset may return -1 or zero, depending on ST angle position and MT resolution. Exact position relies on offset values (α) in the ST offset register. An alternative is to implement MT offset in the controller side by reading MT position data and applying offset.

Figure 5: Relationship of MT Position Values after Performing the MT Reset Command

This diagram illustrates the relationship between ST Raw Zero, MT reset states (MT=0, MT=-1), and offset values (α°).

4.6 Multi-turn and Single-Turn Absolute Resolution Setting

Configure absolute position output by updating Page 7 Address 0x16, referring to Tables 17 and 18.

Table 17: Memory Map for Absolute Resolution Settings
Page [Decimal] Address [hex] Bit Default Value
76543210
7 22 16 N/A MT_Select [2:0] N/A N/A ST_Select [1:0] 8'h53

NOTE:

  • Unlock the memory.
  • Write new settings at Page 7 and read back to confirm successful writing.
  • Program the memory.
Table 18: Multi-turn and Single-Turn Bits Settings
MT_Select ST_Select
Bits Resolution Bits Resolution
00000015
001120116
010141017
011161118
10020
10124
11032
11139

4.7 Temperature Setting

Read temperature values via the register at Page 7 Address 0x05. Table 19 shows temperature sensor data.

Table 19: Temperature Sensor Data
TemperatureTEMP[7:0]
-64°C1100 0000
-40°C1100 1110
-20°C1110 1100
-1°C1111 1111
0°C0000 0000
1°C0000 0001
10°C0000 1010
25°C0001 1001
50°C0011 0010
85°C0101 0101
127°C0111 1111

NOTE:

  • Minimum temperature support range is –64°C.
  • Negative values are from -1°C to –64°C only.
  • Maximum positive value is 191°C.

Table 20 lists configurations for temperature values and alarms. The temperature upper limit defaults to 0x7D (125°C).

Table 20: Temperature Alarm Limit Setting and Temperature Output Address
Page Address [hex] Bit Initialize Value
76543210
7 02 Temp Max Limit Offset [7:0] 8'h00
03 Temp Offset [7:0] 8'h00
04 Temperature Limit [7:0] 8'h7D
05 Temperature Output [7:0] N/A

Table 21 provides examples of temperature sensor offset settings. Case 1 shows no offset. Case 2 shows a positive offset where the Upper Limit Offset matches the Temperature Offset. Case 3 and 4 demonstrate negative offset values, where the absolute value is added to the default Upper Limit.

Table 21: Temperature Sensor Offset Setting Examples
Case Offset Value (Decimal) 0x02 Temperature Upper Limit Offset (hex) 0x03 Temperature Offset (hex) 0x04 Temperature Upper Limit (hex) 0x05 Temp Output Data (Dec) Raw Temperature without Offset (Dec) Alarm Trigger
10007D124124N
125125Y
126126Y
2100A0A7D124114N
125115Y
126116Y
3-10FF7D+01124125N
125126Y
126127Y
4-100F67D+0A124134N
125135Y
126136Y

5 Calibration of the AS20-M42M Encoder

5.1 Full Auto-Calibration with Accuracy Correction Enabled

Figure 6: Flow Chart for Full Auto-calibration Process

This flowchart outlines the full auto-calibration process with accuracy correction enabled. It involves steps for Clockwise (CW) and Counterclockwise (CCW) calibration.

5.1.1 Calibrate in Clockwise (CW) Direction
  1. Unlock the memory: write Page 9, Address 0x00 = 0xAB.
  2. Spin the spindle motor in the clockwise direction at 60 rpm to 5000 rpm; select the least ripple speed, not to exceed 5000 rpm. Wait for motor speed stability.
  3. Write Page 9, Address 0x04[0] = 1b.
  4. Loop read the Calibration Status, Address 0x28:
    • If Address 0x28[1:0] = 00b, calibration is in progress.
    • If Address 0x28[1:0] = 10b, calibration is done.
    • If Address 0x28[1:0] = 01b, calibration is in error.
  5. Clear the Calibration Register, Address 0x04 = 0h.
  6. If calibration is unsuccessful, repeat Step 3 and Step 4. Retries up to 10 times are possible.
5.1.2 Calibrate in the Counterclockwise (CCW) Direction
  1. Spin the spindle motor in the counterclockwise direction at 60 rpm to 5000 rpm; select the least ripple speed, not to exceed 5000 rpm. Wait for motor speed stability.
  2. Write Page 9, Address 0x04[2] = 1b.
  3. Loop read the Calibration Status, Address 0x28:
    • If Address 0x28[1:0] = 00b, calibration is in progress.
    • If Address 0x28[1:0] = 10b, calibration is done.
    • If Address 0x28[1:0] = 01b, calibration is in error.
  4. Clear the Calibration Register, Address 0x04 = 0h.
  5. If calibration is unsuccessful, repeat Step 2 and Step 3. Retries up to 10 times are possible.

5.2 Auto-Calibration without Accuracy Correction

  1. Unlock the memory: write Page 9, Address 0x00 = 0xAB.
  2. Spin the spindle motor in the clockwise direction at 60 rpm to 5000 rpm; select the least ripple speed, not to exceed 5000 rpm. Wait for motor speed stability.
  3. Write Page 9, Address 0x04[1] = 1b.
  4. Loop read the Calibration Status, Address 0x28:
    • If Address 0x28[1:0] = 00b, calibration is in progress.
    • If Address 0x28[1:0] = 10b, calibration is done.
    • If Address 0x28[1:0] = 01b, calibration is in error.
  5. Clear the Calibration Register, Address 0x04 = 00h.
  6. If calibration is unsuccessful, repeat Step 3 and Step 4. Retries up to 10 times are possible.

5.3 Auto Zero-Reset (Single-Turn)

  1. Unlock the memory.
  2. Write Page 9, Address 0x02[1] = 1b.
  3. Loop read the Calibration Status, Address 0x28:
    • If Address 0x28[3:2] = 00b, calibration is in progress.
    • If Address 0x28[3:2] = 10b, calibration is done.
    • If Address 0x28[3:2] = 01b, calibration is in error.

5.4 Auto Zero-Reset (Multi-Turn)

  1. Unlock the memory.
  2. Write Page 9, Address 0x02[0] = 1b.
  3. Loop read the Calibration Status, Address 0x28:
    • If Address 0x28[3:2] = 00b, calibration is in progress.
    • If Address 0x28[3:2] = 10b, calibration is done.
    • If Address 0x28[3:2] = 01b, calibration is in error.

5.5 Alarm Clear

  1. Unlock the memory.
  2. Write Page 9, Address 0x02[2] = 1b.

5.6 EH Pulse Voltage Monitoring

The AS20 features a built-in function to measure and monitor the EH pulse voltage level (VWC). Measurement requires the final encoder assembly, including the external cover.

  1. Unlock the memory: write Page 9, Address 0x00 = 0xAB.
  2. Enable the VWC Monitoring Self Check by writing Address 0x08 = 04h.
  3. Spin the spindle motor in the clockwise direction for greater than 350 rotations at 3000 rpm.
  4. Loop read the Calibration Status, Page 9, Address 0x45:
    • If Address 0x45[3] = 1b, the measurement is done.
  5. End the VWC Monitoring Self Check by writing Page 9, Address 0x08 = 00h.
  6. Read Page 9, Address 0x46 to 0x47 for the measured data.
  7. Stop the Motor.
  8. Repeat Step 2 to Step 6 with rotation in the counterclockwise direction.

Figure 7: VWC Monitoring Self Test Flow Chart

This flowchart details the VWC Monitoring Self Test process, covering both clockwise (CW) and counterclockwise (CCW) motor rotations, including steps for unlocking memory, starting monitoring, spinning the motor, checking status, clearing bits, reading data, and stopping the motor.

Table 22: EH Pulse Monitoring Measurement Registers
Page [dec] Byte Address [hex] Description Bit
76543210
9 08 Command Vwc_Mon_Trig
9 69 (45h) Status VWC Result Ready
70 46 MT Counter VWC EH Pulse VWC data, Average - 4 Sigma (Target value: 48 to 80 decimal)
71 47 EH Pulse VWC data – Mean (Target: 48 to 80 decimal)

5.7 Code Monotony Measurement

The AS20 measures and monitors the code monotony of the ST position data. This requires the final encoder assembly, including the external cover.

  1. Unlock the memory: write Page 9, Address 0x00 = 0xAB.
  2. Enable the Code Monotony measurement: write Page 9, Address 0x06 = 01h.
  3. Spin the spindle motor in the clockwise direction for greater than three revolutions at low speed (e.g., 2 rpm to 10 rpm).
  4. Read Page 9, Address 0x60 to 0x63 for the measured data.
  5. End the Code Monotony measurement: write Page 9, Address 0x06 = 00h.
  6. Stop the motor.
  7. Repeat Step 2 to Step 5 with rotation in the counterclockwise direction.

Figure 8: Code Monotony Self Test Flow Chart

This flowchart outlines the Code Monotony Self Test process, covering both clockwise (CW) and counterclockwise (CCW) motor rotations. It includes steps for unlocking memory, starting the measurement, spinning the motor, reading data, and clearing the measurement bit.

Table 23: Code Monotony Measurement Registers
SPI Page [dec] Byte Address [hex] Description Bit
76543210
9 06 CM Test CM_Test_En
9 96 (60h) CM_Max[15:0]
9 97 (61h) CM_Max[15:0]
9 98 (62h) CM_Min[15:0]
9 99 (63h) CM_Min[15:0]

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