User Guide for msi models including: D5062, S5062, S5062 Heatsink Module, Heatsink Module, Module
Prepare the Heatsink. Remove any protective film and ensure thermal paste is applied (add if missing). 3. Attach the Heatsink to the Carrier.
2 дня назад — Prepare the Heatsink. Remove any protective film and ensure thermal paste is applied (add if missing). 3. Attach the Heatsink to the Carrier.
G52-S3682X1 CPU and Heatsink Installation D5062 / S5062 QUICK START GUIDE JPWR1 JPICPWR_1 JPICPWR_2 JUSB3_0 M2_1 OCP JBAT1 EDSFF0 LED_H1 BUZZER BATTERY LED_L1 J16 EDSFF1 M2_0 JVROC1 JDC1 JRST_P1 JPWR_P1 JMBP_1 JPASSWORD_C_1 DC_SCM JUART_SEL_1 JTAG_SEL1 JCHASSIS1 RISER1 RISER3 RISER4 RISER5 JPWR2 JPICPWR_3 JPICPWR_4 RISER6 J_IPMB1 JMCIO_P1_1 JFP2 CPU0 CPU1 CPU1_DIMM_A2 CPU1_DIMM_A1 CPU1_DIMM_B2 CPU1_DIMM_B1 CPU1_DIMM_C2 CPU1_DIMM_C1 CPU1_DIMM_D2 CPU1_DIMM_D1 CPU0_DIMM_A2 CPU0_DIMM_A1 CPU0_DIMM_B2 CPU0_DIMM_B1 CPU0_DIMM_C2 CPU0_DIMM_C1 CPU0_DIMM_D2 CPU0_DIMM_D1 CPU1_DIMM_H1 CPU1_DIMM_H2 CPU1_DIMM_G1 CPU1_DIMM_G2 CPU1_DIMM_F1 CPU1_DIMM_F2 CPU1_DIMM_E1 CPU1_DIMM_E2 CPU0_DIMM_H1 CPU0_DIMM_H2 CPU0_DIMM_G1 CPU0_DIMM_G2 CPU0_DIMM_F1 CPU0_DIMM_F2 CPU0_DIMM_E1 CPU0_DIMM_E2 HGF E ABCD HGF E ABCD JMCIO_P0_4 JFP3 JMCIO_P0_3 JPICPWR_5 JMCIO_P0_2 JMCIO_P0_1 JMCIO_P1_4 JMCIO_P1_3 JCPUFAN0 JCPUFAN1 1 FBP_I2C_2 2 FBP_I2C_3 3 FBP_I2C_1 4 FBP_I2C_4 JMCIO_P1_2 JPICPWR_6 4 1 2 3 CPU Dual Intel® Xeon® 6700E-series, 6500P-series and 6700P-series processors, TDP up to 350W. DC-MHS Control Panel Header The DC-MHS (Data Center Modular Hardware System) control panel header for M-PESTI connects the HPM to the server's front panel, enabling essential controls such as power, LED indicators, buttons, and sideband signals for management and monitoring. JFP2~3 20 19 21 1 P12V_AUX 2 GND 3 P12V_AUX 4 BMC_SMB_LVC3_PESTI1_SDA 5 NC 6 BMC_SMB_LVC3_PESTI1_SCL 7 GND 8 GND 9 USB2_BMC_PCP_ESD_D+ 10 FM_FP_HPM_PCP_SB4 11 USB2_BMC_PCP_ESD_D- 12 FM_FP_HPM_PCP_SB3 13 GND 14 FM_FP_HPM_PCP_SB2 15 SPI_BMC_FP_MISO_R 16 FM_FP_HPM_PCP_SB1 17 SPI_BMC_FP_CS0_R 18 GND 19 SPI_BMC_FP_MOSI_R 20 SPI_BMC_FP_CK_R 1U EVAC Heatsink Processor Heatsink Module (PHM) 2U EVAC Heatsink CPU Carrier: E2B CPU Carrier: E2A Socket Cover CPU Socket Bolster Plate 1. Attach the CPU to the Carrier Align the Pin 1 indicators and snap the CPU securely into the carrier. Please refer to the following table for the corresponding CPU carrier. CPU Package Type Thin Package Thick Package CPU Package Name CPU Carrier Code Granite Rapids- SP XCC E2A Granite Rapids- SP HCC/ LCC Sierra Forest- SP E2B 2. Prepare the Heatsink Remove any protective film and ensure thermal paste is applied (add if missing). 3. Attach the Heatsink to the Carrier Align the Pin 1 indicator with the heatsink's cut corner (#1 clip) and press down until all latches engage. 4. Form the PHM(Processor Heatsink Module) Confirm the CPU, carrier, and heatsink are securely latched together. 5. Place the PHM on the Motherboard Remove the socket cover, unlock the 4 anti-tilt wires, align the Pin 1 indicators, and lower the PHM onto the bolster plate. 6. Secure the PHM Lock the anti-tilt wires outward and tighten the heatsink nuts diagonally using a Torx T30 screwdriver. Connectors, Jumpers and LED Indicators Name JPWR1~2 JPICPWR_1~6 RISER1,3 RISER4~6 JMCIO_P0_1~4 JMCIO_P1_1~4 M2_0~1 EDSFF0~1 OCP DC-SCM JCPUFAN0~1 J16 JUSB3_0 JFP2~3 JRST_P1 JPWR_P1 Description CRPS/ M-CRPS 185x73.5mm power connectors 12-Pin PICPWR power connectors SFF-TA-1033 M-XIO slots (PCIe 5.0 x16, from CPU0) SFF-TA-1033 M-XIO slots (PCIe 5.0 x16, from CPU1) MCIO 8i connectors (PCIe 5.0 x8, from CPU0) MCIO 8i connectors (PCIe 5.0 x8, from CPU1) M.2 slots (M Key, PCIe 5.0 x2, 2280/ 22110) E1.S 9.5mm connectors (PCIe 5.0 x4, from CPU1) OCP 3.0 mezzanine slot (PCIe 5.0 x16, from CPU0, NCSI supported) DC-SCM 2.0 edge slot 4-pin fan connectors Liquid leak detection connector USB 3.2 Gen 1 connector (5 Gbps, for 2 USB ports) DC-MHS control panel header Reset button header Power button header Name J_IPMB1 JVROC1 FBP_I2C_1~4 JCHASSIS1 JMBP_1 JBAT1 JPASSWORD_C_1 JUART_SEL1 JTAG_SEL1 LED_H1, LED_L1 Description IPMB header VROC connector I2C headers Chassis intrusion header MBP/ I3C MIPI mode select jumper (default pin 1-2, MBP Mode) CMOS clear jumper (default pin 1-2, Normal) Password clear jumper (default pin 1-2, Normal) UART BMC/ CPLD select jumper (default pin 1-2, UART BMC to CPU) JTAG select jumper (default pin 1-2, BMC to CPLD) Port 80 debug LEDs Memory The server board supports 32 DDR5 DIMM slots, compatible with RDIMMs and MRDIMMs. DIMM Type RDIMM MRDIMM Max Frequency 6400 MT/s (1DPC), 5200 MT/s (2DPC) 8000 MT/s (only support 1DPC) Max Capacity per DIMM 256GB 64GB H G F E A B C D Slot 1 Slot 2 Slot 1 Slot 2 Slot 1 Slot 2 Slot 1 Slot 2 Slot 2 Slot 1 Slot 2 Slot 1 Slot 2 Slot 1 Slot 2 Slot 1 CH4 CH5 CH6 CH7 CPU CH0 CH1 CH2 CH3 IMC7 IMC6 IMC5 IMC4 IMC0 IMC1 IMC2 IMC3 IMC# IMC7 IMC6 IMC5 IMC4 IMC0 IMC1 Channel H G F E A B DDR5 Qty. Chan 7 Chan 6 Chan 5 Chan 4 H1 H2 G1 G2 F1 F2 E1 E2 Chan 0 Chan 1 A2 A1 B2 B1 1 C V 4 V V P V V V V U V V V V V V 8 VV VV VV VV VV VV 12 V VVV VV VV V 16 VVVVVVVV VVVV "V"indicates DIMMs are populated with DDR5. IMC2 C Chan 2 C2 C1 V V VV VV VV IMC3 D Chan 3 D2 D1 V V VV V VV Important Intel® Xeon® 6700E Series does not support 12 DIMMs configuration. There should be at least one DDR5 DIMM per socket. When only one DIMM is used in a channel, it must be populated in the DIMM slot farthest away from the CPU (DIMM slot 1) of a given channel. DDR5 memory configurations requires same DIMM types, ranks, speeds, and densities. Mixing vendors, non-3DS/3DS RDIMMs, 9x4 RDIMMs, or x8/x4 DIMMs is not allowed. Mixing DIMMs with different operating frequencies is not validated. When frequencies differ, the system defaults to the lowest common speed.Adobe PDF Library 17.0 Adobe InDesign 20.1 (Windows)