intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia

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1 FPGA Integer Arithmetic IP Cores

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FPGA Integer Arithmetic IP Cores

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Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia
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ID: 683490 Version: 2020.10.05

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1. Intel FPGA Integer Arithmetic IP Cores ………………………………………………………………… 5
2. LPM_COUNTER (Counter) IP Core……………………………………………………………………………….. 7 2.1. Nta ………………………………………………………………………………………………………… 7 2.2. Verilog HDL Prototype……………………………………………………………………………….. 8 2.3. VHDL Component Declaration………………………………………………………………….8 2.4. VHDL LIBRARY_USE Tshaj Tawm……………………………………………………………………………… 9 2.5. Ports…………………………………………………………………………………………………………..9 2.6. Parameters …………………………………………………………………………………………… 10
3. LPM_DIVIDE (Divider) Intel FPGA IP Core…………………………………………………….. 12 3.1. Nta…………………………………………………………………………………………………………. 12 3.2. Verilog HDL Prototype ………………………………………………………………… 12 3.3. VHDL Component Declaration……………………………………………………………………………… 13 3.4. VHDL LIBRARY_USE tshaj tawm…………………………………………………………………. 13 3.5. Ports …………………………………………………………………………………………… 13 3.6. Parameters …………………………………………………………………………………………… 14
4. LPM_MULT (Multiplier) IP Core………………………………………………………………………………. 16 4.1. Nta…………………………………………………………………………………………………………. 16 4.2 ib. Verilog HDL Prototype ………………………………………………………………… 17 4.3. VHDL Component Declaration ……………………………………………………………………………… 17 4.4. VHDL LIBRARY_USE tshaj tawm…………………………………………………………………. 17 ib. Cov teeb liab ………………………………………………………………………………………………………… 4.5 18. Parameters rau Stratix V, Arria V, Cyclone V, thiab Intel Cyclone 4.6 LP Devices…………… 10 18. General Tab…………………………………………………………………………………………… 4.6.1 18. General 4.6.2 Tab……………………………………………………………………………… 2 19. Pipelining Tab…………………………………………………………………………………………… 4.6.3 19. Parameters rau Intel Stratix 4.7, Intel Arria 10, thiab Intel Cyclone 10 GX Devices……….. 10 20. General Tab…………………………………………………………………………………………… 4.7.1 20. General 4.7.2 Tab……………………………………………………………………………… 2 20. Pipelining …………………………………………………………………………………………… 4.7.3
5. LPM_ADD_SUB (Adder/Subtractor)……………………………………………………………………………… 22 5.1. Nta…………………………………………………………………………………………………………. 22 5.2 ib. Verilog HDL Prototype ………………………………………………………………… 23 5.3. VHDL Component Declaration………………………………………………………………….. 23 5.4. VHDL LIBRARY_USE tshaj tawm…………………………………………………………………. 23 5.5 ib. Ports………………………………………………………………………………………………………… 23 5.6. Parameters …………………………………………………………………………………………… 24
6. LPM_COMPARE (Comparator) ……………………………………………………………………………… 26 6.1. Nta…………………………………………………………………………………………………………. 26 6.2 ib. Verilog HDL Prototype ………………………………………………………………… 27 6.3. VHDL Component Declaration………………………………………………………………….. 27 6.4. VHDL LIBRARY_USE tshaj tawm…………………………………………………………………. 27 ib. Ports………………………………………………………………………………………………………… 6.5 27. Parameters …………………………………………………………………………………………… 6.6

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7. ALTECC (Yam Kho Code: Encoder/Decoder) IP Core……………………………………… 30
7.1. ALTECC Encoder Nta………………………………………………………………………………..31 7.2. Verilog HDL Prototype (ALTECC_ENCODER) ……………………………………………………. 32 7.3. Verilog HDL Prototype (ALTECC_DECODER) ……………………………………………………. 32 ib. VHDL Component Declaration (ALTECC_ENCODER)……………………………………………………7.4 33. VHDL Component Declaration (ALTECC_DECODER)……………………………………………………7.5 33. VHDL LIBRARY_USE tshaj tawm………………………………………………………………………………. 7.6 ib. Encoder Ports …………………………………………………………………………………………… 33 7.7. Decoder Ports …………………………………………………………………………………………… 33 7.8. Encoder Parameters ……………………………………………………………………………… 34 7.9. Decoder Parameters ……………………………………………………………………………… 34
8. Intel FPGA Multiply Adder IP Core……………………………………………………………………. 36
8.1. Nta…………………………………………………………………………………………………………. 37 ib. Pre-adder……………………………………………………………………………………… 8.1.1 38. Systolic Delay Register………………………………………………………………….. 8.1.2 40. Pre-load Constant ………………………………………………………………… 8.1.3 43. Ob chav Accumulator ………………………………………………………………… 8.1.4
8.2. Verilog HDL Prototype ……………………………………………………………………………… 44 8.3. VHDL Component Declaration………………………………………………………………….. 44 8.4. VHDL LIBRARY_USE tshaj tawm…………………………………………………………………. 44 ib. Cov teeb liab ………………………………………………………………………………………………………… 8.5 44. Parameters …………………………………………………………………………………………… 8.6
8.6.1 ib. General Tab…………………………………………………………………………………………… 47 8.6.2. Extra Modes Tab……………………………………………………………………………….. 47 8.6.3. Multipliers Tab……………………………………………………………………………………. 49 8.6.4. Preadder Tab………………………………………………………………………………. 51 ib. Accumulator Tab……………………………………………………………………………….. 8.6.5 53. Systolic/Chainout Tab…………………………………………………………………. 8.6.6 55 ib. Pipelining Tab……………………………………………………………………………… 8.6.7
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core………………………… 57
9.1. Nta…………………………………………………………………………………………………………. 57 ib. Verilog HDL Prototype ………………………………………………………………… 9.2 58. VHDL Component Declaration……………………………………………………………………………… 9.3 58. Ports …………………………………………………………………………………………… 9.4 59. Parameters …………………………………………………………………………………………… 9.5
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core…………………………………………………… 61
10.1. Nta……………………………………………………………………………………………..62 10.2. Verilog HDL Prototype…………………………………………………………………..62 10.3. VHDL Component Declaration………………………………………………………………… 63 10.4. VHDL LIBRARY_USE Tshaj Tawm……………………………………………………………………………… 63 10.5. Ports …………………………………………………………………………………………………………. 63 10.6 ib. Parameters ……………………………………………………………………………………………. 64
11. ALTMULT_ADD (Multiply-Adder) IP Core……………………………………………………..69
11.1. Nta……………………………………………………………………………………………..71 11.2. Verilog HDL Prototype……………………………………………………………………..72 11.3. VHDL Component Declaration………………………………………………………………… 72 11.4. VHDL LIBRARY_USE tshaj tawm……………………………………………………………………………… 72

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11.5. Ports …………………………………………………………………………………………………………. 72 11.6 ib. Parameters ……………………………………………………………………………………………. 73
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core…………………………………………………… 86 12.1. Complex Multiplication……………………………………………………………………………… 86 12.2 ib. Canonical Representation………………………………………………………………… 87 12.3. Conventional Representation……………………………………………………………………. 87 12.4 ib. Nta……………………………………………………………………………………………..88 12.5. Verilog HDL Prototype……………………………………………………………………………….88 12.6. VHDL Component Declaration………………………………………………………………… 89 12.7. VHDL LIBRARY_USE Tshaj Tawm ………………………………………………………………… 89 12.8. Signals…………………………………………………………………………………………………………. 89 12.9 ib. Parameters ……………………………………………………………………………………………. 90
13. ALTSQRT (Integer Square Root) IP Core………………………………………………………………… 92 13.1. Nta……………………………………………………………………………………………..92 13.2. Verilog HDL Prototype……………………………………………………………………..92 13.3. VHDL Component Declaration………………………………………………………………… 93 13.4. VHDL LIBRARY_USE Tshaj Tawm……………………………………………………………………………… 93 13.5. Ports …………………………………………………………………………………………………………. 93 ib. Parameters ……………………………………………………………………………………………. 13.6
14. PARALLEL_ADD (Parallel Adder) IP Core…………………………………………………….. 95 14.1. Feature…………………………………………………………………………………………….95 14.2. Verilog HDL Prototype……………………………………………………………………..95 14.3. VHDL Component Declaration………………………………………………………………… 96 14.4. VHDL LIBRARY_USE tshaj tawm……………………………………………………………………………… 96 14.5. Ports …………………………………………………………………………………………………………. 96 14.6 ib. Parameters ……………………………………………………………………………………………. 97
15. Integer Arithmetic IP Cores User Guide Document Archives……………………………………… 98
16. Cov ntaub ntawv kho dua tshiab rau Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia…. 99

Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia 4

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683490 | 2020.10.05 Xa lus tawm tswv yim

1. Intel FPGA Integer Arithmetic IP Cores

Koj tuaj yeem siv Intel® FPGA integer IP cores los ua lej ua haujlwm hauv koj tus qauv tsim.

Cov haujlwm no muab kev sib txuas lus zoo dua thiab kev siv cuab yeej siv ntau dua li coding koj tus kheej lub luag haujlwm. Koj tuaj yeem kho tus IP cores kom haum raws li koj qhov kev xav tau tsim.

Intel integer arithmetic IP cores tau muab faib ua ob pawg hauv qab no: · Lub tsev qiv ntawv ntawm cov ntsuas ntsuas tsis tau (LPM) IP cores · Intel-specific (ALT) IP cores

Cov lus hauv qab no teev cov lej lej lej IP cores.

Table 1.

Cov npe ntawm IP Cores

IP Cores

LPM IP cores

LPM_COUNTER

LPM_DIVIDE

LPM_MULT

LPM_ADD_SUB
LPM_COMPARE
Intel-specific (ALT) IP cores ALTECC

Muaj nuj nqi Tshajview Counter Divider Multiplier
Adder lossis subtractor Comparator
ECC Encoder/Decoder

Txhawb Ntaus
Arria® II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone® IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP,
Intel Cyclone 10 GX, MAX® II, MAX V, MAX 10, Stratix® IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V txuas ntxiv…

Intel Corporation. Txhua txoj cai. Intel, Intel logo, thiab lwm yam Intel cov cim yog cov cim lag luam ntawm Intel Corporation lossis nws cov koom haum. Intel lav kev ua tau zoo ntawm nws cov FPGA thiab cov khoom lag luam semiconductor rau cov kev qhia tshwj xeeb tam sim no raws li Intel tus qauv kev lees paub, tab sis muaj txoj cai los hloov cov khoom thiab cov kev pabcuam txhua lub sijhawm yam tsis muaj ntawv ceeb toom. Intel xav tias tsis muaj lub luag haujlwm lossis kev lav phib xaub uas tshwm sim los ntawm daim ntawv thov lossis siv cov ntaub ntawv, cov khoom lag luam, lossis cov kev pabcuam uas tau piav qhia hauv no tshwj tsis yog raws li tau pom zoo hauv kev sau ntawv los ntawm Intel. Intel cov neeg siv khoom tau qhia kom tau txais qhov tseeb version ntawm cov cuab yeej tshwj xeeb ua ntej tso siab rau cov ntaub ntawv tshaj tawm thiab ua ntej muab xaj rau cov khoom lossis cov kev pabcuam. * Lwm lub npe thiab hom yuav raug lees paub raws li cov cuab yeej ntawm lwm tus.

Daim ntawv pov thawj ISO 9001: 2015

1. Intel FPGA Integer Arithmetic IP Cores 683490 | 2020.10.05

IP Cores Intel FPGA Multiply Adder lossis ALTERA_MULT_ADD ALTMEMMULT
ALTMULT_ACCUM ALTMULT_ADD ALTMULT_COMPLEX
ALTSQRT
PARALLEL_ADD

Muaj nuj nqi Tshajview Multiplier-Adder
Memory-based Constant Coefficient Multiplier
Multiplier-Accumulator Multiplier-Adder
Kev sib txuam ntau
Integer Square-hauv paus
Parallel Adder

Txhawb Ntaus
Arria V, Stratix V, Cyclone V, Intel Stratix 10, Intel Arria 10, Intel Cyclone
10 XNUMX GX
Arria II GX, Arria II GZ, Arria V, Intel Arria 10 (Intel Quartus® Prime Standard Edition), Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Cyclone 10 LP, MAX II, MAX V, MAX 10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Intel Arria 10, Arria V, Arria V GZ, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Cyclone 10 GX, Intel Cyclone 10 LP, MAX 10, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V

Cov ntaub ntawv ntsig txog
· Intel FPGAs thiab Programmable Devices Release Notes
· Taw qhia rau Intel FPGA IP Cores Muab cov ntaub ntawv ntau ntxiv txog Intel FPGA IP Cores.
· Floating-Point IP Cores Tus Neeg Siv Qhia Muab cov ntaub ntawv ntau ntxiv txog Intel FPGA Floating-Point IP cores.
· Taw qhia rau Intel FPGA IP Cores Muab cov ntaub ntawv dav dav txog tag nrho Intel FPGA IP cores, suav nrog parameterizing, tsim, kho dua tshiab, thiab simulating IP cores.
· Tsim Version-Independent IP thiab Qsys Simulation Scripts Tsim simulation scripts uas tsis xav tau phau ntawv hloov tshiab rau software lossis IP version hloov khoom dua tshiab.
· Kev Tswj Xyuas Txoj Haujlwm Zoo Tshaj Plaws Cov Lus Qhia rau kev tswj hwm thiab kev txav mus los ntawm koj qhov project thiab IP files.
· Integer Arithmetic IP Cores User Guide Document Archives ntawm nplooj 98 Muab cov npe ntawm cov neeg siv cov lus qhia rau yav dhau los versions ntawm Integer Arithmetic IP cores.

Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia 6

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2. LPM_COUNTER (Counter) IP Core

Daim duab 1.

Lub LPM_COUNTER IP core yog lub txee binary uas tsim cov txee, cov txee thiab nce lossis nqis txee nrog cov khoom tawm txog li 256 qhov dav.

Cov duab hauv qab no qhia cov chaw nres nkoj rau LPM_COUNTER IP core.

LPM_COUNTER Chaw nres nkoj

LPM_COUNTER

ssclr sload sset data[]

q[]

hloov dua tshiab

cout

aclr ua

clk_en cnt_en cin
inst

2.1. Nta
Lub LPM_COUNTER IP core muaj cov yam ntxwv hauv qab no: · Tsim cov txee nce, nqis, thiab nce / nqis · Tsim cov txee hauv qab no:
- Plain binary- cov txee nce pib los ntawm xoom lossis txo qis pib los ntawm 255
- Modulus-tus txee increments los yog decrements los ntawm tus nqi modulus teev los ntawm tus neeg siv thiab rov ua dua
· Txhawb kev xaiv synchronous clear, load, thiab teeb input ports · Txhawb kev xaiv asynchronous clear, load, thiab teeb input ports · Txhawb kev xaiv suav enables thiab moos pab input ports · Txhawb kev xaiv nqa-hauv thiab nqa tawm ports

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2. LPM_COUNTER (Counter) IP Core
683490 Nws 2020.10.05 ib
2.2. Verilog HDL Prototype
Cov nram qab no Verilog HDL qauv yog nyob rau hauv Verilog Design File (.v) lpm.v in the edasynthesis directory.
module lpm_counter ( q, data, moos, cin, cout, clk_en, cnt_en, updown, aset, aclr, aload, sset, sclr, sload, eq ); parameter lpm_type = "lpm_counter"; parameter lpm_width = 1; parameter lpm_modulus = 0; parameter lpm_direction = "UNUSED"; parameter lpm_avalue = "UNUSED"; parameter lpm_svalue = "UNUSED"; parameter lpm_pvalue = "UNUSED"; parameter lpm_port_updown = “PORT_CONNECTIVITY”; parameter lpm_hint = "UNUSED"; tso zis [lpm_width-1:0] q; tso zis cout; tso zis [15:0] eq; input cin; input [lpm_width-1:0] cov ntaub ntawv; input moos, clk_en, cnt_en, updown; input asset, aclr, aload; input sset, sclr, sload; endmodule
2.3. VHDL Component Tshaj Tawm
VHDL cov lus tshaj tawm yog nyob hauv VHDL Tsim File (.vhd) LPM_PACK.vhd hauv librariesvhdllpm directory.
tivthaiv LPM_COUNTER generic ( LPM_WIDTH : natural; LPM_MODULUS : natural := 0; LPM_DIRECTION : string := “UNUSED”; LPM_AVALUE : string := “UNUSED”; LPM_SVALUE : string := “UNUSED” = CONDOWN_PORT_PORTITY: LPM_string: ; LPM_PVALUE : string := “UNUSED”; chaw nres nkoj (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0):= (OTHERS =>
'0'); CLOCK: hauv std_logic ; CLK_EN : in std_logic := '1'; CNT_EN : in std_logic := '1'; UPDOWN : in std_logic := '1'; SLOAD : in std_logic := '0'; SSET : in std_logic := '0'; SCLR : in std_logic := '0'; ALOAD : in std_logic := '0'; ASET : in std_logic := '0'; ACLR : in std_logic := '0'; CIN : in std_logic := '1'; COUT : out std_logic := '0'; Q : tawm std_logic_vector(LPM_WIDTH-1 downto 0); EQ : tawm std_logic_vector(15 downto 0));
kawg tivthaiv;

Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia 8

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2. LPM_COUNTER (Counter) IP Core 683490 | 2020.10.05

2.4. VHDL LIBRARY_USE tshaj tawm
Daim ntawv tshaj tawm VHDL LIBRARY-SIV tsis tas yuav yog tias koj siv VHDL Cov Lus Tshaj Tawm.
LIBRARY lpm; USE lpm.lpm_components.all;

2.5. Chaw nres nkoj

Cov lus hauv qab no teev cov tswv yim thiab tso tawm cov chaw nres nkoj rau LPM_COUNTER IP core.

Table 2.

LPM_COUNTER Input Ports

Chaw nres nkoj npe

Yuav tsum tau

Kev piav qhia

cov ntaub ntawv[]

Tsis muaj

Parallel cov ntaub ntawv nkag mus rau lub txee. Qhov loj ntawm qhov chaw nres nkoj nkag yog nyob ntawm LPM_WIDTH parameter tus nqi.

moos

Yog lawm

Positive-edge-triggered moos input.

clk_en

Tsis muaj

Lub moos pab cov tswv yim los pab kom txhua yam haujlwm synchronous. Yog tias tshem tawm, tus nqi pib yog 1.

cnt_en

Tsis muaj

Suav pab cov tswv yim los lov tes taw suav thaum lees paub qis yam tsis muaj kev cuam tshuam rau sload, sset, lossis sclr. Yog tias tshem tawm, tus nqi pib yog 1.

hloov dua tshiab

Tsis muaj

Tswj cov kev taw qhia ntawm suav. Thaum lees paub siab (1), suav cov kev taw qhia nce, thiab thaum lees tias qis (0), suav kev taw qhia qis. Yog tias siv LPM_DIRECTION parameter, qhov chaw nres nkoj updown tsis tuaj yeem txuas nrog. Yog tsis siv LPM_DIRECTION, qhov chaw nres nkoj updown yog xaiv tau. Yog tias tshem tawm, tus nqi pib yog nce (1).

ua cin

Tsis muaj

Nqa mus rau qhov kev txiav txim qis qis. Rau cov txee, tus cwj pwm ntawm cin input yog

zoo ib yam rau tus cwj pwm ntawm cnt_en tswv yim. Yog tias tshem tawm, tus nqi pib yog 1

(VCC).

aclr

Tsis muaj

Asynchronous ntshiab input. Yog tias ob qho tib si aset thiab aclr tau siv thiab lees paub, aclr overrides asset. Yog tias tshem tawm, tus nqi pib yog 0 (disabled).

khoom

Tsis muaj

Asynchronous teeb input. Qhia qhov q[] outputs raws li tag nrho 1s, los yog rau tus nqi teev los ntawm LPM_AVALUE parameter. Yog tias ob qho tib si aset thiab aclr ports tau siv thiab lees paub, tus nqi ntawm qhov chaw nres nkoj aclr overrides tus nqi ntawm qhov chaw nres nkoj aset. Yog tias tshem tawm, tus nqi pib yog 0, xiam oob qhab.

aload ua

Tsis muaj

Asynchronous load input uas asynchronously loads lub txee nrog tus nqi ntawm cov ntaub ntawv nkag. Thaum siv qhov chaw nres nkoj aload, cov ntaub ntawv [] chaw nres nkoj yuav tsum txuas nrog. Yog tias tshem tawm, tus nqi pib yog 0, xiam oob qhab.

ua sclr

Tsis muaj

Synchronous clear input uas clears lub txee ntawm lub tom ntej no active moos ntug. Yog tias ob qho tib si sset thiab sclr chaw nres nkoj tau siv thiab lees paub, tus nqi ntawm qhov chaw nres nkoj sclr overrides tus nqi ntawm qhov chaw nres nkoj sset. Yog tias tshem tawm, tus nqi pib yog 0, xiam oob qhab.

sset

Tsis muaj

Synchronous teeb input uas teeb lub txee rau ntawm lub moos tom ntej. Qhia tus nqi ntawm q cov zis raws li tag nrho 1s, lossis rau tus nqi teev los ntawm LPM_SVALUE parameter. Yog tias ob qho tib si sset thiab sclr chaw nres nkoj tau siv thiab lees paub,
tus nqi ntawm qhov chaw nres nkoj sclr overrides tus nqi ntawm qhov chaw nres nkoj sset. Yog tias tshem tawm, tus nqi pib yog 0 (disabled).

sload

Tsis muaj

Synchronous load input uas thauj cov txee nrog cov ntaub ntawv[] ntawm lub moos tom ntej. Thaum siv qhov chaw nres nkoj sload, cov ntaub ntawv [] chaw nres nkoj yuav tsum txuas nrog. Yog tias tshem tawm, tus nqi pib yog 0 (disabled).

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2. LPM_COUNTER (Counter) IP Core 683490 | 2020.10.05

Table 3.

LPM_COUNTER Output Ports

Chaw nres nkoj npe

Yuav tsum tau

Kev piav qhia

q[]

Tsis muaj

Cov ntaub ntawv tso tawm los ntawm lub txee. Qhov loj ntawm qhov chaw nres nkoj tso zis nyob ntawm qhov

LPM_WIDTH parameter tus nqi. Q[] lossis tsawg kawg ib qho ntawm eq[15..0] chaw nres nkoj

yuav tsum muaj txuas nrog.

ib[15..0]

Tsis muaj

Counter decode tso zis. Qhov chaw nres nkoj eq[15..0] tsis tuaj yeem nkag mus rau hauv qhov parameter editor vim tias qhov parameter tsuas yog txhawb nqa AHDL.
Qhov chaw nres nkoj q[] lossis eq[] chaw nres nkoj yuav tsum txuas nrog. Txog c eq ports tuaj yeem siv tau (0 <= c <= 15). Tsuas yog 16 tus lej suav qis tshaj plaws tau txiav txim siab. Thaum suav tus nqi yog c, cov zis eqc tau lees tias siab (1). Rau example, thaum suav yog 0, eq0 = 1, thaum suav yog 1, eq1 = 1, thiab thaum suav yog 15, eq 15 = 1. Decoded output rau suav qhov tseem ceeb ntawm 16 los yog ntau dua yuav tsum tau sab nraud decoding. Lub eq[15..0] outputs yog asynchronous rau q[] output.

cout

Tsis muaj

Nqa tawm qhov chaw nres nkoj ntawm lub txee lub MSB me ntsis. Nws tuaj yeem siv los txuas rau lwm lub txee los tsim lub txee loj dua.

2.6. Cov tsis

Cov lus hauv qab no teev cov kev txwv rau LPM_COUNTER IP core.

Table 4.

LPM_COUNTER Parameters

Lub npe Parameter

Hom

LPM_WIDTH

Tus lej

LPM_DIRECTION

Txoj hlua

LPM_MODULUS LPM_AVALUE

Tus lej
Integer/String

LPM_SVALUE LPM_HINT

Integer/String
Txoj hlua

LPM_TYPE

Txoj hlua

Yuav Tsum Tau Yog Tsis Yog Tsis Yog No
Tsis muaj
Tsis muaj

Kev piav qhia
Qhia qhov dav ntawm cov ntaub ntawv[] thiab q[] chaw nres nkoj, yog tias lawv siv.
Tus nqi yog nce, nqis, thiab tsis siv. Yog tias siv LPM_DIRECTION parameter, qhov chaw nres nkoj updown tsis tuaj yeem txuas nrog. Thaum qhov chaw nres nkoj updown tsis txuas, LPM_DIRECTION parameter default value yog UP.
Qhov siab tshaj plaws suav, ntxiv rau ib qho. Tus naj npawb ntawm cov xeev tshwj xeeb hauv lub txee lub voj voog. Yog tias tus nqi thauj khoom loj dua li LPM_MODULUS parameter, tus cwj pwm ntawm lub txee tsis tau teev tseg.
Tus nqi tas li uas yog loaded thaum asset asserted siab. Yog tias tus nqi teev loj dua lossis sib npaug , tus cwj pwm ntawm lub txee yog undefined (X) logic theem, qhov twg yog LPM_MODULUS, yog tam sim no, lossis 2 ^ LPM_WIDTH. Intel xav kom koj qhia tus nqi no ua tus lej lej rau AHDL tsim.
Tus nqi tas li uas tau thauj khoom ntawm ntug nce ntawm lub moos chaw nres nkoj thaum lub chaw nres nkoj sset tau lees paub siab. Intel xav kom koj qhia tus nqi no ua tus lej lej rau AHDL tsim.
Thaum koj instantiate lub tsev qiv ntawv ntawm parameterized modules (LPM) muaj nuj nqi hauv VHDL Tsim File (.vhd), koj yuav tsum siv LPM_HINT parameter los qhia txog qhov tshwj xeeb ntawm Intel. Rau example: LPM_HINT = “CHAIN_SIZE = 8, ONE_INPUT_IS_CONSTANT = YOG”
Tus nqi pib yog UNUSED.
Txheeb xyuas lub tsev qiv ntawv ntawm parameterized modules (LPM) lub npe lub npe hauv VHDL tsim files.
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Parameter Name INTENDED_DEVICE_FAMILY CARRY_CNT_EN
LABWIDE_SCLR
LPM_PORT_UPDOWN

Hom hlua hlua
Txoj hlua
Txoj hlua

Yuav tsum tsis muaj
Tsis muaj
Tsis muaj

Kev piav qhia
Qhov kev ntsuas no yog siv rau kev ua qauv thiab kev coj tus cwj pwm simulation lub hom phiaj. Qhov kev ntsuas no yog siv rau kev ua qauv thiab kev coj tus cwj pwm simulation lub hom phiaj. Tus parameter editor xam tus nqi rau qhov parameter no.
Intel tshwj xeeb parameter. Koj yuav tsum siv LPM_HINT parameter los qhia CARRY_CNT_EN parameter hauv VHDL tsim files. Tus nqi yog SMART, ON, OFF, thiab tsis siv. Ua kom lub LPM_COUNTER muaj nuj nqi los tshaj tawm cov teeb liab cnt_en los ntawm cov saw saw. Qee zaum, CARRY_CNT_EN parameter teeb tsa yuav muaj kev cuam tshuam me ntsis ntawm qhov nrawm, yog li koj yuav xav tua nws. Lub neej ntawd tus nqi yog SMART, uas muab qhov zoo tshaj plaws kev lag luam tawm ntawm qhov loj thiab ceev.
Intel tshwj xeeb parameter. Koj yuav tsum siv LPM_HINT parameter los qhia qhov LABWIDE_SCLR parameter hauv VHDL tsim files. Tus nqi yog ON, OFF, lossis tsis siv. Tus nqi pib yog ON. Tso cai rau koj los lov tes taw kev siv LABwide sclr feature pom nyob rau hauv obsoleted cov tsev neeg. Tig qhov kev xaiv no tawm yuav ua rau muaj feem ntau ntawm kev siv tag nrho cov LABs ib nrab, thiab yog li yuav tso cai rau cov logic ceev dua thaum SCLR tsis siv rau LAB ua tiav. Qhov kev ntsuas no muaj rau kev rov qab sib raug zoo, thiab Intel xav kom koj tsis txhob siv qhov ntsuas no.
Qhia meej txog kev siv lub updown input chaw nres nkoj. Yog tias tshem tawm tus nqi qub yog PORT_CONNECTIVITY. Thaum tus nqi chaw nres nkoj tau teem rau PORT_USED, qhov chaw nres nkoj raug kho raws li siv. Thaum tus nqi chaw nres nkoj tau teeb tsa rau PORT_UNUSED, qhov chaw nres nkoj raug kho raws li tsis siv. Thaum tus nqi chaw nres nkoj tau teeb tsa rau PORT_CONNECTIVITY, kev siv chaw nres nkoj txiav txim siab los ntawm kev txheeb xyuas qhov chaw nres nkoj txuas.

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3. LPM_DIVIDE (Divider) Intel FPGA IP Core

Daim duab 2.

Lub LPM_DIVIDE Intel FPGA IP core siv ib qho kev faib los faib tus lej suav nrog tus nqi nkag los ntawm tus lej tus lej nkag los tsim cov khoom siv thiab qhov seem.

Cov duab hauv qab no qhia cov chaw nres nkoj rau LPM_DIVIDE IP core.

LPM_DIVIDE Chaw nres nkoj

LPM_DIVIDE

numer[] denom[] moos

quotient[] nyob []

ua aclr

inst

3.1. Nta
Lub LPM_DIVIDE IP core muaj cov yam ntxwv hauv qab no: · Tsim ib qho kev faib tawm uas faib tus lej suav nrog tus nqi nkag los ntawm tus lej tawm tswv yim
tus nqi los tsim ib qho quotient thiab seem. · Txhawb cov ntaub ntawv dav ntawm 1 ntsis. · Txhawb kev kos npe thiab tsis kos npe cov ntaub ntawv sawv cev rau ob qho tib si tus lej
thiab tus nqi denominator. · Txhawb cheeb tsam lossis kev ua kom zoo. · Muab ib qho kev xaiv los qhia kom meej qhov zoo seem tso zis. · Txhawb pipelining configurable tso zis latency. · Txhawb kev xaiv asynchronous ntshiab thiab moos pab cov chaw nres nkoj.

3.2. Verilog HDL Prototype
Cov nram qab no Verilog HDL qauv yog nyob rau hauv Verilog Design File (.v) lpm.v in the edasynthesis directory.
module lpm_divide ( quotient, seem, tus lej, tus lej, moos, clken, aclr); parameter lpm_type = "lpm_divide"; parameter lpm_widthn = 1; parameter lpm_widthd = 1; parameter lpm_nrepresentation = "UNSIGNED"; parameter lpm_drepresentation = "UNSIGNED"; parameter lpm_remainderpositive = “TRUE”; parameter lpm_pipeline = 0;

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parameter lpm_hint = "UNUSED"; input moos; input clken; input aclr; input [lpm_widthn-1:0] tus lej; input [lpm_widthd-1:0] npe; tso zis [lpm_widthn-1:0] quotient; tso zis [lpm_widthd-1:0] nyob twj ywm; endmodule

3.3. VHDL Component Tshaj Tawm
VHDL cov lus tshaj tawm yog nyob hauv VHDL Tsim File (.vhd) LPM_PACK.vhd hauv librariesvhdllpm directory.
tivthaiv LPM_DIVIDE generic (LPM_WIDTHN : ntuj; LPM_WIDTHD : ntuj;
LPM_NREPRESENTATION : string := “UNSIGNED”; LPM_DREPRESENTATION : string := “UNSIGNED”; LPM_PIPELINE : ntuj := 0; LPM_TYPE : hlua := L_DIVIDE; LPM_HINT : string := "UNUSED"); chaw nres nkoj (NUMER : in std_logic_vector(LPM_WIDTHN-1 downto 0); DENOM : in std_logic_vector(LPM_WIDTHD-1 downto 0); ACLR : in std_logic := '0'; CLOCK : in std_logic := '0'; := '1'; QUOTIENT : out std_logic_vector(LPM_WIDTHN-1 downto 0); kawg tivthaiv;

3.4. VHDL LIBRARY_USE tshaj tawm
Daim ntawv tshaj tawm VHDL LIBRARY-SIV tsis tas yuav yog tias koj siv VHDL Cov Lus Tshaj Tawm.
LIBRARY lpm; USE lpm.lpm_components.all;

3.5. Chaw nres nkoj

Cov lus hauv qab no teev cov tswv yim thiab cov chaw nres nkoj rau LPM_DIVIDE IP core.

Table 5.

LPM_DIVIDE Input Ports

Chaw nres nkoj npe

Yuav tsum tau

tus lej[]

Yog lawm

npe[]

Yog lawm

Kev piav qhia
Numerator data input. Qhov loj ntawm qhov chaw nres nkoj nkag yog nyob ntawm LPM_WIDTHN tus nqi parameter.
Denominator data input. Qhov loj ntawm qhov chaw nres nkoj nkag yog nyob ntawm LPM_WIDTHD parameter tus nqi.
txuas ntxiv…

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Chaw nres nkoj lub npe moos clken
aclr

Yuav tsum tsis muaj
Tsis muaj

Kev piav qhia
Clock input rau pipelined siv. Rau LPM_PIPELINE qhov tseem ceeb uas tsis yog 0 (default), lub moos chaw nres nkoj yuav tsum tau qhib.
Lub moos pab kev siv cov kav dej. Thaum qhov chaw nres nkoj clken tau lees paub siab, kev faib ua haujlwm yuav tshwm sim. Thaum lub teeb liab qis, tsis muaj kev ua haujlwm tshwm sim. Yog tias tshem tawm, tus nqi pib yog 1.
Asynchronous ntshiab chaw nres nkoj siv txhua lub sijhawm los rov pib dua lub raj xa mus rau tag nrho '0's asynchronously rau lub moos nkag.

Table 6.

LPM_DIVIDE Output Ports

Chaw nres nkoj npe

Yuav tsum tau

Kev piav qhia

quotient[]

Yog lawm

Cov ntaub ntawv tso tawm. Qhov loj ntawm qhov chaw nres nkoj tso zis nyob ntawm LPM_WIDTHN

tus nqi parameter.

nyob []

Yog lawm

Cov ntaub ntawv tawm. Qhov loj ntawm qhov chaw nres nkoj tso zis nyob ntawm LPM_WIDTHD

tus nqi parameter.

3.6. Cov tsis

Cov lus hauv qab no teev cov kev txwv rau LPM_DIVIDE Intel FPGA IP core.

Lub npe Parameter

Hom

Yuav tsum tau

Kev piav qhia

LPM_WIDTHN

Tus lej

Yog lawm

Qhia qhov dav ntawm tus lej[] thiab

quotient[] chaw nres nkoj. Tus nqi yog 1 txog 64.

LPM_WIDTHD

Tus lej

Yog lawm

Qhia qhov dav ntawm tus denom[] thiab

nyob [] ports. Tus nqi yog 1 txog 64.

LPM_NREPRESENTATION LPM_DREPRESENTATION

Txoj hlua hlua

Tsis muaj

Kos npe sawv cev ntawm tus lej input.

Tus nqi yog SAU thiab UNSIGNED. Thaum no

parameter yog teem rau SIGNED, lub divider

txhais tus lej[] input raws li kos npe ob tus

ntxiv.

Tsis muaj

Kos npe sawv cev ntawm tus denominator input.

Tus nqi yog SAU thiab UNSIGNED. Thaum no

parameter yog teem rau SIGNED, lub divider

txhais lub denom[] input raws li kos npe ob tus

ntxiv.

LPM_TYPE

Txoj hlua

Tsis muaj

Txheeb xyuas lub tsev qiv ntawv ntawm parameterized

modules (LPM) lub npe chaw nyob hauv VHDL tsim

files (.vhd).

LPM_HINT

Txoj hlua

Tsis muaj

Thaum koj instantiate ib lub tsev qiv ntawv ntawm

parameterized modules (LPM) muaj nuj nqi hauv a

VHDL Design File (.vhd), koj yuav tsum siv lub

LPM_HINT parameter los qhia txog Intel-

tshwj xeeb parameter. Rau example: LPM_HINT

= “CHAIN_SIZE = 8,

ONE_INPUT_IS_CONSTANT = YOG” Tus

default value yog UNUSED.

LPM_REMAINDERPOSITIVE

Txoj hlua

Tsis muaj

Intel tshwj xeeb parameter. Koj yuav tsum siv lub

LPM_HINT parameter los qhia qhov

LPM_REMAINDERPOSITIVE parameter hauv

VHDL tsim files. Tus nqi yog TRUE lossis FALSE.

Yog hais tias qhov parameter no yog teem rau TRUE, ces tus

tus nqi ntawm qhov seem [] chaw nres nkoj yuav tsum ntau dua

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Lub npe Parameter

Hom

MAXIMIZE_SPEED

Tus lej

LPM_PIPELINE

Tus lej

INTENDED_DEVICE_FAMILY SKIP_BITS

Txoj hlua Integer

Yuav tsum tau No
Tsis yog No

Kev piav qhia
tshaj los yog sib npaug rau xoom. Yog tias qhov ntsuas no tau teeb tsa rau TRUE, ces tus nqi ntawm qhov seem [] chaw nres nkoj yog xoom, lossis tus nqi yog tib lub cim, qhov zoo lossis qhov tsis zoo, raws li tus nqi ntawm tus lej chaw nres nkoj. Txhawm rau txo thaj tsam thiab txhim kho kev nrawm, Intel pom zoo kom teeb tsa qhov ntsuas no rau TRUE hauv kev ua haujlwm uas qhov seem yuav tsum yog qhov zoo lossis qhov seem uas tsis tseem ceeb.
Intel tshwj xeeb parameter. Koj yuav tsum siv LPM_HINT parameter los qhia qhov MAXIMIZE_SPEED parameter hauv VHDL tsim files. Tus nqi yog [0..9]. Yog tias siv, Intel Quartus Prime software sim ua kom zoo dua ib qho piv txwv ntawm LPM_DIVIDE muaj nuj nqi rau kev nrawm dua li kev ua haujlwm, thiab overrides qhov chaw ntawm Optimization Technique logic xaiv. Yog tias MAXIMIZE_SPEED tsis siv, tus nqi ntawm Optimization Technique xaiv yog siv los hloov. Yog hais tias tus nqi ntawm MAXIMIZE_SPEED yog 6 los yog siab dua, lub Compiler optimizes LPM_DIVIDE IP core kom ceev dua los ntawm kev siv nqa chains; Yog hais tias tus nqi yog 5 los yog tsawg dua, lub compiler siv tus tsim yam tsis muaj chains.
Qhia tus naj npawb ntawm lub voj voog ntawm latency txuam nrog cov quotient[] thiab nyob twj ywm [] outputs. Tus nqi ntawm xoom (0) qhia tias tsis muaj latency tshwm sim, thiab qhov ua tiav ua ke ua ke yog instantiated. Yog tias tshem tawm, tus nqi pib yog 0 (nonpipelined). Koj tsis tuaj yeem qhia tus nqi rau LPM_PIPELINE parameter uas siab dua LPM_WIDTHN.
Qhov kev ntsuas no yog siv rau kev ua qauv thiab kev coj tus cwj pwm simulation lub hom phiaj. Tus parameter editor xam tus nqi rau qhov parameter no.
Tso cai rau kom muaj txiaj ntsig ntau dua qhov kev faib me me kom ua kom zoo dua cov ntsiab lus ntawm cov khoom ua ntej los ntawm kev muab cov naj npawb ntawm GND rau LPM_DIVIDE IP core. Qhia tus naj npawb ntawm GND ua rau ntawm qhov tso zis tawm rau qhov ntsuas no.

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4. LPM_MULT (Multiplier) IP Core

Daim duab 3.

LPM_MULT IP core siv tus lej sib npaug los muab ob qhov kev nkag siab cov ntaub ntawv tsim nyog los tsim cov khoom lag luam raws li cov khoom tsim tawm.

Cov duab hauv qab no qhia cov chaw nres nkoj rau LPM_MULT IP core.

LPM_Mult Ports

LPM_MULT moos dataa[] result[] datab[] aclr/sclr clken
inst

Cov Ntaub Ntawv Tseem Ceeb Ntawm nplooj 71

4.1. Nta
Lub LPM_MULT IP core muaj cov yam ntxwv hauv qab no: · Tsim kom muaj qhov sib npaug uas sib npaug ntawm ob qhov kev tawm tswv yim cov ntaub ntawv muaj nuj nqis · Txhawb cov ntaub ntawv dav ntawm 1 khoom · Txhawb kev kos npe thiab tsis kos npe cov ntaub ntawv sawv cev · Txhawb cheeb tsam lossis kev ua kom zoo dua · Txhawb cov raj xa dej nrog cov zis tawm latency · Muab ib qho kev xaiv rau kev siv nyob rau hauv kev mob siab rau digital signal processing (DSP)
thaiv circuitry lossis logic ntsiab (LEs) Ceeb toom: Thaum tsim cov multipliers loj dua li qhov kev txhawb nqa ib txwm muaj tuaj yeem /
yuav yog qhov ua tau zoo cuam tshuam los ntawm cascading ntawm DSP blocks. · Txhawb kev xaiv asynchronous ntshiab thiab moos pab cov tswv yim ports · Txhawb kev xaiv synchronous ntshiab rau Intel Stratix 10, Intel Arria 10 thiab Intel Cyclone 10 GX li

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4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05
4.2. Verilog HDL Prototype
Cov nram qab no Verilog HDL qauv yog nyob rau hauv Verilog Design File (.v) lpm.v in the edasynthesis directory.
module lpm_mult ( result, dataa, datab, sum, moos, clken, aclr ) parameter lpm_type = "lpm_mult"; parameter lpm_widtha = 1; parameter lpm_widthb = 1; parameter lpm_widths = 1; parameter lpm_widthp = 1; parameter lpm_representation = "UNSIGNED"; parameter lpm_pipeline = 0; parameter lpm_hint = "UNUSED"; input moos; input clken; input aclr; input [lpm_widtha-1:0] dataa; input [lpm_widthb-1:0] datab; tswv yim [lpm_widths-1:0] sum; tso zis [lpm_widthp-1:0] result; endmodule
4.3. VHDL Component Tshaj Tawm
VHDL cov lus tshaj tawm yog nyob hauv VHDL Tsim File (.vhd) LPM_PACK.vhd hauv librariesvhdllpm directory.
tivthaiv LPM_MULT generic ( LPM_WIDTHA : natural; LPM_WIDTHB : natural; LPM_WIDTHS : natural := 1; LPM_WIDTHP : natural;
LPM_REPRESENTATION : string := “UNSIGNED”; LPM_PIPELINE : ntuj := 0; LPM_TYPE: txoj hlua := L_MULT; LPM_HINT : string := "UNUSED"); port ( DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0); DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0); ACLR : in std_logic := '0'; CLOCK : in std_logic := '0'; := '1'; SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0'); kawg tivthaiv;
4.4. VHDL LIBRARY_USE tshaj tawm
Daim ntawv tshaj tawm VHDL LIBRARY-SIV tsis tas yuav yog tias koj siv VHDL Cov Lus Tshaj Tawm.
LIBRARY lpm; USE lpm.lpm_components.all;

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4.5. Teeb liab

Table 7.

LPM_MULT Input Signals

Lub Npe Lub Npe

Yuav tsum tau

Kev piav qhia

dataa[]

Yog lawm

Cov ntaub ntawv nkag.

Rau Intel Stratix 10, Intel Arria 10, thiab Intel Cyclone 10 GX li, qhov loj ntawm lub teeb liab tawm tswv yim nyob ntawm Dataa width parameter tus nqi.

Rau cov laus thiab Intel Cyclone 10 LP cov khoom siv, qhov loj ntawm cov teeb liab tawm tswv yim nyob ntawm tus nqi LPM_WIDTHA parameter.

datab[]

Yog lawm

Cov ntaub ntawv nkag.

Rau Intel Stratix 10, Intel Arria 10, thiab Intel Cyclone 10 GX pab kiag li lawm, qhov loj ntawm cov tswv yim teeb liab nyob ntawm Datab width parameter tus nqi.

Rau cov laus thiab Intel Cyclone 10 LP cov khoom siv, qhov loj ntawm cov teeb liab tawm tswv yim nyob ntawm

ntawm LPM_WIDTHB tus nqi parameter.

moos

Tsis muaj

Clock input rau pipelined siv.

Rau cov laus thiab Intel Cyclone 10 LP cov khoom siv, lub moos teeb liab yuav tsum tau qhib rau LPM_PIPELINE qhov tseem ceeb uas tsis yog 0 (default).

Rau Intel Stratix 10, Intel Arria 10, thiab Intel Cyclone 10 GX li, lub moos teeb liab yuav tsum tau qhib yog tias tus nqi Latency yog lwm yam tshaj li 1 (default).

clken ua

Tsis muaj

Clock enables rau pipelined siv. Thaum lub teeb liab clken yog asserted siab, lub

kev ua haujlwm adder/subtractor tshwm sim. Thaum lub teeb liab qis, tsis muaj kev ua haujlwm

tshwm sim. Yog tias tshem tawm, tus nqi pib yog 1.

aclr ua

Tsis muaj

Asynchronous meej teeb liab siv txhua lub sijhawm los rov pib dua cov kav dej rau txhua qhov 0s,

asynchronously rau lub moos teeb liab. Lub raj xa dej pib mus rau qhov tsis tau txhais (X)

qib logic. Cov txiaj ntsig tau zoo ib yam, tab sis tsis yog xoom tus nqi.

Tsis muaj

Synchronous ntshiab teeb liab siv txhua lub sijhawm los rov pib dua cov kav dej rau tag nrho 0s,

synchronously rau lub moos teeb liab. Lub raj xa dej pib mus rau qhov tsis tau txhais (X)

qib logic. Cov txiaj ntsig tau zoo ib yam, tab sis tsis yog xoom tus nqi.

Table 8.

LPM_MULT tso zis teeb liab

teeb liab npe

Yuav tsum tau

Kev piav qhia

tshwm sim[]

Yog lawm

Cov ntaub ntawv tawm.

Rau cov laus thiab Intel Cyclone 10 LP cov khoom siv, qhov loj ntawm cov teeb liab tso tawm nyob ntawm LPM_WIDTHP tus nqi parameter. Yog tias LPM_WIDTHP <max (LPM_WIDTHA + LPM_WIDTHB, LPM_WIDTHS) lossis (LPM_WIDTHA + LPM_WIDTHS), tsuas yog LPM_WIDTHP MSBs tam sim no.

Rau Intel Stratix 10, Intel Arria 10 thiab Intel Cyclone 10 GX, qhov loj ntawm cov teeb liab tso tawm nyob ntawm qhov ntsuas qhov dav.

4.6. Parameters rau Stratix V, Arria V, Cyclone V, thiab Intel Cyclone 10 LP Devices

4.6.1. General Tab

Table 9.

General Tab

Parameter

Tus nqi

Multiplier Configuration

Multiply 'dataa' input los ntawm 'datab' input

Default tus nqi

Kev piav qhia

Multiply 'dataa' input los ntawm 'datab' input

Xaiv qhov xav tau configuration rau tus multiplier.
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Parameter
Yuav tsum dav npaum li cas 'dataa' input? Yuav tsum dav npaum li cas 'datab' input? Yuav ua li cas qhov dav ntawm 'qhov tshwm sim' tso zis yuav txiav txim siab? Txwv qhov dav

Tus nqi
Multiply 'dataa' input los ntawm nws tus kheej (squaring lag luam)
1-256 ib

Default tus nqi

Kev piav qhia

8 bits

Qhia qhov dav ntawm dataa[] chaw nres nkoj.

1-256 ib

8 bits

Qhia qhov dav ntawm datab[] chaw nres nkoj.

Cia li xam qhov dav txwv qhov dav
1-512 ib

Automaticall y xam qhov dav

Xaiv txoj kev xav tau los txiav txim qhov dav ntawm qhov tshwm sim[] chaw nres nkoj.

16 bits

Qhia qhov dav ntawm qhov tshwm sim[] chaw nres nkoj.
Tus nqi no tsuas yog siv tau yog tias koj xaiv txwv qhov dav hauv Hom parameter.

4.6.2 ib. General 2 Tab

Table 10. General 2 Tab

Parameter

Tus nqi

Datab Input

Puas yog 'datab' input bus puas muaj tus nqi tas li?

Tsis Yog

Ntau hom

Yam twg

Tsis tau kos npe

koj puas xav tau multiplication? Kos npe

Kev nqis tes ua

Qhov kev siv ntau npaum li cas yuav tsum tau siv?

Siv qhov kev siv ua ntej
Siv lub tshuab hluav taws xob sib txuas ua ke (Tsis muaj rau txhua tsev neeg)
Siv cov ntsiab lus logic

Default tus nqi

Kev piav qhia

Tsis muaj

Xaiv Yog kom qhia tus nqi tas li ntawm qhov

'datab' input bus, yog muaj.

Tsis tau kos npe

Qhia cov qauv kev sawv cev rau ob qho tib si dataa[] thiab datab[] inputs.

Siv lub neej ntawd siv ion

Xaiv txoj kev xav tau los txiav txim qhov dav ntawm qhov tshwm sim[] chaw nres nkoj.

4.6.3. Pipelining Tab

Table 11. Pipelining Tab

Parameter

Koj puas xav xa daim ntawv No

muaj nuj nqi?

Yog lawm

Tus nqi

Tsim ib qho 'aclr'

—

asynchronous clear port

Default tus nqi

Kev piav qhia

Tsis muaj

Xaiv Yog los pab cov raj xa mus rau npe rau

multiplier cov zis thiab qhia qhov xav tau

tso zis latency nyob rau hauv lub voj voog moos. Enabling cov

pipeline register ntxiv latency ntxiv rau lub

tso zis.

Unchecked

Xaiv qhov kev xaiv no los pab kom aclr chaw nres nkoj siv asynchronous ntshiab rau cov raj xa dej npe.
txuas ntxiv…

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Parameter
Tsim lub 'clken' moos pab lub moos
Kev ua kom zoo
Hom kev optimization twg koj xav tau?

Tus nqi —
Default Speed Area

Default tus nqi

Kev piav qhia

Unchecked

Qhia meej lub moos siab ua haujlwm rau lub moos chaw nres nkoj ntawm lub raj xa dej npe

Default

Qhia qhov xav tau optimization rau tus IP core.
Xaiv Default kom cia Intel Quartus Prime software los txiav txim qhov kev ua kom zoo tshaj plaws rau IP core.

4.7. Parameters rau Intel Stratix 10, Intel Arria 10, thiab Intel Cyclone 10 GX Devices

4.7.1. General Tab

Table 12. General Tab

Parameter

Tus nqi

Default tus nqi

Kev piav qhia

Multiplier Configuration Hom
Data Port Widths

Multiply 'dataa' input los ntawm 'datab' input
Multiply 'dataa' input los ntawm nws tus kheej (squaring lag luam)

Multiply 'dataa' input los ntawm 'datab' input

Xaiv qhov xav tau configuration rau tus multiplier.

Data dav

1-256 ib

8 bits

Qhia qhov dav ntawm dataa[] chaw nres nkoj.

Datab dav

1-256 ib

8 bits

Qhia qhov dav ntawm datab[] chaw nres nkoj.

Yuav ua li cas qhov dav ntawm 'qhov tshwm sim' tso zis yuav txiav txim siab?

Hom

Yeej xam qhov dav
Txwv qhov dav

Automaticall y xam qhov dav

Xaiv txoj kev xav tau los txiav txim qhov dav ntawm qhov tshwm sim[] chaw nres nkoj.

Tus nqi

1-512 ib

16 bits

Qhia qhov dav ntawm qhov tshwm sim[] chaw nres nkoj.
Tus nqi no tsuas yog siv tau yog tias koj xaiv txwv qhov dav hauv Hom parameter.

Qhov dav dav

1-512 ib

—

Qhia qhov dav dav ntawm qhov tshwm sim[] chaw nres nkoj.

4.7.2 ib. General 2 Tab

Table 13. General 2 Tab

Parameter

Datab Input

Puas yog 'datab' input bus puas muaj tus nqi tas li?

Tsis Yog

Tus nqi

Default tus nqi

Kev piav qhia

Tsis muaj

Xaiv Yog kom qhia tus nqi tas li ntawm qhov

'datab' input bus, yog muaj.

txuas ntxiv…

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Parameter

Tus nqi

Txhua tus nqi ntau dua 0

Ntau hom

Yam twg

Tsis tau kos npe

koj puas xav tau multiplication? Kos npe

Kev ua qauv

Qhov kev siv ntau npaum li cas yuav tsum tau siv?

Siv qhov kev siv ua ntej
Siv lub tshuab hluav taws xob sib txuas tshwj xeeb
Siv cov ntsiab lus logic

Default tus nqi

Kev piav qhia

Qhia tus nqi tas li ntawm datab[] chaw nres nkoj.

Tsis tau kos npe

Qhia cov qauv kev sawv cev rau ob qho tib si dataa[] thiab datab[] inputs.

Siv lub neej ntawd siv ion

Xaiv txoj kev xav tau los txiav txim qhov dav ntawm qhov tshwm sim[] chaw nres nkoj.

4.7.3 ib. Cov kav dej

Table 14. Pipelining Tab

Parameter

Tus nqi

Koj puas xav xa cov kev ua haujlwm?

Cov kav dej

Tsis Yog

Latency Clear Signal Hom

Txhua tus nqi ntau dua 0.
TSIS MUAJ ACLR SCLR

Tsim lub moos 'clken'

—

qhib lub moos

Hom kev optimization twg koj xav tau?

Hom

Default Speed Area

Default tus nqi

Kev piav qhia

1 NEEJ
—

Xaiv Yog los qhib cov raj xa mus rau tus lej ntau qhov tso zis. Ua kom lub raj xa dej tso npe ntxiv latency ntxiv rau cov zis.
Qhia qhov xav tau tso zis latency hauv lub voj voog moos.
Qhia meej txog hom kev pib dua tshiab rau lub raj xa dej npe. Xaiv TSIS yog tias koj tsis siv cov npe kav dej. Xaiv ACLR los siv asynchronous ntshiab rau lub raj xa dej npe. Qhov no yuav tsim ACLR chaw nres nkoj. Xaiv SCLR siv synchronous ntshiab rau cov raj xa dej npe. Qhov no yuav tsim SCLR chaw nres nkoj.
Qhia meej lub moos siab ua haujlwm rau lub moos chaw nres nkoj ntawm lub raj xa dej npe

Default

Qhia qhov xav tau optimization rau tus IP core.
Xaiv Default kom cia Intel Quartus Prime software los txiav txim qhov zoo tshaj plaws optiomization rau tus tub ntxhais IP.

Xa lus tawm tswv yim

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5. LPM_ADD_SUB (Adder/Subtractor)

Daim duab 4.

LPM_ADD_SUB IP core tso cai rau koj siv tus adder lossis tus rho tawm los ntxiv lossis rho tawm cov ntaub ntawv los tsim cov txiaj ntsig uas muaj cov lej lossis qhov sib txawv ntawm cov khoom nkag.

Cov duab hauv qab no qhia cov chaw nres nkoj rau LPM_ADD_SUB IP core.

LPM_ADD_SUB Ports

LPM_ADD_SUB add_sub cin

dataa[]

moos clken datab[] aclr

result[] overflow cout

inst

5.1. Nta
Lub LPM_ADD_SUB IP core muaj cov yam ntxwv hauv qab no: · Tsim cov adder, rho tawm, thiab dynamically configurable adder/subtractor
muaj nuj nqi. · Txhawb cov ntaub ntawv dav ntawm 1 ntsis. · Txhawb cov ntaub ntawv sawv cev xws li kos npe thiab tsis kos npe. · Txhawb kev xaiv nqa-hauv (qiv-tawm), asynchronous clear, thiab moos pab
input ports. · Txhawb kev yeem nqa tawm (qiv-hauv) thiab cov chaw tso zis ntau dhau. · Muab ib qho ntawm cov ntaub ntawv nkag mus rau qhov tsis tu ncua. · Txhawb pipelining nrog configurable tso zis latency.

Daim ntawv pov thawj ISO 9001: 2015

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05
5.2. Verilog HDL Prototype
Cov nram qab no Verilog HDL qauv yog nyob rau hauv Verilog Design File (.v) lpm.v in the edasynthesis directory.
module lpm_add_sub ( result, cout, overflow, add_sub, cin, dataa, datab, moos, clken, aclr ); parameter lpm_type = "lpm_add_sub"; parameter lpm_width = 1; parameter lpm_direction = "UNUSED"; parameter lpm_representation = "SIGNED"; parameter lpm_pipeline = 0; parameter lpm_hint = "UNUSED"; input [lpm_width-1:0] dataa, datab; input add_sub, cin; input moos; input clken; input aclr; tso zis [lpm_width-1:0] result; tso zis cout, overflow; endmodule
5.3. VHDL Component Tshaj Tawm
VHDL cov lus tshaj tawm yog nyob hauv VHDL Tsim File (.vhd) LPM_PACK.vhd hauv librariesvhdllpm directory.
tivthaiv LPM_ADD_SUB generic (LPM_WIDTH : ntuj;
LPM_DIRECTION : string := “UNUSED”; LPM_REPRESENTATION: txoj hlua := “SIGNED”; LPM_PIPELINE : ntuj := 0; LPM_TYPE : string := L_ADD_SUB; LPM_HINT : string := "UNUSED"); port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0); DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0); ACLR : in std_logic := '0'; CLOCK : in std_logic := '0'; := '1'; CIN : in std_logic := 'Z'; kawg tivthaiv;
5.4. VHDL LIBRARY_USE tshaj tawm
Daim ntawv tshaj tawm VHDL LIBRARY-SIV tsis tas yuav yog tias koj siv VHDL Cov Lus Tshaj Tawm.
LIBRARY lpm; USE lpm.lpm_components.all;
5.5. Chaw nres nkoj
Cov lus hauv qab no teev cov tswv yim thiab cov chaw nres nkoj tawm rau LPM_ADD_SUB IP core.

Xa lus tawm tswv yim

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Table 15. LPM_ADD_SUB IP Core Input Ports

Chaw nres nkoj npe

Yuav tsum tau

Kev piav qhia

ua cin

Tsis muaj

Nqa mus rau qhov kev txiav txim qis qis. Rau kev ua haujlwm ntxiv, tus nqi pib yog 0. Rau

Kev rho tawm haujlwm, tus nqi pib yog 1.

dataa[]

Yog lawm

Cov ntaub ntawv nkag. Qhov loj ntawm qhov chaw nres nkoj nkag yog nyob ntawm LPM_WIDTH parameter tus nqi.

datab[]

Yog lawm

Cov ntaub ntawv nkag. Qhov loj ntawm qhov chaw nres nkoj nkag yog nyob ntawm LPM_WIDTH parameter tus nqi.

add_sub

Tsis muaj

Optional input chaw nres nkoj los pab kom dynamic switching ntawm tus adder thiab subtractor

muaj nuj nqi. Yog siv LPM_DIRECTION parameter, add_sub siv tsis tau. Yog

rho tawm, tus nqi pib yog ADD. Intel xav kom koj siv lub

LPM_DIRECTION parameter qhia txog kev ua haujlwm ntawm LPM_ADD_SUB muaj nuj nqi,

es tsis muab qhov tas mus li rau qhov chaw nres nkoj add_sub.

moos

Tsis muaj

Input rau kev siv pipeline. Lub moos chaw nres nkoj muab lub moos input rau lub raj xa dej

kev ua haujlwm. Rau LPM_PIPELINE qhov tseem ceeb uas tsis yog 0 (default), lub moos chaw nres nkoj yuav tsum yog

qhib.

clken ua

Tsis muaj

Clock enables rau pipelined siv. Thaum qhov chaw nres nkoj clken tau lees paub siab, tus adder /

Kev ua haujlwm subtractor tshwm sim. Thaum lub teeb liab qis, tsis muaj kev ua haujlwm tshwm sim. Yog

rho tawm, tus nqi pib yog 1.

aclr

Tsis muaj

Asynchronous ntshiab rau kev siv pipeline. Lub raj xa dej pib mus rau qhov tsis tau txhais (X)

qib logic. Lub chaw nres nkoj aclr tuaj yeem siv tau txhua lub sijhawm los rov pib dua cov kav dej rau txhua qhov 0s,

asynchronously rau lub moos teeb liab.

Table 16. LPM_ADD_SUB IP Core Output Ports

Chaw nres nkoj npe

Yuav tsum tau

Kev piav qhia

tshwm sim[]

Yog lawm

Cov ntaub ntawv tawm. Qhov loj ntawm qhov chaw nres nkoj tso zis nyob ntawm LPM_WIDTH parameter

tus nqi.

cout

Tsis muaj

Nqa tawm (qiv-hauv) ntawm qhov tseem ceeb tshaj plaws (MSB). Qhov chaw nres nkoj cout muaj lub cev

txhais raws li kev nqa tawm (qhib hauv) ntawm MSB. Qhov chaw nres nkoj cout ntes tau

overflow hauv UNSIGNED cov haujlwm. Qhov chaw nres nkoj cout ua haujlwm tib yam rau

CEEB TOOM thiab UNSIGNED cov haujlwm.

dej ntws

Tsis muaj

Optional overflow exception tso zis. Qhov chaw nres nkoj overflow muaj kev txhais lub cev li

XOR ntawm kev nqa mus rau MSB nrog kev nqa tawm ntawm MSB. Qhov chaw nres nkoj overflow

lees tias thaum cov txiaj ntsig tshaj qhov muaj tseeb, thiab tsuas yog siv thaum lub

LPM_REPRESENTATION tus nqi parameter yog SIGNED.

5.6. Cov tsis

Cov lus hauv qab no teev cov LPM_ADD_SUB IP core parameters.

Table 17. LPM_ADD_SUB IP Core Parameters

Parameter Lub Npe LPM_WIDTH

Ntaus tus lej

Yuav Tsum Tau

Kev piav qhia
Qhia qhov dav ntawm dataa[], datab[], thiab result[] ports.

LPM_DIRECTION

Txoj hlua

Tsis muaj

Tus nqi yog ADD, SUB, thiab TSIS TAU. Yog tias tshem tawm, tus nqi pib yog DEFAULT, uas coj tus parameter coj nws tus nqi los ntawm qhov chaw nres nkoj add_sub. Qhov chaw nres nkoj add_sub siv tsis tau yog tias siv LPM_DIRECTION. Intel xav kom koj siv LPM_DIRECTION parameter los qhia txog kev ua haujlwm ntawm LPM_ADD_SUB muaj nuj nqi, es tsis muab qhov txuas mus ntxiv rau qhov chaw nres nkoj add_sub.
txuas ntxiv…

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5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05

Parameter Lub Npe LPM_REPRESENTATION LPM_PIPELINE LPM_HINT LPM_TYPE ONE_INPUT_IS_CONSTANT MAXIMIZE_SPEED
INTENDED_DEVICE_FAMILY

Hom String Integer String String String Integer
Txoj hlua

Yuav Tsum Tau Tsis Tau Tsis Muaj Tsis Muaj Tsis Muaj
Tsis muaj

Kev piav qhia
Qhia txog hom kev sib ntxiv ua tiav. Tus nqi yog SAU thiab UNSIGNED. Yog tias tshem tawm, tus nqi pib yog SIGNED. Thaum qhov parameter no tau teeb tsa rau SIGNED, tus adder/subtractor txhais cov ntaub ntawv tawm tswv yim raws li kos npe ob qhov ntxiv.
Qhia tus naj npawb ntawm latency moos cycles cuam tshuam nrog cov txiaj ntsig[] tso zis. Tus nqi ntawm xoom (0) qhia tau hais tias tsis muaj latency tshwm sim, thiab qhov kev sib xyaw ua ke ntshiab yuav ua kom sai. Yog tias tshem tawm, tus nqi pib yog 0 (tsis yog raj).
Tso cai rau koj los qhia meej Intel cov kev txwv tshwj xeeb hauv VHDL tsim files (.vhd). Tus nqi pib yog UNUSED.
Txheeb xyuas lub tsev qiv ntawv ntawm parameterized modules (LPM) lub npe lub npe hauv VHDL tsim files.
Intel tshwj xeeb parameter. Koj yuav tsum siv LPM_HINT parameter los qhia qhov ONE_INPUT_IS_CONSTANT parameter hauv VHDL tsim files. Tus nqi yog YOG, TSIS TAU, thiab TSIS TAU. Muab kev ua kom zoo dua qub yog tias ib qho kev tawm tswv yim tas li. Yog tias tshem tawm, tus nqi pib yog NO.
Intel tshwj xeeb parameter. Koj yuav tsum siv LPM_HINT parameter los qhia qhov MAXIMIZE_SPEED parameter hauv VHDL tsim files. Koj tuaj yeem teev tus nqi nruab nrab ntawm 0 thiab 10. Yog tias siv, Intel Quartus Prime software sim ua kom zoo dua ib qho piv txwv ntawm LPM_ADD_SUB muaj nuj nqi kom nrawm dua li kev ua haujlwm, thiab overrides qhov chaw ntawm Optimization Technique logic xaiv. Yog tias MAXIMIZE_SPEED tsis siv, tus nqi ntawm Optimization Technique xaiv yog siv los hloov. Yog hais tias qhov chaw rau MAXIMIZE_SPEED yog 6 los yog siab dua, lub Compiler optimizes LPM_ADD_SUB IP core kom ceev dua siv nqa chains; Yog tias qhov teeb tsa yog 5 lossis tsawg dua, Compiler siv tus qauv tsim yam tsis muaj cov saw hlau. Qhov parameter no yuav tsum tau teev tseg rau Cyclone, Stratix, thiab Stratix GX li tsuas yog thaum lub add_sub chaw nres nkoj tsis siv.
Qhov kev ntsuas no yog siv rau kev ua qauv thiab kev coj tus cwj pwm simulation lub hom phiaj. Tus parameter editor xam tus nqi rau qhov parameter no.

Xa lus tawm tswv yim

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6. LPM_COMPARE (Kev sib piv)

Daim duab 5.

LPM_COMPARE IP core piv tus nqi ntawm ob pawg ntawm cov ntaub ntawv los txiav txim qhov kev sib raug zoo ntawm lawv. Hauv nws daim ntawv yooj yim tshaj plaws, koj tuaj yeem siv qhov tshwj xeeb-los yog lub rooj vag los txiav txim seb ob cov ntaub ntawv sib npaug.

Cov duab hauv qab no qhia cov chaw nres nkoj rau LPM_COMPARE IP core.

LPM_COMPARE Chaw nres nkoj

LPM_COMPARE

clken ua

alb

aeb ib

dataa[]

ua agb

datab[]

laj

moos

ib aneb

aclr

aleb ua

inst

6.1. Nta
Lub LPM_COMPARE IP core muaj cov yam ntxwv hauv qab no: · Tsim cov khoom sib piv los sib piv ob pawg ntawm cov ntaub ntawv · Txhawb cov ntaub ntawv dav ntawm 1 khoom · Txhawb cov ntaub ntawv sawv cev xws li kos npe thiab tsis kos npe · Ua cov khoom tso tawm hauv qab no:
— alb (cov tswv yim A yog tsawg dua cov tswv yim B) — aeb (cov tswv yim A yog sib npaug rau cov tswv yim B) — agb (cov tswv yim A yog ntau dua cov tswv yim B) — ageb (cov tswv yim A ntau dua lossis sib npaug rau cov tswv yim B) — aneb ( input A tsis sib npaug rau cov tswv yim B) — aleb (cov tswv yim A tsawg dua lossis sib npaug rau cov tswv yim B) · Txhawb kev xaiv asynchronous ntshiab thiab moos pab cov tswv yim ports · Muab cov datab[] tawm tswv yim mus tas li · Txhawb cov raj xa dej nrog cov zis latency configurable

Daim ntawv pov thawj ISO 9001: 2015

6. LPM_COMPARE (Piv txwv) 683490 | 2020.10.05
6.2. Verilog HDL Prototype
Cov nram qab no Verilog HDL qauv yog nyob rau hauv Verilog Design File (.v) lpm.v in the edasynthesis directory.
module lpm_compare ( alb, aeb, agb, aleb, aneb, ageb, dataa, datab, moos, clken, aclr ); parameter lpm_type = "lpm_compare"; parameter lpm_width = 1; parameter lpm_representation = "UNSIGNED"; parameter lpm_pipeline = 0; parameter lpm_hint = "UNUSED"; input [lpm_width-1:0] dataa, datab; input moos; input clken; input aclr; output alb, aeb, agb, aleb, aneb, ageb; endmodule
6.3. VHDL Component Tshaj Tawm
VHDL cov lus tshaj tawm yog nyob hauv VHDL Tsim File (.vhd) LPM_PACK.vhd hauv librariesvhdllpm directory.
tivthaiv LPM_COMPARE generic (LPM_WIDTH : ntuj;
LPM_REPRESENTATION : string := “UNSIGNED”; LPM_PIPELINE : ntuj := 0; LPM_TYPE: hlua := L_COMPARE; LPM_HINT : string := "UNUSED"); port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0); DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0); ACLR : in std_logic := '0'; CLOCK : in std_logic := '0'; := '1'; AGB : out std_logic; kawg tivthaiv;
6.4. VHDL LIBRARY_USE tshaj tawm
Daim ntawv tshaj tawm VHDL LIBRARY-SIV tsis tas yuav yog tias koj siv VHDL Cov Lus Tshaj Tawm.
LIBRARY lpm; USE lpm.lpm_components.all;
6.5. Chaw nres nkoj
Cov lus hauv qab no teev cov tswv yim thiab cov chaw nres nkoj rau LMP_COMPARE IP core.

Xa lus tawm tswv yim

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6. LPM_COMPARE (Piv txwv) 683490 | 2020.10.05

Table 18. LPM_COMPARE IP core Input Ports

Chaw nres nkoj npe

Yuav tsum tau

Kev piav qhia

dataa[]

Yog lawm

Cov ntaub ntawv nkag. Qhov loj ntawm qhov chaw nres nkoj nkag yog nyob ntawm LPM_WIDTH parameter tus nqi.

datab[]

Yog lawm

Cov ntaub ntawv nkag. Qhov loj ntawm qhov chaw nres nkoj nkag yog nyob ntawm LPM_WIDTH parameter tus nqi.

moos

Tsis muaj

Clock input rau pipelined siv. Lub moos chaw nres nkoj muab lub moos input rau lub raj xa dej

kev ua haujlwm. Rau LPM_PIPELINE qhov tseem ceeb uas tsis yog 0 (default), lub moos chaw nres nkoj yuav tsum yog

qhib.

clken ua

Tsis muaj

Clock enables rau pipelined siv. Thaum lub clken chaw nres nkoj yog asserted siab, lub

kev ua haujlwm sib piv yuav tshwm sim. Thaum lub teeb liab qis, tsis muaj kev ua haujlwm tshwm sim. Yog

rho tawm, tus nqi pib yog 1.

aclr

Tsis muaj

Asynchronous ntshiab rau kev siv pipeline. Lub raj xa dej pib mus rau qhov tsis tau txhais (X) logic

qib. Lub chaw nres nkoj aclr tuaj yeem siv tau txhua lub sijhawm los rov pib dua cov kav dej rau txhua qhov 0s,

asynchronously rau lub moos teeb liab.

Table 19. LPM_COMPARE IP core Output Ports

Chaw nres nkoj npe

Yuav tsum tau

Kev piav qhia

alb

Tsis muaj

Output chaw nres nkoj rau qhov sib piv. Asserted yog input A tsawg dua input B.

aeb ib

Tsis muaj

Output chaw nres nkoj rau qhov sib piv. Asserted yog input A yog sib npaug rau input B.

ua agb

Tsis muaj

Output chaw nres nkoj rau qhov sib piv. Asserted yog input A ntau tshaj input B.

laj

Tsis muaj

Output chaw nres nkoj rau qhov sib piv. Asserted yog input A ntau dua los yog sib npaug rau input

ib aneb

Tsis muaj

Output chaw nres nkoj rau qhov sib piv. Asserted yog input A tsis sib npaug rau input B.

aleb ua

Tsis muaj

Output chaw nres nkoj rau qhov sib piv. Asserted yog input A tsawg dua los yog sib npaug rau input B.

6.6. Cov tsis

Cov lus hauv qab no teev cov kev txwv rau LPM_COMPARE IP core.

Table 20. LPM_COMPARE IP core Parameters

Lub npe Parameter

Hom

Yuav tsum tau

LPM_WIDTH

Integer Yes

LPM_REPRESENTATION

Txoj hlua

Tsis muaj

LPM_PIPELINE

Integer No

LPM_HINT

Txoj hlua

Tsis muaj

Kev piav qhia
Qhia qhov dav ntawm dataa[] thiab datab[] ports.
Qhia txog hom kev sib piv tau ua. Tus nqi yog SAU thiab UNSIGNED. Yog tias tshem tawm, tus nqi pib yog UNSIGNED. Thaum tus nqi parameter no tau teem rau SIGNED, tus sib piv txhais cov ntaub ntawv tawm tswv yim raws li kos npe ob qhov ntxiv.
Qhia tus naj npawb ntawm lub voj voog ntawm latency txuam nrog alb, aeb, agb, ageb, aleb, lossis aneb tso zis. Tus nqi ntawm xoom (0) qhia tau hais tias tsis muaj latency tshwm sim, thiab qhov kev sib xyaw ua ke ua tiav yuav raug instantiated. Yog tias tshem tawm, tus nqi pib yog 0 (nonpipelined).
Tso cai rau koj los qhia meej Intel cov kev txwv tshwj xeeb hauv VHDL tsim files (.vhd). Tus nqi pib yog UNUSED.
txuas ntxiv…

Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia 28

Xa lus tawm tswv yim

6. LPM_COMPARE (Piv txwv) 683490 | 2020.10.05
Parameter Lub Npe LPM_TYPE INTENDED_DEVICE_FAMILY
ONE_INPUT_IS_CONSTANT

Hom hlua hlua
Txoj hlua

Yuav tsum tsis muaj
Tsis muaj

Kev piav qhia
Txheeb xyuas lub tsev qiv ntawv ntawm parameterized modules (LPM) lub npe lub npe hauv VHDL tsim files.
Qhov kev ntsuas no yog siv rau kev ua qauv thiab kev coj tus cwj pwm simulation lub hom phiaj. Tus parameter editor xam tus nqi rau qhov parameter no.
Intel tshwj xeeb parameter. Koj yuav tsum siv LPM_HINT parameter los qhia qhov ONE_INPUT_IS_CONSTANT parameter hauv VHDL tsim files. Cov txiaj ntsig yog YOG, TSIS MUAJ, lossis tsis siv. Muab kev ua kom zoo dua qub yog tias qhov kev tawm tswv yim tas li. Yog tias tshem tawm, tus nqi pib yog NO.

Xa lus tawm tswv yim

Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia 29

683490 | 2020.10.05 Xa lus tawm tswv yim

7. ALTECC (Yam Kho Code: Encoder/Decoder) IP Core

Daim duab 6.

Intel muab ALTECC IP core los siv ECC kev ua haujlwm. ECC kuaj xyuas cov ntaub ntawv tsis raug uas tshwm sim ntawm tus neeg txais thaum lub sijhawm xa cov ntaub ntawv. Txoj kev kho qhov yuam kev no yog qhov zoo tshaj plaws rau cov xwm txheej uas ua yuam kev tshwm sim ntawm random es tsis yog tawg.

ECC kuaj xyuas qhov yuam kev los ntawm cov txheej txheem ntawm cov ntaub ntawv encoding thiab decoding. Rau example, thaum ECC siv rau hauv daim ntawv thov kev sib kis, cov ntaub ntawv nyeem los ntawm lub hauv paus yog encoded ua ntej xa mus rau tus txais. Cov zis (code lo lus) los ntawm lub encoder muaj cov ntaub ntawv nyoos ntxiv nrog cov lej ntawm cov khoom sib xws. Tus naj npawb ntawm cov parity cov khoom ntxiv yog nyob ntawm tus naj npawb ntawm cov khoom hauv cov ntaub ntawv nkag. Cov lus code generated ces kis mus rau qhov chaw.

Tus txais tau txais cov lus code thiab txiav txim siab nws. Cov ntaub ntawv tau los ntawm tus decoder txiav txim seb puas muaj qhov yuam kev. Lub decoder pom ib-ntsis thiab ob-ntsis yuam kev, tab sis tuaj yeem kho qhov yuam kev ib-ntsis hauv cov ntaub ntawv tsis raug. Hom ECC no yog ib qho kev ua yuam kev kho ob qhov kev ua yuam kev (SECDED).

Koj tuaj yeem teeb tsa encoder thiab decoder ua haujlwm ntawm ALTECC IP core. Cov ntaub ntawv nkag mus rau lub encoder yog encoded los tsim ib lo lus code uas yog kev sib txuas ntawm cov ntaub ntawv tawm tswv yim thiab cov generated parity khoom. Cov lus code generated yog kis mus rau lub decoder module rau kev txiav txim siab ua ntej mus txog nws qhov chaw thaiv. Lub decoder generates ib tug syndrome vector los txiav txim seb puas muaj ib qho kev ua yuam kev nyob rau hauv lub tau txais code lo lus. Tus decoder kho cov ntaub ntawv tsuas yog tias qhov yuam kev ib-ntsis yog los ntawm cov ntaub ntawv cov khoom. Tsis muaj teeb liab raug teeb tsa yog tias qhov yuam kev ib-ntsis yog los ntawm cov khoom sib xws. Tus decoder tseem muaj cov cim chij los qhia cov xwm txheej ntawm cov ntaub ntawv tau txais thiab qhov kev txiav txim los ntawm tus decoder, yog tias muaj.

Cov duab hauv qab no qhia cov chaw nres nkoj rau ALTECC IP core.

ALTECC Encoder Ports

ALTECC_ENCODER

cov ntaub ntawv[]

q[]

moos

aclr

inst

Daim ntawv pov thawj ISO 9001: 2015

7. ALTECC (Yam Kho Code: Encoder/Decoder) IP Core 683490 | 2020.10.05

Daim duab 7. ALTECC Decoder Ports

ALTECC_DECODER

data[] moos moos

q[] err_detected err_corrected
err_fatal

aclr

inst

7.1. ALTECC Encoder nta

ALTECC encoder IP core muaj cov yam ntxwv hauv qab no: · Ua cov ntaub ntawv encoding siv Hamming Coding scheme · Txhawb cov ntaub ntawv dav ntawm 2 khoom · Txhawb kev kos npe thiab tsis kos npe cov ntaub ntawv sawv cev · Txhawb cov kav dej nrog cov zis latency ntawm ib lossis ob lub voj voog · Txhawb kev xaiv asynchronous ntshiab thiab moos pab cov chaw nres nkoj

Lub ALTECC encoder IP core coj mus rau hauv thiab encodes cov ntaub ntawv siv Hamming Coding scheme. Hamming Coding scheme muab cov khoom sib xws thiab ntxiv rau lawv rau cov ntaub ntawv qub los tsim cov lus tso tawm. Tus naj npawb ntawm parity khoom ntxiv nyob ntawm qhov dav ntawm cov ntaub ntawv.

Cov lus hauv qab no teev cov naj npawb ntawm cov khoom sib npaug ntxiv rau qhov sib txawv ntawm cov ntaub ntawv dav. Cov Kab Tag Nrho Tag Nrho sawv cev rau tag nrho cov ntaub ntawv tawm tswv yim thiab cov khoom sib txuas ntxiv.

Table 21.

Number of Parity Bits thiab Code Word Raws li cov ntaub ntawv dav

Cov ntaub ntawv dav

Number of Parity Bits

Tag nrho cov khoom (Code Word)

2-4 : kuv

3+1

6-8 : kuv

5-11 : kuv

4+1

10-16 : kuv

12-26 : kuv

5+1

18-32 : kuv

27-57 : kuv

6+1

34-64 : kuv

58-64 : kuv

7+1

66-72 : kuv

Lub parity me ntsis derivation siv ib qho kev txheeb xyuas qhov sib npaug. Qhov ntxiv 1 me ntsis (pom hauv cov lus li +1) yog ntxiv rau cov khoom sib xws li MSB ntawm lo lus code. Qhov no xyuas kom meej tias cov lus code muaj tus lej ntawm 1 tus. Rau example, yog hais tias cov ntaub ntawv dav yog 4 khoom, 4 parity khoom yog ntxiv rau cov ntaub ntawv los ua ib lo lus code nrog tag nrho ntawm 8 khoom. Yog tias 7 khoom los ntawm LSB ntawm 8-ntsis code lo lus muaj tus lej khib ntawm 1's, 8th me ntsis (MSB) ntawm lo lus code yog 1 ua rau tag nrho cov lej ntawm 1's hauv lo lus code txawm.
Cov duab hauv qab no qhia tau hais tias cov lus code tsim tawm thiab kev teeb tsa ntawm cov khoom sib xws thiab cov ntaub ntawv cov khoom hauv 8-ntsis cov ntaub ntawv nkag.

Xa lus tawm tswv yim

Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia 31

7. ALTECC (Yam Kho Code: Encoder/Decoder) IP Core 683490 | 2020.10.05

Daim duab 8.

Parity Bits thiab Cov Ntaub Ntawv Cov Khoom Siv hauv 8-ntsis Generated Code Word

MSB

LSB

4 ib parity

4 ib data

ALTECC encoder IP core lees txais qhov dav dav ntawm 2 txog 64 khoom ib zaug nkaus xwb. Cov tswv yim dav ntawm 12 cov khoom, 29 khoom, thiab 64 khoom, uas yog qhov haum rau Intel cov khoom siv, tsim cov khoom tawm ntawm 18 khoom, 36 khoom, thiab 72 khoom raws li. Koj tuaj yeem tswj hwm qhov txwv tsis pub dhau qhov kev txwv hauv qhov parameter editor.

7.2. Verilog HDL Prototype (ALTECC_ENCODER)
Cov nram qab no Verilog HDL qauv yog nyob rau hauv Verilog Design File (.v) lpm.v in the edasynthesis directory.
module altecc_encoder #( parameter intended_device_family = "unused", parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = "altecc_encoder", parameter lpm_hint = "unused" moos, muab tso rau hauv hlau clocken, input wire [width_dataword-1:0] data, output wire [width_codeword-1:0] q); endmodule

7.3. Verilog HDL Prototype (ALTECC_DECODER)
Cov nram qab no Verilog HDL qauv yog nyob rau hauv Verilog Design File (.v) lpm.v in the edasynthesis directory.
module altecc_decoder #( parameter intended_device_family = "unused", parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = "altecc_decoder", parameter lpm_hint = "tsis siv" moos, muab tso rau hauv hlau clocken, input wire [width_codeword-1:0] cov ntaub ntawv, tso zis hlau err_corrected, tso zis hlau err_detected, outut wire err_fatal, output wire [width_dataword-1:0] q); endmodule

Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia 32

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7. ALTECC (Yam Kho Code: Encoder/Decoder) IP Core 683490 | 2020.10.05
7.4 ib. VHDL Component Tshaj Tawm (ALTECC_ENCODER)
VHDL cov lus tshaj tawm yog nyob hauv VHDL Tsim File (.vhd) altera_mf_components.vhd hauv librariesvhdlaltera_mf directory.
tivthaiv altecc_encoder generic (independent_device_family:string := "unused"; lpm_pipeline:natural := 0; width_codeword:natural := 8; width_dataword:natural := 8; lpm_hint:string := "UN_USED:_string"; ”); port( aclr:in std_logic := '0'; moos:in std_logic := '0'; moos:in std_logic := '1'; data:in std_logic_vector(width_dataword-1 downto 0); q:out std_logic_vector(width_code -1 mus rau 0)); kawg tivthaiv;
7.5. VHDL Component Tshaj Tawm (ALTECC_DECODER)
VHDL cov lus tshaj tawm yog nyob hauv VHDL Tsim File (.vhd) altera_mf_components.vhd hauv librariesvhdlaltera_mf directory.
tivthaiv altecc_decoder generic ( intended_device_family: hlua := "tsis siv"; lpm_pipeline:natural := 0; width_codeword:natural := 8; width_dataword:natural := 8; lpm_hint:string := "UN_USED:_string"; ”); port( aclr:in std_logic := '0'; moos: in std_logic := '0'; clocken: in std_logic := '1'; data: in std_logic_vector(width_codeword-1 downto 0); err_corrected: out std_logic; : tawm std_logic; q: tawm std_logic_vector(width_dataword-1 downto 0); kawg tivthaiv;
7.6. VHDL LIBRARY_USE tshaj tawm
Daim ntawv tshaj tawm VHDL LIBRARY-SIV tsis tas yuav yog tias koj siv VHDL Cov Lus Tshaj Tawm.
LIBRARY altera_mf; USE altera_mf.altera_mf_components.all;
7.7. Encoder Ports
Cov lus hauv qab no teev cov tswv yim thiab cov chaw nres nkoj rau ALTECC encoder IP core.

Xa lus tawm tswv yim

Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia 33

7. ALTECC (Yam Kho Code: Encoder/Decoder) IP Core 683490 | 2020.10.05

Table 22. ALTECC Encoder Input Ports

Chaw nres nkoj npe

Yuav tsum tau

Kev piav qhia

cov ntaub ntawv[]

Yog lawm

Data input chaw nres nkoj. Qhov loj ntawm qhov chaw nres nkoj nkag yog nyob ntawm WIDTH_DATAWORD

tus nqi parameter. Cov ntaub ntawv [] chaw nres nkoj muaj cov ntaub ntawv raw yuav tsum tau encoded.

moos

Yog lawm

Lub moos input chaw nres nkoj uas muab lub moos teeb liab los synchronize lub encoding lag luam.

Lub moos chaw nres nkoj yuav tsum tau thaum LPM_PIPELINE tus nqi ntau dua 0.

moos

Tsis muaj

Lub moos pab. Yog tias tshem tawm, tus nqi pib yog 1.

aclr

Tsis muaj

Asynchronous ntshiab input. Lub zog siab aclr teeb liab tuaj yeem siv tau txhua lub sijhawm

asynchronously tshem cov npe.

Table 23. ALTECC Encoder Output Ports

Chaw nres nkoj npe q[]

Yuav Tsum Tau

Kev piav qhia
Encoded cov ntaub ntawv tso zis chaw nres nkoj. Qhov loj ntawm qhov chaw nres nkoj tso zis yog nyob ntawm tus nqi WIDTH_CODEWORD parameter.

7.8 ib. Decoder Ports

Cov lus hauv qab no teev cov tswv yim thiab cov chaw nres nkoj rau ALTECC decoder IP core.

Table 24. ALTECC Decoder Input Ports

Chaw nres nkoj npe

Yuav tsum tau

Kev piav qhia

cov ntaub ntawv[]

Yog lawm

Data input chaw nres nkoj. Qhov loj ntawm qhov chaw nres nkoj input nyob ntawm tus nqi WIDTH_CODEWORD parameter.

moos

Yog lawm

Lub moos input chaw nres nkoj uas muab lub moos teeb liab los synchronize lub encoding lag luam. Lub moos chaw nres nkoj yuav tsum tau thaum LPM_PIPELINE tus nqi ntau dua 0.

moos

Tsis muaj

Lub moos pab. Yog tias tshem tawm, tus nqi pib yog 1.

aclr

Tsis muaj

Asynchronous ntshiab input. Lub teeb liab siab aclr tuaj yeem siv tau txhua lub sijhawm kom asynchronously tshem cov npe.

Table 25. ALTECC Decoder Output Ports

Chaw nres nkoj npe q[]

Yuav Tsum Tau

Kev piav qhia
Decoded cov ntaub ntawv tso zis chaw nres nkoj. Qhov loj ntawm qhov chaw nres nkoj tso zis nyob ntawm tus nqi WIDTH_DATAWORD parameter.

err_detected Yog

Chij teeb liab los cuam tshuam cov xwm txheej ntawm cov ntaub ntawv tau txais thiab qhia meej txog qhov yuam kev pom.

err_correcte Yog d

Flag teeb liab los cuam tshuam cov xwm txheej ntawm cov ntaub ntawv tau txais. Denotes ib-ntsis yuam kev pom thiab kho. Koj tuaj yeem siv cov ntaub ntawv vim nws twb raug kho lawm.

err_fatal

Yog lawm

Flag teeb liab los cuam tshuam cov xwm txheej ntawm cov ntaub ntawv tau txais. Denotes ob-ntsis yuam kev pom, tab sis tsis kho. Koj yuav tsum tsis txhob siv cov ntaub ntawv yog tias qhov teeb meem no tau lees paub.

sib_e

Tsis muaj

Lub teeb liab tso zis uas yuav mus siab thaum twg ib qho kev ua yuam kev ib zaug tau kuaj pom ntawm qhov sib luag

me ntsis.

7.9 ib. Encoder Parameters
Cov lus hauv qab no teev cov kev txwv rau ALTECC encoder IP core.

Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia 34

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7. ALTECC (Yam Kho Code: Encoder/Decoder) IP Core 683490 | 2020.10.05

Table 26. ALTECC Encoder Parameters

Lub npe Parameter

Hom

Yuav tsum tau

Kev piav qhia

WIDTH_DATAWORD

Integer Yes

Qhia qhov dav ntawm cov ntaub ntawv nyoos. Tus nqi yog los ntawm 2 mus rau 64. Yog tias tshem tawm, tus nqi qub yog 8.

WIDTH_CODEWORD

Integer Yes

Qhia qhov dav ntawm lo lus coj los siv. Cov nqi siv tau yog los ntawm 6 txog 72, tsis suav nrog 9, 17, 33, thiab 65. Yog tias tshem tawm, tus nqi qub yog 13.

LPM_PIPELINE

Integer No

Qhia cov kav dej rau lub voj voog. Tus nqi yog los ntawm 0 mus rau 2. Yog tias tus nqi yog 0, cov chaw nres nkoj tsis tau sau npe. Yog hais tias tus nqi yog 1, cov zis ports tau sau npe. Yog hais tias tus nqi yog 2, lub input thiab output ports tau sau npe. Yog tias tshem tawm, tus nqi pib yog 0.

7.10 Nws. Decoder Parameters

Cov lus hauv qab no teev cov ALTECC decoder IP core parameters.

Table 27. ALTECC Decoder Parameters

Parameter Lub Npe WIDTH_DATAWORD

Ntaus tus lej

Yuav tsum tau

Kev piav qhia

Yog lawm

Qhia qhov dav ntawm cov ntaub ntawv nyoos. Tus nqi yog 2 txog 64. Tus

default value yog 8.

WIDTH_CODEWORD

Tus lej

Yog lawm

Qhia qhov dav ntawm lo lus coj los siv. Tus nqi yog 6

rau 72, tsis suav nrog 9, 17, 33, thiab 65. Yog tias tshem tawm, tus nqi qub

yog 13.

LPM_PIPELINE

Tus lej

Tsis muaj

Qhia txog kev sau npe ntawm Circuit Court. Tus nqi yog los ntawm 0 mus rau 2. Yog hais tias tus

tus nqi yog 0, tsis muaj npe raug siv. Yog tias tus nqi yog 1, lub

tso zis yog sau npe. Yog tias tus nqi yog 2, ob qho tib si cov tswv yim thiab cov

cov zis tau sau npe. Yog tias tus nqi ntau dua 2, ntxiv

Cov ntawv sau npe raug muab coj los siv rau ntawm qhov tso zis rau qhov ntxiv

latencies. Yog tias tshem tawm, tus nqi pib yog 0.

Tsim ib qhov chaw 'syn_e'

Tus lej

Tsis muaj

Tig rau qhov ntsuas no los tsim qhov chaw nres nkoj syn_e.

Xa lus tawm tswv yim

Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia 35

683490 | 2020.10.05 Xa lus tawm tswv yim

8. Intel FPGA Multiply Adder IP Core

Daim duab 9.

Intel FPGA Multiply Adder (Intel Stratix 10, Intel Arria 10, thiab Intel Cyclone 10 GX li) lossis ALTERA_MULT_ADD (Arria V, Stratix V, thiab Cyclone V li) IP core tso cai rau koj los siv tus lej sib npaug.

Cov duab hauv qab no qhia cov chaw nres nkoj rau Intel FPGA Multiply Adder lossis ALTERA_MULT_ADD IP core.

Intel FPGA Multiply Adder lossis ALTERA_MULT_ADD Ports

Intel FPGA Multiply Adder lossis ALTERA_MULT_ADD

dataa[] signa datab[] signb datac[] coefsel0[] coefsel1[] coefsel2[] coefsel3[] addnsub1 addnsub3 aclr/sclr[] scanina[] moos0 moos1 moos2 ena0 ena1 ena2 sload_accum
accum_sload chainin[]

scanouta[] result[]

aclr0 ib

inst
Tus multiplier-adder lees txais khub ntawm cov khoom siv, muab cov txiaj ntsig ua ke thiab tom qab ntawd ntxiv rau lossis rho tawm los ntawm cov khoom ntawm tag nrho lwm cov khub.
Yog tias tag nrho cov ntaub ntawv nkag dav dav yog 9-ntsis dav lossis me dua, txoj haujlwm siv 9 x 9 me ntsis input multiplier configuration hauv DSP thaiv rau cov khoom siv uas txhawb nqa 9 x 9 configuration. Yog tias tsis yog, DSP thaiv siv 18 × 18-ntsis input multipliers los ua cov ntaub ntawv nrog qhov dav ntawm 10-ntsis thiab 18-ntsis. Yog tias ntau Intel FPGA Multiply Adder lossis ALTERA_MULT_ADD IP cores tshwm sim hauv kev tsim, cov haujlwm tau muab faib ua

Daim ntawv pov thawj ISO 9001: 2015

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05
ntau qhov sib txawv DSP blocks raws li qhov ua tau kom routing rau cov blocks no yooj yim dua. Tsawg dua tus lej ntawm ib qho DSP thaiv tso cai ntau txoj kev xaiv rau hauv qhov thaiv los ntawm kev txo txoj hauv kev mus rau lwm qhov ntawm lub cuab yeej.
Cov ntawv sau npe thiab cov raj xa dej ntxiv rau cov cim hauv qab no kuj tau muab tso rau hauv DSP thaiv: · Cov ntaub ntawv tawm tswv yim · Kos npe lossis tsis kos npe xaiv · Ntxiv lossis rho tawm xaiv · Cov khoom ntawm cov khoom sib npaug
Nyob rau hauv cov ntaub ntawv ntawm qhov tso zis tshwm sim, thawj lub npe yog muab tso rau hauv DSP thaiv. Txawm li cas los xij cov ntawv sau npe latency ntxiv tau muab tso rau hauv cov ntsiab lus logic sab nraum qhov thaiv. Peripheral rau DSP thaiv, suav nrog cov ntaub ntawv nkag mus rau qhov sib npaug, tswj cov teeb liab inputs, thiab cov khoom tawm ntawm tus adder, siv cov kev sib txuas lus tsis tu ncua los sib txuas lus nrog lwm tus ntawm lub cuab yeej. Txhua qhov kev sib txuas hauv kev ua haujlwm siv cov kev sib koom ua ke hauv DSP thaiv. Qhov kev mob siab rau txoj kev no suav nrog kev hloov pauv cov npe chains thaum koj xaiv qhov kev xaiv los hloov tus lej sib npaug ntawm cov ntaub ntawv sau npe nkag los ntawm ib tus lej mus rau tus lej sib npaug.
Yog xav paub ntxiv txog DSP blocks nyob rau hauv ib qho ntawm Stratix V, thiab Arria V ntaus ntawv series, xa mus rau DSP Blocks tshooj ntawm cov phau ntawv uas muaj nyob rau ntawm nplooj ntawv Ntawv thiab Cov Ntaub Ntawv Cov Ntaub Ntawv.
Cov ntaub ntawv ntsig txog AN 306: Siv cov khoom sib txuas hauv FPGA Devices
Muab cov ntaub ntawv ntau ntxiv txog kev siv cov khoom sib txuas siv DSP thiab cov cim xeeb thaiv hauv Intel FPGA cov khoom siv.
8.1. Nta
Intel FPGA Multiply Adder lossis ALTERA_MULT_ADD IP core muaj cov yam ntxwv hauv qab no: · Tsim kom muaj qhov sib npaug los ua haujlwm sib npaug ntawm ob txoj haujlwm.
Tus lej Ceeb Toom: Thaum lub tsev sib faib loj dua li qhov kev txhawb nqa ib txwm muaj tuaj yeem /
yuav yog qhov ua tau zoo cuam tshuam los ntawm cascading ntawm DSP blocks. · Txhawb cov ntaub ntawv dav ntawm 1 256 khoom · Txhawb kev kos npe thiab tsis kos npe cov ntaub ntawv sawv cev · Txhawb cov raj xa dej nrog cov tswv yim tsim latency · Muab kev xaiv rau kev hloov pauv ntawm cov ntaub ntawv kos npe thiab tsis kos npe txhawb · Muab kev xaiv rau dynamically hloov ntawm kev ntxiv thiab rho tawm haujlwm · Txhawb yeem asynchronous thiab synchronous ntshiab thiab moos pab cov tswv yim ports · Txhawb systolic ncua sij hawm sau npe hom · Txhawb pre-adder nrog 8 pre-load coefficients ib tug multiplier · Txhawb pre-load tas mus li ntxiv accumulator tawm tswv yim

Xa lus tawm tswv yim

Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia 37

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

8.1.1. Pre-adder
Nrog pre-adder, ntxiv los yog rho tawm yog ua ua ntej pub tus multiplier.
Muaj tsib hom pre-adder: · Simple hom · Coefficient mode · Input mode · Square mode · Constant mode

Nco tseg:

Thaum siv pre-adder (pre-adder coefficient/input/square hom), tag nrho cov ntaub ntawv inputs rau tus multiplier yuav tsum muaj tib lub moos.

8.1.1.1 ib. Pre-adder Yooj Yim Hom

Nyob rau hauv hom no, ob qho tib si operands muab los ntawm cov tswv yim ports thiab pre-adder tsis siv los yog bypassed. Qhov no yog lub neej ntawd hom.

Daim duab 10. Pre-adder Yooj Yim Hom
ib 0b0

Ntau 0

tshwm sim

8.1.1.2. Pre-adder Coefficient Hom
Nyob rau hauv hom no, ib tug multiplier operand muab los ntawm pre-adder, thiab lwm yam operand muab los ntawm lub internal coefficient cia. Lub coefficient cia tso cai mus txog 8 preset tas mus li. Cov cim xaiv coefficient yog coefsel[0..3].
Hom no yog qhia nyob rau hauv kab zauv nram qab no.

Cov hauv qab no qhia tau hais tias ua ntej-adder coefficient hom ntawm tus multiplier.

Daim duab 11. Pre-adder Coefficient Hom

Preadder

Ntau 0

+/-

tshwm sim

kob 0coef

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05
8.1.1.3. Pre-adder Input Mode Nyob rau hauv hom no, ib tug multiplier operand muab los ntawm pre-adder, thiab lwm yam operand muab los ntawm datac[] input chaw nres nkoj. Hom no yog qhia nyob rau hauv kab zauv nram qab no.

Cov hauv qab no qhia txog pre-adder input hom ntawm tus multiplier.

Daim duab 12. Pre-adder Input Hom
ib 0b0

Ntau 0

+/-

tshwm sim

8.1.1.4 ib. Pre-adder Square Hom Hom no yog qhia nyob rau hauv kab zauv nram qab no.

Cov hauv qab no qhia tau hais tias pre-adder square hom ntawm ob tug multipliers.

Daim duab 13. Pre-adder Square hom
ib 0b0

Ntau 0

+/-

tshwm sim

8.1.1.5. Pre-adder Constant Mode
Nyob rau hauv hom no, ib tug multiplier operand muab los ntawm lub input chaw nres nkoj, thiab lwm yam operand muab los ntawm lub internal coefficient cia. Lub coefficient cia tso cai mus txog 8 preset tas mus li. Cov cim xaiv coefficient yog coefsel[0..3].
Hom no yog qhia nyob rau hauv kab zauv nram qab no.

Xa lus tawm tswv yim

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Cov duab hauv qab no qhia tau hais tias qhov pre-adder tas li hom ntawm tus lej sib npaug.

Daim duab 14. Pre-adder Constant Mode
a0

Ntau 0

tshwm sim

kob 0
kob
8.1.2. Systolic Delay Register
Nyob rau hauv lub systolic architecture, cov ntaub ntawv tawm tswv yim yog pub rau hauv ib qho cascade ntawm cov ntawv sau npe ua raws li cov ntaub ntawv tsis. Txhua tus sau npe xa ib qho kev tawm tswv yim sample mus rau ib tug multiplier qhov twg nws yog multiplied los ntawm cov feem coefficient. Cov saw adder khaws cov txiaj ntsig ua ke maj mam los ntawm tus lej sib npaug thiab cov txiaj ntsig yav dhau los tau sau npe los ntawm chainin[] chaw nres nkoj nkag los ua qhov kawg tshwm sim. Txhua qhov sib ntxiv-ntxiv cov khoom yuav tsum tau ncua los ntawm ib lub voj voog kom cov txiaj ntsig synchronize tsim nyog thaum ntxiv ua ke. Txhua qhov ncua sij hawm txuas ntxiv yog siv los hais txog ob qho tib si lub cim xeeb coefficient thiab cov ntaub ntawv tsis ntawm lawv cov khoom sib txuas ntxiv. Rau example, ib ncua sij hawm rau qhov thib ob multiply ntxiv, ob ncua sij hawm rau qhov thib peb multiply-ntxiv caij, thiab lwm yam.
Daim duab 15. Systolic Registers
Systolic sau npe

x(t) c(0)

S - 1

c(1)

S - 1

c(2)

S - 1

c(N-1)

S - 1

S -1 y(t)

x(t) sawv cev rau cov txiaj ntsig tau los ntawm kev txuas txuas ntxiv ntawm cov tswv yim samples y(t)
sawv cev rau qhov summation ntawm ib pawg input samples, thiab nyob rau hauv lub sij hawm, multiplied los ntawm lawv
yam coefficients. Ob qhov kev tawm tswv yim thiab cov txiaj ntsig tau ntws los ntawm sab laug mus rau sab xis. Tus c(0) rau c(N-1) txhais tau tias cov coefficients. Cov npe systolic ncua sij hawm yog qhia los ntawm S-1, qhov 1 sawv cev rau ib lub moos qeeb. Systolic ncua kev sau npe ntxiv ntawm
cov inputs thiab outputs rau pipelining nyob rau hauv ib txoj kev uas ua kom cov kev tshwm sim los ntawm lub
multiplier operand thiab cov sums nyob rau hauv synch. Cov txheej txheem no
yog replicated los tsim ib lub voj voog uas suav cov kev lim dej. Txoj haujlwm no yog
qhia nyob rau hauv cov kab zauv nram qab no.

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N sawv cev rau tus naj npawb ntawm cov voj voog ntawm cov ntaub ntawv uas tau nkag mus rau hauv lub accumulator, y(t) sawv cev rau cov zis thaum lub sij hawm t, A(t) sawv cev rau cov tswv yim ntawm lub sij hawm t, thiab B(i) yog cov coefficients. Lub t thiab kuv nyob rau hauv kab zauv sib raug mus rau ib qho instant nyob rau hauv lub sij hawm, yog li xam cov zis sample y(t) ntawm lub sij hawm t, ib pawg input samples ntawm N cov ntsiab lus sib txawv hauv lub sijhawm, lossis A(n), A(n-1), A(n-2), ... A(n-N+1) yuav tsum. Pab pawg N input samples yog muab faib los ntawm N coefficients thiab summed ua ke los ua qhov kawg tshwm sim y.
Lub systolic register architecture tsuas yog muaj rau sum-of-2 thiab sum-of-4 hom. Rau ob qho tib si systolic register architecture hom, thawj chainin teeb liab yuav tsum tau muab khi rau 0.
Cov duab hauv qab no qhia tau hais tias systolic ncua kev sau npe siv ntawm 2 tus lej sib npaug.
Daim duab 16. Systolic Delay Register Ua tiav ntawm 2 Qhov Kev Sib Tw
chainin

Ntau 0

+/-

Ntau 1

+/-

tshwm sim
Qhov sib npaug ntawm ob qhov sib npaug yog qhia hauv kab zauv hauv qab no.
Cov duab hauv qab no qhia tau hais tias systolic ncua kev sau npe siv ntawm 4 tus lej sib npaug.

Xa lus tawm tswv yim

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Daim duab 17. Systolic Delay Register Ua tiav ntawm 4 Qhov Kev Sib Tw
chainin

Ntau 0

+/-

Ntau 1

+/-

Ntau 2

+/-

Ntau 3

+/-

tshwm sim
Qhov sum ntawm plaub tus multipliers yog qhia nyob rau hauv kab zauv nram qab no. Daim duab 18. Sum ntawm 4 Qhov Sib Tw
Cov nram qab no teev cov advantages ntawm systolic sau npe siv: · Txo DSP kev pab cuam · Ua kom muaj peev xwm ua tau zoo hauv DSP thaiv siv cov saw txuas ntxiv

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8.1.3 ib. Pre-load Constant
Lub pre-load tas mus li tswj lub accumulator operand thiab complements lub accumulator tawm tswv yim. Qhov siv tau LOADCONST_VALUE nyob ntawm 0. Tus nqi tas li yog sib npaug rau 64N, qhov twg N = LOADCONST_VALUE. Thaum LOADCONST_VALUE tau teeb tsa rau 2, tus nqi tas li yog sib npaug rau 64. Qhov kev ua haujlwm no tuaj yeem siv los ua qhov sib npaug.
Daim duab hauv qab no qhia tau hais tias kev ua haujlwm ua ntej ua ntej.
Daim duab 19. Pre-load Constant

Cov lus qhia ntawm accumulator

tas li

Ntau 0

+/-

Ntau 1

+/b1

tshwm sim

accum_sload sload_accum

Xa mus rau IP cores hauv qab no rau lwm qhov kev siv ntau ntxiv: · ALTMULT_ACCUM · ALTMEMMULT · LPM_MULT
8.1.4 ib. Ob chav Accumulator
Ob chav accumulator feature ntxiv ib qho kev sau npe ntxiv hauv txoj kev tawm tswv yim accumulator. Ob chav accumulator tso npe ua raws li cov ntawv tso tawm, uas suav nrog lub moos, moos pab, thiab aclr. Qhov ntxiv accumulator tso npe rov qab los nrog ib lub voj voog qeeb. Qhov no tso cai rau koj kom muaj ob lub accumulator raws nrog tib cov peev txheej suav.
Daim duab hauv qab no qhia txog kev siv ob chav accumulator.

Xa lus tawm tswv yim

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Daim duab 20. Ob chav Accumulator

Dou ble Accu mulator Sau npe

Accu mulator feedba ck

Ntau 0

+/-

Ntau 1

+/b1

Output result Output Register

8.2. Verilog HDL Prototype
Koj tuaj yeem pom Intel FPGA Multiply Adder lossis ALTERA_MULT_ADD Verilog HDL tus qauv file (altera_mult_add_rtl.v) hauv lub librariesmegafunctions directory.
8.3. VHDL Component Tshaj Tawm
Cov lus tshaj tawm VHDL yog nyob rau hauv altera_lnsim_components.vhd hauv librariesvhdl altera_lnsim directory.
8.4. VHDL LIBRARY_USE tshaj tawm
Daim ntawv tshaj tawm VHDL LIBRARY-SIV tsis tas yuav yog tias koj siv VHDL Cov Lus Tshaj Tawm.
LIBRARY altera_mf; USE altera_mf.altera_mf_components.all;

8.5. Teeb liab

Cov lus hauv qab no teev cov tswv yim thiab cov teeb liab tawm ntawm Multiply Adder Intel FPGA IPor ALTERA_MULT_ADD IP core.

Table 28. Multiply Adder Intel FPGA IPor ALTERA_MULT_ADD Input Signals

Teeb liab

Yuav tsum tau

Kev piav qhia

dataa_0[]/dataa_1[]/

Yog lawm

dataa_2[]/dataa_3[]

Cov ntaub ntawv nkag mus rau tus multiplier. Qhov chaw nres nkoj nkag [NUMBER_OF_MULTIPLIERS * WIDTH_A – 1 … 0] dav
txuas ntxiv…

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Signal datab_0[]/datab_1[]/ datab_2[]/datab_3[] datac_0[] /datac_1[]/ datac_2[]/datac_3[] moos[1:0] aclr[1:0] sclr[1:0] ena [1:0] npe
npe
scanina[] accum_sload

Yuav Tsum Tau Tsis Tau
Tsis Tau Tsis Muaj
Tsis muaj
Tsis muaj

Kev piav qhia
Tus qauv simulation rau tus IP no txhawb nqa tus nqi nkag tsis tau (X) rau cov teeb liab no. Thaum koj muab X tus nqi rau cov teeb liab no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.
Cov ntaub ntawv nkag mus rau tus multiplier. Input signal [NUMBER_OF_MULTIPLIERS * WIDTH_B – 1 … 0] wide Lub simulation qauv rau IP no txhawb undetermined input nqi (X) rau cov teeb liab. Thaum koj muab X tus nqi rau cov teeb liab no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.
Cov ntaub ntawv nkag mus rau tus multiplier. Input signal [NUMBER_OF_MULTIPLIERS * WIDTH_C – 1, … 0] wide Xaiv INPUT rau Xaiv hom preadder parameter kom pab tau cov teeb liab. Tus qauv simulation rau tus IP no txhawb nqa tus nqi nkag tsis tau (X) rau cov teeb liab no. Thaum koj muab X tus nqi rau cov teeb liab no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.
Lub moos input chaw nres nkoj mus rau lub npe sib raug. Cov teeb liab no tuaj yeem siv los ntawm txhua tus neeg sau npe hauv IP core. Tus qauv simulation rau tus IP no txhawb nqa tus nqi nkag tsis tau (X) rau cov teeb liab no. Thaum koj muab X tus nqi rau cov teeb liab no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.
Asynchronous ntshiab input mus rau lub npe sib raug. Tus qauv simulation rau tus IP no txhawb nqa tus nqi nkag tsis tau (X) rau cov teeb liab no. Thaum koj muab X tus nqi rau cov teeb liab no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.
Synchronous ntshiab input mus rau tus sau npe. Tus qauv simulation rau tus IP no txhawb nqa cov tswv yim tsis muaj nqi X rau cov teeb liab no. Thaum koj muab X tus nqi rau cov teeb liab no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm
Qhib lub teeb liab tawm tswv yim rau cov npe sib raug. Tus qauv simulation rau tus IP no txhawb nqa tus nqi nkag tsis tau (X) rau cov teeb liab no. Thaum koj muab X tus nqi rau cov teeb liab no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.
Qhia txog tus lej sawv cev ntawm tus lej sib txuas A. Yog tias lub cim kos npe yog siab, tus multiplier kho tus lej tawm tswv yim A raws li tus lej kos npe. Yog tias lub cim kos npe qis qis, tus lej sib npaug kho qhov sib npaug ntawm cov tswv yim A teeb liab raws li tus lej tsis tau kos npe. Xaiv VARIABLE rau Dab tsi yog cov qauv sawv cev rau Multipliers A inputs parameter los pab kom cov teeb liab no. Tus qauv simulation rau tus IP no txhawb nqa tus nqi nkag tsis tau (X) rau lub teeb liab no. Thaum koj muab X tus nqi rau qhov kev tawm tswv yim no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.
Qhia txog tus lej sawv cev ntawm qhov sib npaug ntawm cov tswv yim B teeb liab. Yog hais tias tus signb teeb liab siab, tus multiplier kho tus multiplier input B teeb liab raws li ib tug kos npe rau ob lub complement tooj. Yog tias lub teeb liab signb qis, tus multiplier kho tus multiplier input B teeb liab raws li tus lej tsis tau kos npe. Tus qauv simulation rau tus IP no txhawb nqa tus nqi nkag tsis tau (X) rau lub teeb liab no. Thaum koj muab X tus nqi rau qhov kev tawm tswv yim no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.
Input rau scan saw A. Input signal [WIDTH_A – 1, … 0] wide. Thaum lub INPUT_SOURCE_A parameter muaj tus nqi ntawm SCANA, lub scanina[] teeb liab yuav tsum tau.
Dynamically qhia seb tus nqi accumulator puas tas mus li. Yog hais tias lub teeb liab accum_sload tsawg, ces cov zis multiplier yog loaded rau hauv lub accumulator. Tsis txhob siv accum_sload thiab sload_accum ib txhij.
txuas ntxiv…

Xa lus tawm tswv yim

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Teeb liab sload_accum
chainin[] addnsub1
addnub 3
coefsel0[]coefsel1[]coefsel2[]coefsel3[]

Yuav tsum tau No
Tsis muaj
Tsis muaj
Tsis Tau Tsis Muaj

Kev piav qhia
Tus qauv simulation rau tus IP no txhawb nqa tus nqi nkag tsis tau (X) rau lub teeb liab no. Thaum koj muab X tus nqi rau qhov kev tawm tswv yim no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.
Dynamically qhia seb tus nqi accumulator puas tas mus li. Yog hais tias lub teeb liab sload_accum siab, ces cov zis multiplier yog loaded rau hauv lub accumulator. Tsis txhob siv accum_sload thiab sload_accum ib txhij. Tus qauv simulation rau tus IP no txhawb nqa tus nqi nkag tsis tau (X) rau lub teeb liab no. Thaum koj muab X tus nqi rau qhov kev tawm tswv yim no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.
Adder result input bus los ntawm stage. Input signal [WIDTH_CHAININ – 1, … 0] dav.
Ua qhov sib ntxiv lossis rho tawm rau cov txiaj ntsig los ntawm thawj khub ntawm tus lej sib npaug. Cov tswv yim 1 rau addnsub1 teeb liab ntxiv cov zis tawm los ntawm thawj khub ntawm tus lej sib npaug. Cov tswv yim 0 rau addnsub1 teeb liab los rho tawm cov txiaj ntsig los ntawm thawj khub ntawm tus lej sib npaug. Tus qauv simulation rau tus IP no txhawb nqa tus nqi nkag tsis tau (X) rau lub teeb liab no. Thaum koj muab X tus nqi rau qhov kev tawm tswv yim no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.
Ua qhov sib ntxiv lossis rho tawm rau cov txiaj ntsig los ntawm thawj khub ntawm tus lej sib npaug. Cov tswv yim 1 rau addnsub3 teeb liab ntxiv cov khoom tawm los ntawm ob khub ntawm cov sib npaug. Cov tswv yim 0 rau addnsub3 teeb liab los rho tawm cov txiaj ntsig los ntawm thawj khub ntawm tus lej sib npaug. Tus qauv simulation rau tus IP no txhawb nqa tus nqi nkag tsis tau (X) rau lub teeb liab no. Thaum koj muab X tus nqi rau qhov kev tawm tswv yim no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.
Coefficient input signal [0:3] mus rau thawj qhov sib npaug. Tus qauv simulation rau tus IP no txhawb nqa tus nqi nkag tsis tau (X) rau lub teeb liab no. Thaum koj muab X tus nqi rau qhov kev tawm tswv yim no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.
Coefficient input signal[0:3] mus rau qhov thib ob tus lej. Tus qauv simulation rau tus IP no txhawb nqa tus nqi nkag tsis tau (X) rau lub teeb liab no. Thaum koj muab X tus nqi rau qhov kev tawm tswv yim no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.
Coefficient input signal [0:3] mus rau qhov thib peb tus lej. Tus qauv simulation rau tus IP no txhawb nqa tus nqi nkag tsis tau (X) rau lub teeb liab no. Thaum koj muab X tus nqi rau qhov kev tawm tswv yim no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.
Coefficient input signal [0:3] mus rau plaub tus lej. Tus qauv simulation rau tus IP no txhawb nqa tus nqi nkag tsis tau (X) rau lub teeb liab no. Thaum koj muab X tus nqi rau qhov kev tawm tswv yim no, tus nqi X tau nthuav tawm ntawm cov khoom tso tawm.

Table 29. Multiply Adder Intel FPGA IP Output Signals

Teeb liab

Yuav tsum tau

Kev piav qhia

tshwm sim []

Yog lawm

Multiplier tso zis teeb liab. Cov zis teeb liab [WIDTH_RESULT – 1… 0] dav

Tus qauv simulation rau tus IP no txhawb nqa tus nqi tso tawm tsis tau (X). Thaum koj muab X tus nqi raws li cov tswv yim, X tus nqi tau nthuav tawm ntawm qhov teeb meem no.

scanouta []

Tsis muaj

Cov zis ntawm scan saw A. Cov zis teeb liab [WIDTH_A – 1..0] dav.

Xaiv ntau dua 2 rau cov lej ntawm cov lej sib npaug thiab xaiv Scan saw input rau Dab tsi yog cov tswv yim A ntawm cov khoom sib txuas txuas nrog rau qhov ntsuas kom pab tau qhov teeb meem no.

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8.6. Cov tsis

8.6.1. General Tab

Table 30. General Tab

Parameter

IP Generated Parameter

Tus nqi

Tus naj npawb ntawm cov multipliers yog dab tsi?

num_of_m 1 – 4 ultipliers

Qhov dav npaum li cas yuav tsum A width_a input buses?

1–256 : kuv

B width_b input bus yuav dav npaum li cas?

1–256 : kuv

Yuav tsum dav npaum li cas 'qhov tshwm sim' lub tsheb npav yuav tsum?

dav_result

1–256 : kuv

Tsim ib lub moos uas cuam tshuam rau txhua lub moos

gui_associate On d_clock_enabl Off e

8.6.2 ib. Ntxiv Hom Tab

Table 31. Ntxiv Hom Tab

Parameter

IP Generated Parameter

Tus nqi

Outputs Configuration

Sau npe tso zis ntawm lub adder unit

gui_output_re On

gister

Tawm

Dab tsi yog lub hauv paus rau lub moos input?

gui_output_re gister_clock

moos 0 moos 1 moos 2

Lub hauv paus rau asynchronous clear input yog dab tsi?

gui_output_re gister_aclr

TSIS MUAJ ACLR0 ACLR1

Dab tsi yog qhov chaw rau synchronous ntshiab input?

gui_output_re gister_sclr

TSIS MUAJ SCLR0 SCLR1

Kev ua haujlwm ntxiv

Yuav ua li cas yuav tsum tau ua nyob rau hauv lub outputs ntawm thawj khub ntawm multipliers?

gui_multiplier 1_direction

ADD, SUB, VARIABLE

Default Tus nqi 1
16

Kev piav qhia
Tus naj npawb ntawm cov multipliers yuav tsum tau ntxiv ua ke. Tus nqi yog 1 txog 4. Qhia qhov dav ntawm dataa[] chaw nres nkoj.

Qhia qhov dav ntawm datab[] chaw nres nkoj.

Qhia qhov dav ntawm qhov tshwm sim[] chaw nres nkoj.

Tawm

Xaiv qhov kev xaiv no los tsim lub moos qhib

rau txhua lub moos.

Default tus nqi

Kev piav qhia

Tawm Clock0
TSIS MUAJ

Xaiv qhov kev xaiv no los pab kom tso zis tso npe ntawm tus adder module.
Xaiv Clock0, Clock1 lossis Clock2 kom pab tau thiab qhia meej lub moos rau kev tso npe tso tawm. Koj yuav tsum xaiv Register output ntawm lub adder unit kom pab tau qhov parameter no.
Qhia meej qhov asynchronous clear source rau lub adder tso zis register. Koj yuav tsum xaiv Register output ntawm lub adder unit kom pab tau qhov parameter no.
Qhia meej lub synchronous ntshiab qhov chaw rau lub adder tso zis register. Koj yuav tsum xaiv Register output ntawm lub adder unit kom pab tau qhov parameter no.

Ntxiv

Xaiv qhov sib ntxiv lossis rho tawm haujlwm los ua rau cov txiaj ntsig ntawm thawj thiab thib ob tus lej sib npaug.
· Xaiv ADD los ua haujlwm ntxiv.
· Xaiv SUB los ua haujlwm rho tawm.
· Xaiv VARIABLE los siv addnsub1 chaw nres nkoj rau dynamic ntxiv / rho tawm tswj.
txuas ntxiv…

Xa lus tawm tswv yim

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Parameter

IP Generated Parameter

Tus nqi

Sau npe 'addnsub1' input

gui_addnsub_ On multiplier_reg Off ister1

Dab tsi yog lub hauv paus rau lub moos input?

gui_addnsub_ multiplier_reg ister1_clock

moos 0 moos 1 moos 2

Lub hauv paus rau asynchronous clear input yog dab tsi?

gui_addnsub_cov multiplier_aclr 1

TSIS MUAJ ACLR0 ACLR1

Dab tsi yog qhov chaw rau synchronous ntshiab input?

gui_addnsub_ multiplier_sclr 1

TSIS MUAJ SCLR0 SCLR1

Yuav ua li cas yuav tsum tau ua nyob rau hauv lub outputs ntawm ob khub ntawm multipliers?

gui_multiplier 3_direction

ADD, SUB, VARIABLE

Sau npe 'addnsub3' input

gui_addnsub_ On multiplier_reg Off ister3

Dab tsi yog lub hauv paus rau lub moos input?

gui_addnsub_ multiplier_reg ister3_clock

moos 0 moos 1 moos 2

Default tus nqi
Off Clock0 NEEJ TSIS PAUB
Tawm Clock0

Kev piav qhia
Thaum VARIABLE tus nqi raug xaiv: · Tsav addnsub1 teeb liab kom siab rau
kev ua haujlwm ntxiv. · Tsav addnsub1 teeb liab kom qis rau
kev rho tawm. Koj yuav tsum xaiv ntau tshaj ob qhov sib npaug kom pab tau qhov ntsuas no.
Xaiv qhov kev xaiv no txhawm rau txhawm rau tso npe nkag rau addnsub1 chaw nres nkoj. Koj yuav tsum xaiv VARIABLE rau Dab tsi ua haujlwm yuav tsum tau ua ntawm cov txiaj ntsig ntawm thawj khub ntawm kev sib tw kom pab tau qhov ntsuas no.
Xaiv Clock0 , Clock1 lossis Clock2 txhawm rau qhia meej lub moos lub teeb liab rau addnsub1 rau npe. Koj yuav tsum xaiv Register 'addnsub1' input kom pab tau qhov parameter no.
Qhia meej asynchronous clear source rau addnsub1 register. Koj yuav tsum xaiv Register 'addnsub1' input kom pab tau qhov parameter no.
Qhia meej qhov tseeb synchronous rau addnsub1 sau npe. Koj yuav tsum xaiv Register 'addnsub1' input kom pab tau qhov parameter no.
Xaiv qhov ntxiv lossis rho tawm ua haujlwm los ua rau cov txiaj ntsig ntawm qhov thib peb thiab plaub tus lej. · Xaiv ADD los ua ntxiv
kev ua haujlwm. · Xaiv SUB kom rho tawm
kev ua haujlwm. · Xaiv VARIABLE los siv addnsub1
chaw nres nkoj rau dynamic ntxiv / rho tawm tswj. Thaum VARIABLE tus nqi raug xaiv: · Tsav addnsub1 teeb liab kom siab rau kev ua haujlwm ntxiv. · Tsav addnsub1 teeb liab kom qis rau kev rho tawm haujlwm. Koj yuav tsum xaiv tus nqi 4 rau Tus lej ntawm tus lej yog dab tsi? kom pab tau qhov parameter no.
Xaiv qhov kev xaiv no txhawm rau txhawm rau tso npe nkag rau addnsub3 teeb liab. Koj yuav tsum xaiv VARIABLE rau Dab tsi ua haujlwm yuav tsum tau ua ntawm cov txiaj ntsig ntawm ob khub ntawm kev sib tw kom pab tau qhov ntsuas no.
Xaiv Clock0 , Clock1 lossis Clock2 kom qhia meej lub moos lub teeb liab rau addnsub3 rau npe. Koj yuav tsum xaiv Register 'addnsub3' input kom pab tau qhov parameter no.
txuas ntxiv…

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Parameter
Lub hauv paus rau asynchronous clear input yog dab tsi?

IP Generated Parameter

Tus nqi

gui_addnsub_cov multiplier_aclr 3

TSIS MUAJ ACLR0 ACLR1

Dab tsi yog qhov chaw rau synchronous ntshiab input?

gui_addnsub_ multiplier_sclr 3

TSIS MUAJ SCLR0 SCLR1

Polarity Pab kom 'use_subadd'

gui_use_subn On

ntxiv

Tawm

8.6.3 ib. Multipliers Tab

Table 32. Multipliers Tab

Parameter

IP Generated Parameter

Tus nqi

Dab tsi yog qhov

gui_represent

sawv cev format ation_a

rau Multipliers A inputs?

SAIB, UNSIGNED, VARIABLE

Sau npe 'signa' input

gui_register_s On

ua igna

Tawm

Dab tsi yog lub hauv paus rau lub moos input?

gui_register_s igna_clock

moos 0 moos 1 moos 2

Lub hauv paus rau asynchronous clear input yog dab tsi?

gui_register_s igna_aclr

TSIS MUAJ ACLR0 ACLR1

Dab tsi yog qhov chaw rau synchronous ntshiab input?

gui_register_s igna_sclr

TSIS MUAJ SCLR0 SCLR1

Dab tsi yog qhov

gui_represent

sawv cev format ation_b

rau Multipliers B inputs?

SAIB, UNSIGNED, VARIABLE

Sau npe 'signb' input

gui_register_s On

ignb ib

Tawm

Default Value TSIS MUAJ
TSIS MUAJ

Kev piav qhia
Qhia meej asynchronous clear source rau addnsub3 register. Koj yuav tsum xaiv Register 'addnsub3' input kom pab tau qhov parameter no.
Qhia meej qhov tseeb synchronous rau lub npe addnsub3. Koj yuav tsum xaiv Register 'addnsub3' input kom pab tau qhov parameter no.

Tawm

Xaiv qhov kev xaiv no los thim rov qab txoj haujlwm

ntawm addnsub input port.

Tsav addnsub kom siab rau kev rho tawm haujlwm.

Tsav addnsub kom qis rau kev ua haujlwm ntxiv.

Default tus nqi

Kev piav qhia

UNSIGNED Qhia cov qauv sawv cev rau tus lej sib npaug A.

Tawm

Xaiv qhov kev xaiv no los pab kom kos npe

sau npe.

Koj yuav tsum xaiv VARIABLE tus nqi rau Cov qauv sawv cev rau Multipliers A inputs yog dab tsi? parameter kom pab tau qhov kev xaiv no.

Moos 0

Xaiv Clock0 , Clock1 lossis Clock2 kom pab tau thiab qhia meej lub moos lub teeb liab rau kev kos npe rau npe.
Koj yuav tsum xaiv Register 'signa' input kom pab tau qhov parameter no.

TSIS MUAJ

Qhia qhov tseeb asynchronous rau lub npe kos npe.
Koj yuav tsum xaiv Register 'signa' input kom pab tau qhov parameter no.

TSIS MUAJ

Qhia meej qhov tseeb synchronous rau daim ntawv sau npe.
Koj yuav tsum xaiv Register 'signa' input kom pab tau qhov parameter no.

UNSIGNED Qhia cov qauv sawv cev rau tus lej sib npaug B input.

Tawm

Xaiv qhov kev xaiv no los pab kom signb

sau npe.

txuas ntxiv…

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Parameter

IP Generated Parameter

Tus nqi

Default tus nqi

Dab tsi yog lub hauv paus rau lub moos input?

gui_register_s ignb_clock

moos 0 moos 1 moos 2

Moos 0

Lub hauv paus rau asynchronous clear input yog dab tsi?

gui_register_s ignb_aclr

TSIS MUAJ ACLR0 ACLR1

Dab tsi yog qhov chaw rau synchronous ntshiab input?

gui_register_s ignb_sclr

TSIS MUAJ SCLR0 SCLR1

Input Configuration
Sau npe input A ntawm tus multiplier
Dab tsi yog lub hauv paus rau lub moos input?

gui_input_reg On

ister_ ua

Tawm

gui_input_reg ister_a_clock

moos 0 moos 1 moos 2

TSIS MUAJ
Tawm Clock0

Lub hauv paus rau asynchronous clear input yog dab tsi?

gui_input_reg ister_a_aclr

TSIS MUAJ ACLR0 ACLR1

Dab tsi yog qhov chaw rau synchronous ntshiab input?

gui_input_reg ister_a_sclr

TSIS MUAJ SCLR0 SCLR1

Sau npe input B ntawm tus multiplier
Dab tsi yog lub hauv paus rau lub moos input?

gui_input_reg On

ister_ ib

Tawm

gui_input_reg ister_b_clock

moos 0 moos 1 moos 2

TSIS MUAJ TEEB MEEM 0

Lub hauv paus rau asynchronous clear input yog dab tsi?

gui_input_reg ister_b_aclr

TSIS MUAJ ACLR0 ACLR1

TSIS MUAJ

Dab tsi yog qhov chaw rau synchronous ntshiab input?

gui_input_reg ister_b_sclr

TSIS MUAJ SCLR0 SCLR1

TSIS MUAJ

Dab tsi yog qhov input A ntawm qhov sib txuas txuas nrog?

gui_multiplier Multiplier input Multiplier

_a_input

Luam theej duab chain input input

Kev piav qhia
Koj yuav tsum xaiv VARIABLE tus nqi rau Cov qauv sawv cev rau Multipliers B inputs yog dab tsi? parameter kom pab tau qhov kev xaiv no.
Xaiv Clock0 , Clock1 lossis Clock2 kom pab tau thiab qhia meej lub moos input teeb liab rau kos npe rau npe. Koj yuav tsum xaiv Register 'signb' input kom pab tau qhov parameter no.
Qhia qhov tseeb asynchronous rau lub npe kos npe. Koj yuav tsum xaiv Register 'signb' input kom pab tau qhov parameter no.
Qhia qhov tseeb synchronous qhov chaw rau lub signb register. Koj yuav tsum xaiv Register 'signb' input kom pab tau qhov parameter no.
Xaiv qhov kev xaiv no txhawm rau txhawm rau tso npe nkag rau dataa input npav.
Xaiv Clock0 , Clock1 lossis Clock2 kom pab tau thiab qhia meej cov npe nkag hauv moos teeb liab rau dataa input tsheb npav. Koj yuav tsum xaiv Register input A ntawm tus multiplier kom pab tau qhov parameter no.
Qhia meej cov npe asynchronous ntshiab qhov chaw rau dataa input npav. Koj yuav tsum xaiv Register input A ntawm tus multiplier kom pab tau qhov parameter no.
Qhia meej cov npe synchronous ntshiab qhov chaw rau dataa input npav. Koj yuav tsum xaiv Register input A ntawm tus multiplier kom pab tau qhov parameter no.
Xaiv qhov kev xaiv no txhawm rau txhawm rau tso npe nkag rau datab input npav.
Xaiv Clock0 , Clock1 lossis Clock2 kom pab tau thiab qhia meej cov npe nkag hauv moos teeb liab rau datab input tsheb npav. Koj yuav tsum xaiv Register input B ntawm tus multiplier kom pab tau qhov parameter no.
Qhia meej cov npe asynchronous clear source rau datab input bus. Koj yuav tsum xaiv Register input B ntawm tus multiplier kom pab tau qhov parameter no.
Qhia meej cov npe synchronous ntshiab qhov chaw rau datab input npav. Koj yuav tsum xaiv Register input B ntawm tus multiplier kom pab tau qhov parameter no.
Xaiv qhov input qhov chaw rau input A ntawm tus multiplier.
txuas ntxiv…

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Parameter

IP Generated Parameter

Tus nqi

Scanout A Register Configuration

Sau npe tso zis ntawm lub scan saw

gui_scanouta Rau

_ sau npe

Tawm

Dab tsi yog lub hauv paus rau lub moos input?

gui_scanouta _register_cloc k

moos 0 moos 1 moos 2

Lub hauv paus rau asynchronous clear input yog dab tsi?

gui_scanouta _register_aclr

TSIS MUAJ ACLR0 ACLR1

Dab tsi yog qhov chaw rau synchronous ntshiab input?

gui_scanouta _register_sclr

TSIS MUAJ SCLR0 SCLR1

8.6.4 ib. Preadder Tab

Table 33. Preadder Tab

Parameter

IP Generated Parameter

Tus nqi

Xaiv hom preadder

preadder_mo de

SIMPLE, COEF, INPUT, SQUARE, CONSTANT

Default tus nqi

Kev piav qhia
Xaiv Multiplier input siv dataa input bus ua lub hauv paus rau tus multiplier. Xaiv Scan saw input siv lub tsheb npav scanin input ua lub hauv paus rau tus lej sib npaug thiab pab kom lub tsheb npav scanout tawm. Qhov kev ntsuas no muaj nyob rau thaum koj xaiv 2, 3 lossis 4 rau Tus lej ntawm tus lej yog dab tsi? parameter.

Tawm Clock0 TSIS MUAJ

Xaiv qhov kev xaiv no los pab kom tso npe tso npe rau scanouta tso zis tsheb npav.
Koj yuav tsum xaiv Scan saw input rau Dab tsi yog cov tswv yim A ntawm tus lej txuas nrog? parameter kom pab tau qhov kev xaiv no.
Xaiv Clock0 , Clock1 lossis Clock2 kom pab tau thiab qhia meej cov npe nkag hauv moos teeb liab rau scanouta tso zis tsheb npav.
Koj yuav tsum qhib Register tso zis ntawm scan saw parameter kom pab tau qhov kev xaiv no.
Qhia meej cov npe asynchronous ntshiab qhov chaw rau lub tsheb npav scanouta tso zis.
Koj yuav tsum qhib Register tso zis ntawm scan saw parameter kom pab tau qhov kev xaiv no.
Qhia meej cov npe synchronous ntshiab qhov chaw rau lub tsheb npav scanouta tso zis.
Koj yuav tsum xaiv Sau npe tso zis ntawm lub scan chain parameter kom pab tau qhov kev xaiv no.

Default tus nqi
SIJ HAWM

Kev piav qhia
Qhia meej hom kev ua haujlwm rau preadder module. YOOJ YIM: Hom no bypass lub preadder. Qhov no yog lub neej ntawd hom. COEF: Hom no siv cov zis ntawm lub preadder thiab coefsel input bus raws li cov inputs rau tus multiplier. INPUT: Hom no siv cov zis ntawm lub preadder thiab datac input bus raws li cov inputs rau tus multiplier. SQUARE: Hom no siv cov zis ntawm tus preadder ua ob qho tib si cov khoom nkag mus rau qhov sib npaug.
txuas ntxiv…

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Parameter

IP Generated Parameter

Tus nqi

Xaiv cov kev taw qhia preadder

gui_preadder ADD,

_kev taw qhia

SUB

Lub tsheb npav C width_c yuav tsum dav npaum li cas?

1–256 : kuv

Cov ntaub ntawv C Input Register Configuration

Sau npe datac input

gui_datac_inp Rau

ut_register

Tawm

Dab tsi yog lub hauv paus rau lub moos input?

gui_datac_inp ut_register_cl ock

moos 0 moos 1 moos 2

Lub hauv paus rau asynchronous clear input yog dab tsi?

gui_datac_inp ut_register_a clr

TSIS MUAJ ACLR0 ACLR1

Dab tsi yog qhov chaw rau synchronous ntshiab input?

gui_datac_inp ut_register_sc lr

TSIS MUAJ SCLR0 SCLR1

Coefficients
Lub coef width yuav tsum dav npaum li cas?

width_cov

1–27 : kuv

Coef Register Configuration

Sau npe rau coefsel input

gui_coef_regi Rau

ster

Tawm

Dab tsi yog lub hauv paus rau lub moos input?

gui_coef_regi ster_clock

moos 0 moos 1 moos 2

Default tus nqi
Ntxiv
16

Kev piav qhia
CONSTANT: Hom no siv dataa input npav nrog preadder bypassed thiab coefsel input tsheb npav raws li cov khoom nkag mus rau qhov sib npaug.
Qhia meej txog kev ua haujlwm ntawm tus preadder. Txhawm rau ua kom qhov kev ntsuas no, xaiv cov hauv qab no rau Xaiv hom preadder: · COEF · INPUT · SQUARE lossis · CONSTANT
Qhia tus naj npawb ntawm cov khoom rau C input npav. Koj yuav tsum xaiv INPUT rau Xaiv hom preadder kom pab tau qhov ntsuas no.

Nyob rau Clock0 TSIS MUAJ

Xaiv qhov kev xaiv no txhawm rau txhawm rau tso npe nkag rau datac input npav. Koj yuav tsum teeb tsa INPUT rau Xaiv hom preadder parameter kom pab tau qhov kev xaiv no.
Xaiv Clock0 , Clock1 lossis Clock2 txhawm rau txheeb xyuas lub moos input teeb liab rau datac input register. Koj yuav tsum xaiv Register datac input kom pab tau qhov parameter no.
Qhia meej qhov asynchronous clear source rau datac input register. Koj yuav tsum xaiv Register datac input kom pab tau qhov parameter no.
Qhia meej lub synchronous ntshiab qhov chaw rau datac input register. Koj yuav tsum xaiv Register datac input kom pab tau qhov parameter no.

Qhia tus naj npawb ntawm cov khoom rau

coefsel input tsheb npav.

Koj yuav tsum xaiv COEF lossis CONSTANT rau hom preadder kom pab tau qhov ntsuas no.

Hauv moos 0

Xaiv qhov kev xaiv no txhawm rau txhawm rau tso npe nkag rau coefsel input npav. Koj yuav tsum xaiv COEF lossis CONSTANT rau hom preadder kom pab tau qhov ntsuas no.
Xaiv Clock0 , Clock1 lossis Clock2 txhawm rau txheeb xyuas lub moos lub teeb liab rau coefsel input register. Koj yuav tsum xaiv Sau npe rau coefsel input kom pab tau qhov parameter no.
txuas ntxiv…

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Parameter
Lub hauv paus rau asynchronous clear input yog dab tsi?

IP Generated Parameter

Tus nqi

gui_coef_regi ster_aclr

TSIS MUAJ ACLR0 ACLR1

Dab tsi yog qhov chaw rau synchronous ntshiab input

gui_coef_regi ster_sclr

TSIS MUAJ SCLR0 SCLR1

Coefficient_0 Configuration

coef0_0 to coef0_7

0x00000 0xFFFFFF

Coefficient_1 Configuration

coef1_0 to coef1_7

0x00000 0xFFFFFF

Coefficient_2 Configuration

coef2_0 to coef2_7

0x00000 0xFFFFFF

Coefficient_3 Configuration

coef3_0 to coef3_7

0x00000 0xFFFFFF

8.6.5 ib. Accumulator Tab

Table 34. Accumulator Tab

Parameter

IP Generated Parameter

Tus nqi

Pab kom accumulator?

accumulator

YOG, TSIS MUAJ

Dab tsi yog hom kev ua haujlwm accumulator?

accum_directi ADD,

SUB

Default Value TSIS MUAJ
TSIS MUAJ
0 x0000000
0 x0000000
0 x0000000
0 x0000000

Kev piav qhia
Qhia meej asynchronous clear source rau lub coefsel input register. Koj yuav tsum xaiv Sau npe rau coefsel input kom pab tau qhov parameter no.
Qhia meej qhov tseeb synchronous rau lub coefsel input register. Koj yuav tsum xaiv Sau npe rau coefsel input kom pab tau qhov parameter no.
Qhia qhov coefficient qhov tseem ceeb rau thawj tus lej no. Tus naj npawb ntawm cov khoom yuav tsum zoo ib yam li teev nyob rau hauv Yuav ua li cas wide yuav tus coef width? parameter. Koj yuav tsum xaiv COEF lossis CONSTANT rau hom preadder kom pab tau qhov ntsuas no.
Qhia tus nqi coefficient rau tus lej thib ob no. Tus naj npawb ntawm cov khoom yuav tsum zoo ib yam li teev nyob rau hauv Yuav ua li cas wide yuav tus coef width? parameter. Koj yuav tsum xaiv COEF lossis CONSTANT rau hom preadder kom pab tau qhov ntsuas no.
Qhia tus nqi coefficient rau qhov thib peb tus lej sib npaug. Tus naj npawb ntawm cov khoom yuav tsum zoo ib yam li teev nyob rau hauv Yuav ua li cas wide yuav tus coef width? parameter. Koj yuav tsum xaiv COEF lossis CONSTANT rau hom preadder kom pab tau qhov ntsuas no.
Qhia qhov coefficient qhov tseem ceeb rau qhov kev sib tw thib plaub. Tus naj npawb ntawm cov khoom yuav tsum zoo ib yam li teev nyob rau hauv Yuav ua li cas wide yuav tus coef width? parameter. Koj yuav tsum xaiv COEF lossis CONSTANT rau hom preadder kom pab tau qhov ntsuas no.

Default Value NO
Ntxiv

Kev piav qhia
Xaiv YES txhawm rau pab kom lub accumulator. Koj yuav tsum xaiv Sau npe tso zis ntawm chav tsev adder thaum siv accumulator feature.
Qhia meej txog kev ua haujlwm ntawm lub accumulator: · ADD rau kev ua haujlwm ntxiv · SUB rau kev rho tawm haujlwm. Koj yuav tsum xaiv YES rau Enable accumulator? parameter kom pab tau qhov kev xaiv no.
txuas ntxiv…

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Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia 53

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Parameter
Preload Constant Enable preload constant

IP Generated Parameter

Tus nqi

gui_ena_prelo Rau

ad_const

Tawm

Dab tsi yog cov tswv yim ntawm cov chaw nres nkoj sib txuas nrog?

gui_accumula ACCUM_SLOAD, te_port_select SLOAD_ACCUM

Xaiv tus nqi rau preload loadconst_val 0 - 64

tas li

Dab tsi yog lub hauv paus rau lub moos input?

gui_accum_sl oad_register_ moos

moos 0 moos 1 moos 2

Lub hauv paus rau asynchronous clear input yog dab tsi?

gui_accum_sl oad_register_ aclr

TSIS MUAJ ACLR0 ACLR1

Dab tsi yog qhov chaw rau synchronous ntshiab input?

gui_accum_sl oad_register_ sclr

TSIS MUAJ SCLR0 SCLR1

Qhib ob chav accumulator

gui_double_a Rau

ua ccum

Tawm

Default tus nqi

Kev piav qhia

Tawm

Qhib lub accum_sload lossis

sload_accum teeb liab thiab sau npe nkag

dynamically xaiv cov tswv yim rau lub

accumulator.

Thaum accum_sload qis lossis sload_accum, cov zis ntau ntxiv yog pub rau hauv accumulator.

Thaum accum_sload siab lossis sload_accum, tus neeg siv tau teev tseg preload tas li yog pub rau hauv accumulator.

Koj yuav tsum xaiv YES rau Enable accumulator? parameter kom pab tau qhov kev xaiv no.

ACCUM_SL OAD

Qhia meej txog tus cwj pwm ntawm accum_sload/ sload_accum teeb liab.
ACCUM_SLOAD: Tsav accum_sload qis kom thauj cov khoom tso tawm ntau ntxiv rau lub accumulator.
SLOAD_ACCUM: Tsav sload_accum siab txhawm rau thauj cov zis ntau ntxiv rau lub accumulator.
Koj yuav tsum xaiv Enable preload constant xaiv kom pab tau qhov parameter no.

Qhia tus nqi preset tas li.

Tus nqi no tuaj yeem yog 2N qhov twg N yog tus nqi preset tas li.

Thaum N = 64, nws sawv cev rau xoom tas li.

Koj yuav tsum xaiv Enable preload constant xaiv kom pab tau qhov parameter no.

Moos 0

Xaiv Clock0 , Clock1 lossis Clock2 kom qhia meej lub cim moos lub cim rau accum_sload / sload_accum sau npe.
Koj yuav tsum xaiv Enable preload constant xaiv kom pab tau qhov parameter no.

TSIS MUAJ

Qhia meej qhov asynchronous clear source rau accum_sload/sload_accum register.
Koj yuav tsum xaiv Enable preload constant xaiv kom pab tau qhov parameter no.

TSIS MUAJ

Qhia meej qhov tseeb synchronous rau accum_sload/sload_accum register.
Koj yuav tsum xaiv Enable preload constant xaiv kom pab tau qhov parameter no.

Tawm

Enables ob lub accumulator register.

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8.6.6 ib. Systolic/Chainout Tab

Table 35. Systolic/Chainout Adder Tab

Parameter Enable chainout adder

IP Generated Parameter

Tus nqi

chainout_add YOG,

TSIS MUAJ

Dab tsi yog chainout adder ua haujlwm hom?

chainout_ntxiv ADD,

er_direction

SUB

Pab kom 'negate' input rau chainout adder?

Port_negate

PORT_USED, PORT_UNUSED

Sau npe 'negate' input? negate_regist ua

TSEEM CEEB, LOCK0, CLOCK1, CLOCK2, CLOCK3

Lub hauv paus rau asynchronous clear input yog dab tsi?

negate_aclr

TSIS MUAJ ACLR0 ACLR1

Dab tsi yog qhov chaw rau synchronous ntshiab input?

negate_sclr

TSIS MUAJ SCLR0 SCLR1

Systolic ncua
Pab kom systolic ncua kev sau npe

gui_systolic_d Rau

elay ua

Tawm

Dab tsi yog lub hauv paus rau lub moos input?

gui_systolic_d CLOCK0,

elay_ moos

CLOCK 1,

Default tus nqi
TSIS MUAJ

Kev piav qhia
Xaiv YES txhawm rau pab kom chainout adder module.

Ntxiv

Qhia meej txog chainout adder ua haujlwm.
Rau kev rho tawm haujlwm, SIGNED yuav tsum raug xaiv rau Daim ntawv sawv cev rau Multipliers A inputs yog dab tsi? thiab hom ntawv sawv cev rau Multipliers B inputs yog dab tsi? hauv Multipliers Tab.

PORT_UN siv

Xaiv PORT_USED los pab kom tsis txhob muaj teeb meem tawm tswv yim.
Qhov parameter no tsis siv tau thaum chainout adder raug kaw.

UNREGIST ERED

Txhawm rau pab kom lub input register rau negate input signal thiab qhia txog lub input moos teeb liab rau negate register.
Xaiv UNREGISTERED yog tias tsis xav tau kev tso npe nkag nkag mus
Qhov no parameter yog invalid thaum koj xaiv:
· TSIS MUAJ rau Enable chainout adder los yog
· PORT_UNUSED rau Enable 'negate' input rau chainout adder? parameter lub

TSIS MUAJ

Qhia meej qhov asynchronous clear source rau lub npe negate.
Qhov no parameter yog invalid thaum koj xaiv:
· TSIS MUAJ rau Enable chainout adder los yog
· PORT_UNUSED rau Enable 'negate' input rau chainout adder? parameter lub

TSIS MUAJ

Qhia meej lub synchronous ntshiab qhov chaw rau lub npe negate.
Qhov no parameter yog invalid thaum koj xaiv:
· TSIS MUAJ rau Enable chainout adder los yog
· PORT_UNUSED rau Enable 'negate' input rau chainout adder? parameter lub

Tawm CLOCK 0

Xaiv qhov kev xaiv no los pab kom systolic hom. Qhov kev ntsuas no muaj nyob rau thaum koj xaiv 2, lossis 4 rau Tus lej ntawm tus lej yog dab tsi? parameter. Koj yuav tsum ua kom lub npe tso zis ntawm chav tsev adder siv cov systolic ncua kev sau npe.
Qhia meej lub moos input teeb liab rau systolic ncua kev sau npe.
txuas ntxiv…

Xa lus tawm tswv yim

Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia 55

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Parameter

IP Generated Parameter

Tus nqi

CLOCK 2,

Lub hauv paus rau asynchronous clear input yog dab tsi?

gui_systolic_d elay_aclr

TSIS MUAJ ACLR0 ACLR1

Dab tsi yog qhov chaw rau synchronous ntshiab input?

gui_systolic_d elay_sclr

TSIS MUAJ SCLR0 SCLR1

Default tus nqi
TSIS MUAJ
TSIS MUAJ

Kev piav qhia
Koj yuav tsum xaiv qhib systolic ncua kev sau npe kom pab tau qhov kev xaiv no.
Qhia meej asynchronous clear source rau lub systolic ncua sij hawm. Koj yuav tsum xaiv qhib systolic ncua kev sau npe kom pab tau qhov kev xaiv no.
Qhia meej lub synchronous ntshiab qhov chaw rau lub systolic ncua kev sau npe. Koj yuav tsum xaiv qhib systolic ncua kev sau npe kom pab tau qhov kev xaiv no.

8.6.7. Pipelining Tab

Table 36. Pipelining Tab

Parameter Pipelining Configuration

IP Generated Parameter

Tus nqi

Koj puas xav ntxiv cov raj xa mus rau cov tswv yim?

gui_pipelining Tsis yog, Yog

Default tus nqi
Tsis muaj

Thov qhia qhov

latency

tus naj npawb ntawm latency moos

lub voj voog

Txhua tus nqi ntau dua 0 dua 0

Dab tsi yog lub hauv paus rau lub moos input?

gui_input_late ncy_clock

TUG 0, TUG 1, TUG 2

Lub hauv paus rau asynchronous clear input yog dab tsi?

gui_input_late ncy_aclr

TSIS MUAJ ACLR0 ACLR1

Dab tsi yog qhov chaw rau synchronous ntshiab input?

gui_input_late ncy_sclr

TSIS MUAJ SCLR0 SCLR1

CLOCK0 TSIS MUAJ

Kev piav qhia
Xaiv Yog los ua kom muaj qib ntxiv ntawm cov raj xa mus rau cov cim nkag. Koj yuav tsum qhia tus nqi ntau dua 0 rau Thov qhia tus naj npawb ntawm latency moos cycles parameter.
Qhia qhov xav tau latency hauv lub voj voog moos. Ib theem ntawm cov raj xa dej npe = 1 latency hauv lub voj voog moos. Koj yuav tsum xaiv YES rau Koj puas xav ntxiv cov raj xa mus rau cov tswv yim? kom pab tau qhov kev xaiv no.
Xaiv Clock0 , Clock1 lossis Clock2 kom pab tau thiab qhia meej lub raj xa dej tso npe nkag lub moos teeb liab. Koj yuav tsum xaiv YES rau Koj puas xav ntxiv cov raj xa mus rau cov tswv yim? kom pab tau qhov kev xaiv no.
Qhia meej txog cov npe asynchronous ntshiab qhov chaw rau cov npe pipeline ntxiv. Koj yuav tsum xaiv YES rau Koj puas xav ntxiv cov raj xa mus rau cov tswv yim? kom pab tau qhov kev xaiv no.
Qhia meej txog cov npe synchronous ntshiab qhov chaw rau cov npe pipeline ntxiv. Koj yuav tsum xaiv YES rau Koj puas xav ntxiv cov raj xa mus rau cov tswv yim? kom pab tau qhov kev xaiv no.

Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia 56

Xa lus tawm tswv yim

683490 | 2020.10.05 Xa lus tawm tswv yim

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core

Nco ntsoov:

Intel tau tshem tawm qhov kev txhawb nqa ntawm tus IP no hauv Intel Quartus Prime Pro Edition version 20.3. Yog tias tus IP tseem ceeb hauv koj lub hom phiaj tsim khoom siv hauv Intel Quartus Prime Pro Edition, koj tuaj yeem hloov tus IP nrog LPM_MULT Intel FPGA IP lossis rov tsim dua tus IP thiab suav koj tus qauv siv Intel Quartus Prime Standard Edition software.

ALTMEMMULT IP core yog siv los tsim cov cim xeeb raws li kev sib tw siv cov cim cim xeeb onchip pom hauv Intel FPGAs (nrog M512, M4K, M9K, thiab MLAB nco blocks). Cov tub ntxhais IP no muaj txiaj ntsig yog tias koj tsis muaj peev txheej txaus los siv cov khoom sib npaug hauv cov ntsiab lus logic (LEs) lossis cov peev txheej ntau ntxiv.
ALTMEMMULT IP core yog ib qho kev ua haujlwm synchronous uas xav tau lub moos. ALTMEMMULT IP core siv ib qho kev sib npaug nrog qhov tsawg tshaj plaws ntawm kev xa tawm thiab latency ua tau rau cov txheej txheem thiab cov kev qhia tshwj xeeb.
Cov duab hauv qab no qhia cov chaw nres nkoj rau ALTMEMMULT IP core.

Daim duab 21. ALTMEMMULT Ports

ALTMEMMULT

data_in[] sload_data coeff_in[]

result[] result_valid load_done

sload_cov

sclr sij
inst

Cov Ntaub Ntawv Tseem Ceeb Ntawm nplooj 71

9.1. Nta
ALTMEMMULT IP core muaj cov yam ntxwv hauv qab no: · Tsim tsuas yog kev nco-raws li kev sib tw uas siv cov cim xeeb ntawm lub cim xeeb pom hauv
Intel FPGAs · Txhawb cov ntaub ntawv dav ntawm 1 khoom · Txhawb kev kos npe thiab tsis kos npe cov ntaub ntawv sawv cev · Txhawb cov raj xa dej nrog cov zis latency ruaj khov

Daim ntawv pov thawj ISO 9001: 2015

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05
· Khaws ntau qhov tsis tu ncua hauv random-access memory (RAM)
· Muab kev xaiv los xaiv RAM thaiv hom
· Txhawb kev xaiv synchronous ntshiab thiab load-tswj cov tswv yim ports
9.2. Verilog HDL Prototype
Cov nram qab no Verilog HDL qauv yog nyob rau hauv Verilog Design File (.v) altera_mf.v hauv eda synthesis directory.
module altmemmult #( parameter coeff_representation = "SIGNED", parameter coefficient0 = "UNUSED", parameter data_representation = "SIGNED", parameter intended_device_family = "unused", parameter max_clock_cycles_per_result = 1_AU, parameter number_officient meter total_latency = 1, parameter width_c = 1, parameter width_d = 1, parameter width_r = 1, parameter width_s = 1, parameter lpm_type = “altmemmult”, parameter lpm_hint = “unused”) (input wire moos, input wire [width_c-1: 1]coeff_in, input wire [dav_d-0:1] data_in, output wire load_done, output wire [width_r-0:1] result, output wire result_valid, input wire sclr, input wire [dav_s-0:1] sel, input xaim sload_coeff, input wire sload_data)/* synthesis syn_black_box=0 */; endmodule
9.3. VHDL Component Tshaj Tawm
VHDL cov lus tshaj tawm yog nyob hauv VHDL Tsim File (.vhd) altera_mf_components.vhd hauv librariesvhdlaltera_mf directory.
tivthaiv altmemmult generic (coeff_representation:string := “SIGNED”; coefficient0:string := “UNUSED”; data_representation:string := “SIGNED”; purpose_device_family:string := “unused”; max_clock_cycles_fatural_result: alt; := 1; ram_block_type:string := “AUTO”; total_latency:natural; width_d:natural; "altmemmult"); port( moos:in std_logic; coeff_in:in std_logic_vector(width_c-1 downto 1):= (lwm yam => '1'); data_in:in std_logic_vector(width_d-0 downto 0);

Intel FPGA Integer Arithmetic IP Cores Tus Neeg Siv Qhia 58

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9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

load_done: tawm std_logic; result:out std_logic_vector(width_r-1 downto 0); result_valid: tawm std_logic; scr:in std_logic := '0'; sel:in std_logic_vector(width_s-1 downto 0):= (lwm yam => '0'); sload_coeff:in std_logic := '0'; sload_data:in std_logic := '0'); kawg tivthaiv;

9.4. Chaw nres nkoj

Cov lus hauv qab no teev cov tswv yim thiab cov chaw nres nkoj rau ALTMEMMULT IP core.

Table 37. ALTMEMMULT Input Ports

Chaw nres nkoj npe

Yuav tsum tau

Kev piav qhia

moos

Yog lawm

Clock input rau tus multiplier.

cov_in[]

Tsis muaj

Coefficient input chaw nres nkoj rau lub multiplier. Qhov loj ntawm qhov chaw nres nkoj nkag yog nyob ntawm tus nqi WIDTH_C parameter.

data_in[]

Yog lawm

Cov ntaub ntawv input chaw nres nkoj mus rau tus multiplier. Qhov loj ntawm qhov chaw nres nkoj nkag yog nyob ntawm tus nqi WIDTH_D parameter.

ua sclr

Tsis muaj

Synchronous ntshiab input. Yog tias tsis siv, tus nqi pib ua haujlwm siab.

sel[]

Tsis muaj

Kev xaiv coefficient ruaj khov. Qhov loj ntawm qhov chaw nres nkoj nkag yog nyob ntawm WIDTH_S

tus nqi parameter.

sload_cov

Tsis muaj

Synchronous load coefficient input chaw nres nkoj. Hloov tus nqi coefficient uas tau xaiv tam sim no nrog tus nqi teev tseg hauv coeff_in input.

sload_data

Tsis muaj

Synchronous load data input chaw nres nkoj. Lub teeb liab uas qhia txog kev ua haujlwm sib npaug tshiab thiab tshem tawm txhua qhov kev ua haujlwm sib npaug uas twb muaj lawm. Yog tias MAX_CLOCK_CYCLES_PER_RESULT parameter muaj tus nqi ntawm 1, sload_data input chaw nres nkoj tsis quav ntsej.

Table 38. ALTMEMMULT Output Ports

Chaw nres nkoj npe

Yuav tsum tau

Kev piav qhia

tshwm sim[]

Yog lawm

Multiplier output chaw nres nkoj. Qhov loj ntawm qhov chaw nres nkoj nkag yog nyob ntawm tus nqi WIDTH_R parameter.

result_valid

Yog lawm

Qhia tias thaum cov zis yog qhov txiaj ntsig tau ntawm kev ua tiav qhov sib npaug. Yog hais tias MAX_CLOCK_CYCLES_PER_RESULT parameter muaj tus nqi ntawm 1, qhov result_valid tso zis chaw nres nkoj tsis siv.

load_done

Tsis muaj

Qhia thaum lub coefficient tshiab tau ua tiav kev thauj khoom. Lub teeb liab load_done lees paub thaum lub coefficient tshiab tau ua tiav kev thauj khoom. Tshwj tsis yog lub teeb liab load_done siab, tsis muaj lwm tus nqi coefficient tuaj yeem thauj mus rau hauv lub cim xeeb.

9.5. Cov tsis

Cov lus hauv qab no teev cov kev txwv rau ATMEMMULT IP core.

Table 39.
WIDTH_D WIDTH_C

ALTMEMMULT Parameters
Lub npe Parameter

Yam yuav tsum tau muaj

Kev piav qhia

Integer Yes

Qhia qhov dav ntawm data_in[] chaw nres nkoj.

Integer Yes

Qhia qhov dav ntawm coeff_in[] chaw nres nkoj. txuas ntxiv…

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9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

Parameter Lub Npe WIDTH_R WIDTH

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FPGA Integer Arithmetic IP Cores, Integer Arithmetic IP Cores, Tus lej IP Cores, IP Cores

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