intel FPGA Integer Arithmetic IP Cores alakaʻi hoʻohana

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1 FPGA Integer Arithmetic IP Cores

2 Palapala / Punawai

2.1 Nā kuhikuhi

3 Nā leka pili

FPGA Integer Arithmetic IP Cores

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Intel FPGA Integer Arithmetic IP Cores Guide User
Hoʻohou ʻia no Intel® Quartus® Prime Design Suite: 20.3

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ID: 683490 Version: 2020.10.05

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1. Intel FPGA Integer Arithmetic IP Cores……………………………………………………………….. 5
2. LPM_COUNTER (Counter) IP Core………………………………………………………………………….. 7 2.1. Nā hiʻohiʻona……………………………………………………………………………………7 2.2. Verilog HDL Prototype…………………………………………………………………………………….. 8 2.3. Hōʻike Hui VHDL……………………………………………………………………………….8 2.4. VHDL LIBRARY_USE Hōʻike………………………………………………………………………… 9 2.5. Nā Awa………………………………………………………………………………………………..9 2.6. Nā ʻāpana………………………………………………………………………………………… 10
3. LPM_DIVIDE (Divider) Intel FPGA IP Core……………………………………………………………….. 12 3.1. Nā hiʻohiʻona……………………………………………………………………………………. 12 3.2. Verilog HDL Prototype…………………………………………………………………………………… 12 3.3. Hōʻike Hui VHDL………………………………………………………………………….. 13 3.4. VHDL LIBRARY_USE Hōʻike…………………………………………………………………………. 13 3.5. Nā Awa……………………………………………………………………………………………… 13 3.6. Nā ʻāpana………………………………………………………………………………………… 14
4. LPM_MULT (Multiplier) IP Core…………………………………………………………………………. 16 4.1. Nā hiʻohiʻona……………………………………………………………………………………. 16 4.2. Verilog HDL Prototype…………………………………………………………………………………… 17 4.3. Olelo Hoolaha Hui VHDL………………………………………………………………………….. 17 4.4. VHDL LIBRARY_USE Hōʻike…………………………………………………………………………. 17 4.5. Nā hōʻailona……………………………………………………………………………………………… 18 4.6. Nā ʻāpana no Stratix V, Arria V, Cyclone V, a me Intel Cyclone 10 LP Devices……………… 18 4.6.1. Papa Laulā……………………………………………………………………………………18 4.6.2. Nui 2 Tab……………………………………………………………………………… 19 4.6.3. Paipai Paipu……………………………………………………………………………… 19 4.7. Nā ʻāpana no Intel Stratix 10, Intel Arria 10, a me Intel Cyclone 10 GX Devices……….. 20 4.7.1. Papa Laulā……………………………………………………………………………………20 4.7.2. Nui 2 Tab…………………………………………………………………… 20 4.7.3. Ka Paipaipa……………………………………………………………………………………21
5. LPM_ADD_SUB (Adder/Subtractor)………………………………………………………………………… 22 5.1. Nā hiʻohiʻona……………………………………………………………………………………. 22 5.2. Verilog HDL Prototype…………………………………………………………………………………… 23 5.3. Olelo Hoolaha Hui VHDL………………………………………………………………………….. 23 5.4. VHDL LIBRARY_USE Hōʻike…………………………………………………………………………. 23 5.5. Nā Awa……………………………………………………………………………………………… 23 5.6. Nā ʻāpana………………………………………………………………………………………… 24
6. LPM_COMPARE (Hoʻohālikelike)………………………………………………………………………… 26 6.1. Nā hiʻohiʻona……………………………………………………………………………………. 26 6.2. Verilog HDL Prototype…………………………………………………………………………………… 27 6.3. Olelo Hoolaha Hui VHDL………………………………………………………………………….. 27 6.4. VHDL LIBRARY_USE Hōʻike…………………………………………………………………………. 27 6.5. Nā Awa……………………………………………………………………………………………… 27 6.6. Nā ʻāpana………………………………………………………………………………………… 28

Intel FPGA Integer Arithmetic IP Cores User Guide 2

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7. ALTECC (Kāhea Hoʻoponopono Hapa: Encoder/Decoder) IP Core…………………………………… 30
7.1. Nā hiʻohiʻona ALTECC Encoder…………………………………………………………………………..31 7.2. Verilog HDL Prototype (ALTECC_ENCODER)……………………………………………………. 32 7.3. Verilog HDL Prototype (ALTECC_DECODER)……………………………………………………. 32 7.4. Hōʻike Hui VHDL (ALTECC_ENCODER)……………………………………………33 7.5. Hōʻike Hui VHDL (ALTECC_DECODER)……………………………………………33 7.6. VHDL LIBRARY_USE Hōʻike…………………………………………………………………………. 33 7.7. Nā Awa Encoder……………………………………………………………………………………………… 33 7.8. Nā Awa Decoder…………………………………………………………………………………………34 7.9. Nā ʻāpana Hoʻopili…………………………………………………………………………………… 34 7.10. Nā ʻāpana hoʻokaʻawale ……………………………………………………………………………… 35
8. Intel FPGA Multiply Adder IP Core………………………………………………………………. 36
8.1. Nā hiʻohiʻona……………………………………………………………………………………. 37 8.1.1. Mea hoʻohui mua……………………………………………………………………………… 38 8.1.2. Palapala Hoʻopaneʻe Systolic………………………………………………………………………… 40 8.1.3. Mamua o ka hoouka mau………………………………………………………………………… 43 8.1.4. Mea Hoʻohui ʻAlua…………………………………………………………………… 43
8.2. Verilog HDL Prototype…………………………………………………………………………………… 44 8.3. Olelo Hoolaha Hui VHDL………………………………………………………………………….. 44 8.4. VHDL LIBRARY_USE Hōʻike…………………………………………………………………………. 44 8.5. Nā hōʻailona……………………………………………………………………………………………… 44 8.6. Nā ʻāpana………………………………………………………………………………………… 47
8.6.1. Papa Laulā……………………………………………………………………………………47 8.6.2. Ka Papa Mana Mana Hou………………………………………………………………………….. 47 8.6.3. Papa Hoʻonui…………………………………………………………………………………… 49 8.6.4. Ka Papa Hoʻolaha ……………………………………………………………………………. 51 8.6.5. Ka Papa Hoʻohui …………………………………………………………………………….. 53 8.6.6. Systolic/Chainout Tab……………………………………………………………………. 55 8.6.7. Paipai Paipu……………………………………………………………………………… 56
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core…………………… 57
9.1. Nā hiʻohiʻona……………………………………………………………………………………. 57 9.2. Verilog HDL Prototype…………………………………………………………………………………… 58 9.3. Olelo Hoolaha Hui VHDL………………………………………………………………………….. 58 9.4. Nā Awa……………………………………………………………………………………………… 59 9.5. Nā ʻāpana………………………………………………………………………………………… 59
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core……………………………………………… 61
10.1. Nā hiʻohiʻona……………………………………………………………………………………………… 62 10.2. Verilog HDL Prototype……………………………………………………………………………………..62 10.3. Hōʻike Hui VHDL………………………………………………………………………… 63 10.4. VHDL LIBRARY_USE Hōʻike……………………………………………………………………63 10.5. Nā Awa………………………………………………………………………………………………. 63 10.6. Nā ʻāpana…………………………………………………………………………………………. 64
11. ALTMULT_ADD (Multiply-Adder) IP Core………………………………………………………………..69
11.1. Nā hiʻohiʻona……………………………………………………………………………………………… 71 11.2. Verilog HDL Prototype……………………………………………………………………………………..72 11.3. Hōʻike Hui VHDL………………………………………………………………………… 72 11.4. VHDL LIBRARY_USE Hōʻike…………………………………………………………………72

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Intel FPGA Integer Arithmetic IP Cores User Guide 3

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11.5. Nā Awa………………………………………………………………………………………………. 72 11.6. Nā ʻāpana…………………………………………………………………………………………. 73
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core……………………………………………… 86 12.1. Hoʻonui Paʻakikī…………………………………………………………………………. 86 12.2. Hōʻike Canonical………………………………………………………………………… 87 12.3. Hōʻike Kuʻuna …………………………………………………………………. 87 12.4. Nā hiʻohiʻona……………………………………………………………………………………………….. 88 12.5. Verilog HDL Prototype………………………………………………………………………………..88 12.6. Hōʻike Hui VHDL………………………………………………………………………… 89 12.7. VHDL LIBRARY_USE Hōʻike……………………………………………………………………89 12.8. Nā hōʻailona………………………………………………………………………………………………. 89 12.9. Nā ʻāpana…………………………………………………………………………………………. 90
13. ALTSQRT (Integer Square Root) IP Core……………………………………………………………… 92 13.1. Nā hiʻohiʻona……………………………………………………………………………………………… 92 13.2. Verilog HDL Prototype……………………………………………………………………………………..92 13.3. Hōʻike Hui VHDL………………………………………………………………………… 93 13.4. VHDL LIBRARY_USE Hōʻike………………………………………………………………… 93 13.5. Nā Awa………………………………………………………………………………………………. 93 13.6. Nā ʻāpana…………………………………………………………………………………………. 94
14. PARALLEL_ADD (Parallel Adder) IP Core……………………………………………………………….. 95 14.1. Hiʻona…………………………………………………………………………………….95 14.2. Verilog HDL Prototype……………………………………………………………………………………..95 14.3. Hōʻike Hui VHDL………………………………………………………………………… 96 14.4. VHDL LIBRARY_USE Hōʻike…………………………………………………………………… 96 14.5. Nā Awa………………………………………………………………………………………………. 96 14.6. Nā ʻāpana…………………………………………………………………………………………. 97
15. Integer Arithmetic IP Cores User Guide Document Archives…………………………………… 98
16. Moʻolelo Hoʻoponopono Palapala no Intel FPGA Integer Arithmetic IP Cores User Guide…. 99

Intel FPGA Integer Arithmetic IP Cores User Guide 4

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1. Intel FPGA Integer Arithmetic IP Cores

Hiki iā ʻoe ke hoʻohana i nā cores IP integer Intel® FPGA e hana i nā hana makemakika i kāu hoʻolālā.

Hāʻawi kēia mau hana i ʻoi aku ka maikaʻi o ka logic synthesis a me ka hoʻokō ʻana i nā mea hana ma mua o ka hoʻopili ʻana i kāu mau hana ponoʻī. Hiki iā ʻoe ke hana i nā cores IP e hoʻokō i kāu mau koi hoʻolālā.

Ua māhele ʻia nā cores IP helu helu Intel integer i nā ʻāpana ʻelua: · Ka waihona o nā modules parameterized (LPM) IP cores · Intel-specific (ALT) IP cores

Hōʻike ka papa ma lalo nei i nā core IP helu helu helu.

Papa 1.

Ka papa inoa o nā IP Core

Koi IP

LPM IP cores

LPM_COUNTER

LPM_DIVIDE

LPM_MULT

LPM_ADD_SUB
LPM_COMPARE
Intel-specific (ALT) IP core ALTECC

Hana ma lunaview Mea hoʻonui helu helu
Mea hoʻohui a unuhi paha
ECC Encoder/Decoder

Mea kākoʻo ʻia
Arria® II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone® IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP,
Intel Cyclone 10 GX, MAX® II, MAX V, MAX 10, Stratix® IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Hikina V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Hikina V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Kapilipili IV E, Kapilipili IV GX, Kapilipili V, Intel Kapilipili 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Kapilipili IV E, Kapilipili IV GX, Kapilipili V, Intel Kapilipili 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Ka makani ino V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V hoʻomau…

Huina Intel. Ua mālama ʻia nā kuleana āpau. ʻO Intel, ka Intel logo, a me nā hōʻailona Intel ʻē aʻe he mau hōʻailona o Intel Corporation a i ʻole kāna mau lālā. Mālama ʻo Intel i ka hana o kāna mau huahana FPGA a me semiconductor i nā kikoʻī o kēia manawa e like me ka palapala hōʻoia maʻamau o Intel, akā aia ke kuleana e hoʻololi i nā huahana a me nā lawelawe i kēlā me kēia manawa me ka ʻole o ka hoʻolaha. ʻAʻole ʻo Intel i kuleana a i ʻole kuleana e puka mai ana mai ka noi a i ʻole ka hoʻohana ʻana i kekahi ʻike, huahana, a i ʻole lawelawe i wehewehe ʻia ma ʻaneʻi koe wale nō i ʻae ʻia ma ke kākau ʻana e Intel. Manaʻo ʻia nā mea kūʻai aku Intel e loaʻa i ka mana hou o nā kikoʻī o nā hāmeʻa ma mua o ka hilinaʻi ʻana i kekahi ʻike i paʻi ʻia a ma mua o ke kau ʻana i nā kauoha no nā huahana a i ʻole nā lawelawe. * Hiki ke koi ʻia nā inoa a me nā hōʻailona ʻē aʻe ma ke ʻano he waiwai o nā poʻe ʻē aʻe.

ISO 9001:2015 Kakau

1. Intel FPGA Integer Arithmetic IP Cores 683490 | 2020.10.05

Nā Kohu IP Intel FPGA Multiply Adder a i ʻole ALTERA_MULT_ADD ALTMEMMULT
ALTMULT_ACCUM ALTMULT_ADD ALTMULT_COMPLEX
ALTSQRT
PARALLEL_ADD

Hana ma lunaview Mea hoʻonui-mea hoʻohui
Mea hoʻonui hoʻonui mau ma ka hoʻomanaʻo
Mea hoʻonui-Accumulator Multiplier-Adder
Mea hoʻonui paʻakikī
Integer Square-Root
Pākuʻi Kaulike

Mea kākoʻo ʻia
Arria V, Stratix V, Hikina V, Intel Stratix 10, Intel Arria 10, Intel Cyclone
10 GX
Arria II GX, Arria II GZ, Arria V, Intel Arria 10 (Intel Quartus® Prime Standard Edition), Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
ʻAiʻino 10 LP, MAX II, MAX V, MAX 10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Intel Arria 10, Arria V, Arria V GZ, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Ka makani ino 10 GX, Intel 10 LP, MAX 10, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Huli ʻino V, Huli ʻino Intel 10 LP, Huli ʻino Intel 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Hikina V, Intel Huni 10 LP, Intel Huni 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V

ʻIke pili
· Nā memo hoʻokuʻu ʻia nā Intel FPGA a me nā memo i hoʻokuʻu ʻia
· Introduction to Intel FPGA IP Cores Hāʻawi i ka ʻike hou aku e pili ana i Intel FPGA IP Cores.
· Nā Kohu IP Launae Alakaʻi Mea Hoʻohana Hāʻawi i nā ʻike hou aku e pili ana i nā cores IP Floating-Point Intel FPGA.
· Introduction to Intel FPGA IP Cores Hāʻawi i ka ʻike maʻamau e pili ana i nā cores IP FPGA Intel āpau, me ka hoʻohālikelike ʻana, ka hana ʻana, ka hoʻonui ʻana, a me ka hoʻohālikelike ʻana i nā cores IP.
· Ka Hoʻokumu ʻana i ka IP Kūʻokoʻa Kūʻokoʻa a me Qsys Simulation Scripts.
· Nā Papahana Hoʻomaʻamaʻa maikaʻi loa no ka hoʻokele maikaʻi a me ka lawe ʻana o kāu papahana a me IP files.
· Integer Arithmetic IP Cores User Guide Document Archives ma ka ʻaoʻao 98 Hāʻawi i ka papa inoa o nā alakaʻi alakaʻi no nā mana mua o nā cores Integer Arithmetic IP.

Intel FPGA Integer Arithmetic IP Cores User Guide 6

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2. LPM_COUNTER (Counter) IP Core

Kiʻi 1.

ʻO ka LPM_COUNTER IP core he helu helu helu e hana ana i nā helu helu, nā helu iho a me nā helu i luna a i lalo paha me nā huahana a hiki i 256 mau ʻāpana ākea.

Hōʻike kēia kiʻi i nā awa no ka LPM_COUNTER IP core.

Nā Awa LPM_COUNTER

LPM_COUNTER

ssclr sload sset data[]

q[]

hōʻano hou ʻia

cout

aclr aload aset

clk_en cnt_en cin
inst

2.1. Nā hiʻohiʻona
Hāʻawi ka LPM_COUNTER IP core i kēia mau hiʻohiʻona: · Hoʻokumu i nā helu helu i luna, lalo, a i luna/lalo · Hoʻokumu i nā ʻano helu helu penei:
— Binary Plain– nā hoʻonui counter e hoʻomaka ana mai ka zero a i ʻole nā mea hoʻemi e hoʻomaka ana mai ka 255
— Modulus—e hoʻonui a hoʻemi ʻia ka helu modulus i kuhikuhi ʻia e ka mea hoʻohana a hana hou
· Kākoʻo i nā awa hoʻokomo koho koho ʻia, hoʻouka, a hoʻonohonoho i nā awa hoʻokomo · Kākoʻo i ke koho asynchronous clear, hoʻouka, a hoʻonohonoho i nā awa komo · Kākoʻo i ka helu koho a hiki i ka uaki ke hoʻokomo i nā awa hoʻokomo

ISO 9001:2015 Kakau

2. LPM_COUNTER (Counter) IP Core
683490 | 2020.10.05
2.2. ʻO Verilog HDL Prototype
Aia ka prototype Verilog HDL ma ka Verilog Design File (.v) lpm.v i ka papa kuhikuhi edasynthesis.
module lpm_counter (q, data, uaki, cin, cout, clk_en, cnt_en, updown, aseta, aclr, aload, sset, sclr, sload, eq ); ka palena lpm_type = “lpm_counter”; ka palena lpm_width = 1; ka palena lpm_modulus = 0; parameter lpm_direction = “ʻAʻole hoʻohana ʻia”; parameter lpm_value = “ʻAʻole hoʻohana ʻia”; parameter lpm_svalue = “ʻAʻole hoʻohana ʻia”; parameter lpm_pvalue = “ʻAʻole hoʻohana ʻia”; parameter lpm_port_updown = “PORT_CONNECTIVITY”; parameter lpm_hint = “ʻAʻole hoʻohana ʻia”; puka [lpm_width-1:0] q; puka puka; puka [15:0] like; hoʻokomo cin; hoʻokomo i ka ʻikepili [lpm_width-1:0]; uaki komo, clk_en, cnt_en, updown; hoʻokomo aset, aclr, aload; hoʻokomo sset, sclr, sload; hopemodule
2.3. Hōʻike Hui VHDL
Aia ka ʻōlelo hoʻolaha ʻāpana VHDL ma ka VHDL Design File (.vhd) LPM_PACK.vhd i ka waihona waihona vhdllpm.
ʻāpana LPM_COUNTER maʻamau ( LPM_WIDTH: kūlohelohe; LPM_MODULUS: kūlohelohe: = 0; LPM_DIRECTION: string: = "UNUSED"; LPM_AVALUE: string: = "UNUSED"; LPM_SVALUE: string: = "UNUSED"; LPM_PORT_UPDOWN: string: = "PORT_CONNECT" ; LPM_PVALUE : string := “UNUSED”; awa (DATA: ma std_logic_vector(LPM_WIDTH-1 a hiki i 0):= (NĀ ʻAʻE =>
'0'); KAUKA: ma std_logic; CLK_EN : in std_logic : = '1'; CNT_EN : ma std_logic : = '1'; UPDOWN : in std_logic : = '1'; SLOAD : ma std_logic : = '0'; SSET: ma std_logic: = '0'; SCLR : ma std_logic : = '0'; ALOAD : in std_logic := '0'; ASET : ma std_logic := '0'; ACLR : in std_logic : = '0'; CIN: ma std_logic: = '1'; COUT : out std_logic : = '0'; N: waho std_logic_vector(LPM_WIDTH-1 a hiki i ka 0); EQ: i waho std_logic_vector (15 a hiki i ka 0));
mea hope;

Intel FPGA Integer Arithmetic IP Cores User Guide 8

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2. LPM_COUNTER (Counter) IP Core 683490 | 2020.10.05

2.4. Hōʻike VHDL LIBRARY_USE
ʻAʻole koi ʻia ka ʻōlelo hoʻolaha VHDL LIBRARY-USE inā hoʻohana ʻoe i ka VHDL Component Declaration.
HAAWINA lpm; E hoohana i lpm.lpm_components.all;

2.5. Awa

Hoʻopuka nā papa ma lalo nei i nā awa hoʻokomo a me nā puka puka no ka LPM_COUNTER IP core.

Papa 2.

LPM_COUNTER Nā Awa Hookomo

inoa awa

Pono

wehewehe

ʻikepili []

ʻAʻole

Hoʻokomo ʻikepili like i ka counter. ʻO ka nui o ke awa hoʻokomo e pili ana i ka waiwai hoʻohālikelike LPM_WIDTH.

uaki

ʻAe

Hoʻokomo ʻana i ka uaki i hoʻokomo ʻia i ka ʻaoʻao maikaʻi.

clk_en

ʻAʻole

Hiki i ka uaki ke hoʻokomo i nā hana synchronous a pau. Inā haʻalele ʻia, ʻo 1 ka waiwai paʻamau.

cnt_en

ʻAʻole

Hiki i ka helu ke hoʻokomo i ka helu ke hoʻopau ʻia ka helu ke haʻahaʻa ʻole ʻia me ka hoʻopilikia ʻole i ka sload, sset, a i ʻole sclr. Inā haʻalele ʻia, ʻo 1 ka waiwai paʻamau.

hōʻano hou ʻia

ʻAʻole

Manaʻo i ke kuhikuhi o ka helu. Ke ʻōlelo ʻia he kiʻekiʻe (1), piʻi ka ʻaoʻao helu, a i ka haʻahaʻa haʻahaʻa (0), ua iho ka ʻaoʻao helu. Inā hoʻohana ʻia ka ʻāpana LPM_DIRECTION, ʻaʻole hiki ke hoʻopili ʻia ke awa i lalo. Inā ʻaʻole hoʻohana ʻia ʻo LPM_DIRECTION, koho ʻia ke awa i lalo. Inā haʻalele ʻia, piʻi ka waiwai paʻamau (1).

cin

ʻAʻole

Lawe i loko o ka ʻāpana haʻahaʻa. No nā helu helu, ʻo ke ʻano o ka hoʻokomo cin

e like me ke ʻano o ka hoʻokomo cnt_en. Inā haʻalele ʻia, ʻo 1 ka waiwai paʻamau

(VCC).

aclr

ʻAʻole

Hoʻokomo asynchronous maopopo. Inā hoʻohana ʻia ka aseta a me ka aclr a hoʻopaʻa ʻia, hoʻopau ʻo aclr i ka aseta. Inā haʻalele ʻia, ʻo ka waiwai paʻamau ʻo 0 (pāʻole).

waiwai

ʻAʻole

Hoʻokomo hoʻonohonoho ʻokoʻa. Hōʻike i nā hua q[] e like me nā 1 a pau, a i ʻole ka waiwai i kuhikuhi ʻia e ka LPM_AVALUE. Inā hoʻohana ʻia nā awa ʻelua a me nā awa aclr, ʻoi aku ka waiwai o ke awa aclr i ka waiwai o ke awa aseta. Inā haʻalele ʻia, ʻo 0 ka waiwai paʻamau, pio.

hoʻouka

ʻAʻole

Hoʻokomo hoʻouka ʻokoʻa i hoʻouka like ʻole i ka counter me ka waiwai ma ka hoʻokomo ʻikepili. Ke hoʻohana ʻia ke awa hoʻouka, pono e hoʻopili ʻia ke awa [] data. Inā haʻalele ʻia, ʻo 0 ka waiwai paʻamau, pio.

sclr

ʻAʻole

Hoʻokomo ʻokoʻa ʻokoʻa e hoʻomaʻemaʻe i ka counter ma ka ʻaoʻao o ka uaki hana. Inā hoʻohana ʻia nā awa sset a me sclr, ʻoi aku ka waiwai o ka awa sclr i ka waiwai o ke awa sset. Inā haʻalele ʻia, ʻo 0 ka waiwai paʻamau, pio.

sset

ʻAʻole

Hoʻokomo pūlima hoʻonohonoho e hoʻonohonoho ana i ka counter ma ka ʻaoʻao o ka uaki hana. Hōʻike i ka waiwai o nā hua q e like me nā 1 a pau, a i ʻole ka waiwai i kuhikuhi ʻia e ka LPM_SVALUE parameter. Inā hoʻohana ʻia nā awa sset a me sclr,
ka waiwai o ke awa sclr e hoopau ana i ka waiwai o ke awa sset. Inā haʻalele ʻia, ʻo ka waiwai paʻamau ʻo 0 (pāʻole).

sload

ʻAʻole

Hoʻokomo hoʻouka like ʻole e hoʻouka ana i ka counter me ka ʻikepili [] ma ka ʻaoʻao o ka uaki hana. Ke hoʻohana ʻia ke awa sload, pono e hoʻopili ʻia ke awa data[]. Inā haʻalele ʻia, ʻo ka waiwai paʻamau ʻo 0 (pāʻole).

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 9

2. LPM_COUNTER (Counter) IP Core 683490 | 2020.10.05

Papa 3.

LPM_COUNTER Nā Awa Hoʻopuka

inoa awa

Pono

wehewehe

q[]

ʻAʻole

Hoʻopuka ʻikepili mai ka counter. ʻO ka nui o ka puka puka ma muli o ka

LPM_WIDTH waiwai hoʻohālikelike. ʻO q[] a i ʻole kekahi o nā awa eq[15..0].

pono e pili.

eq[15..0]

ʻAʻole

Hoʻopuka helu helu helu. ʻAʻole hiki ke loaʻa ke awa eq[15..0] i ka mea hoʻoponopono hoʻohālikelike no ka mea kākoʻo wale ka ʻāpana iā AHDL.
Pono e hoʻopili ʻia ke awa q[] a i ʻole eq[]. Hiki ke hoʻohana i nā awa a hiki i c eq (0 <= c <= 15). ʻO nā helu helu haʻahaʻa haʻahaʻa he 16 wale nō i unuhi ʻia. Inā he c ka helu helu, ua ʻōlelo ʻia ke kiʻekiʻe (1). No example, ina he 0 ka helu, eq0 = 1, ina he 1 ka helu, eq1 = 1, a ina he 15 ka helu, eq 15 = 1. No ka helu ana he 16 a oi, e koi aku i ka wehe ana i waho. ʻAʻole like ka eq[15..0] i ka q[].

cout

ʻAʻole

Awa lawe o ka bit MSB o ka counter. Hiki ke hoʻohana ʻia no ka hoʻohui ʻana i kekahi counter e hana i kahi counter ʻoi aku ka nui.

2.6. Parameter

Hōʻike ka papa ma lalo i nā ʻāpana no ka LPM_COUNTER IP core.

Papa 4.

LPM_COUNTER Nā ʻāpana

Ka inoa ʻāpana

ʻAno

LPM_WIDTH

Integer

LPM_DIRECTION

kaulahao

LPM_MODULUS LPM_AVALUE

Integer
Integer/ string

LPM_SVALUE LPM_HINT

Integer/ string
kaulahao

LPM_TYPE

kaulahao

Pono ʻAe ʻAʻole ʻAʻole
ʻAʻole ʻAʻole
ʻAʻole

wehewehe
Hōʻike i ka laulā o nā awa [] a me q[], inā hoʻohana ʻia.
ʻO nā waiwai he UP, DOWN, a me UNUSED. Inā hoʻohana ʻia ka ʻāpana LPM_DIRECTION, ʻaʻole hiki ke hoʻopili ʻia ke awa i lalo. Ke pili ʻole ke awa i lalo, ʻo UP ka LPM_DIRECTION parameter paʻamau.
ʻO ka helu kiʻekiʻe loa, me hoʻokahi. Ka helu o nā mokuʻāina kūʻokoʻa i ka pōʻai o ka counter. Inā ʻoi aku ka nui o ka ukana ma mua o ka LPM_MODULUS parameter, ʻaʻole i kuhikuhi ʻia ke ʻano o ka counter.
ʻO ka waiwai mau i hoʻouka ʻia i ka wā i ʻōlelo ʻia he kiʻekiʻe. Inā ʻoi aku ka nui o ka waiwai i ʻōlelo ʻia ma mua a i ʻole like , ʻo ka hana o ka counter he undefined logic level, kahi he LPM_MODULUS, inā aia, a i ʻole 2 ^ LPM_WIDTH. Manaʻo ʻo Intel e kuhikuhi ʻoe i kēia waiwai ma ke ʻano he helu decimal no nā hoʻolālā AHDL.
Waiwai mau i hoʻouka ʻia ma ka ʻaoʻao piʻi o ke awa uaki ke hōʻoia ʻia ke awa sset kiʻekiʻe. Manaʻo ʻo Intel e kuhikuhi ʻoe i kēia waiwai ma ke ʻano he helu decimal no nā hoʻolālā AHDL.
Ke hoʻomaka koke ʻoe i kahi waihona o nā modules parameterized (LPM) hana i kahi Hoʻolālā VHDL File (.vhd), pono ʻoe e hoʻohana i ka ʻāpana LPM_HINT e kuhikuhi i kahi ʻāpana kikoʻī Intel. No example: LPM_HINT = “CHAIN_SIZE = 8, ONE_INPUT_IS_CONSTANT = YES”
ʻO UNUSED ka waiwai paʻamau.
Hoʻomaopopo i ka waihona o nā modules parameterized (LPM) inoa hui ma ka hoʻolālā VHDL files.
hoʻomau…

Intel FPGA Integer Arithmetic IP Cores User Guide 10

Hoʻouna Manaʻo

2. LPM_COUNTER (Counter) IP Core 683490 | 2020.10.05

Ka inoa ʻāpana INTENDED_DEVICE_FAMILY CARRY_CNT_EN
LAWIDE_SCLR
LPM_PORT_UPDOWN

E hoʻokomo i ke kaula
kaulahao
kaulahao

Pono ʻAʻole No
ʻAʻole
ʻAʻole

wehewehe
Hoʻohana ʻia kēia ʻāpana no ke kumu hoʻohālike a me ka hoʻohālikelike ʻano. Hoʻohana ʻia kēia ʻāpana no ke kumu hoʻohālike a me ka hoʻohālikelike ʻano. Hoʻopili ka mea hoʻoponopono hoʻoponopono i ka waiwai no kēia ʻāpana.
ʻāpana kikoʻī Intel. Pono ʻoe e hoʻohana i ka ʻāpana LPM_HINT e kuhikuhi i ka ʻāpana CARRY_CNT_EN ma ka hoʻolālā VHDL files. ʻO nā waiwai he SMART, ON, OFF, a me UNUSED. Hiki i ka hana LPM_COUNTER ke hoʻolaha i ka hōʻailona cnt_en ma o ke kaulahao lawe. I kekahi mau hihia, hiki i ka hoʻonohonoho hoʻonohonoho CARRY_CNT_EN ke hoʻololi iki i ka wikiwiki, no laila makemake paha ʻoe e hoʻopau. ʻO ka waiwai paʻamau ʻo SMART, ka mea e hāʻawi i ke kālepa maikaʻi loa ma waena o ka nui a me ka wikiwiki.
ʻāpana kikoʻī Intel. Pono ʻoe e hoʻohana i ka ʻāpana LPM_HINT e kuhikuhi i ka ʻāpana LAWIDE_SCLR ma ka hoʻolālā VHDL files. ON, OFF a i ʻole UNUSED nā waiwai. ʻO ON ka waiwai paʻamau. ʻAe iā ʻoe e hoʻopau i ka hoʻohana ʻana i ka hiʻohiʻona LABwide sclr i loaʻa i nā ʻohana hāmeʻa kahiko. ʻO ka hoʻohuli ʻana i kēia koho e hoʻonui i ka manawa o ka hoʻohana piha ʻana i nā LAB i hoʻopiha piha ʻia, a no laila hiki ke ʻae ʻia ke kiʻekiʻe o ka noʻonoʻo inā ʻaʻole pili ʻo SCLR i kahi LAB piha. Loaʻa kēia ʻāpana no ka hoʻohālikelike hope, a ʻōlelo ʻo Intel iā ʻoe ʻaʻole e hoʻohana i kēia ʻāpana.
Hōʻike i ka hoʻohana ʻana i ke awa hoʻokomo i luna. Inā ha'alele 'ia ka waiwai pa'amau 'o PORT_CONNECTIVITY. Ke hoʻonoho ʻia ka waiwai awa iā PORT_USED, mālama ʻia ke awa e like me ka hoʻohana ʻana. Ke hoʻonoho ʻia ka waiwai awa iā PORT_UNUSED, mālama ʻia ke awa me he mea lā ʻaʻole i hoʻohana ʻia. Ke hoʻonoho ʻia ka waiwai awa i PORT_CONNECTIVITY, e hoʻoholo ʻia ka hoʻohana ʻana i ke awa ma ka nānā ʻana i ka hoʻopili ʻana i ke awa.

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 11

683490 | 2020.10.05 Hoʻouna Manaʻo

3. LPM_DIVIDE (Divider) Intel FPGA IP Core

Kiʻi 2.

Hoʻokomo ka LPM_DIVIDE Intel FPGA IP core i ka mea hoʻokaʻawale e puʻunaue i ka waiwai hoʻokomo helu me kahi waiwai hoʻokomo denominator e hana i kahi quotient a me ke koena.

Hōʻike kēia kiʻi i nā awa no ka LPM_DIVIDE IP core.

Nā Awa LPM_DIVIDE

LPM_DIVIDE

helu[] denom[] uaki

quotient [] koe []

clken aclr

inst

3.1. Nā hiʻohiʻona
Hāʻawi ka LPM_DIVIDE IP core i kēia mau hiʻohiʻona: · Hoʻokumu i kahi mea hoʻokaʻawale e puʻunaue ana i ka waiwai hoʻokomo helu me kahi hoʻokomo denominator.
waiwai e hana i ka quotient a me ke koena. · Kākoʻo i ka laulā ʻikepili o 1 bits. · Kākoʻo i ka hōʻike hōʻike ʻikepili i pūlima ʻia a ʻaʻole pūlima ʻia no ka helu helu
a me ka helu helu. · Kākoʻo i ka ʻāpana a i ʻole ka wikiwiki wikiwiki. · Hāʻawi i kahi koho e hōʻike i ke koena hopena maikaʻi. · Kākoʻo pipelining configurable output latency. · Kākoʻo i ka asynchronous maʻemaʻe a me ka uaki hiki i nā awa.

3.2. ʻO Verilog HDL Prototype
Aia ka prototype Verilog HDL ma ka Verilog Design File (.v) lpm.v i ka papa kuhikuhi edasynthesis.
module lpm_divide ( quotient, remain, numer, denom, clock, clken, aclr); ka palena lpm_type = “lpm_divide”; ka palena lpm_widthn = 1; ka palena lpm_widthd = 1; hoʻohālikelike lpm_nrepresentation = “UNSIGNEED”; hoʻohālikelike lpm_drepresentation = “UNSIGNEED”; parameter lpm_remainderpositive = “TRUE”; palena lpm_pipeline = 0;

ISO 9001:2015 Kakau

3. LPM_DIVIDE (Divider) Intel FPGA IP Core 683490 | 2020.10.05

parameter lpm_hint = “ʻAʻole hoʻohana ʻia”; uaki komo; komo clken; hoʻokomo aclr; hoʻokomo [lpm_widthn-1:0] helu; hoʻokomo [lpm_widthd-1:0] denom; puka [lpm_widthn-1:0] quotient; puka [lpm_widthd-1:0] koe; hopemodule

3.3. Hōʻike Hui VHDL
Aia ka ʻōlelo hoʻolaha ʻāpana VHDL ma ka VHDL Design File (.vhd) LPM_PACK.vhd i ka waihona waihona vhdllpm.
ʻāpana LPM_DIVIDE generic (LPM_WIDTHN : kūlohelohe; LPM_WIDTHD : kūlohelohe;
LPM_NREPRESENTATION : kaula : = “A’ole KAU”; LPM_DREPRESENTATION : kaula : = “A’ole KAU”; LPM_PIPELINE : kūlohelohe := 0; LPM_TYPE : kaula : = L_DIVIDE; LPM_HINT : string := “UNUSED”); awa (NUMER: ma std_logic_vector(LPM_WIDTHN-1 iho i ka 0); DENOM: ma std_logic_vector(LPM_WIDTHD-1 iho i 0); ACLR: ma std_logic:= '0'; UIKA: ma std_logic:= '0'; CLKEN: ma std_logic : = '1'; QUOTIENT : waho std_logic_vector(LPM_WIDTHN-1 a hiki i ka 0) mea hope;

3.4. Hōʻike VHDL LIBRARY_USE
ʻAʻole koi ʻia ka ʻōlelo hoʻolaha VHDL LIBRARY-USE inā hoʻohana ʻoe i ka VHDL Component Declaration.
HAAWINA lpm; E hoohana i lpm.lpm_components.all;

3.5. Awa

Hoʻopuka nā papa ma lalo nei i nā awa hoʻokomo a me nā puka puka no ka LPM_DIVIDE IP core.

Papa 5.

LPM_DIVIDE Nā Awa Hookomo

inoa awa

Pono

helu []

ʻAe

denom []

ʻAe

wehewehe
Hoʻokomo ʻikepili helu. ʻO ka nui o ke awa hoʻokomo e pili ana i ka waiwai hoʻohālikelike LPM_WIDTHN.
Hoʻokomo ʻikepili denominator. ʻO ka nui o ke awa hoʻokomo e pili ana i ka waiwai hoʻohālikelike LPM_WIDTHD.
hoʻomau…

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 13

3. LPM_DIVIDE (Divider) Intel FPGA IP Core 683490 | 2020.10.05

Uaki inoa awa clken
aclr

Pono ʻAʻole No
ʻAʻole

wehewehe
Hoʻokomo uaki no ka hoʻohana ʻana i ka pipeline. No nā waiwai LPM_PIPELINE ʻē aʻe ma mua o 0 (paʻamau), pono e ʻae ʻia ke awa uaki.
Hiki i ka uaki ke hoʻohana i ka pipelined. I ka manawa i hoʻokūpaʻa ʻia ai ke awa clken kiʻekiʻe, lawe ʻia ka hana mahele. Ke haʻahaʻa ka hōʻailona, ʻaʻohe hana. Inā haʻalele ʻia, ʻo 1 ka waiwai paʻamau.
Ua hoʻohana ʻia ke awa asynchronous i kēlā me kēia manawa e hoʻonohonoho hou i ka paipu i nā '0' asynchronously i ka hoʻokomo ʻana i ka uaki.

Papa 6.

LPM_DIVIDE Nā Awa Hoʻopuka

inoa awa

Pono

wehewehe

quotient []

ʻAe

Hoʻopuka ʻikepili. Aia ka nui o ka puka puka ma ka LPM_WIDTHN

waiwai hoʻohālikelike.

noho []

ʻAe

Hoʻopuka ʻikepili. Aia ka nui o ka puka puka ma ka LPM_WIDTHD

waiwai hoʻohālikelike.

3.6. Parameter

Hōʻike ka papa ma lalo nei i nā ʻāpana no ka LPM_DIVIDE Intel FPGA IP core.

Ka inoa ʻāpana

ʻAno

Pono

wehewehe

LPM_WIDTHN

Integer

ʻAe

Hōʻike i nā laula o ka helu [] a

quotient [] nā awa. He 1 a 64 ka waiwai.

LPM_WIDTHD

Integer

ʻAe

Hōʻike i nā laula o ka denom [] a

noho [] nā awa. He 1 a 64 ka waiwai.

LPM_NREPRESENTATION LPM_DREPRESENTATION

kaula kaula

ʻAʻole

Hōʻailona hōʻailona o ka hoʻokomo helu.

KAUKAU ʻia nā waiwai a UNSIGNED. I keia

ua hoʻonohonoho ʻia ka ʻāpana iā SIGNED, ka mea hoʻokaʻawale

unuhi i ka helu helu [] e like me ka lua i kakau inoa ia

hoʻokō.

ʻAʻole

Hōʻailona hōʻailona o ka hoʻokomo denominator.

KAUKAU ʻia nā waiwai a UNSIGNED. I keia

ua hoʻonohonoho ʻia ka ʻāpana iā SIGNED, ka mea hoʻokaʻawale

unuhi i ka helu denom[] e like me ka lua o ka pūlima

hoʻokō.

LPM_TYPE

kaulahao

ʻAʻole

Hoʻomaopopo i ka waihona o parameterized

modules (LPM) inoa hui ma ka hoʻolālā VHDL

files (.vhd).

LPM_HINT

kaulahao

ʻAʻole

Ke hoʻomaka koke ʻoe i kahi waihona o

hana nā modules parameterized (LPM) i kahi

Hoʻolālā VHDL File (.vhd), pono ʻoe e hoʻohana i ka

LPM_HINT hoʻohālikelike e kuhikuhi i kahi Intel-

ʻāpana kikoʻī. No example: LPM_HINT

= “CHAIN_SIZE = 8,

ONE_INPUT_IS_CONSTANT = YES” Ka

ʻAʻole hoʻohana ʻia ka waiwai paʻamau.

LPM_REMAINDERPOSITIVE

kaulahao

ʻAʻole

ʻāpana kikoʻī Intel. Pono ʻoe e hoʻohana i ka

LPM_HINT hoʻohālikelike e kuhikuhi i ka

LPM_REMAINDERPOSITIVE ka palena i loko

Hoʻolālā VHDL files. He TRUE a FALSE paha nā waiwai.

Inā hoʻonoho ʻia kēia ʻāpana i TRUE, a laila ka

ʻoi aku ka nui o ka waiwai o ke koena [] awa

hoʻomau…

Intel FPGA Integer Arithmetic IP Cores User Guide 14

Hoʻouna Manaʻo

3. LPM_DIVIDE (Divider) Intel FPGA IP Core 683490 | 2020.10.05

Ka inoa ʻāpana

ʻAno

MAXIMIZE_SPEED

Integer

LPM_PIPELINE

Integer

INTENDED_DEVICE_FAMILY SKIP_BITS

Hui Pū ʻIa

Koi ʻia No
ʻAʻole ʻAʻole ʻAʻole

wehewehe
ʻoi a i ʻole like me ka ʻole. Inā hoʻonoho ʻia kēia ʻāpana i TRUE, a laila ʻo ka waiwai o ke koena [] awa he zero, a i ʻole ʻo ia ka hōʻailona like, maikaʻi a maikaʻi ʻole paha, me ka waiwai o ke awa helu. I mea e hōʻemi ai i ka ʻāpana a hoʻomaikaʻi i ka wikiwiki, manaʻo ʻo Intel e hoʻonohonoho i kēia ʻāpana i TRUE i nā hana kahi e pono ai ke koena a i ʻole he mea nui ʻole ke koena.
ʻāpana kikoʻī Intel. Pono ʻoe e hoʻohana i ka ʻāpana LPM_HINT e kuhikuhi i ka ʻāpana MAXIMIZE_SPEED ma ka hoʻolālā VHDL files. ʻO nā waiwai he [0..9]. Inā hoʻohana ʻia, hoʻāʻo ka polokalamu Intel Quartus Prime e hoʻopaʻa i kahi hiʻohiʻona kikoʻī o ka hana LPM_DIVIDE no ka wikiwiki ma mua o ka holo ʻana, a hoʻopau i ka hoʻonohonoho ʻana i ke koho loiloi Optimization Technique. Inā ʻaʻole i hoʻohana ʻia ʻo MAXIMIZE_SPEED, hoʻohana ʻia ka waiwai o ke koho Optimization Technique. Inā he 6 a ʻoi paha ka waiwai o MAXIMIZE_SPEED, hoʻoponopono ka Compiler i ka LPM_DIVIDE IP core no ka wikiwiki kiʻekiʻe ma o ka hoʻohana ʻana i nā kaulahao lawe; inā he 5 a i ʻole ka liʻiliʻi, hoʻokō ka mea hōʻuluʻulu i ka hoʻolālā me ka ʻole o nā kaulahao.
Hōʻike i ka helu o nā pōʻai uaki o ka latency e pili ana me ka quotient [] a koe [] mau pukana. Hōʻike ka waiwai o ka ʻole (0) ʻaʻole loaʻa ka latency, a ua hoʻomaka koke ʻia kahi hana hui maʻemaʻe. Inā haʻalele ʻia, ʻo ka waiwai paʻamau ʻo 0 (nonpipelined). ʻAʻole hiki iā ʻoe ke kuhikuhi i kahi waiwai no ka LPM_PIPELINE ʻoi aku ka kiʻekiʻe ma mua o LPM_WIDTHN.
Hoʻohana ʻia kēia ʻāpana no ke kumu hoʻohālike a me ka hoʻohālikelike ʻano. Hoʻopili ka mea hoʻoponopono hoʻoponopono i ka waiwai no kēia ʻāpana.
ʻAe i ka mahele ʻāpana hakina ʻoi aku ka maikaʻi e hoʻopaʻa pono i ka loiloi ma nā ʻāpana alakaʻi ma o ka hāʻawi ʻana i ka helu o ke alakaʻi GND i ka LPM_DIVIDE IP core. E wehewehe i ka helu o ke alakaʻi GND ma ka quotient output i kēia ʻāpana.

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 15

683490 | 2020.10.05 Hoʻouna Manaʻo

4. LPM_MULT (Multiplier) IP Core

Kiʻi 3.

Hoʻokomo ka LPM_MULT IP core i ka mea hoʻonui e hoʻonui i ʻelua mau helu helu helu komo e hana i kahi huahana ma ke ʻano he puka.

Hōʻike kēia kiʻi i nā awa no ka LPM_MULT IP core.

LPM_Nā Awa Nui

LPM_MULT uaki dataa[] hopena[] datab[] aclr/sclr clken
inst

Nā hiʻohiʻona ʻike pili ma ka ʻaoʻao 71

4.1. Nā hiʻohiʻona
Hāʻawi ka LPM_MULT IP core i kēia mau hiʻohiʻona: · Hoʻohua i kahi multiplier e hoʻonui i ʻelua mau helu helu komo · Kākoʻo i ka laula ʻikepili o 1 bits · Kākoʻo i ka hōʻike hōʻike hōʻike ʻana i kau inoa ʻole ʻia · Kākoʻo i ka ʻāpana a i ʻole ka wikiwiki wikiwiki · Kākoʻo i ka pipelining me ka configurable output latency · Hāʻawi i kahi koho no ka hoʻokō ʻana i ka hoʻoili hōʻailona kikohoʻe hoʻolaʻa (DSP)
block circuitry or logic elements (LEs) Nānā: Ke kūkulu ʻia nā mea hoʻonui i ʻoi aku ka nui ma mua o ka nui i kākoʻo maoli ʻia,
he hopena hana ia ma muli o ka hoʻokahe ʻana o nā poloka DSP. · Kākoʻo i ka asynchronous clear a me ka uaki hiki ke hoʻokomo i nā awa hoʻokomo · Kākoʻo i ke koho synchronous clear no nā polokalamu Intel Stratix 10, Intel Arria 10 a me Intel Cyclone 10 GX.

ISO 9001:2015 Kakau

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05
4.2. ʻO Verilog HDL Prototype
Aia ka prototype Verilog HDL ma ka Verilog Design File (.v) lpm.v i ka papa kuhikuhi edasynthesis.
module lpm_mult (hopena, dataa, datab, sum, clock, clken, aclr ) parameter lpm_type = “lpm_mult”; ka palena lpm_widtha = 1; ka palena lpm_widthb = 1; ka palena lpm_widths = 1; ka palena lpm_widthp = 1; hoʻohālikelike lpm_representation = “UNSIGNED”; palena lpm_pipeline = 0; parameter lpm_hint = “ʻAʻole hoʻohana ʻia”; uaki komo; komo clken; hoʻokomo aclr; hookomo [lpm_widtha-1:0] dataa; hookomo [lpm_widthb-1:0] datab; hookomo [lpm_widths-1:0] huina; hoʻopuka [lpm_widthp-1:0] hopena; hopemodule
4.3. Hōʻike Hui VHDL
Aia ka ʻōlelo hoʻolaha ʻāpana VHDL ma ka VHDL Design File (.vhd) LPM_PACK.vhd i ka waihona waihona vhdllpm.
ʻāpana LPM_MULT generic ( LPM_WIDTHA : kūlohelohe; LPM_WIDTHB : kūlohelohe; LPM_WIDTHS : kūlohelohe := 1; LPM_WIDTHP : kūlohelohe;
LPM_REPRESENTATION : string : = “Aʻole i hoʻopaʻa inoa ʻia”; LPM_PIPELINE : kūlohelohe := 0; LPM_TYPE: kaula : = L_MULT; LPM_HINT : string := “UNUSED”); awa (DATAA: ma std_logic_vector(LPM_WIDTHA-1 iho i ka 0); DATAB: ma std_logic_vector(LPM_WIDTHB-1 iho i ka 0); ACLR: ma std_logic:= '0'; CLOCK: ma std_logic:= '0'; CLKEN: ma std_logic : = '1'; SUM : i ka std_logic_vector(LPM_WIDTHS-1 a hiki i ka 0) := (NĀ 'A'E => '0' HUA: out std_logic_vector(LPM_WIDTHP-1 a hiki i ka 0)); mea hope;
4.4. Hōʻike VHDL LIBRARY_USE
ʻAʻole koi ʻia ka ʻōlelo hoʻolaha VHDL LIBRARY-USE inā hoʻohana ʻoe i ka VHDL Component Declaration.
HAAWINA lpm; E hoohana i lpm.lpm_components.all;

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 17

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

4.5. Nā hōʻailona

Papa 7.

LPM_MULT Nā hōʻailona hoʻokomo

inoa hōʻailona

Pono

wehewehe

ʻikepili []

ʻAe

Hoʻokomo ʻikepili.

No nā polokalamu Intel Stratix 10, Intel Arria 10, a me Intel Cyclone 10 GX, ʻo ka nui o ka hōʻailona hoʻokomo e pili ana i ka waiwai o ka laulā Dataa.

No nā mea kahiko a me Intel Cyclone 10 LP, pili ka nui o ka hōʻailona hoʻokomo i ka waiwai hoʻohālikelike LPM_WIDTHA.

datab []

ʻAe

Hoʻokomo ʻikepili.

No nā polokalamu Intel Stratix 10, Intel Arria 10, a me Intel Cyclone 10 GX, ʻo ka nui o ka hōʻailona hoʻokomo e hilinaʻi ʻia i ka waiwai o ka laulā Datab.

No nā mea kahiko a me Intel Cyclone 10 LP, pili ka nui o ka hōʻailona hoʻokomo

ma ka helu koho LPM_WIDTHB.

uaki

ʻAʻole

Hoʻokomo uaki no ka hoʻohana ʻana i ka pipeline.

No nā mea kahiko a me Intel Cyclone 10 LP, pono e ʻae ʻia ka hōʻailona uaki no nā waiwai LPM_PIPELINE ʻē aʻe ma mua o 0 (paʻamau).

No nā polokalamu Intel Stratix 10, Intel Arria 10, a me Intel Cyclone 10 GX, pono e ʻae ʻia ka hōʻailona uaki inā ʻokoʻa ka waiwai Latency ma mua o 1 (paʻamau).

clken

ʻAʻole

Hiki i ka uaki ke hoʻohana i ka pipeline. I ka manawa i hoʻokūpaʻaʻia ka hōʻailona clken kiʻekiʻe,ʻo ka

hana ʻia ka mea hoʻohui/unuhi. Ke haʻahaʻa ka hōʻailona, ʻaʻohe hana

hiki mai. Inā haʻalele ʻia, ʻo 1 ka waiwai paʻamau.

aclr sclr

ʻAʻole

Hoʻohana ʻia ka hōʻailona maʻemaʻe Asynchronous i kēlā me kēia manawa e hoʻihoʻi i ka pipeline i nā 0 a pau,

asynchronously i ka hōʻailona uaki. Hoʻomaka ka pipeline i kahi wehewehe ʻole (X)

pae noʻonoʻo. He kūlike nā huahana, akā ʻaʻole waiwai ʻole.

ʻAʻole

Hoʻohana ʻia ka hōʻailona maʻemaʻe i kēlā me kēia manawa e hoʻihoʻi i ka pipeline i nā 0 a pau,

synchronously i ka hōʻailona uaki. Hoʻomaka ka pipeline i kahi wehewehe ʻole (X)

pae noʻonoʻo. He kūlike nā huahana, akā ʻaʻole waiwai ʻole.

Papa 8.

LPM_MULT Nā hōʻailona puka

inoa hōʻailona

Pono

wehewehe

hopena []

ʻAe

Hoʻopuka ʻikepili.

No nā mea kahiko a me Intel Cyclone 10 LP, pili ka nui o ka hōʻailona hoʻopuka i ka waiwai hoʻohālikelike LPM_WIDTHP. Inā LPM_WIDTHP < max (LPM_WIDTHA + LPM_WIDTHB, LPM_WIDTHS) a i ʻole (LPM_WIDTHA + LPM_WIDTHS), aia nā LPM_WIDTHP MSB wale nō.

No Intel Stratix 10, Intel Arria 10 a me Intel Cyclone 10 GX, ʻo ka nui o nā hōʻailona hoʻopuka e pili ana i ka ʻāpana ākea o ka hopena.

4.6. Nā ʻāpana no Stratix V, Arria V, Cyclone V, a me Intel Cyclone 10 LP Devices

4.6.1. Tab General

Papa 9.

Tab Nui

ʻĀpana

Waiwai

Hoʻonohonoho hoʻonui

E hoʻonui i ka hoʻokomo 'dataa' me ka hoʻokomo 'datab'

Waiwai Paʻamau

wehewehe

E hoʻonui i ka hoʻokomo 'dataa' me ka hoʻokomo 'datab'

E koho i ka hoʻonohonoho i makemake ʻia no ka multiplier.
hoʻomau…

Intel FPGA Integer Arithmetic IP Cores User Guide 18

Hoʻouna Manaʻo

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

ʻĀpana
Pehea ka laula o ka 'dataa' hookomo? Pehea ka laula o ke komo 'datab'? Pehea e hoʻoholo ai i ka laulā o ka 'hopena' puka? Kaohi i ka laula

Waiwai
E hoʻonui i ka hoʻokomo 'dataa' iā ia iho (ka hana hoʻohālikelike)
1 - 256 mau ʻāpana

Waiwai Paʻamau

wehewehe

8 bit

E wehewehe i ka laula o ke awa dataa[].

1 - 256 mau ʻāpana

8 bit

E wehewehe i ka laula o ke awa datab[].

E helu 'akomi i ka laula E kaohi i ka laula
1 - 512 mau ʻāpana

Kahea 'akomi y helu i ka laula

E koho i ke ala i makemake ʻia e hoʻoholo i ka laulā o ka hopena[] awa.

16 bit

E wehewehe i ka laula o ka hopena[] awa.
E hoʻohana wale ʻia kēia waiwai inā koho ʻoe e hoʻopaʻa i ka laulā ma ke ʻano ʻano.

4.6.2. Nui 2 Tab

Papa 10. Nui 2 Tab

ʻĀpana

Waiwai

Hoʻokomo ʻikepili

He waiwai mau ka 'datab' input bus?

ʻAʻole ʻAe

ʻAno hoʻonui

ʻO ke ʻano o

Kakauinoa ole

makemake ʻoe i ka hoʻonui? Kaulima

Hoʻokō

He aha ka hoʻokō multiplier pono e hoʻohana ʻia?

E hoʻohana i ka hoʻokō paʻamau
E hoʻohana i ka circuitry multiplier i hoʻolaʻa ʻia (ʻAʻole i loaʻa no nā ʻohana āpau)
E hoʻohana i nā mea loiloi

Waiwai Paʻamau

wehewehe

ʻAʻole

E koho i ka ʻAe e kuhikuhi i ka waiwai mau o ka

kaʻa hoʻokomo 'datab', inā loaʻa.

Kakauinoa ole

E wehewehe i ke ʻano hōʻike no nā hoʻokomo dataa[] a me datab[].

E hoʻohana i ka ion implementat paʻamau

E koho i ke ala i makemake ʻia e hoʻoholo i ka laulā o ka hopena[] awa.

4.6.3. Paipai Paipu

Papa 11. Pipelining Tab

ʻĀpana

Makemake ʻoe e hoʻopili i ka No

hana?

ʻAe

Waiwai

E hana i kahi 'aclr'

—

awa asynchronous maopopo

Waiwai Paʻamau

wehewehe

ʻAʻole

E koho iā ʻAe e hiki ai ke hoʻopaʻa inoa pipeline i ka

ka mea hoʻonui a kuhikuhi i ka mea i makemake ʻia

ka lōʻihi o ka puka ʻana ma ka pōʻai uaki. E ho'ā ana i ka

Hoʻohui ka papa inoa pipeline i ka latency hou i ka

hoʻopuka.

Hoʻopaʻa ʻole ʻia

E koho i kēia koho e hiki ai i ke awa aclr ke hoʻohana i ka asynchronous clear no ka papa inoa pipeline.
hoʻomau…

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 19

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

ʻĀpana
E hana i ka uaki hiki 'clken'
Hoʻonui
He aha ke ʻano o ka loiloi āu e makemake ai?

Waiwai —
Wahi Holomua Paʻamau

Waiwai Paʻamau

wehewehe

Hoʻopaʻa ʻole ʻia

Hōʻike i ka uaki kiʻekiʻe ikaika e hiki ai i ke awa uaki o ka papa inoa paipu

Paʻamau

E wehewehe i ka hoʻonui ʻana i makemake ʻia no ka IP core.
E koho i ka Default no ka ʻae ʻana i ka polokalamu Intel Quartus Prime e hoʻoholo i ka loiloi maikaʻi loa no ke kumu IP.

4.7. Nā ʻāpana no Intel Stratix 10, Intel Arria 10, a me Intel Cyclone 10 GX Devices

4.7.1. Tab General

Papa 12. Tab Nui

ʻĀpana

Waiwai

Waiwai Paʻamau

wehewehe

ʻAno hoʻonohonoho multiplier
Nā Laulā ʻIkepili

E hoʻonui i ka hoʻokomo 'dataa' me ka hoʻokomo 'datab'
E hoʻonui i ka hoʻokomo 'dataa' iā ia iho (ka hana hoʻohālikelike)

E hoʻonui i ka hoʻokomo 'dataa' me ka hoʻokomo 'datab'

E koho i ka hoʻonohonoho i makemake ʻia no ka multiplier.

Laulā ʻikepili

1 - 256 mau ʻāpana

8 bit

E wehewehe i ka laula o ke awa dataa[].

Laulā ʻikepili

1 - 256 mau ʻāpana

8 bit

E wehewehe i ka laula o ke awa datab[].

Pehea e ʻike ʻia ai ka laulā o ka 'hopena' puka?

ʻAno

E helu 'akomi i ka laula
Kaohi i ka laula

Kahea 'akomi y helu i ka laula

E koho i ke ala i makemake ʻia e hoʻoholo i ka laulā o ka hopena[] awa.

Waiwai

1 - 512 mau ʻāpana

16 bit

E wehewehe i ka laula o ka hopena[] awa.
E hoʻohana wale ʻia kēia waiwai inā koho ʻoe e hoʻopaʻa i ka laulā ma ke ʻano ʻano.

Laulā hopena

1 - 512 mau ʻāpana

—

Hōʻike i ka laulā kūpono o ka hopena[] awa.

4.7.2. Nui 2 Tab

Papa 13. Nui 2 Tab

ʻĀpana

Hoʻokomo ʻikepili

He waiwai mau ka 'datab' input bus?

ʻAʻole ʻAe

Waiwai

Waiwai Paʻamau

wehewehe

ʻAʻole

E koho i ka ʻAe e kuhikuhi i ka waiwai mau o ka

kaʻa hoʻokomo 'datab', inā loaʻa.

hoʻomau…

Intel FPGA Integer Arithmetic IP Cores User Guide 20

Hoʻouna Manaʻo

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

ʻĀpana

Waiwai

Kekahi waiwai i oi aku mamua o 0

ʻAno hoʻonui

ʻO ke ʻano o

Kakauinoa ole

makemake ʻoe i ka hoʻonui? Kaulima

Kaila hoʻokō

He aha ka hoʻokō multiplier pono e hoʻohana ʻia?

E hoʻohana i ka hoʻokō paʻamau
E hoʻohana i ka circuitry multiplier i hoʻolaʻa ʻia
E hoʻohana i nā mea loiloi

Waiwai Paʻamau

wehewehe

E wehewehe i ka waiwai mau o ke awa datab[].

Kakauinoa ole

E wehewehe i ke ʻano hōʻike no nā hoʻokomo dataa[] a me datab[].

E hoʻohana i ka ion implementat paʻamau

E koho i ke ala i makemake ʻia e hoʻoholo i ka laulā o ka hopena[] awa.

4.7.3. Paipaipa

Papa 14. Pipelining Tab

ʻĀpana

Waiwai

Makemake ʻoe e hoʻopili i ka hana?

Paipu

ʻAʻole ʻAe

ʻAno hōʻailona hoʻomaʻemaʻe Latency

Kekahi waiwai i oi aku mamua o 0.
ʻAʻohe ACLR SCLR

E hana i ka uaki 'clken'

—

hiki i ka uaki

He aha ke ʻano o ka loiloi āu e makemake ai?

ʻAno

Wahi Holomua Paʻamau

Waiwai Paʻamau

wehewehe

ʻAʻole 1 ʻAʻole
—

E koho iā ʻAe e hiki ai ke hoʻopaʻa inoa pipeline i ka hoʻopuka o ka mea hoʻonui. ʻO ka ʻae ʻana i ka papa inoa pipeline e hoʻohui i ka latency hou i ka puka.
E wehewehe i ka latency puka i makemake ʻia ma ka pōʻai uaki.
E wehewehe i ke ʻano o ka hoʻoponopono hou ʻana no ka papa inoa pipeline. E koho ʻAʻole inā ʻaʻole ʻoe e hoʻohana i kekahi papa inoa pipeline. E koho iā ACLR e hoʻohana i ka asynchronous clear no ka papa inoa paipu. E hana ana kēia i ke awa ACLR. E koho iā SCLR e hoʻohana i ka synchronous clear no ka papa inoa pipeline. E hana kēia i ka port SCLR.
Hōʻike i ka uaki kiʻekiʻe ikaika e hiki ai i ke awa uaki o ka papa inoa paipu

Paʻamau

E wehewehe i ka hoʻonui ʻana i makemake ʻia no ka IP core.
E koho i Default no ka ʻae ʻana i ka polokalamu Intel Quartus Prime e hoʻoholo i ka optimization maikaʻi loa no ke kumu IP.

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 21

683490 | 2020.10.05 Hoʻouna Manaʻo

5. LPM_ADD_SUB (mea hoʻohui/hōʻemi)

Kiʻi 4.

ʻO ka LPM_ADD_SUB IP core ka mea hiki iā ʻoe ke hoʻokomo i kahi mea hoʻohui a i ʻole ka mea unuhi e hoʻohui a unuhi i nā pūʻulu ʻikepili e hana ai i kahi puka i loaʻa ka huina a i ʻole ka ʻokoʻa o nā waiwai hoʻokomo.

Hōʻike kēia kiʻi i nā awa no ka LPM_ADD_SUB IP core.

Nā Awa LPM_ADD_SUB

LPM_ADD_SUB add_sub cin

ʻikepili []

uaki clken datab[] aclr

hopena[] overflow cout

inst

5.1. Nā hiʻohiʻona
Hāʻawi ka LPM_ADD_SUB IP core i kēia mau hiʻohiʻona: · Hoʻopuka i ka mea hoʻohui, subtractor, a me ka mea hoʻohui / subtractor hiki ke hoʻonohonoho pono.
nā hana. · Kākoʻo i ka laulā ʻikepili o 1 bits. · Kākoʻo i ka hōʻike hōʻike ʻikepili e like me ka pūlima a me ka inoa ʻole. · Kākoʻo i ka lawe ʻana i loko (borrow-out), asynchronous clear, a hiki i ka uaki
nā awa hoʻokomo. · Kākoʻo i ka lawe ʻana i waho (borrow-in) a me nā awa puka puka. · Hāʻawi i kekahi o nā kaʻa ʻikepili hoʻokomo i kahi mau. · Kākoʻo pipelining me configurable output latency.

ISO 9001:2015 Kakau

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05
5.2. ʻO Verilog HDL Prototype
Aia ka prototype Verilog HDL ma ka Verilog Design File (.v) lpm.v i ka papa kuhikuhi edasynthesis.
module lpm_add_sub (hopena, cout, overflow,add_sub, cin, dataa, datab, clock, clken, aclr ); hoʻohālikelike lpm_type = “lpm_add_sub”; ka palena lpm_width = 1; parameter lpm_direction = “ʻAʻole hoʻohana ʻia”; parameter lpm_representation = “KAUKAU”; palena lpm_pipeline = 0; parameter lpm_hint = “ʻAʻole hoʻohana ʻia”; hookomo [lpm_width-1:0] dataa, datab; hoʻokomo add_sub, cin; uaki komo; komo clken; hoʻokomo aclr; puka [lpm_width-1:0] hopena; output cout, overflow; hopemodule
5.3. Hōʻike Hui VHDL
Aia ka ʻōlelo hoʻolaha ʻāpana VHDL ma ka VHDL Design File (.vhd) LPM_PACK.vhd i ka waihona waihona vhdllpm.
ʻāpana LPM_ADD_SUB maʻamau (LPM_WIDTH : kūlohelohe;
LPM_DIRECTION : kaula : = “UNUSED”; LPM_REPRESENTATION: string : = “KAUKAU”; LPM_PIPELINE : kūlohelohe := 0; LPM_TYPE : kaula : = L_ADD_SUB; LPM_HINT : string := “UNUSED”); awa (DATAA: ma std_logic_vector(LPM_WIDTH-1 iho i ka 0); DATAB: ma std_logic_vector(LPM_WIDTH-1 iho i ka 0); ACLR: ma std_logic:= '0'; CLOCK: ma std_logic:= '0'; CLKEN: ma std_logic : = '1' ; mea hope;
5.4. Hōʻike VHDL LIBRARY_USE
ʻAʻole koi ʻia ka ʻōlelo hoʻolaha VHDL LIBRARY-USE inā hoʻohana ʻoe i ka VHDL Component Declaration.
HAAWINA lpm; E hoohana i lpm.lpm_components.all;
5.5. Awa
Hoʻopuka nā papa ma lalo nei i nā awa hoʻokomo a me nā puka puka no ka LPM_ADD_SUB IP core.

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 23

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05

Papa 15. LPM_ADD_SUB Nā Awa Koho IP

inoa awa

Pono

wehewehe

cin

ʻAʻole

Lawe i loko o ka ʻāpana haʻahaʻa. No nā hana hoʻohui, ʻo ka waiwai paʻamau he 0. No ka

nā hana unuhi, ʻo ka waiwai paʻamau ʻo 1.

ʻikepili []

ʻAe

Hoʻokomo ʻikepili. ʻO ka nui o ke awa hoʻokomo e pili ana i ka waiwai hoʻohālikelike LPM_WIDTH.

datab []

ʻAe

Hoʻokomo ʻikepili. ʻO ka nui o ke awa hoʻokomo e pili ana i ka waiwai hoʻohālikelike LPM_WIDTH.

add_sub

ʻAʻole

ʻO ke awa hoʻokomo koho e hiki ai ke hoʻololi ikaika ma waena o ka mea hoʻohui a me ka subtractor

nā hana. Inā hoʻohana ʻia ka ʻāpana LPM_DIRECTION, ʻaʻole hiki ke hoʻohana ʻia ka add_sub. Ina

waiho ʻia, ʻo ka waiwai paʻamau ʻo ADD. Manaʻo ʻo Intel e hoʻohana ʻoe i ka

LPM_DIRECTION hoʻohālikelike e kuhikuhi i ka hana o ka hana LPM_ADD_SUB,

ma mua o ka hāʻawi ʻana i kahi mea mau i ka add_sub port.

uaki

ʻAʻole

Hoʻokomo no ka hoʻohana ʻana i ka pipeline. Hāʻawi ke awa uaki i ka hoʻokomo uaki no kahi pipelined

hana. No nā waiwai LPM_PIPELINE ʻē aʻe ma mua o 0 (paʻamau), pono ke awa o ka uaki

hiki.

clken

ʻAʻole

Hiki i ka uaki ke hoʻohana i ka pipeline. I ka wā i hoʻokiʻekiʻe ʻia ka awa clken, ʻo ka mea hoʻohui /

lawe ʻia ka hana unuhi. Ke haʻahaʻa ka hōʻailona, ʻaʻohe hana. Ina

haʻalele ʻia, ʻo 1 ka waiwai paʻamau.

aclr

ʻAʻole

Asynchronous maopopo no ka hoʻohana ʻana i ka pipelined. Hoʻomaka ka pipeline i kahi wehewehe ʻole (X)

pae noʻonoʻo. Hiki ke hoʻohana ʻia ke awa aclr i kēlā me kēia manawa e hoʻonohonoho hou i ka pipeline i nā 0s āpau,

asynchronously i ka hōʻailona uaki.

Papa 16. LPM_ADD_SUB IP Core Output Ports

inoa awa

Pono

wehewehe

hopena []

ʻAe

Hoʻopuka ʻikepili. Aia ka nui o ka puka puka ma ka LPM_WIDTH parameter

waiwai.

cout

ʻAʻole

Ka lawe ʻana i waho (hōʻaiʻē i loko) o ka bit nui loa (MSB). He kino ko ke awa cout

ka wehewehe ʻana e like me ka lawe ʻana i waho (borrow-in) o ka MSB. ʻIke ʻia ke awa cout

kahe nui ma nā hana UNSIGNED. Ke hana nei ke awa cout ma ke ano like no

KAUKAU a UNSIGNED hana.

e kahe ana

ʻAʻole

ʻO ka hoʻokuʻu ʻana o ka overflow koho. ʻO ke awa overflow he wehewehe kino e like me

ka XOR o ka lawe ʻana i ka MSB me ka lawe ʻana o ka MSB. ʻO ke awa kahe nui

ʻōlelo ʻia inā ʻoi aku ka hopena ma mua o ka pololei i loaʻa, a hoʻohana wale ʻia i ka wā o ka

LPM_REPRESENTATION ua hoailona ia.

5.6. Parameter

Hōʻike ka papa ʻaina i nā ʻāpana kumu LPM_ADD_SUB IP.

Papa 17. LPM_ADD_SUB IP Koko'o Ko'o

Ka Inoa LPM_WIDTH

ʻAno huinahelu

Pono ʻAe

wehewehe
Hōʻike i nā laula o nā awa dataa[], datab[], a me ka hopena[].

LPM_DIRECTION

kaulahao

ʻAʻole

ʻO nā waiwai he ADD, SUB, a me UNUSED. Inā haʻalele ʻia, ʻo DEFAULT ka waiwai paʻamau, nāna e kuhikuhi i ka ʻāpana e lawe i kona waiwai mai ka add_sub port. ʻAʻole hiki ke hoʻohana ʻia ke awa add_sub inā hoʻohana ʻia ʻo LPM_DIRECTION. Manaʻo ʻo Intel iā ʻoe e hoʻohana i ka LPM_DIRECTION parameter e kuhikuhi i ka hana o ka hana LPM_ADD_SUB, ma mua o ka hāʻawi ʻana i kahi mau i ka add_sub port.
hoʻomau…

Intel FPGA Integer Arithmetic IP Cores User Guide 24

Hoʻouna Manaʻo

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05

Ka inoa ʻāpana LPM_REPRESENTATION LPM_PIPELINE LPM_HINT LPM_TYPE ONE_INPUT_IS_CONSTANT MAXIMIZE_SPEED
INTENDED_DEVICE_FAMILY

E ʻano ʻano hui pū ʻia
kaulahao

Pono ʻAʻole ʻAʻole ʻAʻole ʻAʻole
ʻAʻole

wehewehe
Hōʻike i ke ʻano o ka hoʻohui i hana ʻia. KAUKAU ʻia nā waiwai a UNSIGNED. Inā haʻalele ʻia, ua KAUKAU ʻia ka waiwai paʻamau. Ke hoʻonoho ʻia kēia ʻāpana iā SIGNED, wehewehe ka mea hoʻohui/subtractor i ka hoʻokomo ʻikepili e like me ka hoʻokō ʻana o ʻelua.
Hōʻike i ka helu o nā pōʻaiapuni o ka uaki i pili me ka hopena[] puka. Hōʻike ka waiwai o ka ʻole (0) ʻaʻohe latency, a e hoʻomaka koke ʻia kahi hana hoʻohui maʻemaʻe. Inā haʻalele ʻia, ʻo 0 ka waiwai paʻamau (ʻaʻole i hoʻopaʻa ʻia).
Hiki iā ʻoe ke kuhikuhi i nā ʻāpana kikoʻī Intel i ka hoʻolālā VHDL files (.vhd). ʻO UNUSED ka waiwai paʻamau.
Hoʻomaopopo i ka waihona o nā modules parameterized (LPM) inoa hui ma ka hoʻolālā VHDL files.
ʻāpana kikoʻī Intel. Pono ʻoe e hoʻohana i ka ʻāpana LPM_HINT e kuhikuhi i ka ʻāpana ONE_INPUT_IS_CONSTANT ma ka hoʻolālā VHDL files. ʻO nā waiwai he YES, NO, a UNUSED. Hāʻawi i ka loiloi ʻoi aku ka maikaʻi inā paʻa kahi hoʻokomo. Inā haʻalele ʻia, ʻo ka waiwai paʻamau ʻo NO.
ʻāpana kikoʻī Intel. Pono ʻoe e hoʻohana i ka ʻāpana LPM_HINT e kuhikuhi i ka ʻāpana MAXIMIZE_SPEED ma ka hoʻolālā VHDL files. Hiki iā ʻoe ke kuhikuhi i kahi waiwai ma waena o 0 a me 10. Inā hoʻohana ʻia, hoʻāʻo ka polokalamu Intel Quartus Prime e hoʻopaʻa i kahi kikoʻī kikoʻī o ka hana LPM_ADD_SUB no ka wikiwiki ma mua o ka holo ʻana, a overrides i ka hoʻonohonoho ʻana o ka Optimization Technique logic koho. Inā ʻaʻole i hoʻohana ʻia ʻo MAXIMIZE_SPEED, hoʻohana ʻia ka waiwai o ke koho Optimization Technique. Inā ʻo ka hoʻonohonoho ʻana no MAXIMIZE_SPEED he 6 a ʻoi aku paha, hoʻonohonoho ka Compiler i ka LPM_ADD_SUB IP core no ka wikiwiki kiʻekiʻe me ka hoʻohana ʻana i nā kaulahao lawe; inā ʻo 5 a i ʻole ka liʻiliʻi o ka hoʻonohonoho, hoʻokō ka Compiler i ka hoʻolālā me ka ʻole o nā kaulahao lawe. Pono e kuhikuhi ʻia kēia ʻāpana no nā polokalamu Cyclone, Stratix, a me Stratix GX wale nō ke hoʻohana ʻole ʻia ke awa add_sub.
Hoʻohana ʻia kēia ʻāpana no ke kumu hoʻohālike a me ka hoʻohālikelike ʻano. Hoʻopili ka mea hoʻoponopono hoʻoponopono i ka waiwai no kēia ʻāpana.

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 25

683490 | 2020.10.05 Hoʻouna Manaʻo

6. LPM_COMPARE (mea hoʻohālikelike)

Kiʻi 5.

Hoʻohālikelike ka LPM_COMPARE IP core i ka waiwai o ʻelua pūʻulu ʻikepili e hoʻoholo ai i ka pilina ma waena o lākou. Ma kāna ʻano maʻalahi, hiki iā ʻoe ke hoʻohana i kahi puka kūʻokoʻa-OR e hoʻoholo ai inā like nā ʻāpana ʻelua o ka ʻikepili.

Hōʻike kēia kiʻi i nā awa no ka LPM_COMPARE IP core.

Nā Awa LPM_COMPARE

LPM_COMPARE

clken

alb

aeb

ʻikepili []

agb

datab []

makahikib

uaki

aneb

aclr

aleb

inst

6.1. Nā hiʻohiʻona
Hāʻawi ka LPM_COMPARE IP core i kēia mau hiʻohiʻona: · Hoʻokumu i kahi hana hoʻohālikelike e hoʻohālikelike i ʻelua pūʻulu ʻikepili · Kākoʻo i ka laulā ʻikepili o 1 bits · Kākoʻo i ke ʻano hōʻike hōʻike ʻikepili e like me ka pūlima a me ka hoʻopaʻa inoa ʻole ʻia · Hoʻopuka i nā ʻano huahana penei:
— alb (ʻoi aku ka liʻiliʻi o ka hoʻokomo A ma mua o ka hoʻokomo B) - aeb (ʻoi aku ka nui o ka hoʻokomo A me ka hoʻokomo B) - agb (ʻoi aku ka nui o ka hoʻokomo A ma mua o ka hoʻokomo B) - ageb (ʻoi aku ka nui o ka hoʻokomo A ma mua a i ʻole ka like me ka hoʻokomo B) - aneb ( ʻAʻole like ka hoʻokomo A me ka hoʻokomo B) — aleb (ʻoi aku ka liʻiliʻi o ka hoʻokomo A ma mua o a i ʻole ka like me ka hoʻokomo B) · Kākoʻo i ke koho asynchronous clear a hiki i ka uaki ke hoʻokomo i nā awa hoʻokomo · Hāʻawi i ka datab [] hoʻokomo i kahi mau · Kākoʻo i ka pipelining me ka latency output configurable

ISO 9001:2015 Kakau

6. LPM_COMPARE (Hoʻohālikelike) 683490 | 2020.10.05
6.2. ʻO Verilog HDL Prototype
Aia ka prototype Verilog HDL ma ka Verilog Design File (.v) lpm.v i ka papa kuhikuhi edasynthesis.
module lpm_compare ( alb, aeb, agb, aleb, aneb, ageb, dataa, datab, uaki, clken, aclr ); parameter lpm_type = “lpm_compare”; ka palena lpm_width = 1; hoʻohālikelike lpm_representation = “UNSIGNED”; palena lpm_pipeline = 0; parameter lpm_hint = “ʻAʻole hoʻohana ʻia”; hookomo [lpm_width-1:0] dataa, datab; uaki komo; komo clken; hoʻokomo aclr; puka alb, aeb, agb, aleb, aneb, ageb; hopemodule
6.3. Hōʻike Hui VHDL
Aia ka ʻōlelo hoʻolaha ʻāpana VHDL ma ka VHDL Design File (.vhd) LPM_PACK.vhd i ka waihona waihona vhdllpm.
ʻāpana LPM_COMPARE maʻamau (LPM_WIDTH : kūlohelohe;
LPM_REPRESENTATION : string : = “Aʻole i hoʻopaʻa inoa ʻia”; LPM_PIPELINE : kūlohelohe := 0; LPM_TYPE: kaula : = L_COMPARE; LPM_HINT : string := “UNUSED”); awa (DATAA: ma std_logic_vector(LPM_WIDTH-1 iho i ka 0); DATAB: ma std_logic_vector(LPM_WIDTH-1 iho i ka 0); ACLR: ma std_logic:= '0'; CLOCK: ma std_logic:= '0'; CLKEN: ma std_logic : = '1' ; mea hope;
6.4. Hōʻike VHDL LIBRARY_USE
ʻAʻole koi ʻia ka ʻōlelo hoʻolaha VHDL LIBRARY-USE inā hoʻohana ʻoe i ka VHDL Component Declaration.
HAAWINA lpm; E hoohana i lpm.lpm_components.all;
6.5. Awa
Hoʻopuka nā papa ma lalo nei i nā awa hoʻokomo a me nā puka puka no ka LMP_COMPARE IP core.

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 27

6. LPM_COMPARE (Hoʻohālikelike) 683490 | 2020.10.05

Papa 18. LPM_COMPARE IP kumu hookomo awa

inoa awa

Pono

wehewehe

ʻikepili []

ʻAe

Hoʻokomo ʻikepili. ʻO ka nui o ke awa hoʻokomo e pili ana i ka waiwai hoʻohālikelike LPM_WIDTH.

datab []

ʻAe

Hoʻokomo ʻikepili. ʻO ka nui o ke awa hoʻokomo e pili ana i ka waiwai hoʻohālikelike LPM_WIDTH.

uaki

ʻAʻole

Hoʻokomo uaki no ka hoʻohana ʻana i ka pipeline. Hāʻawi ke awa uaki i ka hoʻokomo uaki no kahi pipelined

hana. No nā waiwai LPM_PIPELINE ʻē aʻe ma mua o 0 (paʻamau), pono ke awa o ka uaki

hiki.

clken

ʻAʻole

Hiki i ka uaki ke hoʻohana i ka pipeline. I ka wa i oleloia ai ke awa clken kiekie, ka

hana hoʻohālikelike. Ke haʻahaʻa ka hōʻailona, ʻaʻohe hana. Ina

haʻalele ʻia, ʻo 1 ka waiwai paʻamau.

aclr

ʻAʻole

Asynchronous maopopo no ka hoʻohana ʻana i ka pipelined. Hoʻomaka ka pipeline i kahi loina maopopo ʻole (X).

pae. Hiki ke hoʻohana ʻia ke awa aclr i kēlā me kēia manawa e hoʻonohonoho hou i ka pipeline i nā 0s āpau,

asynchronously i ka hōʻailona uaki.

Papa 19. LPM_COMPARE IP kumu puka puka

inoa awa

Pono

wehewehe

alb

ʻAʻole

awa puka no ka mea hoohalike. Manaʻo ʻia inā ʻoi aku ka liʻiliʻi o ka hoʻokomo A ma mua o ka hoʻokomo B.

aeb

ʻAʻole

awa puka no ka mea hoohalike. Manaʻo ʻia inā like ka hoʻokomo A me ka hoʻokomo B.

agb

ʻAʻole

awa puka no ka mea hoohalike. Manaʻo ʻia inā ʻoi aku ka nui o ka hoʻokomo A ma mua o ka hoʻokomo B.

makahikib

ʻAʻole

awa puka no ka mea hoohalike. Manaʻo ʻia inā ʻoi aku ka nui o ka hoʻokomo A ma mua o a i ʻole like me ka hoʻokomo

aneb

ʻAʻole

awa puka no ka mea hoohalike. Manaʻo ʻia inā ʻaʻole like ka hoʻokomo A me ka hoʻokomo B.

aleb

ʻAʻole

awa puka no ka mea hoohalike. Manaʻo ʻia inā ʻoi aku ka liʻiliʻi o ka hoʻokomo A ma mua a i ʻole like me ka hoʻokomo B.

6.6. Parameter

Hōʻike ka papa ma lalo nei i nā ʻāpana no ka LPM_COMPARE IP core.

Papa 20. LPM_COMPARE IP kumu

Ka inoa ʻāpana

ʻAno

Pono

LPM_WIDTH

Integer ʻAe

LPM_REPRESENTATION

kaulahao

ʻAʻole

LPM_PIPELINE

Integer No

LPM_HINT

kaulahao

ʻAʻole

wehewehe
Hōʻike i nā laula o nā awa dataa[] a me datab[].
Hōʻike i ke ʻano o ka hoʻohālikelike i hana ʻia. KAUKAU ʻia nā waiwai a UNSIGNED. Inā haʻalele ʻia, UNSIGNED ka waiwai paʻamau. Ke hoʻonoho ʻia kēia waiwai hoʻohālikelike iā SIGNED, wehewehe ka mea hoʻohālikelike i ka hoʻokomo ʻikepili e like me ka hoʻohui ʻana o ʻelua.
Hōʻike i ka helu o nā pōʻai uaki o ka latency e pili ana me ka alb, aeb, agb, ageb, aleb, a i ʻole aneb output. Hōʻike ka waiwai o ka ʻole (0) ʻaʻohe latency, a e hoʻomaka koke ʻia kahi hana hoʻohui maʻemaʻe. Inā haʻalele ʻia, ʻo ka waiwai paʻamau ʻo 0 (nonpipelined).
Hiki iā ʻoe ke kuhikuhi i nā ʻāpana kikoʻī Intel i ka hoʻolālā VHDL files (.vhd). ʻO UNUSED ka waiwai paʻamau.
hoʻomau…

Intel FPGA Integer Arithmetic IP Cores User Guide 28

Hoʻouna Manaʻo

6. LPM_COMPARE (Hoʻohālikelike) 683490 | 2020.10.05
Ka inoa ʻāpana LPM_TYPE INTENDED_DEVICE_FAMILY
ONE_INPUT_IS_CONSTANT

E hoʻokomo i ke kaula
kaulahao

Pono ʻAʻole No
ʻAʻole

wehewehe
Hoʻomaopopo i ka waihona o nā modules parameterized (LPM) inoa hui ma ka hoʻolālā VHDL files.
Hoʻohana ʻia kēia ʻāpana no ke kumu hoʻohālike a me ka hoʻohālikelike ʻano. Hoʻopili ka mea hoʻoponopono hoʻoponopono i ka waiwai no kēia ʻāpana.
ʻāpana kikoʻī Intel. Pono ʻoe e hoʻohana i ka ʻāpana LPM_HINT e kuhikuhi i ka ʻāpana ONE_INPUT_IS_CONSTANT ma ka hoʻolālā VHDL files. ʻO nā waiwai he YES, NO, a i ʻole UNUSED. Hāʻawi i ka ʻoi aku ka maikaʻi inā paʻa ka hoʻokomo. Inā haʻalele ʻia, ʻo ka waiwai paʻamau ʻo NO.

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 29

683490 | 2020.10.05 Hoʻouna Manaʻo

7. ALTECC (Ka helu hoʻoponopono hewa: Encoder/Decoder) IP Core

Kiʻi 6.

Hāʻawi ʻo Intel i ka ALTECC IP core e hoʻokō i ka hana ECC. ʻIke ʻo ECC i nā ʻikepili hewa i loaʻa ma ka ʻaoʻao hoʻokipa i ka wā o ka lawe ʻana i ka ʻikepili. ʻOi aku ka maikaʻi o kēia ʻano hoʻoponopono hewa no nā kūlana i loaʻa ai nā hewa ma ke ʻano ma mua o ka pohā.

ʻIke ka ECC i nā hewa ma o ke kaʻina o ka hoʻopili ʻana i ka ʻikepili a me ka decoding. No exampa, ke hoʻohana ʻia ka ECC i kahi palapala hoʻouna, hoʻopili ʻia ka ʻikepili i heluhelu ʻia mai ke kumu ma mua o ka hoʻouna ʻia ʻana i ka mea lawe. ʻO ka huaʻōlelo (huaʻōlelo code) mai ka encoder aia nā ʻikepili maka i hoʻopili ʻia me ka helu o nā ʻāpana parity. ʻO ka helu pololei o nā bit parity i hoʻopili ʻia ma muli o ka helu o nā bits i ka ʻikepili hoʻokomo. Hoʻouna ʻia ka huaʻōlelo code i hana ʻia i kahi e hele ai.

Loaʻa i ka mea hoʻokipa ka huaʻōlelo code a hoʻokaʻawale iā ia. Hoʻoholo ka ʻike i loaʻa e ka decoder inā ʻike ʻia kahi hewa. ʻIke ka decoder i nā hewa hoʻokahi-bit a ʻelua-bit, akā hiki ke hoʻoponopono i nā hewa hoʻokahi-bit wale nō i ka ʻikepili i hewa. ʻO kēia ʻano ECC he hoʻoponopono hewa hoʻokahi ʻelua ʻike hewa (SECDED).

Hiki iā ʻoe ke hoʻonohonoho i nā hana encoder a me decoder o ka ALTECC IP core. Hoʻopili ʻia ka hoʻokomo ʻikepili i ka encoder e hana i kahi huaʻōlelo code i hui pū ʻia o ka hoʻokomo ʻikepili a me nā ʻāpana parity i hana ʻia. Hoʻouna ʻia ka huaʻōlelo code i hana ʻia i ka module decoder no ka hoʻokaʻawale ʻana ma mua o ka hiki ʻana i kona poloka huakaʻi. Hoʻokumu ka decoder i kahi vector syndrome e hoʻoholo ai inā he hewa i ka huaʻōlelo code i loaʻa. Hoʻoponopono ka decoder i ka ʻikepili inā loaʻa ka hewa hoʻokahi-bit mai nā bit data. ʻAʻohe hōʻailona i hōʻailona ʻia inā loaʻa ka hewa hoʻokahi-bit mai nā ʻāpana parity. He mau hōʻailona hae ka decoder e hōʻike i ke kūlana o ka ʻikepili i loaʻa a me ka hana i hana ʻia e ka decoder, inā he.

Hōʻike nā kiʻi ma lalo nei i nā awa no ka ALTECC IP core.

Nā Awa Encoder ALTECC

ALTECC_ENCODER

ʻikepili []

q[]

uaki

aclr

inst

ISO 9001:2015 Kakau

7. ALTECC (Kāhea Hoʻoponopono Hapa: Encoder/Decoder) IP Core 683490 | 2020.10.05

Kii 7. ALTECC Decoder Awa

ALTECC_DECODER

ʻikepili [] uaki

q [] ʻike ʻia err_corrected
err_fatal

aclr

inst

7.1. Nā hiʻohiʻona ALTECC Encoder

Hāʻawi ka ALTECC encoder IP core i kēia mau hiʻohiʻona: · Hana i ka hoʻopili ʻana i ka ʻikepili me ka hoʻohana ʻana i ka Hamming Coding scheme · Kākoʻo i ka laulā ʻikepili o 2 bits · Kākoʻo i ke ʻano hōʻike hōʻike ʻikepili i kau inoa ʻia a ʻaʻole i hoʻopaʻa inoa ʻia · Kākoʻo pipelining me ka latency output o hoʻokahi a i ʻole ʻelua mau pōʻai uaki. asynchronous maopopo a hiki i ka uaki ke awa

Lawe ka ALTECC encoder IP core a hoʻopili i ka ʻikepili me ka hoʻohana ʻana i ka papahana Hamming Coding. Na ka Hamming Coding scheme e loaʻa nā ʻāpana parity a hoʻopili iā lākou i ka ʻikepili kumu e hana ai i ka huaʻōlelo code output. ʻO ka helu o nā bit parity i hoʻopili ʻia ma muli o ka laulā o ka ʻikepili.

Hōʻike ka papa ma lalo nei i ka helu o nā ʻāpana parity i hoʻopili ʻia no nā pae like ʻole o nā laula ʻikepili. Hōʻike ka kolamu Total Bits i ka huina o nā bit data hoʻokomo a me nā bit parity i hoʻohui ʻia.

Papa 21.

Ka helu o nā parity bits a me ka huaʻōlelo code e like me ka laula ʻikepili

Laulā ʻIkepili

Ka helu o nā Bits Parity

Huina Bits (Hu'ōlelo Code)

2-4

3+1

6-8

5-11

4+1

10-16

12-26

5+1

18-32

27-57

6+1

34-64

58-64

7+1

66-72

Hoʻohana ka derivation bit parity i ka nānā like-parity. Hoʻopili ʻia ka 1 bit (hōʻike ʻia ma ka pākaukau me +1) i nā ʻāpana parity e like me ka MSB o ka huaʻōlelo code. Hoʻomaopopo kēia i ka helu ʻana o ka huaʻōlelo code i nā helu 1. No exampe, inā he 4 mau ʻāpana ka laula ʻikepili, ua hoʻopili ʻia nā ʻāpana parity 4 i ka ʻikepili e lilo i huaʻōlelo code me ka huina o 8 mau ʻāpana. Inā loaʻa i nā 7 bit mai ka LSB o ka huaʻōlelo code 8-bit ka helu ʻē aʻe o ka 1, ʻo ka 8th bit (MSB) o ka huaʻōlelo code ʻo ia ka 1 e hana ana i ka huina o nā 1 ma ka huaʻōlelo code even.
Hōʻike kēia kiʻi i ka huaʻōlelo code i hana ʻia a me ka hoʻonohonoho ʻana o nā bit parity a me nā bit data i loko o kahi hoʻokomo ʻikepili 8-bit.

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 31

7. ALTECC (Kāhea Hoʻoponopono Hapa: Encoder/Decoder) IP Core 683490 | 2020.10.05

Kiʻi 8.

Hoʻonohonoho ʻia ʻo Parity Bits a me Data Bits ma kahi huaʻōlelo 8-Bit Generated Code Word

MSB

LSB

4 mau ʻāpana parity

4 mau ʻikepili

ʻO ka ALTECC encoder IP core e ʻae wale i nā laula komo o 2 a 64 mau bits i ka manawa hoʻokahi. ʻO nā laula hoʻokomo o 12 bits, 29 bits, a me 64 bits, i kūpono i nā polokalamu Intel, e hoʻopuka i nā huahana o 18 bits, 36 bits, a me 72 bits. Hiki iā ʻoe ke hoʻomalu i ka palena koho bits i ka hoʻoponopono hoʻoponopono.

7.2. Verilog HDL Prototype (ALTECC_ENCODER)
Aia ka prototype Verilog HDL ma ka Verilog Design File (.v) lpm.v i ka papa kuhikuhi edasynthesis.
module altecc_encoder #( parameter intended_device_family = "hoʻohana ʻole", parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = "altecc_encoder", ʻāpana lpm_hint = "ʻaʻole hoʻohana ʻia") ( uea hoʻokomo aclr, uaki uea hoʻokomo uaki uea, uea hookomo [width_dataword-1:0] ikepili, uea puka [width_codeword-1:0] q); hopemodule

7.3. Verilog HDL Prototype (ALTECC_DECODER)
Aia ka prototype Verilog HDL ma ka Verilog Design File (.v) lpm.v i ka papa kuhikuhi edasynthesis.
module altecc_decoder #( parameter intended_device_family = "ʻaʻole i hoʻohana ʻia", parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = "altecc_decoder", parameter lpm_hint = "ʻaʻole i hoʻohana ʻia") ( uea hoʻokomo aclr, uaki uea hoʻokomo uaki uea, uea hookomo [width_codeword-1:0] ikepili, uea puka err_corrected, uea puka err_detected, uea puka err_fatal, uea puka [width_dataword-1:0] q); hopemodule

Intel FPGA Integer Arithmetic IP Cores User Guide 32

Hoʻouna Manaʻo

7. ALTECC (Kāhea Hoʻoponopono Hapa: Encoder/Decoder) IP Core 683490 | 2020.10.05
7.4. Hōʻike Hui VHDL (ALTECC_ENCODER)
Aia ka ʻōlelo hoʻolaha ʻāpana VHDL ma ka VHDL Design File (.vhd) altera_mf_components.vhd ma ka waihona waihona vhdlaltera_mf.
ʻāpana altecc_encoder maʻamau (meaʻo_device_family: string: = "ʻaʻole i hoʻohana ʻia"; lpm_pipeline: kūlohelohe: = 0; width_codeword: kūlohelohe: = 8; width_dataword: kūlohelohe: = 8; lpm_hint: string: = "UNUSED"; lpm_type: string: = "altecc_encoder" ”); awa (aclr: ma std_logic: = '0'; uaki: ma std_logic: = '0'; uaki: ma std_logic: = '1'; data: ma std_logic_vector (width_dataword-1 a hiki i 0); q: out std_logic_vector (width_codeword -1 a hiki i ka 0)); mea hope;
7.5. Hōʻike Hui VHDL (ALTECC_DECODER)
Aia ka ʻōlelo hoʻolaha ʻāpana VHDL ma ka VHDL Design File (.vhd) altera_mf_components.vhd ma ka waihona waihona vhdlaltera_mf.
ʻāpana altecc_decoder generic ( intended_device_family: string: = "ʻaʻole i hoʻohana ʻia"; lpm_pipeline: kūlohelohe: = 0; width_codeword: kūlohelohe: = 8; width_dataword: kūlohelohe: = 8; lpm_hint: string: = "UNUSED"; lpm_type: string: = "altecc_decoder" ”); awa (aclr: ma std_logic: = '0'; uaki: ma std_logic: = '0'; uaki: ma std_logic: = '1'; data: ma std_logic_vector (width_codeword-1 a hiki i 0); err_corrected: out std_logic; err_detected : out std_logic q: out std_logic_vector(width_dataword-1 down to 0); mea hope;
7.6. Hōʻike VHDL LIBRARY_USE
ʻAʻole koi ʻia ka ʻōlelo hoʻolaha VHDL LIBRARY-USE inā hoʻohana ʻoe i ka VHDL Component Declaration.
HAAWINA altera_mf; E hoohana i altera_mf.altera_mf_components.all;
7.7. Nā Awa Encoder
Aia nā papa ma lalo nei i nā awa hoʻokomo a me nā puka puka no ka ALTECC encoder IP core.

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 33

7. ALTECC (Kāhea Hoʻoponopono Hapa: Encoder/Decoder) IP Core 683490 | 2020.10.05

Papa 22. ALTECC Encoder Input Ports

inoa awa

Pono

wehewehe

ʻikepili []

ʻAe

awa komo ʻikepili. Aia ka nui o ke awa hookomo i ka WIDTH_DATAWORD

waiwai hoʻohālikelike. Aia i loko o ka awa ʻikepili [] ka ʻikepili maka e hoʻopaʻa ʻia.

uaki

ʻAe

ʻO ke awa hoʻokomo uaki e hāʻawi ana i ka hōʻailona uaki e hoʻonohonoho i ka hana hoʻopili.

Pono ke awa uaki inā ʻoi aku ka nui o ka waiwai LPM_PIPELINE ma mua o 0.

uaki

ʻAʻole

Hiki i ka uaki. Inā haʻalele ʻia, ʻo 1 ka waiwai paʻamau.

aclr

ʻAʻole

Hoʻokomo asynchronous maopopo. Hiki ke hoʻohana ʻia ka hōʻailona kiʻekiʻe aclr i kēlā me kēia manawa

asynchronously holoi i nā papa inoa.

Papa 23. ALTECC Encoder Output Ports

inoa awa q[]

Pono ʻAe

wehewehe
Ua hoʻopili ʻia ke awa puka ʻikepili. Aia ka nui o ka puka puka ma ka WIDTH_CODEWORD waiwai.

7.8. Nā Awa Decoder

Hoʻopaʻa nā papa ma lalo nei i nā awa hoʻokomo a me nā puka puka no ka ALTECC decoder IP core.

Papa 24. ALTECC Decoder Input Ports

inoa awa

Pono

wehewehe

ʻikepili []

ʻAe

awa komo ʻikepili. ʻO ka nui o ke awa hoʻokomo e pili ana i ka waiwai hoʻohālikelike WIDTH_CODEWORD.

uaki

ʻAe

ʻO ke awa hoʻokomo uaki e hāʻawi ana i ka hōʻailona uaki e hoʻonohonoho i ka hana hoʻopili. Pono ke awa uaki inā ʻoi aku ka nui o ka waiwai LPM_PIPELINE ma mua o 0.

uaki

ʻAʻole

Hiki i ka uaki. Inā haʻalele ʻia, ʻo 1 ka waiwai paʻamau.

aclr

ʻAʻole

Hoʻokomo asynchronous maopopo. Hiki ke hoʻohana ʻia ka hōʻailona kiʻekiʻe aclr i kēlā me kēia manawa e hoʻomaʻemaʻe ʻole i nā papa inoa.

Papa 25. ALTECC Decoder Output Ports

inoa awa q[]

Pono ʻAe

wehewehe
Ua wehe ʻia ke awa puka ʻikepili. Aia ka nui o ka puka puka ma ka WIDTH_DATAWORD waiwai.

err_detected ʻAe

Hōʻailona hae e hōʻike i ke kūlana o ka ʻikepili i loaʻa a kuhikuhi i nā hewa i loaʻa.

err_correcte ʻAe d

Hōʻailona hae e hōʻike i ke kūlana o ka ʻikepili i loaʻa. Hōʻike i ka hewa bit-bit i loaʻa a hoʻoponopono ʻia. Hiki iā ʻoe ke hoʻohana i ka ʻikepili no ka mea ua hoʻoponopono ʻia.

err_fatal

ʻAe

Hōʻailona hae e hōʻike i ke kūlana o ka ʻikepili i loaʻa. Hōʻike i ka hewa pālua-bit i loaʻa, akā ʻaʻole i hoʻoponopono ʻia. ʻAʻole pono ʻoe e hoʻohana i ka ʻikepili inā hōʻoia ʻia kēia hōʻailona.

syn_e

ʻAʻole

He hōʻailona hoʻopuka e piʻi kiʻekiʻe ke ʻike ʻia kahi hewa hoʻokahi-bit ma ka parity

nā ʻāpana.

7.9. Nā ʻāpana hoʻopili
Hōʻike ka papa ma lalo nei i nā ʻāpana no ka ALTECC encoder IP core.

Intel FPGA Integer Arithmetic IP Cores User Guide 34

Hoʻouna Manaʻo

7. ALTECC (Kāhea Hoʻoponopono Hapa: Encoder/Decoder) IP Core 683490 | 2020.10.05

Papa 26. ALTECC Encoder Parameter

Ka inoa ʻāpana

ʻAno

Pono

wehewehe

WIDTH_DATAWORD

Integer ʻAe

Hōʻike i ka laulā o ka ʻikepili maka. Mai ka 2 a hiki i ka 64. Inā ha'alele, 'o 8 ka waiwai pa'amau.

WIDTH_CODEWORD

Integer ʻAe

Hōʻike i ka laulā o ka huaʻōlelo code pili. Mai ka 6 a hiki i ka 72, koe ka 9, 17, 33, a me 65. Inā waiho ʻia, ʻo 13 ka waiwai paʻamau.

LPM_PIPELINE

Integer No

Hōʻike i ka pipeline no ke kaapuni. Mai ka 0 a hiki i ka 2. Inā he 0 ka waiwai, ʻaʻole i kākau inoa ʻia nā awa. Inā he 1 ka waiwai, ua hoʻopaʻa inoa ʻia nā awa puka. Inā he 2 ka waiwai, hoʻopaʻa inoa ʻia nā awa komo a me nā puka puka. Inā haʻalele ʻia, ʻo 0 ka waiwai paʻamau.

7.10. Nā ʻāpana decoder

Hōʻike ka papa ma lalo i nā ʻāpana kumu IP decoder ALTECC.

Papa 27. ALTECC Decoder Parameter

Ka inoa ʻāpana WIDTH_DATAWORD

ʻAno huinahelu

Pono

wehewehe

ʻAe

Hōʻike i ka laulā o ka ʻikepili maka. He 2 a 64 ka waiwai

ʻO ka waiwai paʻamau he 8.

WIDTH_CODEWORD

Integer

ʻAe

Hōʻike i ka laulā o ka huaʻōlelo code pili. He 6 ka waiwai

i ka 72, koe ka 9, 17, 33, a me 65.

ʻo 13.

LPM_PIPELINE

Integer

ʻAʻole

Hōʻike i ka papa inoa o ke kaapuni. Mai ka 0 a hiki i ka 2. Ina ka

ʻO ka waiwai he 0, ʻaʻohe papa inoa i hoʻokō ʻia. Inā he 1 ka waiwai, ʻo ka

hoʻopaʻa inoa ʻia ka huahana. Inā he 2 ka waiwai, ʻo ka hoʻokomo a me ka

hoʻopaʻa inoa ʻia nā huahana. Inā ʻoi aku ka waiwai ma mua o 2, hoʻohui

Hoʻokomo ʻia nā papa inoa ma ka hoʻopuka no ka mea hou

nā palena. Inā haʻalele ʻia, ʻo 0 ka waiwai paʻamau.

E hana i kahi awa 'syn_e'

Integer

ʻAʻole

E hoʻā i kēia ʻāpana e hana i kahi awa syn_e.

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 35

683490 | 2020.10.05 Hoʻouna Manaʻo

8. Intel FPGA Multiply Adder IP Core

Kiʻi 9.

ʻO ka Intel FPGA Multiply Adder (Intel Stratix 10, Intel Arria 10, a me Intel Cyclone 10 GX device) a i ʻole ALTERA_MULT_ADD (Arria V, Stratix V, a me Cyclone V mau mea) hiki iā ʻoe ke hoʻokō i kahi multiplier-adder.

Hōʻike kēia kiʻi i nā awa no ka Intel FPGA Multiply Adder a i ʻole ALTERA_MULT_ADD IP core.

Intel FPGA Multiply Adder a i ʻole ALTERA_MULT_ADD Ports

Intel FPGA Multiply Adder a i ʻole ALTERA_MULT_ADD

dataa[] signa datab[] signb datac[] coefsel0[] coefsel1[] coefsel2[] coefsel3[] addnsub1 addnsub3 aclr/sclr[] scanina[] clock0 clock1 clock2 ena0 ena1 ena2 sload_accum
accum_sload chainin[]

scanouta[] hopena[]

aclr0 aclr1

inst
ʻAe ka multiplier-adder i nā pālua o nā mea hoʻokomo, hoʻonui i nā waiwai a laila hoʻohui a unuhi paha i nā huahana o nā hui ʻē aʻe.
Inā he 9-bit ka laula a i ʻole ka liʻiliʻi o ka laula ʻikepili komo, hoʻohana ka hana i ka 9 x 9 bit input multiplier configuration ma ka poloka DSP no nā mea e kākoʻo ana i ka hoʻonohonoho 9 x 9. Inā ʻaʻole, hoʻohana ka poloka DSP i 18 × 18-bit multipliers e hoʻoponopono i ka ʻikepili me nā laula ma waena o 10 bits a me 18 bits. Inā nui nā Intel FPGA Multiply Adder a i ʻole ALTERA_MULT_ADD IP cores i loko o kahi hoʻolālā, e māhele ʻia nā hana i

ISO 9001:2015 Kakau

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05
he nui nā poloka DSP like ʻole i hiki ke maʻalahi ke ala ʻana i kēia mau poloka. ʻOi aku ka liʻiliʻi o nā mea hoʻonui i kēlā me kēia poloka DSP e ʻae i nā koho alahele hou aʻe i loko o ka poloka ma ka hōʻemi ʻana i nā ala i ke koena o ka hāmeʻa.
Hoʻokomo pū ʻia nā mea hoʻopaʻa inoa a me nā mea hoʻopaʻa inoa pipeline hou no nā hōʻailona ma lalo o ka poloka DSP: · Hoʻokomo ʻikepili · Koho ʻia a ʻaʻole i kau inoa ʻia · Hoʻohui a unuhi i ke koho · Nā huahana o nā mea hoʻonui.
I ka hopena o ka hopena, ua kau ʻia ka papa inoa mua ma ka poloka DSP. Eia nō naʻe, hoʻokomo ʻia nā papa inoa latency ʻē aʻe i loko o nā mea loiloi ma waho o ka poloka. ʻO ka ʻaoʻao i ka poloka DSP, me nā hoʻokomo ʻikepili i ka multiplier, nā hoʻokomo hōʻailona hoʻomalu, a me nā mea hoʻopuka o ka mea hoʻohui, hoʻohana i ke ala ala maʻamau e kamaʻilio me ke koena o ka hāmeʻa. Hoʻohana nā pilina a pau i ka hana i hoʻolaʻa ʻia i loko o ka poloka DSP. Aia kēia alahele hoʻolaʻa i nā kaulahao hoʻopaʻa inoa hoʻololi ke koho ʻoe i ke koho e hoʻololi i ka ʻikepili hoʻokomo i hoʻopaʻa inoa ʻia mai kahi multiplier i kahi multiplier pili.
No ka ʻike hou aku e pili ana i nā poloka DSP ma kekahi o ka Stratix V, a me Arria V, e nānā i ka mokuna DSP Blocks o nā puke kikoʻī ma ka ʻaoʻao Literature and Technical Documentation.
ʻIkepili e pili ana AN 306: Hoʻokō i nā mea hoʻonui i nā polokalamu FPGA
Hāʻawi i ka ʻike hou aʻe e pili ana i ka hoʻokō ʻana i nā multipliers me ka hoʻohana ʻana i ka DSP a me nā poloka hoʻomanaʻo ma nā polokalamu Intel FPGA.
8.1. Nā hiʻohiʻona
Hāʻawi ka Intel FPGA Multiply Adder a i ʻole ALTERA_MULT_ADD IP core i kēia mau hiʻohiʻona: · Hana i kahi multiplier e hana i nā hana hoʻonui o ʻelua paʻakikī.
Nānā: Ke kūkulu ʻana i nā mea hoʻonui i ʻoi aku ka nui ma mua o ka nui i kākoʻo ʻia ma laila.
e lilo i hopena hana ma muli o ka hoʻokahe ʻana o nā poloka DSP. · Kākoʻo i nā laula ʻikepili o 1 256 bits · Kākoʻo i ka hōʻike hōʻikeʻike ʻikepili i kau inoa ʻia a ʻaʻole i hoʻopaʻa inoa ʻia · Kākoʻo i ka pipelining me ka latency hoʻokomo configurable · Hāʻawi i kahi koho e hoʻololi ikaika ma waena o ke kākoʻo ʻikepili i kau inoa ʻia a me ka hoʻopaʻa ʻole ʻia. hiki i ka asynchronous a me ka synchronous clear a me ka uaki ke hiki i nā awa hoʻokomo · Kākoʻo i ke ʻano hoʻopaʻa inoa hoʻopaneʻe systolic · Kākoʻo i ka pre-adder me 8 pre-load coefficients no multiplier · Kākoʻo i ka pre-load mau e hoʻokō i ka manaʻo accumulator

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 37

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

8.1.1. Pre-adder
Me ka pre-adder, hoʻohui a unuhi ʻia ma mua o ka hānai ʻana i ka mea hoʻonui.
ʻElima mau ʻano hana hoʻohui mua: · Ke ʻano maʻalahi · Ke ʻano coefficient · Ke ʻano hoʻokomo · Ke ʻano pāhaʻi · Ke ʻano mau.

Nānā:

Ke hoʻohana ʻia ka pre-adder (pre-adder coefficient/input/square mode), pono e loaʻa i nā hoʻokomo ʻikepili āpau i ka multiplier ke hoʻonohonoho ʻana i ka uaki like.

8.1.1.1. Hoʻohui mua i ke ʻano maʻalahi

Ma kēia ʻano, loaʻa nā operand ʻelua mai nā awa hoʻokomo a ʻaʻole hoʻohana ʻia ka pre-adder. ʻO kēia ke ʻano paʻamau.

Kiʻi 10. Pre-adder mode maʻalahi
a0 b0

Mult0

hopena

8.1.1.2. ʻAno hoʻohui mua
Ma kēia ʻano, loaʻa kekahi operand multiplier mai ka pre-adder, a ʻo kekahi operand e loaʻa mai ka waihona coefficient kūloko. Hiki i ka waihona coefficient ke hiki i ka 8 preset mau. ʻO nā hōʻailona koho coefficient he coefsel [0..3].
Hōʻike ʻia kēia ʻano ma ka hoohalike aʻe.

Hōʻike kēia ma lalo i ke ʻano hoʻohui mua o ka mea hoʻonui.

Kiʻi 11. Pre-adder Coefficient Mode

Mea heluhelu mua

Mult0

+/-

hopena

coefsel0 coef

Intel FPGA Integer Arithmetic IP Cores User Guide 38

Hoʻouna Manaʻo

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05
8.1.1.3. Ma kēia ʻano, hoʻokahi operand multiplier e loaʻa mai ka pre-adder, a ʻo kekahi operand e loaʻa mai ka datac[] awa komo. Hōʻike ʻia kēia ʻano ma ka hoohalike aʻe.

Hōʻike kēia i ke ʻano hoʻokomo pre-adder o kahi multiplier.

Kiʻi 12. Pre-adder Input Mode
a0 b0

Mult0

+/-

hopena

8.1.1.4. Pre-adder Square Mode Hōʻike ʻia kēia ʻano ma ka hoohalike aʻe.

Hōʻike kēia ma lalo nei i ke ʻano pākuʻi pre-adder o ʻelua multipliers.

Kiʻi 13. Pre-adder Square Mode
a0 b0

Mult0

+/-

hopena

8.1.1.5. Pre-adder Ke ano mau
Ma kēia ʻano, loaʻa kekahi operand multiplier mai ke awa hoʻokomo, a loaʻa ka operand ʻē aʻe mai ka waihona coefficient kūloko. Hiki i ka waihona coefficient ke hiki i ka 8 preset mau. ʻO nā hōʻailona koho coefficient he coefsel [0..3].
Hōʻike ʻia kēia ʻano ma ka hoohalike aʻe.

Hoʻouna Manaʻo

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Hōʻike ke kiʻi ma lalo nei i ke ʻano hana mau o ka mea hoʻonui.

Kiʻi 14. Pre-adder Keʻano mau
a0

Mult0

hopena

pūʻulu0
coef
8.1.2. Palapala Hoʻopaneʻe Systolic
Ma kahi hoʻolālā systolic, ua hānai ʻia ka ʻikepili i loko o kahi cascade o nā papa inoa e hana ana ma ke ʻano he pale data. Hāʻawi kēlā me kēia papa inoa i kahi hoʻokomo sample i ka mea hoonui kahi i hoonuiia me ka huina hoonui. Mālama ka mea hoʻohui kaulahao i nā hualoaʻa i hui mālie ʻia mai ka multiplier a me ka hopena i hoʻopaʻa inoa mua ʻia mai ke awa hoʻokomo chainin[] e hana i ka hopena hope. Pono e hoʻopaneʻe ʻia kēlā me kēia mea hoʻonui-hoʻohui e ka pōʻai hoʻokahi i hiki i nā hopena ke hoʻonohonoho kūpono ke hoʻohui pū ʻia. Hoʻohana ʻia kēlā me kēia lohi e hoʻoponopono i ka hoʻomanaʻo coefficient a me ka pale data o kā lākou mau mea hoʻonui-hoʻohui. No example, hoʻokahi lohi no ka mea hoʻonui hoʻonui lua, ʻelua lohi no ke kolu o ka mea hoʻonui-hoʻohui, a pēlā aku.
Kiʻi 15. Nā papa inoa Systolic
Nā papa inoa systolic

x(t) c(0)

S -1

c(1)

S -1

c(2)

S -1

c(N-1)

S -1

S -1 y(t)

Hōʻike ka x(t) i nā hualoaʻa mai ke kahawai mau o nā hoʻokomo samples a me y(t)
hōʻike i ka hōʻuluʻulu ʻana o kahi hoʻokomo samples, a ma ka manawa, hoonuiia e ko lakou
pakahi like. Kahe nā hualoaʻa komo a me ka puka mai ka hema a i ka ʻākau. ʻO ka c(0) a i ka c(N-1) e hōʻike ana i nā coefficient. Hōʻike ʻia nā papa inoa hoʻopaneʻe systolic e S-1, ʻoiai ʻo ka 1 e hōʻike ana i kahi lohi o ka uaki hoʻokahi. Hoʻohui ʻia nā papa inoa hoʻopaneʻe systolic ma
nā mea hoʻokomo a me nā mea hoʻopuka no ka pipelining i kahi ala e hōʻoia ai i nā hopena mai ka
operand multiplier a me nā huina i hōʻiliʻili ʻia i ka synch. ʻO kēia mea hana
hana hou ʻia e hana i kahi kaapuni e helu ana i ka hana kānana. ʻO kēia hana
i hoikeia ma keia hoohalike.

Intel FPGA Integer Arithmetic IP Cores User Guide 40

Hoʻouna Manaʻo

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Hōʻike ka N i ka helu o nā pōʻaiapuni o ka ʻikepili i komo i loko o ka mea hōʻiliʻili, hōʻike ʻo y(t) i ka hoʻopuka ʻana i ka manawa t, ʻo A(t) ka mea hoʻokomo i ka manawa t, a ʻo B(i) nā coefficients. ʻO ka t a me ka i i loko o ka hoohalike e pili ana i kekahi manawa i ka manawa, no laila e helu i ka hua sample y(t) i ka manawa t, he hui o ka hookomo samples ma N mau kiko like ʻole i ka manawa, a i ʻole A(n), A(n-1), A(n-2), … Pono ʻia ʻo A(n-N+1). ʻO ka hui o N hoʻokomo sampHoʻonui ʻia nā les me nā koena N a hōʻuluʻulu ʻia e hana i ka hopena hope y.
Loaʻa ka hale hoʻopaʻa inoa systolic no nā mode sum-of-2 a me sum-of-4. No nā ʻano hana hoʻopaʻa inoa systolic ʻelua, pono e hoʻopaʻa ʻia ka hōʻailona chainin mua i 0.
Hōʻike kēia kiʻi i ka hoʻokō hoʻopaʻa inoa hoʻopaneʻe systolic o 2 multipliers.
Kiʻi 16. Systolic Delay Register Implementation of 2 Multipliers
kaulahao

Mult0

+/-

Mult1

+/-

hopena
Hōʻike ʻia ka huina o nā mea hoʻonui ʻelua ma ka hoohalike aʻe.
Hōʻike kēia kiʻi i ka hoʻokō hoʻopaʻa inoa hoʻopaneʻe systolic o 4 multipliers.

Hoʻouna Manaʻo

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Kiʻi 17. Systolic Delay Register Implementation of 4 Multipliers
kaulahao

Mult0

+/-

Mult1

+/-

Mult2

+/-

Mult3

+/-

hopena
Hōʻike ʻia ka huina o nā mea hoʻonui ʻehā ma ka hoohalike aʻe. Helu 18. Huina o 4 Mea hoonui
Eia ka papa inoa o ka advantagʻO ka hoʻokō ʻana i ka hoʻopaʻa inoa systolic: · Hoʻemi i ka hoʻohana ʻana i nā kumuwaiwai DSP.

Intel FPGA Integer Arithmetic IP Cores User Guide 42

Hoʻouna Manaʻo

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8.1.3. Hoʻouka mua mau
Mālama ka pre-load mau i ka operand accumulator a hoʻokō i ka manaʻo accumulator. Loaʻa ka LOADCONST_VALUE kūpono mai 0. Ua like ka waiwai mau me 64N, kahi N = LOADCONST_VALUE. Ke hoʻonoho ʻia ka LOADCONST_VALUE i 2, ua like ka waiwai mau me 64. Hiki ke hoʻohana ʻia kēia hana ma ke ʻano he pōʻai ʻokoʻa.
Hōʻike ka helu ma lalo nei i ka hoʻokō mau ʻana ma mua o ka hoʻouka.
Kiʻi 19. Pre-load Constant

ʻO ka manaʻo o ka accumulator

mau

Mult0

+/-

Mult1

+/b1

hopena

accum_sload sload_accum

E nānā i kēia mau core IP no nā hoʻokō hoʻonui ʻē aʻe: · ALTMULT_ACCUM · ALTMEMMULT · LPM_MULT
8.1.4. Mea Hoʻohui ʻAlua
Hoʻohui ka hiʻohiʻona pālua accumulator i kahi papa inoa hou ma ke ala manaʻo accumulator. Hoʻopili ka papa helu helu ʻelua i ka papa inoa hoʻopuka, e komo pū me ka uaki, hiki i ka uaki, a me ka aclr. Hoʻihoʻi ka papa inoa accumulator hou i ka hopena me ka lohi hoʻokahi. Hāʻawi kēia hiʻohiʻona iā ʻoe e loaʻa i ʻelua mau kaila accumulator me ka helu waiwai like.
Hōʻike ka kiʻi ma lalo nei i ka hoʻokō ʻana i ka accumulator pālua.

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 43

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Kiʻi 20. Mea Hoʻohui ʻelua

Hoʻopaʻa inoa ʻelua Accu mulator

Accu mulator feedba ck

Mult0

+/-

Mult1

+/b1

Kakau hoʻopuka hopena

8.2. ʻO Verilog HDL Prototype
Hiki iā ʻoe ke loaʻa ka Intel FPGA Multiply Adder a i ʻole ALTERA_MULT_ADD Verilog HDL prototype file (altera_mult_add_rtl.v) ma ka librariesmegafunctions directory.
8.3. Hōʻike Hui VHDL
Aia ka ʻōlelo hoʻolaha ʻāpana VHDL ma ka altera_lnsim_components.vhd ma ka librariesvhdl altera_lnsim papa kuhikuhi.
8.4. Hōʻike VHDL LIBRARY_USE
ʻAʻole koi ʻia ka ʻōlelo hoʻolaha VHDL LIBRARY-USE inā hoʻohana ʻoe i ka VHDL Component Declaration.
HAAWINA altera_mf; E hoohana i altera_mf.altera_mf_components.all;

8.5. Nā hōʻailona

Aia nā papa ma lalo nei i nā hōʻailona hoʻokomo a me nā hōʻailona hoʻopuka o ka Multiply Adder Intel FPGA IPor ALTERA_MULT_ADD IP core.

Papa 28. Hoʻonui i ka mea hoʻohui Intel FPGA IP a i ʻole ALTERA_MULT_ADD nā hōʻailona hoʻokomo.

hōʻailona

Pono

wehewehe

dataa_0[]/dataa_1[]/

ʻAe

dataa_2[]/dataa_3[]

Hoʻokomo ʻikepili i ka multiplier. awa hookomo [NUMBER_OF_MULTIPLIERS * WIDTH_A – 1 … 0] laula
hoʻomau…

Intel FPGA Integer Arithmetic IP Cores User Guide 44

Hoʻouna Manaʻo

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Hōʻailona datab_0[]/datab_1[]/ datab_2[]/datab_3[] datac_0[] /datac_1[]/ datac_2[]/datac_3[] uaki[1:0] aclr[1:0] sclr[1:0] ena [1:0] hoailona
hōʻailonab
scanina[] accum_sload

Pono ʻAe ʻAʻole
ʻAʻole ʻAʻole ʻAʻole
ʻAʻole
ʻAʻole ʻAʻole

wehewehe
Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole (X) i kēia mau hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia mau hōʻailona, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.
Hoʻokomo ʻikepili i ka multiplier. Hōʻailona hoʻokomo [NUMBER_OF_MULTIPLIERS * WIDTH_B – 1 … 0] ākea Ke kākoʻo ʻia ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo i ʻike ʻole ʻia (X) i kēia mau hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia mau hōʻailona, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.
Hoʻokomo ʻikepili i ka multiplier. Hōʻailona hoʻokomo [NUMBER_OF_MULTIPLIERS * WIDTH_C – 1, … 0] ākea E koho i ka INPUT no ke koho ʻana i ke ʻano preadder mode e hiki ai i kēia mau hōʻailona. Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole (X) i kēia mau hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia mau hōʻailona, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.
awa hookomo uaki i ke kakau inoa pili. Hiki ke hoʻohana ʻia kēia hōʻailona e kekahi papa inoa ma ka IP core. Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole (X) i kēia mau hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia mau hōʻailona, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.
Hoʻokomo asynchronous maopopo i ka papa inoa pili. Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole (X) i kēia mau hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia mau hōʻailona, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.
Hoʻokomo maopopo ʻia i ka papa inoa pili. Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole ʻia X i kēia mau hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia mau hōʻailona, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka
E ho'ā i ka hoʻokomo hōʻailona i ka papa inoa pili. Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole (X) i kēia mau hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia mau hōʻailona, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.
Hōʻike i ka hōʻike helu o ka mea hoʻokomo hoʻonui A. Inā kiʻekiʻe ka hōʻailona hōʻailona, e mālama ka mea hoʻonui i ka hōʻailona hoʻokomo A ma ke ʻano he helu pūlima. Inā haʻahaʻa ka hōʻailona hōʻailona, e mālama ka mea hoʻonui i ka hoʻokomo hoʻonui A hōʻailona ma ke ʻano he helu ʻole. E koho i ka VARIABLE no He aha ke ʻano hōʻike no ka Multipliers A hoʻokomo ʻāpana e hiki ai i kēia hōʻailona. Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole (X) i kēia hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia hoʻokomo, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.
Hōʻike i ka hōʻike helu o ka hōʻailona B hoʻokomo multiplier. Inā kiʻekiʻe ka hōʻailona signb, mālama ka mea hoʻonui i ka hōʻailona hoʻokomo B ma ke ʻano he helu hoʻohui ʻelua i pūlima ʻia. Inā haʻahaʻa ka hōʻailona signb, mālama ka mea hoʻonui i ka hōʻailona hoʻokomo B ma ke ʻano he helu ʻole. Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole (X) i kēia hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia hoʻokomo, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.
Hookomo no ke kaulahao scan A. Hoailona hookomo [WIDTH_A – 1, … 0] laula. Ke loaʻa ka waiwai o SCANA i ka INPUT_SOURCE_A, pono ka hōʻailona scanina[].
Hōʻike maʻamau inā paʻa ka waiwai accumulator. Inā haʻahaʻa ka hōʻailona accum_sload, a laila hoʻouka ʻia ka mea hoʻonui i loko o ka accumulator. Mai hoʻohana i ka accum_sload a me ka sload_accum i ka manawa like.
hoʻomau…

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 45

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Hōʻailona sload_accum
chainin[] addnsub1
addnsub3
kaila0[] kaila1[] kaila2[] kaila3[]

Koi ʻia No
ʻAʻole ʻAʻole
ʻAʻole
ʻAʻole ʻAʻole ʻAʻole

wehewehe
Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole (X) i kēia hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia hoʻokomo, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.
Hōʻike maʻamau inā paʻa ka waiwai accumulator. Inā kiʻekiʻe ka hōʻailona sload_accum, a laila hoʻouka ʻia ka mea hoʻonui i loko o ka accumulator. Mai hoʻohana i ka accum_sload a me ka sload_accum i ka manawa like. Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole (X) i kēia hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia hoʻokomo, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.
kaʻa hoʻokomo hopena mea hoʻohui mai nā s muatage. Hōʻailona hoʻokomo [WIDTH_CHAININ – 1, … 0] ākea.
Hana i ka hoʻohui a i ʻole ka unuhi ʻana i nā mea i hoʻopuka ʻia mai ka pālua mua o nā mea hoʻonui. Hoʻokomo 1 i ka hōʻailona addnsub1 e hoʻohui i nā mea hoʻopuka mai ka pālua mua o nā mea hoʻonui. E hoʻokomo i ka 0 i ka hōʻailona addnsub1 e unuhi i nā mea hoʻopuka mai ka hui mua o nā mea hoʻonui. Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole (X) i kēia hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia hoʻokomo, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.
Hana i ka hoʻohui a i ʻole ka unuhi ʻana i nā mea i hoʻopuka ʻia mai ka pālua mua o nā mea hoʻonui. Hoʻokomo i ka 1 i ka hōʻailona addnsub3 e hoʻohui i nā huahana mai ka lua o nā mea hoʻonui. E hoʻokomo i ka 0 i ka hōʻailona addnsub3 e unuhi i nā huahana mai ka pālua mua o nā mea hoʻonui. Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole (X) i kēia hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia hoʻokomo, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.
Hōʻailona hoʻokomo helu [0:3] i ka mea hoʻonui mua. Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole (X) i kēia hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia hoʻokomo, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.
Hōʻailona hoʻokomo helu [0:3] i ka mea hoʻonui lua. Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole (X) i kēia hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia hoʻokomo, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.
Hōʻailona hoʻokomo helu [0:3] i ke kolu o ka mea hoʻonui. Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole (X) i kēia hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia hoʻokomo, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.
Hōʻailona hoʻokomo helu [0:3] i ka mea hoʻonui ʻehā. Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻokomo ʻole (X) i kēia hōʻailona. Ke hāʻawi ʻoe i ka waiwai X i kēia hoʻokomo, hoʻolaha ʻia ka waiwai X ma nā hōʻailona puka.

Papa 29. Hoʻonui i ka mea hoʻohui Intel FPGA IP Output Signals

hōʻailona

Pono

wehewehe

hopena []

ʻAe

Hōʻailona puka hoʻonui. Hōʻailona puka [WIDTH_RESULT – 1 … 0] ākea

Kākoʻo ke kumu hoʻohālike no kēia IP i ka waiwai hoʻopuka ʻike ʻole ʻia (X). Ke hāʻawi ʻoe i ka waiwai X ma ke ʻano he hoʻokomo, hoʻolaha ʻia ka waiwai X ma kēia hōʻailona.

scanouta []

ʻAʻole

Hoʻopuka o ke kaulahao scan A. Hōʻailona puka [WIDTH_A – 1..0] ākea.

E koho ma mua o 2 no nā helu o nā mea hoʻonui a koho i ka hoʻokomo kaulahao scan no He aha ka hoʻokomo A o ka mea hoʻonui i hoʻopili ʻia i ka ʻāpana e hiki ai i kēia hōʻailona.

Intel FPGA Integer Arithmetic IP Cores User Guide 46

Hoʻouna Manaʻo

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

8.6. Parameter

8.6.1. Tab General

Papa 30. Tab Nui

ʻĀpana

IP i hana ʻia

Waiwai

He aha ka helu o nā mea hoʻonui?

helu_o_m 1 – 4 ultipliers

Pehea ka laula o na pahi komo komo A width_a?

1 – 256

Pehea ka laula o na kaa hookomo B width_b?

1 – 256

Pehea ka laula o ke kaʻa hoʻopuka 'hopena'?

width_hasil

1 – 256

E hana i kahi uaki pili no kēlā me kēia uaki

gui_associate Ma ka d_clock_enabl Paʻa e

8.6.2. ʻO ka papa hana ʻokoʻa

Papa 31. Ka Papa Hana Hou

ʻĀpana

IP i hana ʻia

Waiwai

Hoʻonohonoho hoʻopukapuka

E hoʻopaʻa inoa i nā mea hoʻopuka o ka mea hoʻohui

gui_output_re On

ʻōniʻoniʻo

Paʻa

He aha ke kumu o ka hookomo uaki?

gui_output_re gister_clock

Uaki0 Uaki1 Uaki2

He aha ke kumu no ka hoʻokomo maopopo asynchronous?

gui_output_re gister_aclr

ʻAʻohe ACLR0 ACLR1

He aha ke kumu no ka hoʻokomo maopopo synchronous?

gui_output_re gister_sclr

ʻAʻohe SCLR0 SCLR1

Hana mea hoʻohui

He aha ka hana e pono ai ke hana i na hua o na mea hoonui mua?

gui_multiplier 1_direction

HUI, SUB, VARIABLE

Waiwai Paʻamau 1
16

wehewehe
Ka helu o nā mea hoʻonui e hoʻohui pū ʻia. He 1 a hiki i ka 4. E wehewehe i ka laula o ke awa dataa[].

E wehewehe i ka laula o ke awa datab[].

E wehewehe i ka laula o ka hopena[] awa.

Paʻa

E koho i kēia koho e hana i ka uaki hiki

no kēlā me kēia uaki.

Waiwai Paʻamau

wehewehe

Paʻa uaki0
AOLE AOLE

E koho i kēia koho e hiki ai ke hoʻopaʻa inoa puka o ka module adder.
E koho i ka Clock0, Clock1 a i ʻole Clock2 e hiki ai a kuhikuhi i ke kumu wati no nā papa inoa puka. Pono ʻoe e koho i ka hoʻopaʻa inoa puka o ka ʻāpana mea hoʻohui e hiki ai i kēia ʻāpana.
Hōʻike i ke kumu maopopo asynchronous no ka papa inoa o nā mea hoʻohui. Pono ʻoe e koho i ka hoʻopaʻa inoa puka o ka ʻāpana mea hoʻohui e hiki ai i kēia ʻāpana.
Hōʻike i ke kumu maopopo synchronous no ka papa inoa o nā mea hoʻohui. Pono ʻoe e koho i ka hoʻopaʻa inoa puka o ka ʻāpana mea hoʻohui e hiki ai i kēia ʻāpana.

HOOLAHA

E koho i ka hoʻohui a i ʻole ka unuhi ʻana e hana ai no nā pukana ma waena o nā mea hoʻonui mua a me ka lua.
· E koho iā ADD e hana i ka hana hoʻohui.
· E koho iā SUB e hana i ka hana unuhi.
· E koho i ka VARIABLE no ka hoʻohana ʻana i ke awa addnsub1 no ka mana hoʻohui / unuhi hoʻoikaika.
hoʻomau…

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 47

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

ʻĀpana

IP i hana ʻia

Waiwai

E hoʻopaʻa inoa 'addnsub1' hoʻokomo

gui_addnsub_ On multiplier_reg Off ister1

He aha ke kumu o ka hookomo uaki?

gui_addnsub_ multiplier_reg ister1_clock

Uaki0 Uaki1 Uaki2

He aha ke kumu no ka hoʻokomo maopopo asynchronous?

gui_addnsub_ multiplier_aclr 1

ʻAʻohe ACLR0 ACLR1

He aha ke kumu no ka hoʻokomo maopopo synchronous?

gui_addnsub_ multiplier_sclr 1

ʻAʻohe SCLR0 SCLR1

He aha ka hana e pono ai ke hana ma nā puka o ka lua o nā mea hoʻonui?

gui_multiplier 3_direction

HUI, SUB, VARIABLE

E hoʻopaʻa inoa 'addnsub3' hoʻokomo

gui_addnsub_ On multiplier_reg Off ister3

He aha ke kumu o ka hookomo uaki?

gui_addnsub_ multiplier_reg ister3_clock

Uaki0 Uaki1 Uaki2

Waiwai Paʻamau
Paʻa ka hola0 ʻAʻohe mea hoʻohui
Paʻa uaki0

wehewehe
Ke koho ʻia ka waiwai VARIABLE: · E hoʻohuli i ka hōʻailona addnsub1 i kiʻekiʻe no
hana hoʻohui. · E hoʻolele i ka hōʻailona addnsub1 i haʻahaʻa no
hana unuhi. Pono ʻoe e koho i ʻoi aku ma mua o ʻelua mau mea hoʻonui e hiki ai i kēia ʻāpana.
E koho i kēia koho e hiki ai ke hoʻopaʻa inoa komo no ke awa addnsub1. Pono ʻoe e koho i ka VARIABLE no ka mea he aha ka hana e hana ʻia ma nā mea hoʻopuka o nā mea hoʻonui mua e hiki ai i kēia ʻāpana.
E koho i ka Clock0 , Clock1 a i ʻole Clock2 e kuhikuhi i ka hōʻailona uaki komo no ka hoʻopaʻa inoa addnsub1. Pono ʻoe e koho i ka hoʻokomo 'addnsub1' e hiki ai i kēia ʻāpana.
Hōʻike i ke kumu asynchronous maopopo no ka addnsub1 register. Pono ʻoe e koho i ka hoʻokomo 'addnsub1' e hiki ai i kēia ʻāpana.
Hōʻike i ke kumu maopopo synchronous no ka addnsub1 register. Pono ʻoe e koho i ka hoʻokomo 'addnsub1' e hiki ai i kēia ʻāpana.
E koho i ka hana hoʻohui a i ʻole ka unuhi ʻana e hana ai no nā pukana ma waena o nā mea hoʻonui ʻekolu a me ka hā. · E koho iā ADD e hana i ka hoʻohui
hana. · E koho iā SUB e hoʻoemi
hana. · E koho i ka VARIABLE e hoʻohana i addnsub1
awa no ka mana hoʻohui/hōʻemi ikaika. Ke koho ʻia ka waiwai VARIABLE: · E hoʻohuli i ka hōʻailona addnsub1 i kiʻekiʻe no ka hana hoʻohui. · E hoʻolei i ka hōʻailona addnsub1 i haʻahaʻa no ka hana unuhi. Pono ʻoe e koho i ka waiwai 4 no ka He aha ka helu o nā mea hoʻonui? e hiki ai i kēia ʻāpana.
E koho i kēia koho e hiki ai ke kākau inoa komo no ka hōʻailona addnsub3. Pono ʻoe e koho i ka VARIABLE no ka mea he aha ka hana e hana ʻia ma nā mea hoʻopuka o ka lua o nā mea hoʻonui e hiki ai i kēia ʻāpana.
E koho i ka Clock0 , Clock1 a i ʻole Clock2 e kuhikuhi i ka hōʻailona uaki komo no ka hoʻopaʻa inoa addnsub3. Pono ʻoe e koho i ka hoʻokomo 'addnsub3′ e hiki ai i kēia ʻāpana.
hoʻomau…

Intel FPGA Integer Arithmetic IP Cores User Guide 48

Hoʻouna Manaʻo

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

ʻĀpana
He aha ke kumu no ka hoʻokomo maopopo asynchronous?

IP i hana ʻia

Waiwai

gui_addnsub_ multiplier_aclr 3

ʻAʻohe ACLR0 ACLR1

He aha ke kumu no ka hoʻokomo maopopo synchronous?

gui_addnsub_ multiplier_sclr 3

ʻAʻohe SCLR0 SCLR1

Hiki i ka Polarity 'ho'ohana_subadd'

gui_use_subn On

hoʻohui

Paʻa

8.6.3. Pāpā hoʻonui

Papa 32. Mea hoonui

ʻĀpana

IP i hana ʻia

Waiwai

He aha ka

gui_represent

hōʻike hōʻike ation_a

no nā mea hoʻokomo Multipliers A?

KAUKAU, KANAWAI, ANOAI

E hoʻopaʻa inoa i ka hoʻokomo 'signa'

gui_register_s On

igna

Paʻa

He aha ke kumu o ka hookomo uaki?

gui_register_s igna_clock

Uaki0 Uaki1 Uaki2

He aha ke kumu no ka hoʻokomo maopopo asynchronous?

gui_register_s igna_aclr

ʻAʻohe ACLR0 ACLR1

He aha ke kumu no ka hoʻokomo maopopo synchronous?

gui_register_s igna_sclr

ʻAʻohe SCLR0 SCLR1

He aha ka

gui_represent

hōʻike hōʻike ation_b

no nā mea hoʻokomo Multipliers B?

KAUKAU, KANAWAI, ANOAI

Kakau inoa 'signb'

gui_register_s On

ignb

Paʻa

Waiwai Paʻamau NONE
AOLE

wehewehe
Hōʻike i ke kumu asynchronous maopopo no ka addnsub3 register. Pono ʻoe e koho i ka hoʻokomo 'addnsub3' e hiki ai i kēia ʻāpana.
Hōʻike i ke kumu maopopo synchronous no ka hoʻopaʻa inoa addnsub3. Pono ʻoe e koho i ka hoʻokomo 'addnsub3′ e hiki ai i kēia ʻāpana.

Paʻa

E koho i kēia koho e hoʻohuli i ka hana

o ke awa hookomo addnsub.

E hoʻolei i addnsub i ke kiʻekiʻe no ka hana unuhi.

E hoʻokuʻu i addnsub i haʻahaʻa no ka hana hoʻohui.

Waiwai Paʻamau

wehewehe

UNSIGNED E wehewehe i ke ʻano hōʻike no ka mea hoʻokomo A multiplier.

Paʻa

E koho i kēia koho e hiki ai iā signa

kakau inoa.

Pono ʻoe e koho i ka waiwai VARIABLE no He aha ke ʻano hōʻike no nā mea hoʻokomo Multipliers A? ʻāpana e hiki ai i kēia koho.

Uaki0

E koho i ka Clock0, Clock1 a i ʻole Clock2 e hiki ai a kuhikuhi i ka hōʻailona hōʻailona hōʻailona no ka hoʻopaʻa inoa.
Pono ʻoe e koho i ka hoʻokomo 'signa' e hiki ai i kēia ʻāpana.

AOLE

Hōʻike i ke kumu maopopo asynchronous no ka papa inoa hōʻailona.
Pono ʻoe e koho i ka hoʻokomo 'signa' e hiki ai i kēia ʻāpana.

AOLE

Hōʻike i ke kumu maopopo synchronous no ka papa inoa signa.
Pono ʻoe e koho i ka hoʻokomo 'signa' e hiki ai i kēia ʻāpana.

UNSIGNED E wehewehe i ke ʻano hōʻike no ka hoʻokomo hoʻonui B.

Paʻa

E koho i kēia koho e hiki ai iā signb

kakau inoa.

hoʻomau…

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 49

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

ʻĀpana

IP i hana ʻia

Waiwai

Waiwai Paʻamau

He aha ke kumu o ka hookomo uaki?

gui_register_s ignb_clock

Uaki0 Uaki1 Uaki2

Uaki0

He aha ke kumu no ka hoʻokomo maopopo asynchronous?

gui_register_s ignb_aclr

ʻAʻohe ACLR0 ACLR1

He aha ke kumu no ka hoʻokomo maopopo synchronous?

gui_register_s ignb_sclr

ʻAʻohe SCLR0 SCLR1

Hoʻohui hoʻokomo
E hoʻopaʻa inoa i ka hoʻokomo A o ka mea hoʻonui
He aha ke kumu o ka hookomo uaki?

gui_input_reg On

ister_a

Paʻa

gui_input_reg ister_a_clock

Uaki0 Uaki1 Uaki2

AOLE AOLE
Paʻa uaki0

He aha ke kumu no ka hoʻokomo maopopo asynchronous?

gui_input_reg ister_a_aclr

ʻAʻohe ACLR0 ACLR1

He aha ke kumu no ka hoʻokomo maopopo synchronous?

gui_input_reg ister_a_sclr

ʻAʻohe SCLR0 SCLR1

E hoʻopaʻa inoa i ka hoʻokomo B o ka mea hoʻonui
He aha ke kumu o ka hookomo uaki?

gui_input_reg On

ister_b

Paʻa

gui_input_reg ister_b_clock

Uaki0 Uaki1 Uaki2

ʻAʻohe ʻAʻohe Paʻa Uaka0

He aha ke kumu no ka hoʻokomo maopopo asynchronous?

gui_input_reg ister_b_aclr

ʻAʻohe ACLR0 ACLR1

AOLE

He aha ke kumu no ka hoʻokomo maopopo synchronous?

gui_input_reg ister_b_sclr

ʻAʻohe SCLR0 SCLR1

AOLE

He aha ka mea hoʻokomo A o ka mea hoʻonui i hoʻohui ʻia?

gui_multiplier Mea hookomo hoonui

_a_hookomo

Hoʻokomo hoʻokomo kaulahao scan

wehewehe
Pono ʻoe e koho i ka waiwai VARIABLE no He aha ke ʻano hōʻike no nā mea hoʻokomo Multipliers B? ʻāpana e hiki ai i kēia koho.
E koho i ka Clock0, Clock1 a i ʻole Clock2 e hiki ai a kuhikuhi i ka hōʻailona uaki hoʻokomo no ka hoʻopaʻa inoa signb. Pono ʻoe e koho i ka hoʻokomo 'signb' e hiki ai i kēia ʻāpana.
Hōʻike i ke kumu maopopo asynchronous no ka papa inoa signb. Pono ʻoe e koho i ka hoʻokomo 'signb' e hiki ai i kēia ʻāpana.
Hōʻike i ke kumu maopopo synchronous no ka papa inoa signb. Pono ʻoe e koho i ka hoʻokomo 'signb' e hiki ai i kēia ʻāpana.
E koho i kēia koho e hiki ai ke hoʻopaʻa inoa komo no ka pahi hoʻokomo data.
E koho i ka Clock0, Clock1 a i ʻole Clock2 e hiki ai a kuhikuhi i ka hōʻailona hōʻailona hōʻailona hōʻailona no ka pahi hoʻokomo data. Pono ʻoe e koho E hoʻopaʻa inoa i ka hoʻokomo A o ka multiplier e hiki ai i kēia ʻāpana.
Hōʻike i ke kumu hoʻopaʻa inoa asynchronous no ka pahi hoʻokomo dataa. Pono ʻoe e koho E hoʻopaʻa inoa i ka hoʻokomo A o ka multiplier e hiki ai i kēia ʻāpana.
Hōʻike i ke kumu hoʻopaʻa inoa maʻalahi no ke kaʻa hoʻokomo dataa. Pono ʻoe e koho E hoʻopaʻa inoa i ka hoʻokomo A o ka multiplier e hiki ai i kēia ʻāpana.
E koho i kēia koho e hiki ai ke hoʻopaʻa inoa komo no ka pahi hoʻokomo datab.
E koho i ka Clock0, Clock1 a i ʻole Clock2 e hiki ai a kuhikuhi i ka hōʻailona hōʻailona hōʻailona hōʻailona no ka pahi hoʻokomo datab. Pono ʻoe e koho E hoʻopaʻa inoa i ka hoʻokomo B o ka multiplier e hiki ai i kēia ʻāpana.
Hōʻike i ke kumu hoʻopaʻa inoa asynchronous no ka pahi hoʻokomo datab. Pono ʻoe e koho i ka hoʻokomo inoa B o ka mea hoʻonui e hiki ai i kēia ʻāpana.
Hōʻike i ke kumu hoʻopaʻa inoa ʻokoʻa no ka pahi hoʻokomo datab. Pono ʻoe e koho i ka hoʻokomo inoa B o ka mea hoʻonui e hiki ai i kēia ʻāpana.
E koho i ke kumu hookomo no ka hookomo A o ka mea hoonui.
hoʻomau…

Intel FPGA Integer Arithmetic IP Cores User Guide 50

Hoʻouna Manaʻo

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

ʻĀpana

IP i hana ʻia

Waiwai

Scanout A Hoʻopaʻa inoa

E hoʻopaʻa inoa i ka hoʻopuka o ke kaulahao scan

gui_scanouta On

_kakau inoa

Paʻa

He aha ke kumu o ka hookomo uaki?

gui_scanouta _register_cloc k

Uaki0 Uaki1 Uaki2

He aha ke kumu no ka hoʻokomo maopopo asynchronous?

gui_scanouta _register_aclr

ʻAʻohe ACLR0 ACLR1

He aha ke kumu no ka hoʻokomo maopopo synchronous?

gui_scanouta _register_sclr

ʻAʻohe SCLR0 SCLR1

8.6.4. ʻO Preadder Tab

Papa 33. Preadder Tab

ʻĀpana

IP i hana ʻia

Waiwai

E koho i ke ʻano preadder

preadder_mo de

MAʻalahi, COEF, INPUT, SQUARE, MAU

Waiwai Paʻamau

wehewehe
E koho i ka multiplier input no ka hoʻohana ʻana i ka bus input data ma ke kumu o ka multiplier. E koho i ka hoʻokomo kaulahao scan e hoʻohana i ke kaʻa hoʻokomo scanin ma ke ʻano he kumu no ka mea hoʻonui a hiki i ke kaʻa puka scanout. Loaʻa kēia ʻāpana ke koho ʻoe i ka 2, 3 a i ʻole 4 no He aha ka helu o nā mea hoʻonui? ʻāpana.

Paʻa Uaka0 ʻAʻohe

E koho i kēia koho e hiki ai ke hoʻopaʻa inoa puka no ke kaʻa puka scanouta.
Pono ʻoe e koho Scan chain input no He aha ka hoʻokomo A o ka mea hoʻonui i hoʻopili ʻia? ʻāpana e hiki ai i kēia koho.
E koho i ka Clock0, Clock1 a i ʻole Clock2 e hiki ai a kuhikuhi i ka hōʻailona hōʻailona hōʻailona hōʻailona no ke kaʻa puka scanouta.
Pono ʻoe e hoʻā i ka hoʻopaʻa inoa puka o ka ʻāpana kaulahao scan e hiki ai i kēia koho.
Hōʻike i ke kumu hoʻopaʻa inoa asynchronous no ka pahi hoʻopuka scanouta.
Pono ʻoe e hoʻā i ka hoʻopaʻa inoa puka o ka ʻāpana kaulahao scan e hiki ai i kēia koho.
Hōʻike i ke kumu hoʻopaʻa inoa maʻemaʻe no ka pahi hoʻopuka scanouta.
Pono ʻoe e koho i ka hoʻopaʻa inoa puka o ka ʻāpana kaulahao scan e hiki ai i kēia koho.

Waiwai Paʻamau
MAKEMAKE

wehewehe
Hōʻike i ke ʻano hana no ka module preadder. MAʻalahi: ʻAi kēia ʻano i ka preadder. ʻO kēia ke ʻano paʻamau. COEF: Hoʻohana kēia ʻano i ka puka o ka preadder a me ka coefsel input bus ma ke ʻano he hoʻokomo i ka multiplier. INPUT: Hoʻohana kēia ʻano i ka puka o ka preadder a me datac input bus ma ke ʻano he hoʻokomo i ka multiplier. SQUARE: Ke hoʻohana nei kēia ʻano i ka hoʻopuka o ka preadder e like me nā mea hoʻokomo ʻelua i ka multiplier.
hoʻomau…

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 51

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

ʻĀpana

IP i hana ʻia

Waiwai

E koho i ke kuhikuhi preadder

gui_preadder ADD,

_ kuhikuhi

SUB

Pehea ka laula o na kaa hookomo C width_c?

1 – 256

ʻIkepili C Input Register Configuration

Kākau i ka hoʻokomo datac

gui_datac_inp Aia

ut_register

Paʻa

He aha ke kumu o ka hookomo uaki?

gui_datac_inp ut_register_cl ock

Uaki0 Uaki1 Uaki2

He aha ke kumu no ka hoʻokomo maopopo asynchronous?

gui_datac_inp ut_register_a clr

ʻAʻohe ACLR0 ACLR1

He aha ke kumu no ka hoʻokomo maopopo synchronous?

gui_datac_inp ut_register_sc lr

ʻAʻohe SCLR0 SCLR1

Coefficients
Pehea ka laula o ka coef?

width_coef

1 – 27

Hoʻonohonoho hoʻopaʻa inoa Coef

E hoʻopaʻa inoa i ka hoʻokomo coefsel

gui_coef_regi On

ster

Paʻa

He aha ke kumu o ka hookomo uaki?

gui_coef_regi ster_clock

Uaki0 Uaki1 Uaki2

Waiwai Paʻamau
HOOLAHA
16

wehewehe
MAU: Ke hoʻohana nei kēia ʻano i ka pahi hoʻokomo data me ka preadder i kāʻalo ʻia a me ka coefsel input bus e like me nā mea hoʻokomo i ka multiplier.
Hōʻike i ka hana o ka preadder. No ka hoʻohana ʻana i kēia ʻāpana, koho i kēia no ke ʻano koho preadder mode: · COEF · INPUT · SQUARE a i ʻole · CONSTANT
Hōʻike i ka helu o nā bits no ka pahi hoʻokomo C. Pono ʻoe e koho INPUT no ke ʻano koho preadder e hiki ai i kēia ʻāpana.

Ma ka Uaki0 AOLE AOLE

E koho i kēia koho e hiki ai ke hoʻopaʻa inoa komo no ka pahi hoʻokomo datac. Pono ʻoe e hoʻonoho i ka INPUT e koho i ke ʻano preadder mode e hiki ai i kēia koho.
E koho i ka Clock0, Clock1 a i ʻole Clock2 e kuhikuhi i ka hōʻailona uaki hoʻokomo no ka papa inoa hoʻokomo datac. Pono ʻoe e koho i ka hoʻokomo ʻikepili datac e hiki ai i kēia ʻāpana.
Hōʻike i ke kumu maopopo asynchronous no ka papa inoa hoʻokomo datac. Pono ʻoe e koho i ka hoʻokomo ʻikepili datac e hiki ai i kēia ʻāpana.
Hōʻike i ke kumu maopopo synchronous no ka papa inoa hoʻokomo datac. Pono ʻoe e koho i ka hoʻokomo ʻikepili datac e hiki ai i kēia ʻāpana.

Hōʻike i ka helu o nā bits no

kaʻa hoʻokomo coefsel.

Pono ʻoe e koho i ka COEF a i ʻole CONSTANT no ke ʻano preadder e hiki ai i kēia ʻāpana.

Ma ka uaki0

E koho i kēia koho e hiki ai ke hoʻopaʻa inoa hoʻokomo no ka pahi hoʻokomo coefsel. Pono ʻoe e koho i ka COEF a i ʻole CONSTANT no ke ʻano preadder e hiki ai i kēia ʻāpana.
E koho i ka Clock0, Clock1 a i ʻole Clock2 e kuhikuhi i ka hōʻailona uaki hoʻokomo no ka papa inoa hoʻokomo coefsel. Pono ʻoe e koho E hoʻopaʻa inoa i ka hoʻokomo coefsel e hiki ai i kēia ʻāpana.
hoʻomau…

Intel FPGA Integer Arithmetic IP Cores User Guide 52

Hoʻouna Manaʻo

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

ʻĀpana
He aha ke kumu no ka hoʻokomo maopopo asynchronous?

IP i hana ʻia

Waiwai

gui_coef_regi ster_aclr

ʻAʻohe ACLR0 ACLR1

He aha ke kumu no ka hoʻokomo maopopo synchronous

gui_coef_regi ster_sclr

ʻAʻohe SCLR0 SCLR1

Coefficient_0 Hoʻonohonoho

coef0_0 i ka coef0_7

0x00000 0xFFFFFFFF

Coefficient_1 Hoʻonohonoho

coef1_0 i ka coef1_7

0x00000 0xFFFFFFFF

Coefficient_2 Hoʻonohonoho

coef2_0 i ka coef2_7

0x00000 0xFFFFFFFF

Coefficient_3 Hoʻonohonoho

coef3_0 i ka coef3_7

0x00000 0xFFFFFFFF

8.6.5. Pākuʻu Mea Hoʻohui

Papa 34. Puka Hookuu

ʻĀpana

IP i hana ʻia

Waiwai

Hiki i ka accumulator?

mea hoʻouluulu

ʻAe, ʻAʻole

He aha ke ʻano hana accumulator?

accum_directi ADD,

SUB

Waiwai Paʻamau NONE
AOLE
0x0000000 0
0x0000000 0
0x0000000 0
0x0000000 0

wehewehe
Hōʻike i ke kumu maopopo asynchronous no ka papa inoa hoʻokomo coefsel. Pono ʻoe e koho E hoʻopaʻa inoa i ka hoʻokomo coefsel e hiki ai i kēia ʻāpana.
Hōʻike i ke kumu maopopo synchronous no ka papa inoa hoʻokomo coefsel. Pono ʻoe e koho E hoʻopaʻa inoa i ka hoʻokomo coefsel e hiki ai i kēia ʻāpana.
Hōʻike i nā waiwai coefficient no kēia mea hoʻonui mua. Pono e like ka helu o nā bits e like me ka mea i ʻōlelo ʻia ma Pehea ka laulā o ka laula coef? hoʻohālikelike. Pono ʻoe e koho i ka COEF a i ʻole CONSTANT no ke ʻano preadder e hiki ai i kēia ʻāpana.
Hōʻike i ka helu helu no kēia mea hoʻonui lua. Pono e like ka helu o nā bits e like me ka mea i ʻōlelo ʻia ma Pehea ka laulā o ka laula coef? ʻāpana. Pono ʻoe e koho i ka COEF a i ʻole CONSTANT no ke ʻano preadder e hiki ai i kēia ʻāpana.
Hōʻike i nā waiwai coefficient no kēia mea hoʻonui kolu. Pono e like ka helu o nā bits e like me ka mea i ʻōlelo ʻia ma Pehea ka laulā o ka laula coef? hoʻohālikelike. Pono ʻoe e koho i ka COEF a i ʻole CONSTANT no ke ʻano preadder e hiki ai i kēia ʻāpana.
Hōʻike i ka helu helu no kēia mea hoʻonui ʻehā. Pono e like ka helu o nā bits e like me ka mea i ʻōlelo ʻia ma Pehea ka laulā o ka laula coef? ʻāpana. Pono ʻoe e koho i ka COEF a i ʻole CONSTANT no ke ʻano preadder e hiki ai i kēia ʻāpana.

Waiwai Paʻamau NO
HOOLAHA

wehewehe
E koho i ka YES e hiki ai i ka accumulator. Pono ʻoe e koho i ka hoʻopaʻa inoa i ka puka o ka mea hoʻohui i ka wā e hoʻohana ai i ka hiʻohiʻona accumulator.
Hōʻike i ka hana o ka accumulator: · ADD no ka hana hoʻohui · SUB no ka hana unuhi. Pono ʻoe e koho i ka YES no Enable accumulator? ʻāpana e hiki ai i kēia koho.
hoʻomau…

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 53

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

ʻĀpana
Hoʻomaka mua i ka hoʻokau mau

IP i hana ʻia

Waiwai

gui_ena_prelo On

ad_const

Paʻa

He aha ka hoʻokomo o ka accumulate port i pili i?

gui_accumula ACCUM_SLOAD, ke_port_koho SLOAD_ACCUM

E koho i ka waiwai no ka hoʻouka mua loadconst_val 0 – 64

mau

He aha ke kumu o ka hookomo uaki?

gui_accum_sl oad_register_ clock

Uaki0 Uaki1 Uaki2

He aha ke kumu no ka hoʻokomo maopopo asynchronous?

gui_accum_sl oad_register_ aclr

ʻAʻohe ACLR0 ACLR1

He aha ke kumu no ka hoʻokomo maopopo synchronous?

gui_accum_sl oad_register_ sclr

ʻAʻohe SCLR0 SCLR1

E ho'ā i ka mea hoʻohui pālua

gui_double_a On

ccum

Paʻa

Waiwai Paʻamau

wehewehe

Paʻa

E ho'ā i ka accum_sload a i ʻole

sload_accum hōʻailona a hoʻopaʻa inoa i ka hoʻokomo

e koho ikaika i ka hookomo i ka

mea hōʻiliʻili.

Ke haʻahaʻa ka accum_sload a i ʻole sload_accum, e hānai ʻia ka hua hoʻonui i loko o ka accumulator.

Ke kiʻekiʻe ka accum_sload a i ʻole sload_accum, hānai ʻia kahi mea hoʻohana i hoʻopaʻa ʻia ma mua o ka hoʻouka.

Pono ʻoe e koho i ka YES no Enable accumulator? ʻāpana e hiki ai i kēia koho.

ACCUM_SL OAD

Hōʻike i ke ʻano o ka hōʻailona accum_sload/ sload_accum.
ACCUM_SLOAD: E hoʻokele haʻahaʻa i accum_sload e hoʻouka i ka mea hoʻonui i ka mea hoʻohui.
SLOAD_ACCUM: E hoʻokele i ka sload_accum kiʻekiʻe e hoʻouka i ka hua hoʻonui i ka mea hoʻohui.
Pono ʻoe e koho Enable preload constant koho e hiki ai i kēia ʻāpana.

E wehewehe i ka waiwai mau.

Hiki i kēia waiwai ke 2N kahi N ka waiwai mau.

Inā N=64, hōʻike ia i ka ʻole mau.

Pono ʻoe e koho Enable preload constant koho e hiki ai i kēia ʻāpana.

Uaki0

E koho i ka Clock0 , Clock1 a i ʻole Clock2 e kuhikuhi i ka hōʻailona uaki hoʻokomo no ka hoʻopaʻa inoa accum_sload/sload_accum.
Pono ʻoe e koho Enable preload constant koho e hiki ai i kēia ʻāpana.

AOLE

Hōʻike i ke kumu maopopo asynchronous no ka papa inoa accum_sload/sload_accum.
Pono ʻoe e koho Enable preload constant koho e hiki ai i kēia ʻāpana.

AOLE

Hōʻike i ke kumu maʻemaʻe like ʻole no ka papa inoa accum_sload/sload_accum.
Pono ʻoe e koho Enable preload constant koho e hiki ai i kēia ʻāpana.

Paʻa

Hiki ke hoʻopaʻa inoa pālua accumulator.

Intel FPGA Integer Arithmetic IP Cores User Guide 54

Hoʻouna Manaʻo

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

8.6.6. Systolic/Chainout Tab

Papa 35. Systolic/Chainout Adder Tab

Parameter Ho'ā i ka mea hoʻohui kaulahao

IP i hana ʻia

Waiwai

chainout_add ʻAe,

ʻAʻOLE

He aha ke ʻano hana hoʻohui chainout?

chainout_add ADD,

er_direction

SUB

E hoʻā i ka hoʻokomo 'negate' no ka mea hoʻohui kaulahao?

Port_negate

PORT_USED, PORT_UNUSED

E hoʻopaʻa inoa i ka hoʻokomo 'negate'? negate_regist er

KAKAU ʻAʻole, WIKA0, WIKA1, WIKA2, WIKA3

He aha ke kumu no ka hoʻokomo maopopo asynchronous?

negate_aclr

ʻAʻohe ACLR0 ACLR1

He aha ke kumu no ka hoʻokomo maopopo synchronous?

negate_sclr

ʻAʻohe SCLR0 SCLR1

Hoʻopaneʻe Systolic
E ho'ā i nā papa inoa hoʻopaneʻe systolic

gui_systolic_d On

elay

Paʻa

He aha ke kumu o ka hookomo uaki?

gui_systolic_d CLOCK0,

elay_clock

KAU1,

Waiwai Paʻamau
ʻAʻOLE

wehewehe
E koho i ka YES no ka hoʻohana ʻana i ka module adder chainout.

HOOLAHA

Hōʻike i ka hana hoʻohui chainout.
No ka hana unuhi, pono e koho ʻia ʻo SIGNED no He aha ke ʻano hōʻike no nā mea hoʻokomo Multipliers A? a He aha ke ʻano hōʻike no nā mea hoʻokomo Multipliers B? i loko o ka Multipliers Tab.

PORT_UN HOʻohana

E koho iā PORT_USED no ka hoʻopau ʻana i ka hōʻailona hoʻokomo.
He kūpono ʻole kēia ʻāpana ke pio ka mea hoʻohui chainout.

KAKAU inoa ERED

I mea e hiki ai i ka papa inoa hoʻokomo no ka hōʻole ʻana i ka hōʻailona hoʻokomo a kuhikuhi i ka hōʻailona uaki hoʻokomo no ka hoʻopaʻa inoa negate.
E koho UNREGISTERED inā ʻaʻole pono ka hoʻopaʻa inoa hoʻokomo
He kūpono ʻole kēia ʻāpana ke koho ʻoe:
· ʻAʻole no ka Enable chainout adder a i ʻole
· PORT_UNUSED no ka ho'ā 'ana i ka hoʻokomo 'ana no ka mea hoʻohui chainout? ʻāpana a i ʻole

AOLE

Hōʻike i ke kumu asynchronous maopopo no ka hoʻopaʻa inoa negate.
He kūpono ʻole kēia ʻāpana ke koho ʻoe:
· ʻAʻole no ka Enable chainout adder a i ʻole
· PORT_UNUSED no ka ho'ā 'ana i ka hoʻokomo 'ana no ka mea hoʻohui chainout? ʻāpana a i ʻole

AOLE

Hōʻike i ke kumu maopopo synchronous no ka papa inoa negate.
He kūpono ʻole kēia ʻāpana ke koho ʻoe:
· ʻAʻole no ka Enable chainout adder a i ʻole
· PORT_UNUSED no ka ho'ā 'ana i ka hoʻokomo 'ana no ka mea hoʻohui chainout? ʻāpana a i ʻole

Paʻa KAU0

E koho i kēia koho e hiki ai i ke ʻano systolic. Loaʻa kēia ʻāpana ke koho ʻoe i ka 2, a i ʻole 4 no ka He aha ka helu o nā mea hoʻonui? hoʻohālikelike. Pono ʻoe e hoʻohana i ka hoʻopuka Register o ka mea hoʻohui e hoʻohana i nā papa inoa lohi systolic.
Hōʻike i ka hōʻailona uaki hoʻokomo no ka papa inoa lohi systolic.
hoʻomau…

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 55

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

ʻĀpana

IP i hana ʻia

Waiwai

KAU2,

He aha ke kumu no ka hoʻokomo maopopo asynchronous?

gui_systolic_d elay_aclr

ʻAʻohe ACLR0 ACLR1

He aha ke kumu no ka hoʻokomo maopopo synchronous?

gui_systolic_d elay_sclr

ʻAʻohe SCLR0 SCLR1

Waiwai Paʻamau
AOLE
AOLE

wehewehe
Pono ʻoe e koho e hiki i nā papa inoa hoʻopaneʻe systolic e hiki ai i kēia koho.
Hōʻike i ke kumu maopopo asynchronous no ka papa inoa hoʻopaneʻe systolic. Pono ʻoe e koho e hiki i nā papa inoa hoʻopaneʻe systolic e hiki ai i kēia koho.
Hōʻike i ke kumu maopopo synchronous no ka papa inoa hoʻopaneʻe systolic. Pono ʻoe e koho e hiki i nā papa inoa hoʻopaneʻe systolic e hiki ai i kēia koho.

8.6.7. Paipai Paipu

Papa 36. Pipelining Tab

ʻO ka hoʻonohonoho hoʻonohonoho ʻana o ka pipeline

IP i hana ʻia

Waiwai

Makemake ʻoe e hoʻohui i ka papa inoa pipeline i ka hoʻokomo?

gui_pipelining ʻAʻole, ʻAe

Waiwai Paʻamau
ʻAʻole

E ʻoluʻolu e wehewehe i ka

ka lōʻihi

helu o ka uaki latency

nā pōʻaiapuni

Kekahi waiwai i oi aku ma mua o 0

He aha ke kumu o ka hookomo uaki?

gui_input_late ncy_clock

KAULA0, KAULA1, KAULA2

He aha ke kumu no ka hoʻokomo maopopo asynchronous?

gui_input_late ncy_aclr

ʻAʻohe ACLR0 ACLR1

He aha ke kumu no ka hoʻokomo maopopo synchronous?

gui_input_late ncy_sclr

ʻAʻohe SCLR0 SCLR1

WAKA0 AOLE AOLE

wehewehe
E koho iā ʻAe e hiki ai i kahi pae hou o ka hoʻopaʻa inoa pipeline i nā hōʻailona hoʻokomo. Pono ʻoe e hōʻike i kahi waiwai i ʻoi aku ma mua o 0 no ka E ʻoluʻolu e kuhikuhi i ka helu o nā pōʻaiapuni o ka uaki latency.
Hōʻike i ka latency i makemake ʻia i nā pōʻai uaki. Hoʻokahi pae o ka hoʻopaʻa inoa pipeline = 1 latency i ka pōʻai uaki. Pono ʻoe e koho i ka YES no Makemake ʻoe e hoʻohui i ka papa inoa pipeline i ka hoʻokomo? e hiki ai i keia koho.
E koho i ka Clock0, Clock1 a i ʻole Clock2 e hiki ai a kuhikuhi i ka hōʻailona hōʻailona hōʻailona hoʻopaʻa inoa paipu. Pono ʻoe e koho i ka YES no Makemake ʻoe e hoʻohui i ka papa inoa pipeline i ka hoʻokomo? e hiki ai i keia koho.
Hōʻike i ke kumu hoʻopaʻa inoa asynchronous no ka papa inoa pipeline hou. Pono ʻoe e koho i ka YES no Makemake ʻoe e hoʻohui i ka papa inoa pipeline i ka hoʻokomo? e hiki ai i keia koho.
Hōʻike i ke kumu hoʻopaʻa inoa ʻokoʻa no ka papa inoa pipeline hou. Pono ʻoe e koho i ka YES no Makemake ʻoe e hoʻohui i ka papa inoa pipeline i ka hoʻokomo? e hiki ai i keia koho.

Intel FPGA Integer Arithmetic IP Cores User Guide 56

Hoʻouna Manaʻo

683490 | 2020.10.05 Hoʻouna Manaʻo

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core

Nānā:

Ua wehe ʻo Intel i ke kākoʻo o kēia IP ma Intel Quartus Prime Pro Edition version 20.3. Inā hoʻokumu ka IP core i kāu mau manaʻo hoʻolālā i nā polokalamu ma Intel Quartus Prime Pro Edition, hiki iā ʻoe ke pani i ka IP me LPM_MULT Intel FPGA IP a i ʻole hana hou i ka IP a hoʻohui i kāu hoʻolālā me ka hoʻohana ʻana i ka polokalamu Intel Quartus Prime Standard Edition.

Hoʻohana ʻia ka ALTMEMMULT IP core no ka hana ʻana i nā mea hoʻonui hoʻomanaʻo me ka hoʻohana ʻana i nā poloka hoʻomanaʻo onchip i loaʻa ma Intel FPGAs (me nā poloka hoʻomanaʻo M512, M4K, M9K, a me MLAB). Pono kēia IP core inā ʻaʻole lawa kāu mau kumuwaiwai e hoʻokō i nā mea hoʻonui i loko o nā mea loiloi (LEs) a i ʻole nā kumuwaiwai hoʻolaʻa hoʻonui.
ʻO ka ALTMEMMULT IP core kahi hana synchronous e pono ai ka uaki. Hoʻokomo ka ALTMEMMULT IP core i ka multiplier me ka liʻiliʻi loa o ka throughput a me ka latency i hiki no kahi hoʻonohonoho o nā ʻāpana a me nā kikoʻī.
Hōʻike kēia kiʻi i nā awa no ka ALTMEMMULT IP core.

Kii 21. ALTMEMMULT Awa

ALTMEMMULT

data_in[] sload_data coeff_in[]

hopena[] hopena_kupono load_done

sload_coeff

sclr uaki
inst

Nā hiʻohiʻona ʻike pili ma ka ʻaoʻao 71

9.1. Nā hiʻohiʻona
Hāʻawi ka ALTMEMMULT IP core i kēia mau hiʻohiʻona: · Hana i nā mea hoʻonui hoʻomanaʻo wale nō me ka hoʻohana ʻana i nā poloka hoʻomanaʻo ma-chip i loaʻa ma
Nā Intel FPGA · Kākoʻo i ka laulā ʻikepili o 1 bits · Kākoʻo i ke ʻano hōʻike hōʻike ʻike i kau inoa ʻole ʻia · Kākoʻo i ka pipelining me ka latency output paʻa.

ISO 9001:2015 Kakau

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05
· Hoʻopaʻa i nā mea hoʻopaʻa mau i loko o ka hoʻomanaʻo hoʻomanaʻo (RAM)
· Hāʻawi i kahi koho e koho i ke ʻano poloka RAM
· Kākoʻo koho synchronous maopopo a me ka haawe-mana komo awa
9.2. ʻO Verilog HDL Prototype
Aia ka prototype Verilog HDL ma ka Verilog Design File (.v) altera_mf.v i ka eda synthesis directory.
module altmemmult #( parameter coeff_representation = "KAUKAU", koena hoʻohālikelike0 = "ʻAʻole i hoʻohana ʻia", parameter data_representation = "SIGNED", parameter intended_device_family = "ʻaʻole i hoʻohana ʻia", parameter max_clock_cycles_per_result = 1, helu helu_of_coefficients = 1, ʻano ʻāpana ram_block_type total_latency = 1, ʻāpana width_c = 1, ʻāpana width_d = 1, ʻāpana width_r = 1, ʻāpana width_s = 1, ʻāpana lpm_type = "altmemmult", ʻāpana lpm_hint = "ʻaʻole i hoʻohana ʻia") ( uaki uea komo, uea hoʻokomo [width_c-1: 0] coeff_in, uea hookomo [width_d-1:0] data_in, uea hoopuka load_done, uea puka [width_r-1:0] hopena, uea puka result_valid, uea hookomo sclr, uea hookomo [width_s-1:0] koho, hookomo uea sload_coeff, uea hoʻokomo sload_data)/* synthesis syn_black_box=1 */; hopemodule
9.3. Hōʻike Hui VHDL
Aia ka ʻōlelo hoʻolaha ʻāpana VHDL ma ka VHDL Design File (.vhd) altera_mf_components.vhd ma ka waihona waihona vhdlaltera_mf.
ʻāpana altmemmult generic ( coeff_representation: string : = "SIGNED"; coefficient0: string: = "UNUSED"; data_representation: string: = "SIGNED"; intended_device_family: string: = "ʻAʻole i hoʻohana ʻia"; max_clock_cycles_per_result:natural:= 1; helu_of_coefficient := 1; "altmemult"); awa (uaki: ma std_logic; coeff_in: ma std_logic_vector (width_c-1 a hiki i 1): = (nā mea ʻē aʻe => '0'); data_in: ma std_logic_vector (width_d-0 a hiki i 1);

Intel FPGA Integer Arithmetic IP Cores User Guide 58

Hoʻouna Manaʻo

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

load_done:out std_logic; hopena: mai std_logic_vector(width_r-1 a hiki i 0); result_valid:out std_logic; sclr: in std_logic : = '0'; sel: ma std_logic_vector(width_s-1 a hiki i 0) := (nā mea ʻē aʻe => '0'); sload_coeff:in std_logic := '0'; sload_data:in std_logic := '0'); mea hope;

9.4. Awa

Hoʻopaʻa nā papa ma lalo nei i nā awa hoʻokomo a me nā puka puka no ke kumu IP ALTMEMMULT.

Papa 37. ALTMEMMULT Na Awa Hookomo

inoa awa

Pono

wehewehe

uaki

ʻAe

Hoʻokomo uaki i ka mea hoʻonui.

coeff_in[]

ʻAʻole

awa hookomo coefficient no ka mea hoonui. ʻO ka nui o ke awa hoʻokomo e pili ana i ka waiwai hoʻohālikelike WIDTH_C.

data_in[]

ʻAe

awa hookomo ikepili i ka mea hoonui. ʻO ka nui o ke awa hoʻokomo e pili ana i ka waiwai hoʻohālikelike WIDTH_D.

sclr

ʻAʻole

Hoʻokomo maopopo ʻia. Inā hoʻohana ʻole ʻia, ʻeleu ka waiwai paʻamau.

koho []

ʻAʻole

Paʻa koho coefficient. ʻO ka nui o ke awa hoʻokomo e pili ana i ka WIDTH_S

waiwai hoʻohālikelike.

sload_coeff

ʻAʻole

awa hoʻokomo ʻana i ka hoʻouka ʻana like. Hoʻololi i ka waiwai coefficient i koho ʻia i kēia manawa me ka waiwai i ʻōlelo ʻia ma ka hoʻokomo coeff_in.

sload_data

ʻAʻole

awa hoʻokomo ʻikepili hoʻouka like ʻole. Hōʻailona e kuhikuhi ana i ka hana hoʻonui hou a hoʻopau i kekahi hana hoʻonui i loaʻa. Inā he 1 ka waiwai o ka ʻāpana MAX_CLOCK_CYCLES_PER_RESULT, ʻaʻole mālama ʻia ke awa hoʻokomo sload_data.

Papa 38. ALTMEMMULT Puka Puka

inoa awa

Pono

wehewehe

hopena []

ʻAe

awa puka hoonui. ʻO ka nui o ke awa hoʻokomo e pili ana i ka waiwai hoʻohālikelike WIDTH_R.

hopena_pono

ʻAe

Hōʻike i ka wā o ka hoʻopuka ka hopena kūpono o ka hoʻonui piha. Inā he 1 ka waiwai o ka ʻāpana MAX_CLOCK_CYCLES_PER_RESULT, ʻaʻole hoʻohana ʻia ka puka puka hopena_valid.

load_done

ʻAʻole

Hōʻike i ka pau ʻana o ka hoʻouka ʻana o ka coefficient hou. Hōʻike ka hōʻailona load_done i ka pau ʻana o ka hoʻouka ʻana o kahi coefficient hou. Inā ʻaʻole kiʻekiʻe ka hōʻailona load_done, ʻaʻohe waiwai coefficient ʻē aʻe e hoʻouka ʻia i loko o ka hoʻomanaʻo.

9.5. Parameter

Hōʻike ka papa ma lalo i nā ʻāpana no ka ALTMEMMULT IP core.

Papa 39.
WIDTH_D WIDTH_C

Nā ʻāpana ALTMEMMULT
Ka inoa ʻāpana

Pono ke ʻano

wehewehe

Integer ʻAe

Hōʻike i ka laulā o ka data_in[] awa.

Integer ʻAe

Hōʻike i ka laula o ke awa coeff_in[]. hoʻomau…

Hoʻouna Manaʻo

Intel FPGA Integer Arithmetic IP Cores User Guide 59

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

Ka inoa ʻāpana WIDTH_R WIDTH

Palapala / Punawai

intel FPGA Integer Arithmetic IP Cores [pdf] Ke alakaʻi hoʻohana
FPGA Integer Arithmetic IP Cores, Integer Arithmetic IP Cores, Arithmetic IP Cores, IP Cores

Nā kuhikuhi

Palapala Hoʻohana

FPGA Integer Arithmetic IP Cores

Palapala / Punawai

Nā kuhikuhi

Waiho i kahi manaʻo

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