intel FPGA Integer Irithmetic IP Cores Jagorar mai amfani

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1 FPGA Integer Rithmetic IP Cores

2 Takardu / Albarkatu

2.1 Magana

3 Labarai masu alaka

FPGA Integer Rithmetic IP Cores

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Jagorar Mai Amfani da Integer Integer FPGA IP Cores
An sabunta don Intel® Quartus® Prime Design Suite: 20.3

Sigar Kan layi Aika Amsa

Saukewa: UG-01063

ID: 683490 Shafin: 2020.10.05

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1. Intel FPGA Integer Irithmetic IP Cores………………………………………………………………………………………..
2. LPM_COUNTER (Counter) IP Core……………………………………………………………………………………………….. 7 2.1. Siffofin……………………………………………………………………………………………………………………………………………… Samfurin Verilog HDL……………………………………………………………………………………………….. 7 2.2. Sanarwa na Bangaren VHDL……………………………………………………………………………………………………….8 2.3. Bayanin VHDL LIBRARY_Amfani……………………………………………………………………………………………………………… Tashoshi ………………………………………………………………………………………………………………………………………………………… Siga…………………………………………………………………………………………………………………………………………………………………………………………………
3. LPM_DIVIDE (Masu Rarraba) Intel FPGA IP Core……………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Siffofin……………………………………………………………………………………………………………………………… 12 3.1. Samfurin Verilog HDL……………………………………………………………………………………………………………………………………………… 12 3.2. Sanarwa na Bangaren VHDL……………………………………………………………………………………….. 12 3.3. VHDL LIBRARY_Sanarwar AMFANI………………………………………………………………………………………………. 13 3.4. Tashoshi ………………………………………………………………………………………………………………………………………………………………………………………………………………………… Siga…………………………………………………………………………………………………………………………………………………………………………………………………………
4. LPM_MULT (Multiplier) IP Core……………………………………………………………………………………………………………………… 16 4.1. Siffofin……………………………………………………………………………………………………………………………… 16 4.2. Samfurin Verilog HDL……………………………………………………………………………………………………………………………………… 17 4.3. Sanarwa na Bangaren VHDL………………………………………………………………………………………….. 17 4.4. VHDL LIBRARY_Sanarwar AMFANI………………………………………………………………………………………………. 17 4.5. Sigina………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Siga don Stratix V, Arria V, Cyclone V, da Intel Cyclone 18 LP Na'urorin………………… 4.6 10. Gabaɗaya shafin .................................................................... Gabaɗaya 18 Tab……………………………………………………………………………………………………………………………………………………………………………………… Tabbar bututu……………………………………………………………………………………………………………………………… 4.6.1 18. Ma'auni don Intel Stratix 4.6.2, Intel Arria 2, da Intel Cyclone 19 GX Na'urorin……….. 4.6.3 19. Gabaɗaya Tab………………………………………………………………………………………………………………………………………………………………………………… 4.7 10. Gabaɗaya 10 Tab……………………………………………………………………………………………………………………………………………………………………………………… 10 20. Bututu …………………………………………………………………………………………………………………………………………………
5. LPM_ADD_SUB (Adder/Subtractor)………………………………………………………………………………………………………………………………………………… Siffofin……………………………………………………………………………………………………………………………… 22 5.1. Samfurin Verilog HDL……………………………………………………………………………………………………………………………………………………………… 22 5.2. Bayanin Abubuwan Bangaren VHDL……………………………………………………………………………………….. 23 5.3. VHDL LIBRARY_Sanarwar AMFANI………………………………………………………………………………………………. 23 5.4. Tashoshi ………………………………………………………………………………………………………………………………………………………………………………………… Siga…………………………………………………………………………………………………………………………………………………………………………………………………
6. LPM_COMPARE (Comparator)………………………………………………………………………………………………………………………………………………………….26 6.1. Siffofin……………………………………………………………………………………………………………………………… 26 6.2. Samfurin Verilog HDL……………………………………………………………………………………………………………………………………… 27 6.3. Sanarwa na Bangaren VHDL……………………………………………………………………………………….. 27 6.4. VHDL LIBRARY_Sanarwar AMFANI………………………………………………………………………………………………. 27 6.5. Tashoshi ………………………………………………………………………………………………………………………………………………………………………………………… Siga…………………………………………………………………………………………………………………………………………………………………………………………………

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 2

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7. ALTECC (Lambar Gyara Kuskuren: Encoder/Decoder) IP Core……………………………………………… 30
7.1. Alamar Encoder ALTECC………………………………………………………………………………………………………..31 7.2. Samfurin Verilog HDL (ALTECC_ENCODER)……………………………………………………………………………… 32 7.3. Prototype HDL Verilog (ALTECC_DECODER)……………………………………………………………………………… 32 7.4. Sanarwa na Bangaren VHDL (ALTECC_ENCODER)……………………………………………………………………………………… Sanarwa na Bangaren VHDL (ALTECC_DECODER)……………………………………………………………………… VHDL LIBRARY_Sanarwar AMFANI………………………………………………………………………………………………. 33 7.5. Encoder Ports……………………………………………………………………………………………………………………… 33 7.6. Decoder Ports……………………………………………………………………………………………………………………………………………………………………… Ma'auni na rikodin……………………………………………………………………………………………………………………………… 33 7.7. Matsakaicin Dikoda…………………………………………………………………………………………………………………………………………………………………………………
8. Intel FPGA Multiply Adder IP Core………………………………………………………………………………………………………………… 36
8.1. Siffofin……………………………………………………………………………………………………………………………… 37 8.1.1. Pre-Adder……………………………………………………………………………………………………………………………….. 38 8.1.2. Rijistar jinkirin systolic……………………………………………………………………………………….. 40 8.1.3. Constant Pre-loading ………………………………………………………………………………………………………………………………………… Mai tarawa Biyu………………………………………………………………………………………………………………………………………
8.2. Samfurin Verilog HDL……………………………………………………………………………………………………………………………………… 44 8.3. Sanarwa na Bangaren VHDL……………………………………………………………………………………….. 44 8.4. VHDL LIBRARY_Sanarwar AMFANI………………………………………………………………………………………………. 44 8.5. Sigina………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Siga…………………………………………………………………………………………………………………………………………………………………………………
8.6.1. Gabaɗaya Tab………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………….47 8.6.2. Ƙarin Yanayin Tab……………………………………………………………………………………………….. 47 8.6.3. Multipliers Tab………………………………………………………………………………………………………………………….. 49 8.6.4. Tabbatacce……………………………………………………………………………………………… 51 8.6.5. Tambarin tarawa………………………………………………………………………………………………………….. 53 8.6.6. Systolic/Chainout Tab………………………………………………………………………………………………………. 55 8.6.7. Tabbar bututu…………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………
9. ALTMEMMULT (Tsarin Memory Constant Coefficient Multiplier) IP Core……………………………… 57
9.1. Siffofin……………………………………………………………………………………………………………………………… 57 9.2. Samfurin Verilog HDL……………………………………………………………………………………………………………………………………………………… 58 9.3. Sanarwa na Bangaren VHDL……………………………………………………………………………………………….. 58 9.4. Tashoshi ………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Siga…………………………………………………………………………………………………………………………………………………………………………………………………………………
10. ALTMULT_ACCUM (Yawa-Tara) IP Core……………………………………………………… 61
10.1. Fasaloli………………………………………………………………………………………………………………………….. 62 10.2. Samfurin Verilog HDL………………………………………………………………………………………………………..62 10.3. Sanarwa na Bangaren VHDL……………………………………………………………………………………………… 63 10.4. Bayanin VHDL LIBRARY_Amfani………………………………………………………………………………………………………………….63 10.5. Tashoshi……………………………………………………………………………………………………………………………………… 63 10.6. Ma'auni………………………………………………………………………………………………………………………………………. 64
11. ALTMULT_ADD (Multiply-Adder) IP Core………………………………………………………………………………………..69
11.1. Fasaloli………………………………………………………………………………………………………………………….. 71 11.2. Samfurin Verilog HDL………………………………………………………………………………………………………..72 11.3. Sanarwa na Bangaren VHDL……………………………………………………………………………………………… 72 11.4. VHDL LIBRARY_Sanarwar AMFANI………………………………………………………………………………………….72

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Jagorar Mai Amfani da Integer FPGA Integer IP Cores 3

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11.5. Tashoshi……………………………………………………………………………………………………………………………………… 72 11.6. Ma'auni………………………………………………………………………………………………………………………………………. 73
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core……………………………………………………… 86 12.1. Haɗin Haɓakawa…………………………………………………………………………………………………………………………………. 86 12.2. Wakilin Canonical……………………………………………………………………………………………………………………… 87 12.3. Wakilin Al'ada……………………………………………………………………………………………………………… 87 12.4. Fasaloli………………………………………………………………………………………………………………………….. 88 12.5. Samfurin Verilog HDL………………………………………………………………………………………………………..88 12.6. Sanarwa na Bangaren VHDL……………………………………………………………………………………………………… 89 12.7. Bayanin VHDL LIBRARY_Amfani………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Sigina………………………………………………………………………………………………………………………………………. 89 12.8. Ma'auni………………………………………………………………………………………………………………………………………. 89
13. ALTSQRT (Tsarin Integer Square) IP Core………………………………………………………………………………………………………………………….92 13.1. Fasaloli………………………………………………………………………………………………………………………….. 92 13.2. Samfurin Verilog HDL………………………………………………………………………………………………………..92 13.3. Sanarwa na Bangaren VHDL……………………………………………………………………………………………………… 93 13.4. Bayanin VHDL LIBRARY_Amfani………………………………………………………………………………………………………… Tashoshi……………………………………………………………………………………………………………………………………… 93 13.5. Ma'auni………………………………………………………………………………………………………………………………………. 93
14. PARALLEL_ADD (Parallel Adder) IP Core……………………………………………………………………………….. 95 14.1. Siffar……………………………………………………………………………………………………………………………………….95 14.2. Samfurin Verilog HDL……………………………………………………………………………………………………………….95 14.3. Sanarwa na Bangaren VHDL……………………………………………………………………………………………………… 96 14.4. Bayanin VHDL LIBRARY_Amfani………………………………………………………………………………………………………………… Tashoshi……………………………………………………………………………………………………………………………………… 96 14.5. Ma'auni………………………………………………………………………………………………………………………………………. 96
15. Takardun Takaddun Takardun Jagorar Mai Amfani na IP Cores ......................................... 98
16. Tarihin Bita na Takardu don Intel FPGA Integer Arithmetic IP Cores Guide User…. 99

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 4

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683490 | 2020.10.05 Aika Ra'ayoyin

1. Intel FPGA Integer Arthmetic IP Cores

Kuna iya amfani da Intel® FPGA integer IP cores don aiwatar da ayyukan lissafi a cikin ƙirar ku.

Waɗannan ayyuka suna ba da ingantacciyar haɗaɗɗiyar dabaru da aiwatar da na'urar fiye da ƙididdige ayyukan ku. Kuna iya keɓance maƙallan IP don ɗaukar buƙatun ƙirar ku.

Intel integer IP cores an kasu kashi biyu kamar haka: Library of parameterized modules (LPM) IP cores · Intel-specific (ALT) IP cores

Tebu mai zuwa yana lissafin adadin adadin adireshi na IP.

Tebur 1.

List of IP Cores

IP Cores

Farashin LPM IP

LPM_COUNTER

LPM_DIVIDE

LPM_MULT

LPM_ADD_SUB
LPM_COMPARE
Intel Specific (ALT) IP cores ALTECC

Aiki Ya Ƙareview Mai Raba Mai Rabawa
Adder ko Rage Kwatancen
ECC Encoder/Decoder

Na'urar Tallafi
Arria® II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone® IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP,
Intel Cyclone 10 GX, MAX® II, MAX V, MAX 10, Stratix® IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V ya ci gaba…

Kamfanin Intel. An kiyaye duk haƙƙoƙi. Intel, tambarin Intel, da sauran alamun Intel alamun kasuwanci ne na Kamfanin Intel Corporation ko rassan sa. Intel yana ba da garantin aiwatar da samfuran FPGA da semiconductor zuwa ƙayyadaddun bayanai na yanzu daidai da daidaitaccen garanti na Intel, amma yana da haƙƙin yin canje-canje ga kowane samfuri da sabis a kowane lokaci ba tare da sanarwa ba. Intel ba ya ɗaukar wani nauyi ko alhaki da ya taso daga aikace-aikacen ko amfani da kowane bayani, samfur, ko sabis da aka kwatanta a nan sai dai kamar yadda Intel ya yarda da shi a rubuce. An shawarci abokan cinikin Intel su sami sabon sigar ƙayyadaddun na'urar kafin su dogara ga kowane bayanan da aka buga kuma kafin sanya oda don samfur ko ayyuka. *Wasu sunaye da tambura ana iya da'awarsu azaman mallakar wasu.

ISO 9001: 2015 Rajista

1. Intel FPGA Integer Arthmetic IP Cores 683490 | 2020.10.05

IP Cores Intel FPGA Multiply Adder ko ALTERA_MULT_ADD ALTMEMMULT
ALTMULT_ACCUM ALTMULT_ADD ALTMULT_COMPLEX
ALTSQRT
PARALLEL_ADD

Aiki Ya Ƙareview Multiplier-Adder
Constant Coefficient Multiplier na tushen ƙwaƙwalwar ajiya
Multiplier-Accumulator Multiplier-Adder
Complex Multiplier
Integer Square-Root
Parallel Adder

Na'urar Tallafi
Arria V, Stratix V, Cyclone V, Intel Stratix 10, Intel Arria 10, Intel Cyclone
10 GX
Arria II GX, Arria II GZ, Arria V, Intel Arria 10 (Intel Quartus® Prime Standard Edition), Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Cyclone 10 LP, MAX II, MAX V, MAX 10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Intel Arria 10, Arria V, Arria V GZ, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Cyclone 10 GX, Intel Cyclone 10 LP, MAX 10, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V

Bayanai masu alaƙa
· FPGAs na Intel da na'urori masu shirye-shirye na Sakin Bayanan kula
Gabatarwa zuwa Intel FPGA IP Cores Yana ba da ƙarin bayani game da Intel FPGA IP Cores.
Jagoran mai amfani na IP Cores Point-Point Yana ba da ƙarin bayani game da Intel FPGA Floating-Point IP cores.
Gabatarwa zuwa Intel FPGA IP Cores Yana ba da cikakken bayani game da duk Intel FPGA IP Cores, gami da daidaitawa, ƙirƙira, haɓakawa, da kwaikwaiyon ƙirar IP.
Ƙirƙirar sigar-Independent IP da Qsys Rubutun kwaikwaiyo Ƙirƙirar rubutun kwaikwaiyo waɗanda baya buƙatar ɗaukakawar hannu don haɓaka nau'in software ko IP.
· Gudanar da Ayyuka Mafi kyawun Jagororin Ayyuka don ingantaccen gudanarwa da ɗaukar nauyin aikin ku da IP files.
Takaddun Takaddun Takaddun Bayanan Bayanai a shafi na 98 Yana ba da jerin jagororin masu amfani don sigar baya na Integer Arithmetic IP cores.

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 6

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2. LPM_COUNTER (Counter) IP Core

Hoto na 1.

LPM_COUNTER IP core counter ne na binary wanda ke ƙirƙirar ƙididdiga, ƙasa da ƙididdiga sama ko ƙasa tare da fitowar har zuwa 256 fadi.

Hoto mai zuwa yana nuna tashar jiragen ruwa na LPM_COUNTER IP core.

LPM_COUNTER Tashoshi

LPM_COUNTER

ssclr sload bayanan saiti[]

q[]

sabunta zamani

kutut

aclr kayan aiki

clk_en cin
inst

2.1. Features
LPM_COUNTER IP core yana ba da fasalulluka masu zuwa: · Yana haifar da sama, ƙasa, da sama/ƙasa · Yana haifar da nau'ikan ƙira masu zuwa:
- Binaryar da ke bayyana - ƙididdigar ƙididdiga ta farawa daga sifili ko raguwa farawa daga 255
- Modulus – counter yana ƙaruwa zuwa ko raguwa daga ƙimar modul ɗin da mai amfani ya kayyade kuma yana maimaitawa.
Yana goyan bayan fayyace aiki tare na zaɓi na zaɓi, kaya, da saita tashoshin shigarwa · Yana goyan bayan bayyanannun asynchronous na zaɓi, kaya, da saita tashoshin shigarwa · Yana goyan bayan ƙidayar zaɓi yana ba da damar shigar da agogo.

ISO 9001: 2015 Rajista

2. LPM_COUNTER (Counter) IP Core
683490 | 2020.10.05
2.2. Verilog HDL Prototype
Samfurin Verilog HDL mai zuwa yana cikin Tsarin Verilog File (.v) lpm.v a cikin edisynthesis directory.
module lpm_counter (q, data, clock, cin, cout, clk_en, cnt_en, updown, aset, aclr, aload, sset, sclr, sload, eq); siga lpm_type = "lpm_counter"; siga lpm_width = 1; siga lpm_modul = 0; siga lpm_direction = "UNUSED"; siga lpm_avalue = "UNUSED"; siga lpm_svalue = "UNUSED"; siga lpm_pvalue = "UNUSED"; siga lpm_port_updown = "PORT_CONNECTIVITY"; siga lpm_hint = "Ba a yi amfani da su ba"; fitarwa [lpm_width-1:0] q; fitarwa cout; fitarwa [15:0] eq; shigar cin; shigar [lpm_width-1:0] bayanai; agogon shigarwa, clk_en, cnt_en, sama; shigar da dukiya, aclr, kaya; saitin shigarwa, sclr, sload; endmodule
2.3. Bayanin Bangaren VHDL
Bayanin ɓangaren VHDL yana cikin Tsarin VHDL File (.vhd) LPM_PACK.vhd a cikin librariesvhdllpm directory.
bangaren LPM_COUNTER gamayya ( LPM_WIDTH: na halitta; LPM_MODULUS: na halitta: = 0; LPM_DIRECTION: kirtani: = "Ba a yi amfani da su ba"; LPM_AVALUE : kirtani: = "Ba a amfani da shi"; LPM_SVALUE: na halitta: string : = "Ba a amfani da shi"; LPM_AVALUE ; LPM_PVALUE : kirtani: = "Ba a amfani da shi"; LPM_TYPE: kirtani: = L_COUNTER; LPM_HINT: kirtani: = "Ba a amfani da shi"); tashar jiragen ruwa (DATA: a cikin std_logic_vector(LPM_WIDTH-1 zuwa 0):= (OTHERS =>
'0'); CLOCK: a cikin std_logic ; CLK_EN: a cikin std_logic: = '1'; CNT_EN: a cikin std_logic: = '1'; UPDOWN : a cikin std_logic: = '1'; SLOAD: a cikin std_logic: = '0'; SSET: a cikin std_logic: = '0'; SCLR: a cikin std_logic: = '0'; ALOAD: a cikin std_logic: = '0'; ASET : a cikin std_logic: = '0'; ACLR: a cikin std_logic: = '0'; CIN : in std_logic: = '1'; COUT : fita std_logic: = '0'; Q: fita std_logic_vector(LPM_WIDTH-1 zuwa 0); EQ: fita std_logic_vector (15 zuwa 0));
bangaren ƙarshe;

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 8

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2. LPM_COUNTER (Counter) IP Core 683490 | 2020.10.05

2.4. Bayanin VHDL LIBRARY_USE
Ba a buƙatar bayanin VHDL LIBRARY-USE idan kuna amfani da Sanarwa na Bangaren VHDL.
LABARI: lpm; AMFANI DA lpm.lpm_components.duk;

2.5. Tashoshi

Tebura masu zuwa suna jera abubuwan shigarwa da tashar jiragen ruwa na LPM_COUNTER IP core.

Tebur 2.

LPM_COUNTER Mashigai na Shigarwa

Sunan tashar jiragen ruwa

Da ake bukata

Bayani

bayanai[]

A'a

Daidaitaccen shigar da bayanai zuwa ma'auni. Girman tashar shigarwar ya dogara da ƙimar siga LPM_WIDTH.

agogo

Shigarwar agogo mai kyau-baki-jawowa.

clk_in

A'a

Agogo yana ba da damar shigarwa don kunna duk ayyukan aiki tare. Idan an cire shi, ƙimar tsoho shine 1.

cnt_en

A'a

Ƙididdiga yana ba da damar shigarwa don kashe ƙirga lokacin da aka tabbatar da ƙasa ba tare da rinjayar sload, sset, ko sclr ba. Idan an cire shi, ƙimar tsoho shine 1.

sabunta zamani

A'a

Yana sarrafa alkiblar kirga. Lokacin da aka tabbatar da girma (1), alkiblar ƙidayar tana sama, kuma lokacin da aka tabbatar ƙaramar (0), alkiblar ƙidayar tana ƙasa. Idan ana amfani da ma'aunin LPM_DIRECTION, ba za a iya haɗa tashar saukar da tashar ba. Idan ba a yi amfani da LPM_DIRECTION ba, tashar saukarwa na zaɓi ne. Idan an cire shi, ƙimar tsoho ta haura (1).

cin

A'a

Ci gaba da zuwa ƙaramin tsari. Don masu ƙidayar sama, halin shigar cin shine

yayi daidai da halayen shigarwar cnt_en. Idan an cire shi, ƙimar tsoho shine 1

(VCC).

aclr

A'a

Matsakaicin shigar da asynchronous. Idan an yi amfani da duk aset da aclr kuma an tabbatar da su, aclr ya soke kadara. Idan an cire shi, ƙimar tsoho ita ce 0 (an kashe).

dukiya

A'a

Shigar da saitin asynchronous. Yana ƙayyade abubuwan q[] a matsayin duk 1s, ko zuwa ƙimar da aka ƙayyade ta ma'aunin LPM_AVALUE. Idan an yi amfani da duka kadara da tashoshin aclr kuma an tabbatar da su, ƙimar tashar aclr ta zarce ƙimar tashar tashar kadara. Idan an cire shi, ƙimar tsoho ita ce 0, an kashe.

kayatarwa

A'a

Shigar da kaya asynchronous wanda asynchronously loda ma'aunin tare da kimar shigar da bayanai. Lokacin da ake amfani da tashar jiragen ruwa, dole ne a haɗa tashar tashar data[]. Idan an cire shi, ƙimar tsoho ita ce 0, an kashe.

sclr

A'a

Shigar da bayanai mai aiki tare wanda ke share ma'aunin a gefen agogo mai aiki na gaba. Idan an yi amfani da tashoshin sset da na sclr kuma an tabbatar da su, ƙimar tashar tashar sclr ta zarce darajar tashar jiragen ruwa. Idan an cire shi, ƙimar tsoho ita ce 0, an kashe.

saita

A'a

shigarwar saitin aiki tare wanda ke saita counter akan gefen agogo mai aiki na gaba. Yana ƙayyade ƙimar abubuwan fitar da q a matsayin duk 1s, ko zuwa ƙimar da ma'aunin LPM_SVALUE ya kayyade. Idan an yi amfani da tashoshin sset da sclr kuma an tabbatar da su,
darajar tashar jiragen ruwa na sclr ta zarce darajar tashar jiragen ruwa. Idan an cire shi, ƙimar tsoho ita ce 0 (an kashe).

zage-zage

A'a

Shigar da kaya na aiki tare wanda ke loda ma'ajin tare da bayanai[] a gefen agogo mai aiki na gaba. Lokacin da ake amfani da tashar jiragen ruwa, dole ne a haɗa tashar tashar bayanai. Idan an cire shi, ƙimar tsoho ita ce 0 (an kashe).

Aika da martani

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 9

2. LPM_COUNTER (Counter) IP Core 683490 | 2020.10.05

Tebur 3.

LPM_COUNTER Mashigai Fitowa

Sunan tashar jiragen ruwa

Da ake bukata

Bayani

q[]

A'a

Fitowar bayanai daga ma'auni. Girman tashar fitarwa ya dogara da

ƙimar siga LPM_WIDTH. Ko dai q[] ko aƙalla ɗaya daga cikin eq[15..0].

dole ne a haɗa.

kuma[15]

A'a

Ƙaddamar da fitarwa. Ba a samun damar tashar tashar eq[15..0] a cikin editan sigar saboda siga tana goyan bayan AHDL kawai.
Dole ne a haɗa tashar q[] ko eq[]. Ana iya amfani da tashar jiragen ruwa har zuwa c eq (0 <= c <= 15). Ƙididdigar ƙididdiga mafi ƙasƙanci 16 ne kawai aka yanke. Lokacin da ƙimar ƙidaya ta c, ana tabbatar da fitowar eqc babba (1). Don misaliample, lokacin da ƙidayar ta kasance 0, eq0 = 1, lokacin da ƙidayar ta kasance 1, eq1 = 1, kuma lokacin da ƙidayar ta kasance 15, eq 15 = 1. Ƙididdigar fitarwa don ƙididdige ƙimar 16 ko mafi girma yana buƙatar ƙaddamarwa na waje. Abubuwan eq[15..0] sun yi daidai da fitowar q[].

kutut

A'a

Ci gaba da tashar jiragen ruwa na na'urar ta MSB bit. Ana iya amfani da shi don haɗawa zuwa wani counter don ƙirƙirar ƙira mafi girma.

2.6. Sigogi

Tebur mai zuwa yana lissafin sigogi na LPM_COUNTER IP core.

Tebur 4.

Ma'auni LPM_COUNTER

Sunan Siga

Nau'in

LPM_WIDTH

lamba

LPM_DIRECTION

Zaren

LPM_MODULUS LPM_AVALUE

lamba
Integer/Kira

LPM_SVALUE LPM_HINT

Integer/Kira
Zaren

LPM_TYPE

Zaren

Ana buƙata Ee A'a A'a
A'a A'a
A'a

Bayani
Yana ƙayyade faɗin bayanan[] da q[] tashar jiragen ruwa, idan ana amfani da su.
Ƙimar sun KYAU, KASA, kuma BA a amfani da su. Idan ana amfani da ma'aunin LPM_DIRECTION, ba za a iya haɗa tashar saukar da tashar ba. Lokacin da ba a haɗa tashar jiragen ruwa na sama ba, ƙimar tsohowar siga LPM_DIRECTION ita ce UP.
Matsakaicin ƙidaya, da ɗaya. Adadin jihohi na musamman a cikin zagayowar na'urar. Idan ƙimar lodi ta fi ma'aunin LPM_MODULUS girma, ba a ƙayyade halin ma'ajiya ba.
Ƙimar dindindin da ake lodawa lokacin da aka tabbatar da kadara mai girma. Idan ƙimar da aka ƙayyade ta fi girma ko daidai da ita , Halayen ma'auni matakin tunani ne wanda ba a bayyana shi ba (X), inda shine LPM_MODULUS, idan akwai, ko 2 ^ LPM_WIDTH. Intel yana ba da shawarar cewa ka saka wannan ƙimar azaman lambar ƙima don ƙirar AHDL.
Ƙimar dindindin da aka ɗorawa a gefen tashin agogon tashar agogo lokacin da aka tabbatar da babban tashar jiragen ruwa. Intel yana ba da shawarar cewa ka saka wannan ƙimar azaman lambar ƙima don ƙirar AHDL.
Lokacin da kuka aiwatar da aikin laburare na ma'auni (LPM) a cikin Tsarin VHDL File (.vhd), dole ne ka yi amfani da sigar LPM_HINT don tantance takamaiman ma'aunin Intel. Don misaliample: LPM_HINT = "CHAIN_SIZE = 8, DAYA_INPUT_IS_CONSTANT = YES"
Tsohuwar ƙimar ba ta da amfani.
Gano ɗakin karatu na ma'auni na ma'auni (LPM) sunan mahaɗan a cikin ƙirar VHDL files.
ci gaba…

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 10

Aika da martani

2. LPM_COUNTER (Counter) IP Core 683490 | 2020.10.05

Sunan sigar INTENDED_DEVICE_FAMILY CARRY_CNT_EN
LABWIDE_SCLR
LPM_PORT_UPDOWN

Nau'in Kirtani
Zaren
Zaren

Da ake bukata No
A'a
A'a

Bayani
Ana amfani da wannan siga don ƙirar ƙira da dalilai na kwaikwayo na ɗabi'a. Ana amfani da wannan siga don ƙirar ƙira da dalilai na kwaikwayo na ɗabi'a. Editan siga yana ƙididdige ƙimar wannan siga.
Intel-takamaiman siga. Dole ne ku yi amfani da sigar LPM_HINT don tantance ma'aunin CARRY_CNT_EN a ƙirar VHDL files. Ƙimar suna SMART, ON, KASHE, da BA a yi amfani da su ba. Yana kunna aikin LPM_COUNTER don yada siginar cnt_en ta cikin sarkar ɗauka. A wasu lokuta, saitin ma'aunin CARRY_CNT_EN na iya yin ɗan tasiri akan saurin, don haka kuna iya kashe shi. Ƙimar tsoho ita ce SMART, wanda ke ba da mafi kyawun ciniki tsakanin girma da sauri.
Intel-takamaiman siga. Dole ne ku yi amfani da sigar LPM_HINT don tantance ma'aunin LABWIDE_SCLR a ƙirar VHDL files. Ƙimar suna AUNA, A KASHE, ko BABU AMFANI. Tsohuwar ƙimar tana kunne. Yana ba ku damar musaki amfani da fasalin LABwide sclr da aka samu a cikin tsoffin na'urori. Kashe wannan zaɓi yana ƙara damar yin amfani da cikakken LABs masu cike da ɓangarori, kuma ta haka na iya ba da damar haɓaka ƙima yayin da SCLR bai shafi cikakken LAB ba. Ana samun wannan siga don dacewa da baya, kuma Intel yana ba ku shawarar kada ku yi amfani da wannan siga.
Yana ƙayyadaddun amfani da tashar shigar da sama. Idan an cire tsohuwar ƙimar ita ce PORT_CONNECTIVITY. Lokacin da aka saita ƙimar tashar zuwa PORT_USED, ana kula da tashar kamar yadda aka yi amfani da ita. Lokacin da aka saita ƙimar tashar jiragen ruwa zuwa PORT_UNUSED, ana ɗaukar tashar azaman mara amfani. Lokacin da aka saita ƙimar tashar tashar zuwa PORT_CONNECTIVITY, ana ƙayyade amfani da tashar ta hanyar duba haɗin tashar jiragen ruwa.

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683490 | 2020.10.05 Aika Ra'ayoyin

3. LPM_DIVIDE (Divide) Intel FPGA IP Core

Hoto na 2.

LPM_DIVIDE Intel FPGA IP core yana aiwatar da mai rarraba don raba ƙimar shigar da lamba ta ƙimar shigar da maƙalli don samar da ƙima da saura.

Hoto mai zuwa yana nuna tashar jiragen ruwa na LPM_DIVIDE IP core.

LPM_DIVIDE Tashoshi

LPM_DIVIDE

lamba[] denom[] agogo

magana[] saura[]

cin aclr

inst

3.1. Features
LPM_DIVIDE IP core yana ba da fasalulluka masu zuwa: · Yana samar da mai rarrabawa wanda ke raba ƙimar shigar da ƙima ta hanyar shigar da ƙima.
darajar don samar da ƙima da saura. Yana goyan bayan faɗin bayanai na 1 bits. · Yana goyan bayan sa hannu da tsarin wakilcin bayanan da ba a sanya hannu ba don duka mai ƙididdigewa
da ƙimar ƙima. · Yana goyan bayan haɓaka yanki ko saurin gudu. · Yana ba da zaɓi don tantance ingantaccen abin da ya rage. Yana goyan bayan latency mai daidaita bututun mai. Yana goyan bayan zaɓin asynchronous bayyananne da agogo yana ba da damar tashar jiragen ruwa.

3.2. Verilog HDL Prototype
Samfurin Verilog HDL mai zuwa yana cikin Tsarin Verilog File (.v) lpm.v a cikin edisynthesis directory.
module lpm_divide ( quotient, saura, lamba, denom, agogo, clken, aclr); siga lpm_type = "lpm_divide"; siga lpm_widthn = 1; siga lpm_widthd = 1; siga lpm_nrepresentation = "Ba a SIGNED"; siga lpm_drepresentation = "Ba a SIGNED"; siga lpm_remainderpositive = "GASKIYA"; siga lpm_pipeline = 0;

ISO 9001: 2015 Rajista

3. LPM_DIVIDE (Divide) Intel FPGA IP Core 683490 | 2020.10.05

siga lpm_hint = "Ba a yi amfani da su ba"; agogon shigarwa; shigar da klken; shigar da aclr; shigar [lpm_widthn-1:0] lamba; shigar [lpm_widthd-1:0] denom; fitarwa [lpm_widthn-1:0] quotient; fitarwa [lpm_widthd-1:0] ya rage; endmodule

3.3. Bayanin Bangaren VHDL
Bayanin ɓangaren VHDL yana cikin Tsarin VHDL File (.vhd) LPM_PACK.vhd a cikin librariesvhdllpm directory.
bangaren LPM_DIVIDE gama gari (LPM_WIDTHN: na halitta; LPM_WIDTHD: na halitta;
LPM_NWAKILI: kirtani: = "Ba a sanya hannu ba"; LPM_DRESENTATION : kirtani: = "Ba a sanya hannu ba"; LPM_PIPELINE : na halitta: = 0; LPM_TYPE : kirtani: = L_DIVIDE; LPM_HINT: kirtani: = "Ba a amfani da shi"); tashar jiragen ruwa (NUMER: a cikin std_logic_vector (LPM_WIDTHN-1 zuwa 0); DENOM : a cikin std_logic_vector (LPM_WIDTHD-1 zuwa 0); ACLR: a cikin std_logic: = '0'; CLOCK: a cikin std_logic: CL= 'std : = '0'; QUOTIENT: fita std_logic_vector(LPM_WIDTHN-1 zuwa 1); REMAIN: fita std_logic_vector (LPM_WIDTHD-0 zuwa 1)); bangaren ƙarshe;

3.4. Bayanin VHDL LIBRARY_USE
Ba a buƙatar bayanin VHDL LIBRARY-USE idan kuna amfani da Sanarwa na Bangaren VHDL.
LABARI: lpm; AMFANI DA lpm.lpm_components.duk;

3.5. Tashoshi

Tebura masu zuwa suna jera abubuwan shigarwa da tashar jiragen ruwa na LPM_DIVIDE IP core.

Tebur 5.

LPM_DIVIDE Mashigai na Shigarwa

Sunan tashar jiragen ruwa

Da ake bukata

lamba[]

denom[]

Bayani
Shigar da bayanan ƙididdigewa. Girman tashar shigarwar ya dogara da ƙimar sigar LPM_WIDTHN.
Shigar da ƙima. Girman tashar shigarwar ya dogara da ƙimar siga LPM_WIDTHD.
ci gaba…

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3. LPM_DIVIDE (Divide) Intel FPGA IP Core 683490 | 2020.10.05

Agogon sunan tashar jiragen ruwa
aclr

Da ake bukata No
A'a

Bayani
Shigar da agogo don amfani da bututun mai. Don ƙimar LPM_PIPELINE banda 0 (tsoho), dole ne a kunna tashar agogo.
Agogo yana ba da damar amfani da bututun mai. Lokacin da aka tabbatar da tashar tashar klken mai girma, aikin rarraba yana faruwa. Lokacin da siginar tayi ƙasa, babu wani aiki da ke faruwa. Idan an cire shi, ƙimar tsoho shine 1.
Asynchronous clear port da ake amfani dashi a kowane lokaci don sake saita bututun zuwa duk '0's asynchronously zuwa shigar da agogo.

Tebur 6.

LPM_DIVIDE Mashigai Fitowa

Sunan tashar jiragen ruwa

Da ake bukata

Bayani

magana[]

Fitar bayanai. Girman tashar fitarwa ya dogara da LPM_WIDTHN

ƙimar siga.

zauna[]

Fitar bayanai. Girman tashar fitarwa ya dogara da LPM_WIDTHD

ƙimar siga.

3.6. Sigogi

Tebur mai zuwa yana lissafin sigogi don LPM_DIVIDE Intel FPGA IP core.

Sunan Siga

Nau'in

Da ake bukata

Bayani

LPM_WIDTHN

lamba

Yana ƙayyade nisa na lamba[] da

tashar jiragen ruwa[]. Ƙimar ita ce 1 zuwa 64.

LPM_WIDTHD

lamba

Yana ƙayyadaddun faɗin ma'aunin ƙima[] da

zauna[] tashar jiragen ruwa. Ƙimar ita ce 1 zuwa 64.

LPM_NREPRESENTATION LPM_DREPRESENTATION

Zaren Zaren

A'a

Alamar wakilcin shigarwar lamba.

An SANYA KYAUTA kuma BA a sanya hannu ba. Lokacin da wannan

an saita siga zuwa SIGNED, mai rarrabawa

yana fassara shigarwar lamba[] kamar yadda aka sa hannu biyu

cika.

A'a

Alamar wakilcin shigarwar ƙima.

An SANYA KYAUTA kuma BA a sanya hannu ba. Lokacin da wannan

an saita siga zuwa SIGNED, mai rarrabawa

yana fassara shigarwar denom[] kamar yadda aka sa hannu na biyu

cika.

LPM_TYPE

Zaren

A'a

Gano ɗakin karatu na parameterized

modules (LPM) sunan mahaluži a cikin ƙirar VHDL

files (.vhd).

LPM_HINT

Zaren

A'a

Lokacin da kuka kunna ɗakin karatu na

parameterized modules (LPM) aiki a cikin a

Farashin VHDL File (.vhd), dole ne ka yi amfani da

LPM_HINT siga don tantance Intel-

takamaiman siga. Don misaliampda: LPM_HINT

= "CHAIN_SIZE = 8,

DAYA_INPUT_IS_CONSTANT = YES” The

TSOHUWAR darajar ba ta da amfani.

LPM_REMAINDER POSITIVE

Zaren

A'a

Intel-takamaiman siga. Dole ne ku yi amfani da

Sigar LPM_HINT don tantance

LPM_REMAINDERPOSITIVE siga a ciki

Farashin VHDL files. Dabi'u GASKIYA ne ko KARYA.

Idan an saita wannan sigar zuwa GASKIYA, to

ƙimar ragowar[] tashar jiragen ruwa dole ne ta fi girma

ci gaba…

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 14

Aika da martani

3. LPM_DIVIDE (Divide) Intel FPGA IP Core 683490 | 2020.10.05

Sunan Siga

Nau'in

MAXIMIZE_SPEED

lamba

LPM_PIPELINE

lamba

INTENDED_DEVICE_FAMILY SKIP_BITS

Adadin kirtani

Da ake bukata A'a
Babu Babu Babu

Bayani
fiye ko daidai da sifili. Idan an saita wannan siga zuwa GASKIYA, to ƙimar tashar tashar ta rage[] ko dai sifili ne, ko ƙimar ita ce alama ɗaya, ko dai tabbatacce ko mara kyau, azaman ƙimar tashar lamba. Don rage yanki da haɓaka gudu, Intel yana ba da shawarar saita wannan siga zuwa GASKIYA a cikin ayyukan da ragowar dole ne ya zama tabbatacce ko kuma inda ragowar ba shi da mahimmanci.
Intel-takamaiman siga. Dole ne ku yi amfani da sigar LPM_HINT don tantance ma'aunin MAXIMIZE_SPEED a ƙirar VHDL files. Darajoji sune [0..9]. Idan aka yi amfani da shi, Intel Quartus Prime software yana ƙoƙarin inganta takamaiman misali na aikin LPM_DIVIDE don saurin aiki maimakon daidaitawa, kuma ya soke saitin zaɓi na Haɓaka Dabarun dabaru. Idan MAXIMIZE_SPEED ba a yi amfani da shi ba, ana amfani da ƙimar zaɓin Fasahar Ingantawa maimakon. Idan darajar MAXIMIZE_SPEED ita ce 6 ko sama da haka, Mai Haɗawa yana inganta LPM_DIVIDE IP core don mafi girma ta hanyar amfani da sarƙoƙi; idan darajar ta kasance 5 ko ƙasa da haka, mai tarawa yana aiwatar da ƙira ba tare da ɗaukar sarƙoƙi ba.
Yana ƙayyadadden adadin zagayowar agogo na jinkirin da ke da alaƙa da adadin[] kuma ya kasance[] fitarwa. Ƙimar sifili (0) tana nuna cewa babu jinkiri, kuma ana aiwatar da aikin haɗin kai kawai. Idan an cire shi, ƙimar tsoho ita ce 0 (mara bututu). Ba za ku iya tantance ƙimar ma'aunin LPM_PIPELINE da ta fi LPM_WIDTHN girma ba.
Ana amfani da wannan siga don ƙirar ƙira da dalilai na kwaikwayo na ɗabi'a. Editan siga yana ƙididdige ƙimar wannan siga.
Yana ba da izinin ƙwaƙƙwarar rarrabuwar ɓoyayyiyar juzu'i don haɓaka dabaru akan manyan raƙuman ruwa ta hanyar samar da adadin jagorar GND zuwa LPM_DIVIDE IP core. Ƙayyade adadin manyan GND akan fitarwar ƙima zuwa wannan siga.

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683490 | 2020.10.05 Aika Ra'ayoyin

4. LPM_MULT (Multiplier) IP Core

Hoto na 3.

LPM_MULT IP core yana aiwatar da mai ninka don ninka ƙimar bayanan shigarwa guda biyu don samar da samfur azaman fitarwa.

Hoto mai zuwa yana nuna tashar jiragen ruwa na LPM_MULT IP core.

LPM_Mult Ports

LPM_MULT bayanan agogo [] sakamako[] datab[] aclr/sclr clken
inst

Siffofin Bayani masu alaƙa a shafi na 71

4.1. Features
LPM_MULT IP core yana ba da fasali kamar haka: · Yana samar da mai ninkawa wanda ke ninka ƙimar bayanan shigarwa guda biyu · Yana goyan bayan faɗin bayanai na 1 bits · Yana goyan bayan sa hannu da tsarin wakilcin bayanan da ba a sanya hannu ba · Yana goyan bayan inganta yanki ko haɓakawa da sauri · Yana goyan bayan bututun mai da latency mai daidaitawa · Yana ba da wani tsari. zaɓi don aiwatarwa a cikin aikin sarrafa siginar dijital (DSP)
toshe kewayawa ko abubuwan dabaru (LEs) Lura: Lokacin gina masu ninka girma fiye da girman goyan baya na asali ana iya/
zai zama tasirin aiki wanda ya haifar da rushewar tubalan DSP. Yana goyan bayan share fage na asynchronous na zaɓi da agogo yana ba da damar shigar da tashar jiragen ruwa · Yana goyan bayan tsararren aiki tare na zaɓi don Intel Stratix 10, Intel Arria 10 da na'urorin Intel Cyclone 10 GX

ISO 9001: 2015 Rajista

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05
4.2. Verilog HDL Prototype
Samfurin Verilog HDL mai zuwa yana cikin Tsarin Verilog File (.v) lpm.v a cikin edisynthesis directory.
module lpm_mult (sakamako, dataa, datab, jimla, agogo, clken, aclr ) siga lpm_type = "lpm_mult"; siga lpm_widtha = 1; siga lpm_widthb = 1; siga lpm_widths = 1; siga lpm_widthp = 1; siga lpm_representation = "UNSIGNED"; siga lpm_pipeline = 0; siga lpm_hint = "Ba a yi amfani da su ba"; agogon shigarwa; shigar da klken; shigar da aclr; shigar [lpm_widtha-1:0] data; shigar [lpm_widthb-1:0] datab; shigar [lpm_widths-1:0] jimla; fitarwa [lpm_widthp-1:0] sakamako; endmodule
4.3. Bayanin Bangaren VHDL
Bayanin ɓangaren VHDL yana cikin Tsarin VHDL File (.vhd) LPM_PACK.vhd a cikin librariesvhdllpm directory.
bangaren LPM_MULT generic ( LPM_WIDTHA : na halitta; LPM_WIDTHB : na halitta; LPM_WIDTHS : na halitta: = 1; LPM_WIDTHP : na halitta;
LPM_WAKILI: kirtani: = "Ba a sanya hannu ba"; LPM_PIPELINE : na halitta: = 0; LPM_TYPE: kirtani: = L_MULT; LPM_HINT: kirtani: = "Ba a amfani da shi"); tashar jiragen ruwa (DATAA: a cikin std_logic_vector (LPM_WIDTHA-1 zuwa 0); DATAB: a cikin std_logic_vector (LPM_WIDTHB-1 zuwa 0); ACLR: a cikin std_logic: = '0'; CLOCK: a cikin std_logic: CL=' std : = '0'; SUM : a cikin std_logic_vector (LPM_WIDTHS-1 zuwa 1): = (OTHERS => '0'); SAKAMAKO: fita std_logic_vector (LPM_WIDTHP-0 zuwa 1)); bangaren ƙarshe;
4.4. Bayanin VHDL LIBRARY_USE
Ba a buƙatar bayanin VHDL LIBRARY-USE idan kuna amfani da Sanarwa na Bangaren VHDL.
LABARI: lpm; AMFANI DA lpm.lpm_components.duk;

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4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

4.5. Sigina

Tebur 7.

LPM_MULT Siginan Shigarwa

Sunan siginar

Da ake bukata

Bayani

data[]

Shigar da bayanai.

Don Intel Stratix 10, Intel Arria 10, da Intel Cyclone 10 GX na'urorin, girman siginar shigarwa ya dogara da ƙimar ma'aunin faɗin Dataa.

Don tsofaffi da na'urorin Intel Cyclone 10 LP, girman siginar shigarwa ya dogara da ƙimar siga LPM_WIDTHA.

data[]

Shigar da bayanai.

Don Intel Stratix 10, Intel Arria 10, da Intel Cyclone 10 GX na'urorin, girman siginar shigarwa ya dogara da ƙimar ma'aunin faɗin Datab.

Don tsofaffi da na'urorin Intel Cyclone 10 LP, girman siginar shigarwa ya dogara

akan ƙimar ma'aunin LPM_WIDTHB.

agogo

A'a

Shigar da agogo don amfani da bututun mai.

Don tsofaffi da na'urorin Intel Cyclone 10 LP, dole ne a kunna siginar agogo don ƙimar LPM_PIPELINE banda 0 (tsoho).

Don Intel Stratix 10, Intel Arria 10, da Intel Cyclone 10 GX na'urorin, dole ne a kunna siginar agogo idan ƙimar Latency ban da 1 (tsoho).

ƙulla

A'a

Kunna agogo don amfani da bututun mai. Lokacin da aka tabbatar da siginar claken babba, da

Adder/Subtractor aiki yana faruwa. Lokacin da siginar tayi ƙasa, babu aiki

faruwa. Idan an cire shi, ƙimar tsoho shine 1.

ku sclr

A'a

Siginar da aka yi amfani da ita a kowane lokaci don sake saita bututun zuwa duk 0s,

asynchronously zuwa siginar agogo. Bututun yana farawa zuwa wanda ba a bayyana shi ba (X)

matakin dabaru. Abubuwan da aka fitar sun daidaita, amma ƙima mara sifili.

A'a

Sigina bayyanannen aiki tare da ake amfani dashi a kowane lokaci don sake saita bututun zuwa duk 0s,

daidai da siginar agogo. Bututun yana farawa zuwa wanda ba a bayyana shi ba (X)

matakin dabaru. Abubuwan da aka fitar sun daidaita, amma ƙima mara sifili.

Tebur 8.

LPM_MULT Sigina na fitarwa

Sunan sigina

Da ake bukata

Bayani

sakamako[]

Fitar bayanai.

Don tsofaffi da na'urorin Intel Cyclone 10 LP, girman siginar fitarwa ya dogara da ƙimar siga LPM_WIDTHP. Idan LPM_WIDTHP <max (LPM_WIDTHA + LPM_WIDTHB, LPM_WIDTHS) ko (LPM_WIDTHA + LPM_WIDTHS), LPM_WIDTHP MSBs kawai ke nan.

Don Intel Stratix 10, Intel Arria 10 da Intel Cyclone 10 GX, girman siginar fitarwa ya dogara da ma'aunin faɗin sakamako.

4.6. Ma'auni don Stratix V, Arria V, Cyclone V, da Intel Cyclone 10 LP Na'urorin

4.6.1. Gabaɗaya Tab

Tebur 9.

Gabaɗaya Tab

Siga

Daraja

Kanfigareshan Multiplier

Ƙirƙirar shigarwar 'data' ta hanyar shigar da 'datab'

Default Value

Bayani

Ƙirƙirar shigarwar 'data' ta hanyar shigar da 'datab'

Zaɓi tsarin da ake so don mai yawa.
ci gaba…

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4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

Siga
Yaya fadi ya kamata shigar da 'data' ya kasance? Yaya fadi ya kamata shigar da 'datab' ya kasance? Ta yaya za a tantance nisa na fitowar 'sakamako'? Ƙuntata faɗin

Daraja
Ƙirƙirar shigarwar 'data' da kanta (aikin murabba'i)
1-256 guda

Default Value

Bayani

8 bits

Ƙayyade faɗin tashar tashar bayanai[].

1-256 guda

8 bits

Ƙayyade faɗin tashar tashar bayanai[].

Lissafta nisa ta atomatik Ƙuntata faɗin
1-512 guda

Ta atomatik y lissafta faɗin

Zaɓi hanyar da ake so don tantance faɗin tashar tashar sakamakon[].

16 bits

Ƙayyade nisa na tashar tashar [] sakamakon.
Wannan ƙimar za ta yi tasiri kawai idan kun zaɓi Ƙuntata nisa a cikin sigar Nau'in.

4.6.2. Gabaɗaya 2 Tab

Tebur 10. Gabaɗaya 2 Tab

Siga

Daraja

Shigar da Bayanai

Shin bas ɗin shigar da 'datab' yana da ƙima koyaushe?

A'a Ee

Nau'in Yawa

Wani irin

Ba a sanya hannu ba

ninkawa kuke so? Sa hannu

Aiwatarwa

Wanne aiwatar da ninkawa ya kamata a yi amfani da shi?

Yi amfani da tsoho aiwatarwa
Yi amfani da keɓaɓɓen keɓaɓɓen kewayawa mai yawa (Ba samuwa ga duk iyalai)
Yi amfani da abubuwan tunani

Default Value

Bayani

A'a

Zaɓi Ee don ƙididdige ƙimar ƙimar

Bus shigar datab, idan akwai.

Ba a sanya hannu ba

Ƙayyade tsarin wakilci na duka bayanai[] da bayanai[] bayanai.

Yi amfani da tsoho aiwatar da ion

Zaɓi hanyar da ake so don tantance faɗin tashar tashar sakamakon[].

4.6.3. Tabbar bututun mai

Tebur 11. Tabbar bututun mai

Siga

Kuna son bututun mai No

aiki?

Daraja

Ƙirƙiri 'aclr'

—

asynchronous share tashar jiragen ruwa

Default Value

Bayani

A'a

Zaɓi Ee don kunna rajistar bututun mai zuwa

fitarwa mai yawa kuma saka abin da ake so

latency fitarwa a cikin zagayowar agogo. Ana kunna

rajistar bututun yana ƙara ƙarin jinkiri ga

fitarwa.

Ba a tantance ba

Zaɓi wannan zaɓi don kunna tashar tashar aclr don amfani da asynchronous share don rajistar bututun.
ci gaba…

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Siga
Ƙirƙiri agogon kunna agogon 'clken'
Ingantawa
Wane irin ingantawa kuke so?

Darajar -
Wurin Gudun Tsohuwar

Default Value

Bayani

Ba a tantance ba

Yana ƙayyadad da damar babban agogo mai aiki don tashar agogon rajistar bututun mai

Default

Ƙayyade haɓakawa da ake so don ainihin IP.
Zaɓi Default don barin Intel Quartus Prime software don tantance mafi kyawun haɓakawa ga ainihin IP.

4.7. Ma'auni don Intel Stratix 10, Intel Arria 10, da Intel Cyclone 10 GX na'urorin

4.7.1. Gabaɗaya Tab

Tebur 12. Gabaɗaya Tab

Siga

Daraja

Default Value

Bayani

Nau'in Kanfigareshan Multiplier
Faɗin Tashar Data

Ƙirƙirar shigarwar 'data' ta hanyar shigar da 'datab'
Ƙirƙirar shigarwar 'data' da kanta (aikin murabba'i)

Ƙirƙirar shigarwar 'data' ta hanyar shigar da 'datab'

Zaɓi tsarin da ake so don mai yawa.

Faɗin Data

1-256 guda

8 bits

Ƙayyade faɗin tashar tashar bayanai[].

Faɗin bayanai

1-256 guda

8 bits

Ƙayyade faɗin tashar tashar bayanai[].

Ta yaya za a tantance nisa na fitowar 'sakamako'?

Nau'in

Lissafin faɗin ta atomatik
Ƙuntata faɗin

Ta atomatik y lissafta faɗin

Zaɓi hanyar da ake so don tantance faɗin tashar tashar sakamakon[].

Daraja

1-512 guda

16 bits

Ƙayyade nisa na tashar tashar [] sakamakon.
Wannan ƙimar za ta yi tasiri kawai idan kun zaɓi Ƙuntata nisa a cikin sigar Nau'in.

Faɗin sakamako

1-512 guda

—

Yana Nuna tasiri mai faɗin tashar tashar tashar sakamakon[].

4.7.2. Gabaɗaya 2 Tab

Tebur 13. Gabaɗaya 2 Tab

Siga

Shigar da Bayanai

Shin bas ɗin shigar da 'datab' yana da ƙima koyaushe?

A'a Ee

Daraja

Default Value

Bayani

A'a

Zaɓi Ee don ƙididdige ƙimar ƙimar

Bus shigar datab, idan akwai.

ci gaba…

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 20

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4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

Siga

Daraja

Duk wani darajar da ta fi 0

Nau'in Yawa

Wani irin

Ba a sanya hannu ba

ninkawa kuke so? Sa hannu

Salon aiwatarwa

Wanne aiwatar da ninkawa ya kamata a yi amfani da shi?

Yi amfani da tsoho aiwatarwa
Yi amfani da keɓaɓɓen keɓaɓɓen da'ira mai yawa
Yi amfani da abubuwan tunani

Default Value

Bayani

Ƙayyade yawan ƙimar datab[] tashar jiragen ruwa.

Ba a sanya hannu ba

Ƙayyade tsarin wakilci na duka bayanai[] da bayanai[] bayanai.

Yi amfani da tsoho aiwatar da ion

Zaɓi hanyar da ake so don tantance faɗin tashar tashar sakamakon[].

4.7.3. Bututun man fetur

Tebur 14. Tabbar bututun mai

Siga

Daraja

Kuna son bututun aikin?

Bututu

A'a Ee

Nau'in Siginar Latency

Duk wani darajar da ta fi 0.
BABU ACLR SCLR

Ƙirƙiri agogon 'clken'

—

kunna agogo

Wane irin ingantawa kuke so?

Nau'in

Wurin Gudun Tsohuwar

Default Value

Bayani

A'a 1 BABU
—

Zaɓi Ee don ba da damar yin rijistar bututun mai zuwa fitarwar mai yawa. Ƙaddamar da rajistar bututun yana ƙara ƙarin jinkiri ga fitarwa.
Ƙayyade jinkirin fitarwa da ake so a zagayowar agogo.
Ƙayyade nau'in sake saiti don rajistar bututun mai. Zaɓi BABU idan ba ku yi amfani da kowane rajistar bututun mai ba. Zaɓi ACLR don amfani da asynchronous share don rajistar bututun. Wannan zai haifar da tashar ACLR. Zaɓi SCLR don amfani da bayanan aiki tare don rajistar bututun mai. Wannan zai haifar da tashar jiragen ruwa na SCLR.
Yana ƙayyadad da damar babban agogo mai aiki don tashar agogon rajistar bututun mai

Default

Ƙayyade haɓakawa da ake so don ainihin IP.
Zaɓi Default don barin Intel Quartus Prime software don tantance mafi kyawun ingantawa ga ainihin IP.

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5. LPM_ADD_SUB (Adder/Subtractor)

Hoto na 4.

LPM_ADD_SUB IP core yana ba ku damar aiwatar da adder ko mai ragewa don ƙara ko ragi saitin bayanai don samar da fitarwa mai ɗauke da jimla ko bambancin ƙimar shigarwar.

Hoto mai zuwa yana nuna tashar jiragen ruwa na LPM_ADD_SUB IP core.

LPM_ADD_SUB Mashigai

LPM_ADD_SUB add_sub cin

data[]

agogo claken datab[] aclr

sakamako[] zubar da ruwa

inst

5.1. Features
LPM_ADD_SUB IP core yana ba da fasalulluka masu zuwa: · Yana haifar da adder, mai ragewa, da mai iya daidaitawa da ƙarfi.
ayyuka. Yana goyan bayan faɗin bayanai na 1 bits. · Yana goyan bayan tsarin wakilcin bayanai kamar sa hannu da rashin sa hannu. Yana goyan bayan ɗaukar zaɓi na zaɓi (ƙirƙira aro), bayyananniyar asynchronous, da kunna agogo
shigar da tashar jiragen ruwa. Yana goyan bayan aiwatar da zaɓi na zaɓi (abo-a) da mashigai na fitarwa. · Sanya ko dai ɗaya daga cikin bas ɗin bayanan shigarwa zuwa akai-akai. · Yana goyan bayan bututun mai tare da lat ɗin fitarwa mai daidaitawa.

ISO 9001: 2015 Rajista

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05
5.2. Verilog HDL Prototype
Samfurin Verilog HDL mai zuwa yana cikin Tsarin Verilog File (.v) lpm.v a cikin edisynthesis directory.
module lpm_add_sub (sakamako, cout, ambaliya, add_sub, cin, dataa, datab, clock, clken, aclr); siga lpm_type = "lpm_add_sub"; siga lpm_width = 1; siga lpm_direction = "UNUSED"; siga lpm_representation = "SIGNED"; siga lpm_pipeline = 0; siga lpm_hint = "Ba a yi amfani da su ba"; shigar [lpm_width-1:0] data, datab; shigar add_sub, cin; agogon shigarwa; shigar da klken; shigar da aclr; fitarwa [lpm_width-1:0] sakamako; fitarwa cout, ambaliya; endmodule
5.3. Bayanin Bangaren VHDL
Bayanin ɓangaren VHDL yana cikin Tsarin VHDL File (.vhd) LPM_PACK.vhd a cikin librariesvhdllpm directory.
bangaren LPM_ADD_SUB gama gari (LPM_WIDTH: na halitta;
LPM_DIRECTION : kirtani: = "Ba a yi amfani da su ba"; LPM_WAKILI: kirtani: = "AN SANYA"; LPM_PIPELINE : na halitta: = 0; LPM_TYPE : kirtani: = L_ADD_SUB; LPM_HINT: kirtani: = "Ba a amfani da shi"); tashar jiragen ruwa (DATAA: a cikin std_logic_vector (LPM_WIDTH-1 zuwa 0); DATAB: a cikin std_logic_vector (LPM_WIDTH-1 zuwa 0); ACLR: a cikin std_logic: = '0'; CLOCK: a cikin std_logic a cikin: CL '0'; : = '1'; CIN : a cikin std_logic: = 'Z'; ADD_SUB: a cikin std_logic: = '1'; SAKAMAKO: fita std_logic_vector (LPM_WIDTH-1 zuwa 0); COUT: fita std_logic; OVERFLOW : fita); std_logic bangaren ƙarshe;
5.4. Bayanin VHDL LIBRARY_USE
Ba a buƙatar bayanin VHDL LIBRARY-USE idan kuna amfani da Sanarwa na Bangaren VHDL.
LABARI: lpm; AMFANI DA lpm.lpm_components.duk;
5.5. Tashoshi
Tebura masu zuwa suna jera abubuwan shigarwa da tashar jiragen ruwa na LPM_ADD_SUB IP core.

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Jagorar Mai Amfani da Integer FPGA Integer IP Cores 23

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05

Tebur 15. LPM_ADD_SUB IP Core Input Ports

Sunan tashar jiragen ruwa

Da ake bukata

Bayani

cin

A'a

Ci gaba da zuwa ƙaramin tsari. Don ƙarin ayyuka, ƙimar tsoho shine 0. Don

ayyukan ragewa, ƙimar tsoho shine 1.

data[]

Shigar da bayanai. Girman tashar shigarwar ya dogara da ƙimar siga LPM_WIDTH.

data[]

Shigar da bayanai. Girman tashar shigarwar ya dogara da ƙimar siga LPM_WIDTH.

add_sub

A'a

Tashar shigar da zaɓi na zaɓi don ba da damar sauyawa mai ƙarfi tsakanin adder da mai ragewa

ayyuka. Idan ana amfani da ma'aunin LPM_DIRECTION, ba za a iya amfani da add_sub ba. Idan

an tsallake shi, ƙimar tsoho ita ce ADD. Intel yana ba da shawarar ku yi amfani da

LPM_DIRECTION siga don tantance aikin LPM_ADD_SUB,

maimakon sanya madaidaicin zuwa tashar add_sub.

agogo

A'a

Shigarwa don amfani da bututun mai. Tashar tashar agogo tana ba da shigarwar agogo don bututun mai

aiki. Don ƙimar LPM_PIPELINE banda 0 (tsoho), dole ne tashar tashar agogo ta kasance

kunna.

ƙulla

A'a

Kunna agogo don amfani da bututun mai. Lokacin da tashar tashar klken aka tabbatar da girma, ƙara/

aikin ragewa yana faruwa. Lokacin da siginar tayi ƙasa, babu wani aiki da ke faruwa. Idan

an tsallake shi, ƙimar tsoho shine 1.

aclr

A'a

Asynchronous bayyananne don amfani da bututun mai. Bututun yana farawa zuwa wanda ba a bayyana shi ba (X)

matakin dabaru. Ana iya amfani da tashar aclr a kowane lokaci don sake saita bututun zuwa duk 0s,

asynchronously zuwa siginar agogo.

Tebur 16. LPM_ADD_SUB IP Core Output Ports

Sunan tashar jiragen ruwa

Da ake bukata

Bayani

sakamako[]

Fitar bayanai. Girman tashar fitarwa ya dogara da sigar LPM_WIDTH

daraja.

kutut

A'a

Ci gaba (baron-a) na mafi mahimmancin bit (MSB). Gidan tashar jirgin ruwa yana da jiki

fassarar a matsayin ɗaukar nauyin (abo-in) na MSB. Tashar tashar jirgin ruwa ta gano

ambaliya a ayyukan UNSIGNED. Cout port yana aiki a cikin hanya guda don

Ayyukan da aka sa hannu kuma ba su da hannu.

ambaliya

A'a

Fitowar keɓantawa na zaɓi na zaɓi. Tashar jiragen ruwa mai ambaliya tana da fassarar jiki kamar

XOR na ɗaukar kaya zuwa MSB tare da fitar da MSB. Tashar jiragen ruwa mai ambaliya

yana tabbatarwa lokacin da sakamakon ya wuce daidaitattun samuwa, kuma ana amfani dashi kawai lokacin da

LPM_REPRESENTATION ƙimar siga ita ce SIGNED.

5.6. Sigogi

Tebur mai zuwa yana jera ma'auni na LPM_ADD_SUB IP.

Tebur 17. LPM_ADD_SUB IP Core Parameters

Sigar Sunan LPM_WIDTH

Nau'in Integer

Da ake bukata Ee

Bayani
Yana ƙayyadadden faɗin mashigai[], datab[], da sakamako[] mashigai.

LPM_DIRECTION

Zaren

A'a

Dabi'u sune ADD, SUB, da BA a yi amfani da su ba. Idan an cire shi, ƙimar tsoho ita ce DEFAULT, wanda ke jagorantar ma'aunin don ɗaukar ƙimarsa daga tashar add_sub. Ba za a iya amfani da tashar add_sub ba idan ana amfani da LPM_DIRECTION. Intel yana ba da shawarar cewa kayi amfani da ma'aunin LPM_DIRECTION don tantance aikin LPM_ADD_SUB, maimakon sanya madaidaicin zuwa tashar add_sub.
ci gaba…

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 24

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5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05

Sigar Suna LPM_REPRESENTATION LPM_PIPELINE LPM_HINT LPM_TYPE ONE_INPUT_IS_CONSTANT MAXIMIZE_SPEED
INTENDED_DEVICE_FAMILY

Rubuta nau'in kirtani mai lamba kirjin kirtani kirtani
Zaren

Ana Bukatar Babu Babu Babu Babu Babu
A'a

Bayani
Yana ƙayyade nau'in ƙari da aka yi. An SANYA KYAUTA kuma BA a sanya hannu ba. Idan an cire shi, ana sa hannu a tsohuwar ƙimar. Lokacin da aka saita wannan siga zuwa SIGNED, mai ƙara/masu ragi na fassara bayanan shigar da bayanai kamar yadda aka sanya hannu biyu.
Yana ƙayyadadden adadin zagayowar agogon jinkirin da ke da alaƙa da fitowar[]. Ƙimar sifili (0) tana nuna cewa babu jinkiri, kuma aikin haɗin gwiwa zalla za'a yi nan take. Idan an cire shi, ƙimar tsoho shine 0 (ba bututu).
Yana ba ku damar tantance takamaiman sigogin Intel a ƙirar VHDL files (.vhd). Tsohuwar ƙimar ba ta da amfani.
Gano ɗakin karatu na ma'auni na ma'auni (LPM) sunan mahaɗan a cikin ƙirar VHDL files.
Intel-takamaiman siga. Dole ne ku yi amfani da sigar LPM_HINT don tantance ma'aunin ONE_INPUT_IS_CONSTANT a ƙirar VHDL files. Dabi'u YES, A'A, kuma BA a yi amfani da su ba. Yana ba da babban haɓakawa idan shigarwa ɗaya ta kasance akai-akai. Idan an cire shi, ƙimar tsoho ita ce NO.
Intel-takamaiman siga. Dole ne ku yi amfani da sigar LPM_HINT don tantance ma'aunin MAXIMIZE_SPEED a ƙirar VHDL files. Kuna iya ƙididdige ƙima tsakanin 0 da 10. Idan aka yi amfani da su, Intel Quartus Prime software yana ƙoƙarin inganta takamaiman misalin aikin LPM_ADD_SUB don saurin aiki maimakon aiki mai sauƙi, kuma ya soke saitin zaɓi na Haɓaka Fasaha. Idan MAXIMIZE_SPEED ba a yi amfani da shi ba, ana amfani da ƙimar zaɓin Fasahar Ingantawa maimakon. Idan saitin MAXIMIZE_SPEED shine 6 ko sama da haka, Mai tarawa yana inganta LPM_ADD_SUB IP core don mafi girman gudu ta amfani da sarƙoƙi; idan saitin ya kasance 5 ko ƙasa da haka, Mai haɗawa yana aiwatar da ƙirar ba tare da ɗaukar sarƙoƙi ba. Dole ne a ƙayyade wannan siga don na'urorin Cyclone, Stratix, da Stratix GX kawai lokacin da ba a yi amfani da tashar add_sub ba.
Ana amfani da wannan siga don ƙirar ƙira da dalilai na kwaikwayo na ɗabi'a. Editan siga yana ƙididdige ƙimar wannan siga.

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6. LPM_COMPARE (Comparator)

Hoto na 5.

LPM_COMPARE IP core yana kwatanta ƙimar saitin bayanai guda biyu don tantance alaƙar da ke tsakaninsu. A mafi sauƙin tsari, zaku iya amfani da keɓantaccen kofa-OR don tantance ko rago biyu na bayanai daidai suke.

Hoto mai zuwa yana nuna tashar jiragen ruwa na LPM_COMPARE IP core.

LPM_COMPARE Tashoshi

LPM_COMPARE

ƙulla

alb

abin

data[]

agb

data[]

zamani

agogo

abin

aclr

abin

inst

6.1. Features
LPM_COMPARE IP core yana ba da fasali kamar haka: · Yana samar da aikin kwatancen don kwatanta bayanai guda biyu · Yana goyan bayan faɗin bayanai na 1 bits · Yana goyan bayan tsarin wakilcin bayanai kamar sa hannu da ba a sanya hannu ba · Yana samar da nau'ikan fitarwa kamar haka:
- alb (shigarwar A ta kasa da shigarwar B) - aeb (shigarwar A tana daidai da shigar B) - agb (shigarwar A ta fi shigar B) - ageb (shigar A ta fi ko daidai da shigar B) - aneb ( shigarwar A baya daidai da shigarwar B) — aleb (shigarwar A bai kai ko daidai da shigarwar B ba) · Yana goyan bayan zaɓin asynchronous fili da agogo yana ba da damar shigar da tashar jiragen ruwa · Yana ba da bayanan shigar da bayanai zuwa akai-akai · Yana goyan bayan bututun mai tare da latency mai daidaitawa.

ISO 9001: 2015 Rajista

6. LPM_COMPARE (Comparator) 683490 | 2020.10.05
6.2. Verilog HDL Prototype
Samfurin Verilog HDL mai zuwa yana cikin Tsarin Verilog File (.v) lpm.v a cikin edisynthesis directory.
module lpm_compare (alb, aeb, agb, aleb, aneb, ageb, dataa, datab, clock, clken, aclr); siga lpm_type = "lpm_compare"; siga lpm_width = 1; siga lpm_representation = "UNSIGNED"; siga lpm_pipeline = 0; siga lpm_hint = "Ba a yi amfani da su ba"; shigar [lpm_width-1:0] data, datab; agogon shigarwa; shigar da klken; shigar da aclr; fitarwa alb, aeb, agb, aleb, aneb, ageb; endmodule
6.3. Bayanin Bangaren VHDL
Bayanin ɓangaren VHDL yana cikin Tsarin VHDL File (.vhd) LPM_PACK.vhd a cikin librariesvhdllpm directory.
bangaren LPM_COMPARE gama gari (LPM_WIDTH: na halitta;
LPM_WAKILI: kirtani: = "Ba a sanya hannu ba"; LPM_PIPELINE : na halitta: = 0; LPM_TYPE: kirtani: = L_COMPARE; LPM_HINT: kirtani: = "Ba a amfani da shi"); tashar jiragen ruwa (DATAA: a cikin std_logic_vector (LPM_WIDTH-1 zuwa 0); DATAB: a cikin std_logic_vector (LPM_WIDTH-1 zuwa 0); ACLR: a cikin std_logic: = '0'; CLOCK: a cikin std_logic a cikin: CL '0'; : = '1'; AGB : fita std_logic; AGEB : fita std_logic; AEB : fita std_logic; ANEB : fita std_logic; bangaren ƙarshe;
6.4. Bayanin VHDL LIBRARY_USE
Ba a buƙatar bayanin VHDL LIBRARY-USE idan kuna amfani da Sanarwa na Bangaren VHDL.
LABARI: lpm; AMFANI DA lpm.lpm_components.duk;
6.5. Tashoshi
Tebura masu zuwa suna jera abubuwan shigarwa da tashar jiragen ruwa na LMP_COMPARE IP core.

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Jagorar Mai Amfani da Integer FPGA Integer IP Cores 27

6. LPM_COMPARE (Comparator) 683490 | 2020.10.05

Tebur 18. LPM_COMPARE IP core Input Ports

Sunan tashar jiragen ruwa

Da ake bukata

Bayani

data[]

Shigar da bayanai. Girman tashar shigarwar ya dogara da ƙimar siga LPM_WIDTH.

data[]

Shigar da bayanai. Girman tashar shigarwar ya dogara da ƙimar siga LPM_WIDTH.

agogo

A'a

Shigar da agogo don amfani da bututun mai. Tashar tashar agogo tana ba da shigarwar agogo don bututun mai

aiki. Don ƙimar LPM_PIPELINE banda 0 (tsoho), dole ne tashar tashar agogo ta kasance

kunna.

ƙulla

A'a

Kunna agogo don amfani da bututun mai. Lokacin da tashar tashar klken ta tabbatar da tsayi, da

aikin kwatanta yana faruwa. Lokacin da siginar tayi ƙasa, babu wani aiki da ke faruwa. Idan

an tsallake shi, ƙimar tsoho shine 1.

aclr

A'a

Asynchronous bayyananne don amfani da bututun mai. Bututun yana farawa zuwa dabarar da ba a bayyana ba (X).

matakin. Ana iya amfani da tashar aclr a kowane lokaci don sake saita bututun zuwa duk 0s,

asynchronously zuwa siginar agogo.

Tebur 19. LPM_COMPARE IP core Output Ports

Sunan tashar jiragen ruwa

Da ake bukata

Bayani

alb

A'a

Fitar tashar jiragen ruwa don mai kwatanta. An tabbatar idan shigar A ya kasa da shigarwar B.

abin

A'a

Fitar tashar jiragen ruwa don mai kwatanta. An tabbatar idan shigar A daidai yake da shigarwar B.

agb

A'a

Fitar tashar jiragen ruwa don mai kwatanta. An tabbatar idan shigarwar A ya fi shigar da B.

zamani

A'a

Fitar tashar jiragen ruwa don mai kwatanta. An tabbatar idan shigarwar A ya fi girma ko daidai da shigarwar

abin

A'a

Fitar tashar jiragen ruwa don mai kwatanta. An tabbatar idan shigar A baya daidai da shigarwar B.

abin

A'a

Fitar tashar jiragen ruwa don mai kwatanta. Tabbatarwa idan shigarwar A ya kasa ko daidai da shigarwar B.

6.6. Sigogi

Tebur mai zuwa yana lissafin sigogi na LPM_COMPARE IP core.

Tebur 20. LPM_COMPARE IP core Parameters

Sunan Siga

Nau'in

Da ake bukata

LPM_WIDTH

Integer Ee

LPM_REPRESENTATION

Zaren

A'a

LPM_PIPELINE

lamba No

LPM_HINT

Zaren

A'a

Bayani
Yana ƙayyadadden faɗin mashigai[] da datab[].
Yana ƙayyade nau'in kwatanta da aka yi. An SANYA KYAUTA kuma BA a sanya hannu ba. Idan an cire shi, ƙimar da aka saba ba ta da hannu. Lokacin da aka saita wannan ƙimar siginar zuwa SIGNED, mai kwatancen yana fassara shigar da bayanai azaman haɗin haɗin biyu.
Yana ƙayyadadden adadin zagayowar agogo na latency masu alaƙa da alb, aeb, agb, ageb, aleb, ko fitarwar aneb. Ƙimar sifili (0) tana nuna cewa babu jinkiri, kuma aikin haɗin gwiwa zalla za'a yi nan take. Idan an cire shi, ƙimar tsoho ita ce 0 (mara bututu).
Yana ba ku damar tantance takamaiman sigogin Intel a ƙirar VHDL files (.vhd). Tsohuwar ƙimar ba ta da amfani.
ci gaba…

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 28

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6. LPM_COMPARE (Comparator) 683490 | 2020.10.05
Sunan sigar LPM_TYPE INTENDED_DEVICE_FAMILY
DAYA_INPUT_IS_CONSTANT

Nau'in Kirtani
Zaren

Da ake bukata No
A'a

Bayani
Gano ɗakin karatu na ma'auni na ma'auni (LPM) sunan mahaɗan a cikin ƙirar VHDL files.
Ana amfani da wannan siga don ƙirar ƙira da dalilai na kwaikwayo na ɗabi'a. Editan siga yana ƙididdige ƙimar wannan siga.
Intel-takamaiman siga. Dole ne ku yi amfani da sigar LPM_HINT don tantance ma'aunin ONE_INPUT_IS_CONSTANT a ƙirar VHDL files. Ƙimar YES, A'A, ko BABU AMFANI. Yana ba da babban haɓakawa idan shigarwar ta kasance koyaushe. Idan an cire shi, ƙimar tsoho ita ce NO.

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Jagorar Mai Amfani da Integer FPGA Integer IP Cores 29

683490 | 2020.10.05 Aika Ra'ayoyin

7. ALTECC (Lambar Gyara Kuskuren: Encoder/Decoder) IP Core

Hoto na 6.

Intel yana ba da tushen ALTECC IP don aiwatar da ayyukan ECC. ECC tana gano gurɓatattun bayanai waɗanda ke faruwa a gefen mai karɓa yayin watsa bayanai. Wannan hanyar gyara kuskure ta fi dacewa da yanayin da kurakurai ke faruwa bazuwar maimakon fashewa.

ECC tana gano kurakurai ta hanyar aiwatar da rufaffen bayanai da yankewa. Domin misaliample, lokacin da aka yi amfani da ECC a cikin aikace-aikacen watsawa, ana shigar da bayanan da aka karanta daga tushen kafin a aika zuwa mai karɓa. Fitowar (kalmar lamba) daga mai rikodin ta ƙunshi ɗanyen bayanan da aka haɗa tare da adadin raƙuman ƙima. Madaidaicin adadin raƙuman raƙuman ƙira da aka haɗa ya dogara da adadin rago a cikin bayanan shigarwa. Ana aika kalmar lambar da aka ƙirƙira zuwa inda ake nufi.

Mai karɓa yana karɓar kalmar lambar kuma ya yanke ta. Bayanin da aka samu ta hanyar dikodi yana ƙayyade ko an gano kuskure. Mai ƙididdigewa yana gano kurakuran guda-bit da biyu-bit, amma zai iya gyara kurakurai-biti ɗaya kawai a cikin bayanan da suka lalace. Wannan nau'in ECC shine gano kuskure guda biyu na gyara kuskure (SECDED).

Za ka iya saita encoder da ayyukan gyara na ALTECC IP core. An shigar da shigar da bayanai zuwa mai rikodin don samar da kalmar lamba wacce ke hade da shigar da bayanai da abubuwan da aka samar. Kalmar lambar da aka ƙirƙira ana watsa shi zuwa ƙirar mai ƙididdigewa don yanke hukunci kafin isa toshewar inda za ta. Mai ƙididdigewa yana haifar da ƙwayar cuta don tantance ko akwai wani kuskure a cikin kalmar lambar da aka karɓa. Mai ƙididdigewa yana gyara bayanai kawai idan kuskuren guda-bit ya fito daga ragowar bayanai. Babu sigina da aka yi alama idan kuskuren guda-bit ya fito ne daga raƙuman ƙima. Hakanan mai ƙaddamarwa yana da siginonin tuta don nuna matsayin bayanan da aka karɓa da matakin da mai rikodin ya ɗauka, idan akwai.

Alkaluman da ke gaba suna nuna tashoshin jiragen ruwa na ALTECC IP core.

ALTECC Encoder Ports

ALTECC_ENCODER

bayanai[]

q[]

agogo

aclr

inst

ISO 9001: 2015 Rajista

7. ALTECC (Lambar Gyara Kuskuren: Encoder/Decoder) IP Core 683490 | 2020.10.05

Hoto 7. ALTECC Decoder Ports

ALTECC_DECODER

data[] agogon agogo

q[] err_detected kuskure_gyara
kuskure_fatal

aclr

inst

7.1. AlTECC Encoder Features

AlTECC encoder IP core yana ba da fasalulluka masu zuwa: · Yana yin rikodin bayanai ta amfani da tsarin Hamming Coding · Yana goyan bayan faɗin bayanai na 2 bits · Yana goyan bayan sa hannu da tsarin wakilcin bayanan da ba a sanya hannu ba · Tallafawa bututun mai tare da latency na fitowar agogo ɗaya ko biyu · Yana goyan bayan zaɓin zaɓi. asynchronous bayyananne da agogo yana kunna tashoshin jiragen ruwa

Mai rikodin ALTECC IP core yana ɗauka kuma yana ɓoye bayanan ta amfani da tsarin Hamming Coding. Makircin Hamming Codeing yana samun nau'i-nau'i iri-iri kuma yana haɗa su zuwa ainihin bayanan don samar da kalmar fitarwa. Adadin madaidaicin ragowa da aka haɗa ya dogara da faɗin bayanan.

Tebur mai zuwa yana lissafin adadin raƙuman ma'auni waɗanda aka haɗa don jeri daban-daban na faɗin bayanai. Jimlar ginshiƙi na Bits yana wakiltar jimlar adadin ragowar bayanan shigarwa da raƙuman raƙuman daidaito.

Tebur 21.

Adadin Matsakaicin Rago da Kalmomin Lambobi Bisa Faɗin Bayanai

Fadin Bayanai

Adadin Matsakaicin Rago

Jimlar Bits (Lambar Kalma)

2-4

3+1

6-8

5-11

4+1

10-16

12-26

5+1

18-32

27-57

6+1

34-64

58-64

7+1

66-72

Ƙididdigar ɗan ƙarami tana amfani da duba-daidaita-daidaitacce. Ƙarin ƙarin 1 bit (wanda aka nuna a cikin tebur azaman +1) an haɗa shi zuwa raƙuman ƙima a matsayin MSB na lambar lambar. Wannan yana tabbatar da cewa kalmar lambar tana da madaidaicin lamba na 1. Domin misaliampTo, idan fadin bayanan ya kasance 4 bits, ana saka 4 perity-bits a cikin bayanan don zama kalma mai lamba tare da jimlar 8 bits. Idan 7 ragowa daga LSB na kalmar code 8-bit suna da adadi mara kyau na 1s, bit na 8 (MSB) na kalmar lambar shine 1 yana yin jimlar adadin 1's a cikin kalmar lambar koda.
Hoton da ke gaba yana nuna kalmar lambar da aka samar da tsari na raƙuman ƙima da raƙuman bayanai a cikin shigar da bayanai 8-bit.

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Jagorar Mai Amfani da Integer FPGA Integer IP Cores 31

7. ALTECC (Lambar Gyara Kuskuren: Encoder/Decoder) IP Core 683490 | 2020.10.05

Hoto na 8.

Tsare-tsare Tsare-tsare na Rarraba Bits da Data Bits a cikin Kalman Ƙirƙirar Code 8-bit

MSB

LSB

4 nau'i-nau'i iri-iri

4 data bit

Mai rikodin ALTECC IP core yana karɓar faɗin shigarwa kawai na 2 zuwa 64 ragowa lokaci ɗaya. Faɗin shigarwa na 12 bits, 29 bits, da 64-bits, waɗanda suka dace da na'urorin Intel, suna samar da kayan aiki na 18 bits, 36 bits, da 72 ragowa bi da bi. Kuna iya sarrafa iyakancewar bitselection a cikin editan siga.

7.2. Prototype na Verilog HDL (ALTECC_ENCODER)
Samfurin Verilog HDL mai zuwa yana cikin Tsarin Verilog File (.v) lpm.v a cikin edisynthesis directory.
module altecc_encoder #( siga da aka nufa_device_family = "ba a yi amfani da shi ba", siga lpm_pipeline = 0, siga wide_codeword = 8, siga wide_dataword = 8, parameter lpm_type = "altecc_encoder", parameter lpm_hint = "ba a yi amfani da shi ba") ( shigarwar waya aclr, shigar da waya agogon waya, waya shigar [width_dataword-1:0] data, waya fitarwa [width_codeword-1:0] q; endmodule

7.3. Prototype na Verilog HDL (ALTECC_DECODER)
Samfurin Verilog HDL mai zuwa yana cikin Tsarin Verilog File (.v) lpm.v a cikin edisynthesis directory.
module altecc_decoder #( siga da aka nufa_device_family = "ba a yi amfani da shi ba", siga lpm_pipeline = 0, siga width_codeword = 8, siga wide_dataword = 8, parameter lpm_type = "altecc_decoder", parameter lpm_hint = "ba a yi amfani da shi ba") ( shigar da waya aclr, shigar da waya agogon waya, waya shigar [width_codeword-1:0] bayanai, gyara waya err_corrected, fitar da waya err_detected, outut waya err_fatal, fitarwa waya [width_dataword-1:0] q); endmodule

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 32

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7. ALTECC (Lambar Gyara Kuskuren: Encoder/Decoder) IP Core 683490 | 2020.10.05
7.4. Sanarwa Bangaren VHDL (ALTECC_ENCODER)
Bayanin ɓangaren VHDL yana cikin Tsarin VHDL File (.vhd) altera_mf_components.vhd a cikin librariesvhdlaltera_mf directory.
bangaren altecc_encoder generic ( nufin_device_family: kirtani: = "mara amfani"; lpm_pipeline: na halitta: = 0; width_codeword: na halitta: = 8; width_dataword: na halitta: = 8; lpm_hint: kirtani: = "UNUSED"; lpm_type: string: string ”); tashar jiragen ruwa (aclr: in std_logic: = '0'; agogo: a cikin std_logic: = '0'; clocken: in std_logic: = '1'; bayanai: a cikin std_logic_vector (ma'anar kalmar sirri-1 zuwa 0); q: fita std_logic_vector (width_logic_vector) -1 zuwa 0); bangaren ƙarshe;
7.5. Sanarwa na Bangaren VHDL (ALTECC_DECODER)
Bayanin ɓangaren VHDL yana cikin Tsarin VHDL File (.vhd) altera_mf_components.vhd a cikin librariesvhdlaltera_mf directory.
bangaren altecc_decoder generic ( nufin_device_family: kirtani: = "mara amfani"; lpm_pipeline: na halitta: = 0; width_codeword: na halitta: = 8; wide_dataword: na halitta: = 8; lpm_hint: kirtani: = "UNUSED"; lpm_type: string: string ”); tashar jiragen ruwa (aclr: in std_logic: = '0'; agogo: a cikin std_logic: = '0'; clocken: in std_logic: = '1'; bayanai: a cikin std_logic_vector (width_codeword-1 zuwa 0); err_corrected: out std_logic: out std_logic : fita std_logic; q: fita std_logic_vector (nisa_dataword-1 zuwa 0); syn_e: fita std_logic); bangaren ƙarshe;
7.6. Bayanin VHDL LIBRARY_USE
Ba a buƙatar bayanin VHDL LIBRARY-USE idan kuna amfani da Sanarwa na Bangaren VHDL.
LIBRARY altera_mf; AMFANI DA altera_mf.altera_mf_components.duk;
7.7. Encoder Ports
Tebura masu zuwa suna jera abubuwan shigarwa da tashar jiragen ruwa na ALTECC encoder IP core.

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Jagorar Mai Amfani da Integer FPGA Integer IP Cores 33

7. ALTECC (Lambar Gyara Kuskuren: Encoder/Decoder) IP Core 683490 | 2020.10.05

Table 22. ALTECC Encoder Input Ports

Sunan tashar jiragen ruwa

Da ake bukata

Bayani

bayanai[]

tashar shigar bayanai. Girman tashar shigarwar ya dogara da WIDTH_DATAWORD

ƙimar siga. Bayanan[] tashar jiragen ruwa ya ƙunshi danyen bayanan da za a rufa masa asiri.

agogo

Tashar shigar da agogo wanda ke ba da siginar agogo don daidaita aikin rufaffiyar.

Ana buƙatar tashar tashar agogo lokacin da ƙimar LPM_PIPELINE ta fi 0.

agogo

A'a

Kunna agogo. Idan an cire shi, ƙimar tsoho shine 1.

aclr

A'a

Matsakaicin shigar da asynchronous. Ana iya amfani da siginar high aclr mai aiki a kowane lokaci don

asynchronously share rijistar.

Table 23. ALTECC Encoder Output Ports

Port Name q[]

Da ake bukata Ee

Bayani
Rufaffen tashar fitarwar bayanai. Girman tashar fitarwa ya dogara da ƙimar sigar WIDTH_CODEWORD.

7.8. Decoder Ports

Tebura masu zuwa suna jera abubuwan shigarwa da tashoshin fitarwa don ainihin IP na ALTECC.

Tebur 24. ALTECC Decoder Input Ports

Sunan tashar jiragen ruwa

Da ake bukata

Bayani

bayanai[]

tashar shigar bayanai. Girman tashar shigarwar ya dogara da ƙimar sigar WIDTH_CODEWORD.

agogo

Tashar shigar da agogo wanda ke ba da siginar agogo don daidaita aikin rufaffiyar. Ana buƙatar tashar tashar agogo lokacin da ƙimar LPM_PIPELINE ta fi 0.

agogo

A'a

Kunna agogo. Idan an cire shi, ƙimar tsoho shine 1.

aclr

A'a

Matsakaicin shigar da asynchronous. Ana iya amfani da siginar babban aclr mai aiki a kowane lokaci don share rijistar.

Table 25. ALTECC Decoder Output Ports

Port Name q[]

Da ake bukata Ee

Bayani
Decoded data fitarwa tashar jiragen ruwa. Girman tashar fitarwa ya dogara da ƙimar sigar WIDTH_DATAWORD.

kuskure_ne

Sanya siginar tuta don nuna matsayin bayanan da aka karɓa da ƙayyadaddun kowane kurakurai da aka samu.

err_gyara Ee d

Sanya siginar tuta don nuna matsayin bayanan da aka karɓa. Yana nuna kuskuren da aka samu kuma an gyara shi. Kuna iya amfani da bayanan saboda an riga an gyara shi.

kuskure_fatal

Sanya siginar tuta don nuna matsayin bayanan da aka karɓa. Yana nuna kuskure biyu-bit da aka samu, amma ba a gyara ba. Kada ku yi amfani da bayanan idan an tabbatar da wannan siginar.

syn_e

A'a

Sigina na fitarwa wanda zai yi girma a duk lokacin da aka gano kuskuren-bit guda akan daidaito

ragowa.

7.9. Ma'auni na Encoder
Tebur mai zuwa yana lissafin sigogi na ALTECC encoder IP core.

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 34

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7. ALTECC (Lambar Gyara Kuskuren: Encoder/Decoder) IP Core 683490 | 2020.10.05

Table 26. ALTECC Encoder Parameters

Sunan Siga

Nau'in

Da ake bukata

Bayani

WIDTH_DATAWORD

Integer Ee

Yana ƙayyade faɗin ɗanyen bayanan. Ƙimar suna daga 2 zuwa 64. Idan an cire shi, ƙimar da aka fi so ita ce 8.

WIDTH_CODEWORD

Integer Ee

Yana ƙayyadad da faɗin kalmar lambar da ta dace. Ƙididdiga masu inganci daga 6 zuwa 72, ban da 9, 17, 33, da 65. Idan an cire shi, ƙimar da aka fi so ita ce 13.

LPM_PIPELINE

lamba No

Yana ƙayyade bututu don kewayawa. Ƙimar suna daga 0 zuwa 2. Idan darajar ta kasance 0, ba a yi rajistar tashoshin jiragen ruwa ba. Idan ƙimar ta kasance 1, ana yin rijistar tashoshin fitarwa. Idan ƙimar ta kasance 2, an yi rajistar shigarwar da tashoshin fitarwa. Idan an cire shi, ƙimar tsoho shine 0.

7.10. Ma'auni na Decoder

Tebu mai zuwa yana jera ma'auni na IP na IP na ALTECC.

Table 27. ALTECC Decoder Parameters

Sigar Suna WIDTH_DATAWORD

Nau'in Integer

Da ake bukata

Bayani

Yana ƙayyade faɗin ɗanyen bayanan. Darajar sune 2 zuwa 64. The

tsoho darajar shine 8.

WIDTH_CODEWORD

lamba

Yana ƙayyadad da faɗin kalmar lambar da ta dace. Darajoji su 6

zuwa 72, ban da 9, 17, 33, da 65. Idan an cire shi, ƙimar tsoho

yana 13.

LPM_PIPELINE

lamba

A'a

Ƙayyadaddun rajista na da'ira. Darajar suna daga 0 zuwa 2. Idan

darajar ita ce 0, ba a aiwatar da rajista ba. Idan darajar ta kasance 1, da

fitarwa an yi rajista. Idan darajar ta kasance 2, duka shigarwar da kuma

an yi rajistar fitarwa. Idan darajar ta fi 2, ƙari

ana aiwatar da rijistar a wurin fitarwa don ƙarin

latencies. Idan an cire shi, ƙimar tsoho shine 0.

Ƙirƙiri tashar 'syn_e'

lamba

A'a

Kunna wannan sigar don ƙirƙirar tashar tashar syn_e.

Aika da martani

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 35

683490 | 2020.10.05 Aika Ra'ayoyin

8. Intel FPGA Multiply Adder IP Core

Hoto na 9.

Intel FPGA Multiply Adder (Intel Stratix 10, Intel Arria 10, da na'urorin Intel Cyclone 10 GX) ko ALTERA_MULT_ADD (Arria V, Stratix V, da Cyclone V na'urorin) IP core yana ba ku damar aiwatar da mai haɓaka-adder.

Hoto mai zuwa yana nuna tashar jiragen ruwa na Intel FPGA Multiply Adder ko ALTERA_MULT_ADD IP core.

Intel FPGA Multiply Adder ko ALTERA_MULT_ADD Ports

Intel FPGA Multiply Adder ko ALTERA_MULT_ADD

dataa[] alamar datab[] signb datac[] coefsel0[] coefsel1[] coefsel2[] coefsel3[] addnsub1 addnsub3 aclr/sclr[] scanina[] clock0 clock1 clock2 ena0 ena1 ena2 sload_accum
accum_sload chainin[]

sakamakon scanouta[]

aclr0 aclr1

inst
Adder mai yawa yana karɓar nau'i-nau'i na bayanai, yana ninka dabi'u tare sannan ya ƙara zuwa ko ragi daga samfuran duk nau'i-nau'i.
Idan duk faɗin bayanan shigarwar suna da faɗin 9-bits ko ƙarami, aikin yana amfani da tsarin shigarwar 9 x 9 bit mai yawa a cikin toshe DSP don na'urori waɗanda ke goyan bayan daidaitawar 9 x 9. Idan ba haka ba, toshe DSP yana amfani da masu haɓaka shigarwar 18 × 18-bit don aiwatar da bayanai tare da faɗin tsakanin rago 10 da 18. Idan yawancin Intel FPGA Multiply Adder ko ALTERA_MULT_ADD IP cores sun faru a cikin ƙira, ana rarraba ayyukan zuwa kamar

ISO 9001: 2015 Rajista

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05
da yawa daban-daban tubalan DSP kamar yadda zai yiwu ta yadda za a kai ga wadannan tubalan ya fi sassauƙa. Ƙananan masu ninkawa a kowane katangar DSP suna ba da damar ƙarin zaɓukan kewayawa cikin toshe ta hanyar rage hanyoyin zuwa sauran na'urar.
Hakanan ana sanya rajistar rajista da ƙarin bututun na sigina masu zuwa a cikin toshewar DSP: · Shigar bayanai · Sa hannu ko ba a sanya hannu ba zaɓi · Ƙara ko cirewa zaɓi · Samfuran masu ninkawa.
A cikin yanayin sakamakon fitarwa, ana sanya rajista na farko a cikin toshe DSP. Koyaya ana sanya ƙarin rajistar latency a cikin abubuwan dabaru a wajen toshe. Na gefe zuwa toshewar DSP, gami da abubuwan shigar da bayanai zuwa mai ninka, sarrafa siginar siginar, da abubuwan da ke cikin adder, yi amfani da tuƙi na yau da kullun don sadarwa tare da sauran na'urar. Duk haɗin da ke cikin aikin suna amfani da keɓancewar hanyar sadarwa a cikin toshewar DSP. Wannan keɓantaccen hanyar kewayawa ya haɗa da sarƙoƙin rajistar canji lokacin da kuka zaɓi zaɓi don matsar da bayanan shigarwar mai rijista daga mai ninkawa ɗaya zuwa mai ninkawa kusa.
Don ƙarin bayani game da tubalan DSP a cikin kowane jerin na'urori na Stratix V, da Arria V, koma zuwa babin DSP Blocks na littattafan jagora daban-daban akan shafi na adabi da fasaha.
Bayani mai alaƙa AN 306: Aiwatar da Maɓalli a cikin na'urorin FPGA
Yana ba da ƙarin bayani game da aiwatar da masu ninkawa ta amfani da DSP da tubalan ƙwaƙwalwa a cikin na'urorin Intel FPGA.
8.1. Features
Intel FPGA Multiply Adder ko ALTERA_MULT_ADD IP core yana ba da fasalulluka masu zuwa: · Yana samar da mai ninka don aiwatar da ayyukan ninkawa na hadaddun biyu.
Lambobin lura: Lokacin gina masu ninka girma fiye da girman goyan baya na asali akwai iya/
zai zama tasirin aiki wanda ya haifar da rushewar tubalan DSP. Yana goyan bayan faɗin bayanai na 1 256 bits · Yana goyan bayan sa hannu da tsarin wakilcin bayanan da ba a sanya hannu ba · Yana goyan bayan bututun mai tare da daidaitawar shigar da bayanai · Yana ba da zaɓi don canzawa tsakanin sa hannu da tallafin bayanan da ba a sanya hannu ba · Yana ba da zaɓi don canzawa tsakanin ƙarawa da rage aiki · Yana goyan bayan na zaɓi asynchronous da synchronous bayyananne da agogon aiki tare yana ba da damar shigar da tashar jiragen ruwa · Yana goyan bayan yanayin rajistar jinkirin systolic · Yana goyan bayan pre-adder tare da adadin pre-load 8 kowane mai yawa

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Jagorar Mai Amfani da Integer FPGA Integer IP Cores 37

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

8.1.1. Pre-Adder
Tare da pre-adder, ana yin kari ko ragi kafin ciyar da mai yawa.
Akwai hanyoyi guda biyar na pre-adder: · Sauƙaƙan yanayi · Yanayin daidaitawa · Yanayin shigarwa · Yanayin murabba'i · Yanayin dindindin

Lura:

Lokacin da aka yi amfani da pre-adder (ƙaddamarwar pre-adder / shigarwa/ yanayin murabba'in), duk abubuwan da aka shigar da bayanai zuwa mai ninka dole ne su kasance da saitin agogo iri ɗaya.

8.1.1.1. Sauƙaƙan Yanayin Pre-Adder

A cikin wannan yanayin, duka operands suna samuwa daga mashigai na shigarwa kuma pre-adder ba a amfani da su ko wucewa. Wannan shine yanayin tsoho.

Hoto 10. Pre-Adder Sauƙaƙan Yanayin
a0 b0

Mult0

sakamako

8.1.1.2. Pre-Adder Coefficient Mode
A cikin wannan yanayin, operand ɗaya mai yawa yana samuwa daga pre-adder, ɗayan kuma yana samo daga ma'ajin ƙididdiga na ciki. Ma'ajiyar ƙididdigewa tana ba da damar har zuwa saitattun saitattun 8. Sigina na zaɓin ƙididdiga sune coefsel[0..3].
Ana bayyana wannan yanayin a cikin ma'auni mai zuwa.

Mai zuwa yana nuna yanayin pre-adder coefficient na mai ninka.

Hoto 11. Pre-adder Coefficient Mode

Mai karantawa

Mult0

+/-

sakamako

kowa 0

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8.1.1.3. Yanayin Input Pre-Adder A wannan yanayin, operand mai haɓakawa ɗaya yana samo daga pre-adder, ɗayan kuma yana samun daga tashar shigar datac[]. Ana bayyana wannan yanayin a cikin ma'auni mai zuwa.

Mai zuwa yana nuna yanayin shigar da pre-adder na mai ninkawa.

Hoto 12. Pre-Adder Input Yanayin
a0 b0

Mult0

+/-

sakamako

8.1.1.4. Yanayin Pre-Adder Square Ana bayyana wannan yanayin a cikin ma'auni mai zuwa.

Mai zuwa yana nuna yanayin murabba'in pre-adder na masu ninka biyu.

Hoto 13. Pre-adder Square Mode
a0 b0

Mult0

+/-

sakamako

8.1.1.5. Pre-Adder Constant Yanayin
A cikin wannan yanayin, operand ɗaya mai yawa yana samowa daga tashar shigar da bayanai, ɗayan operand kuma yana samun daga ma'ajin haɗin gwiwa na ciki. Ma'ajiyar ƙididdigewa tana ba da damar har zuwa saitattun saitattun 8. Sigina na zaɓin ƙididdiga sune coefsel[0..3].
Ana bayyana wannan yanayin a cikin ma'auni mai zuwa.

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Hoton da ke gaba yana nuna yanayin madaidaicin pre-adder na mai ninka.

Hoto 14. Pre-Adder Constant Mode
a0

Mult0

sakamako

kowa 0
kofa
8.1.2. Rijistar jinkirin systolic
A cikin tsarin gine-ginen systolic, ana ciyar da bayanan shigarwa cikin rumbun rajistar da ke aiki azaman ma'ajin bayanai. Kowace rajista tana ba da shigarwar sample zuwa mai ninkawa inda aka ninka ta da madaidaicin adadin. Ƙimar sarkar tana adana sakamakon haɗe-haɗe a hankali daga mai ninka da sakamakon da aka yi rajista a baya daga tashar shigarwar chainin[] don samar da sakamako na ƙarshe. Dole ne a jinkirta kowane nau'i-nau'i-nau'i ta hanyar zagayowar guda ɗaya domin sakamakon ya daidaita daidai lokacin da aka haɗa su tare. Ana amfani da kowane jinkiri mai zuwa don magance duka ma'aunin ƙwaƙwalwar ajiya da ma'ajin bayanai na abubuwan ƙara haɓakawa daban-daban. Don misaliample, jinkiri ɗaya don ninka na biyu ƙara kashi, jinkiri biyu don ƙara yawan haɓaka na uku, da sauransu.
Hoto 15. Systolic Registers
Systolic rajista

x (t) c (0)

S-1

c(1)

S-1

c(2)

S-1

c (N-1)

S-1

S -1 y (t)

x(t) yana wakiltar sakamako daga ci gaba da shigar da samples da y (t)
yana wakiltar taƙaitawar saitin shigarwar samples, kuma a cikin lokaci, an ninka su
bi da bi coefficients. Duka sakamakon shigarwa da fitarwa suna gudana daga hagu zuwa dama. C (0) zuwa c (N-1) yana nuna ƙididdiga. S-1 yana nuna alamun jinkirin systolic, yayin da 1 yana wakiltar jinkirin agogo ɗaya. Ana ƙara rajistar jinkiri na systolic a
abubuwan da aka samu da abubuwan da ake fitarwa don bututun mai ta hanyar da ke tabbatar da sakamako daga
mai ninka operand da tara kudaden da aka tara suna tsayawa a daidaitawa. Wannan nau'in sarrafawa
ana maimaitawa don ƙirƙirar da'ira mai ƙididdige aikin tacewa. Wannan aikin shine
bayyana a cikin ma'auni mai zuwa.

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N yana wakiltar adadin zagayowar bayanan da suka shiga cikin mai tarawa, y (t) yana wakiltar fitarwa a lokaci t, A (t) yana wakiltar shigarwar a lokacin t, B(i) sune ma'auni. t da i a cikin lissafin sun dace da wani lokaci na musamman, don ƙididdige abin da aka fitar sample y (t) a lokacin t, rukunin shigarwar samples a N mabambantan lokaci, ko A(n), A(n-1), A(n-2), …A(n-N+1) ana bukata. Ƙungiyar shigarwar N sampLes ana ninka su ta hanyar N kuma an haɗa su tare don samar da sakamako na ƙarshe y.
Tsarin gine-ginen rajista na systolic yana samuwa ne kawai don jimlar-2 da jimlar-na-4 halaye. Don yanayin tsarin gine-ginen rajista na systolic, siginar farko na chainin yana buƙatar ɗaure zuwa 0.
Hoto mai zuwa yana nuna aiwatar da rijistar jinkirin systolic na masu ninka biyu.
Hoto 16. Yin Rijistar Jinkirin Systolic Yin Aiwatar da Maɓalli 2
sarkar

Mult0

+/-

Mult1

+/-

sakamako
An bayyana jimlar masu ninka biyu a cikin ma'auni mai zuwa.
Hoto mai zuwa yana nuna aiwatar da rijistar jinkirin systolic na masu ninka biyu.

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Hoto 17. Yin Rijistar Jinkirin Systolic Yin Aiwatar da Maɓalli 4
sarkar

Mult0

+/-

Mult1

+/-

Mult2

+/-

Mult3

+/-

sakamako
An bayyana jimlar masu ninkawa huɗu a cikin ma'auni mai zuwa. Hoto 18. Jimlar 4 Multipliers
Mai zuwa yana lissafin advantages of systolic Register: · Rage amfani da albarkatu na DSP · Yana ba da damar yin taswira mai inganci a cikin toshe DSP ta amfani da tsarin ƙarar sarkar.

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8.1.3. Pre-load Constant
Rikicin da aka riga aka yi lodi yana sarrafa operand mai tarawa kuma ya dace da ra'ayin mai tarawa. Madaidaicin LOADCONST_VALUE yana daga 0. Madaidaicin ƙimar yana daidai da 64N, inda N = LOADCONST_VALUE. Lokacin da LOADCONST_VALUE aka saita zuwa 2, ƙimanta akai-akai tana daidai da 64. Ana iya amfani da wannan aikin azaman zagaye na son rai.
Hoton da ke gaba yana nuna aiwatar da kullun da aka riga aka yi lodi.
Hoto 19. Pre-load Constant

Ra'ayin Accumulator

Mult0

+/-

Mult1

+/b1

sakamako

accum_sload sload_accum

Koma zuwa abubuwan haɗin IP masu zuwa don sauran aiwatarwa masu yawa: · ALTMULT_ACCUM · ALTMEMMULT · LPM_MULT
8.1.4. Mai tarawa Biyu
Siffar tarawa sau biyu tana ƙara ƙarin rajista a cikin hanyar mayar da martani. Rijistar tarawa biyu tana bin rajistar fitarwa, wanda ya haɗa da agogo, kunna agogo, da aclr. Ƙarin rijistar tarawa yana dawo da sakamako tare da jinkirin sake zagayowar lokaci ɗaya. Wannan fasalin yana ba ku damar samun tashoshi masu tarawa guda biyu masu ƙidayar albarkatu iri ɗaya.
Hoto mai zuwa yana nuna aiwatar da tarawa biyu.

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Hoto 20. Biyu Accumulator

Biyu ble Accu mulator Register

Accu mulator feedba ck

Mult0

+/-

Mult1

+/b1

Rijistar Fitowar Fitowa

8.2. Verilog HDL Prototype
Kuna iya samun Intel FPGA Multiply Adder ko ALTERA_MULT_ADD Verilog HDL samfur file (altera_mult_add_rtl.v) a cikin librariesmegafunctions directory.
8.3. Bayanin Bangaren VHDL
Sanarwar bangaren VHDL tana cikin altera_lnsim_components.vhd a cikin librariesvhdl altera_lnsim directory.
8.4. Bayanin VHDL LIBRARY_USE
Ba a buƙatar bayanin VHDL LIBRARY-USE idan kuna amfani da Sanarwa na Bangaren VHDL.
LIBRARY altera_mf; AMFANI DA altera_mf.altera_mf_components.duk;

8.5. Sigina

Tebur masu zuwa suna jera siginonin shigarwa da fitarwa na Multiply Adder Intel FPGA IPor ALTERA_MULT_ADD IP core.

Tebur 28. Haɓaka Adder Intel FPGA IPor ALTERA_MULT_ADD Sigina na Shigarwa

Sigina

Da ake bukata

Bayani

dataa_0[]/data_1[]/

dataa_2[]/data_3[]

Shigar da bayanai zuwa mai yawa. Shigar da tashar jiragen ruwa [NUMBER_OF_MULTIPLIERS * WIDTH_A - 1 … 0] fadi
ci gaba…

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Siginar datab_0[]/datab_1[]/ datab_2[]/datab_3[] datac_0[] /datac_1[]/ datac_2[]/datac_3[] agogo[1:0] aclr[1:0] sclr[1:0] ena [1:0] alamar
alamar
scanina[] accum_sload

Ana buƙata Ee A'a
Babu Babu Babu Babu
A'a
A'a A'a

Bayani
Samfurin simintin wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) zuwa waɗannan sigina. Lokacin da kuka samar da ƙimar X ga waɗannan sigina, ƙimar X tana yaduwa akan siginar fitarwa.
Shigar da bayanai zuwa mai yawa. Siginar shigarwa [NUMBER_OF_MULTIPLIERS * WIDTH_B – 1 … 0] faɗin Samfurin simulation na wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) ga waɗannan sigina. Lokacin da kuka samar da ƙimar X ga waɗannan sigina, ƙimar X tana yaduwa akan siginar fitarwa.
Shigar da bayanai zuwa mai yawa. Siginar shigarwa [NUMBER_OF_MULTIPLIERS * WIDTH_C – 1, … 0] fadi Zaɓi INPUT don Zaɓi yanayin yanayin prereader don kunna waɗannan sigina. Samfurin simintin wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) zuwa waɗannan sigina. Lokacin da kuka samar da ƙimar X ga waɗannan sigina, ƙimar X tana yaduwa akan siginar fitarwa.
Ƙaddamar da tashar shigar da agogo zuwa rijistar da ta dace. Ana iya amfani da wannan siginar kowane rajista a cikin ainihin IP. Samfurin simintin wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) zuwa waɗannan sigina. Lokacin da kuka samar da ƙimar X ga waɗannan sigina, ƙimar X tana yaduwa akan siginar fitarwa.
Shigar da Asynchronous share fage zuwa rijista mai dacewa. Samfurin simintin wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) zuwa waɗannan sigina. Lokacin da kuka samar da ƙimar X ga waɗannan sigina, ƙimar X tana yaduwa akan siginar fitarwa.
Share shigarwar aiki tare zuwa rijistar da ta dace. Samfurin simintin wannan IP yana goyan bayan ƙimar shigarwar da ba a tantance ba zuwa waɗannan sigina. Lokacin da kuka samar da ƙimar X ga waɗannan sigina, ƙimar X tana yaduwa akan siginar fitarwa
Kunna shigar da sigina zuwa rijistar da ta dace. Samfurin simintin wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) zuwa waɗannan sigina. Lokacin da kuka samar da ƙimar X ga waɗannan sigina, ƙimar X tana yaduwa akan siginar fitarwa.
Yana ƙayyadad da wakilcin lambobi na shigarwar mai yawa A. Idan siginar siginar yana da girma, mai yawa yana ɗaukar siginar mai yawa A a matsayin lambar sa hannu. Idan siginar siginar ta yi ƙasa, mai ninka yana ɗaukar siginar shigar da yawa A azaman lambar da ba a sanya hannu ba. Zaɓi VARIABLE don Menene tsarin wakilcin ma'aunin bayanai na Multipliers A don kunna wannan siginar. Samfurin simintin wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) zuwa wannan siginar. Lokacin da kuka samar da ƙimar X ga wannan shigarwar, ƙimar X tana yaduwa akan siginar fitarwa.
Yana ƙayyadad da wakilcin lambobi na siginar shigar da yawa B. Idan siginar alamar yana da girma, mai yawa yana ɗaukar siginar shigar da yawa B azaman lambar madaidaicin sa hannu biyu. Idan siginar alamar ta yi ƙasa, mai haɓaka yana ɗaukar siginar shigar da yawa B azaman lamba mara sa hannu. Samfurin simintin wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) zuwa wannan siginar. Lokacin da kuka samar da ƙimar X ga wannan shigarwar, ƙimar X tana yaduwa akan siginar fitarwa.
Shigar da sarkar duba A. Siginar shigarwa [WIDTH_A – 1, … 0] fadi. Lokacin da ma'aunin INPUT_SOURCE_A yana da ƙimar SCANA, ana buƙatar siginar scanina.
Tsayawa yana ƙayyadaddun ko ƙimar tarawa ta kasance koyaushe. Idan siginar accum_sload yayi ƙasa, to ana ɗora fitarwa mai yawa a cikin mai tarawa. Kar a yi amfani da accum_sload da sload_accum lokaci guda.
ci gaba…

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Sigina sload_accum
chainin[] addnsub1
addnsub3
coefsel0[] coefsel1[] coefsel2[] coefsel3[]

Da ake bukata A'a
A'a A'a
A'a
Babu Babu Babu Babu

Bayani
Samfurin simintin wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) zuwa wannan siginar. Lokacin da kuka samar da ƙimar X ga wannan shigarwar, ƙimar X tana yaduwa akan siginar fitarwa.
Tsayawa yana ƙayyadaddun ko ƙimar tarawa ta kasance koyaushe. Idan siginar sload_accum yana da girma, to ana ɗora fitowar mai yawa a cikin mai tarawa. Kar a yi amfani da accum_sload da sload_accum lokaci guda. Samfurin simintin wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) zuwa wannan siginar. Lokacin da kuka samar da ƙimar X ga wannan shigarwar, ƙimar X tana yaduwa akan siginar fitarwa.
Bas ɗin shigar da sakamakon ƙara daga s ɗin da suka gabatatage. Siginar shigarwa [WIDTH_CHAININ - 1, … 0] fadi.
Yi ƙari ko ragi zuwa abubuwan da aka fitar daga farkon nau'ikan masu ninkawa. Shigar da 1 zuwa siginar addnsub1 don ƙara abubuwan da aka fitar daga farkon nau'ikan masu ninkawa. Shigar da 0 zuwa siginar addnsub1 don cire abubuwan da aka samo daga farkon nau'ikan masu ninkawa. Samfurin simintin wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) zuwa wannan siginar. Lokacin da kuka samar da ƙimar X ga wannan shigarwar, ƙimar X tana yaduwa akan siginar fitarwa.
Yi ƙari ko ragi zuwa abubuwan da aka fitar daga farkon nau'ikan masu ninkawa. Shigar da 1 zuwa siginar addnsub3 don ƙara abubuwan da aka fitar daga nau'ikan masu yawa na biyu. Shigar da 0 zuwa siginar addnsub3 don cire abubuwan da aka samo daga farkon nau'ikan masu ninkawa. Samfurin simintin wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) zuwa wannan siginar. Lokacin da kuka samar da ƙimar X ga wannan shigarwar, ƙimar X tana yaduwa akan siginar fitarwa.
Siginar shigar da ƙima[0:3] zuwa mai yawa na farko. Samfurin simintin wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) zuwa wannan siginar. Lokacin da kuka samar da ƙimar X ga wannan shigarwar, ƙimar X tana yaduwa akan siginar fitarwa.
Siginar shigar da ƙima[0:3] zuwa mai ninka na biyu. Samfurin simintin wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) zuwa wannan siginar. Lokacin da kuka samar da ƙimar X ga wannan shigarwar, ƙimar X tana yaduwa akan siginar fitarwa.
Siginar shigar da ƙima[0:3] zuwa mai yawa na uku. Samfurin simintin wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) zuwa wannan siginar. Lokacin da kuka samar da ƙimar X ga wannan shigarwar, ƙimar X tana yaduwa akan siginar fitarwa.
Siginar shigar da ƙima [0:3] zuwa mai yawa na huɗu. Samfurin simintin wannan IP yana goyan bayan ƙimar shigar da ba a tantance ba (X) zuwa wannan siginar. Lokacin da kuka samar da ƙimar X ga wannan shigarwar, ƙimar X tana yaduwa akan siginar fitarwa.

Tebur 29. Haɓaka Adder Intel FPGA IP Sigina na Fitowa

Sigina

Da ake bukata

Bayani

sakamako []

Siginar fitarwa mai yawa. Siginar fitarwa [WIDTH_RESULT - 1 … 0] fadi

Samfurin kwaikwaiyo na wannan IP yana goyan bayan ƙimar fitarwa (X). Lokacin da kuka samar da ƙimar X azaman shigarwar, ƙimar X tana yadawa akan wannan siginar.

scanouta []

A'a

Fitowar sarkar dubawa A. Siginar fitarwa [WIDTH_A - 1..0] fadi.

Zaɓi fiye da 2 don lambobin masu ninkawa kuma zaɓi shigarwar sarkar Scan don Menene shigarwar A na mai ninka da aka haɗa da siga don kunna wannan siginar.

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8.6. Sigogi

8.6.1. Gabaɗaya Tab

Tebur 30. Gabaɗaya Tab

Siga

IP Generated Parameter

Daraja

Menene adadin masu ninkawa?

adadin_m 1 - 4 ultipliers

Yaya fadi ya kamata motocin shigar da A width_a su kasance?

1-256

Yaya fadi ya kamata motocin shigar da B width_b su kasance?

1-256

Yaya faɗin 'sakamakon' bas ɗin fitarwa?

width_result

1-256

Ƙirƙirar agogo mai alaƙa don kowane agogo

gui_associate A kan d_clock_enabl Kashe e

8.6.2. Ƙarin Yanayin Tab

Tebur 31. Ƙarin Yanayin Tab

Siga

IP Generated Parameter

Daraja

Kanfigareshan Fitarwa

Yi rijistar fitarwa na sashin ƙara

gui_output_re Kunna

gister

Kashe

Menene tushen shigar agogo?

gui_output_re gister_clock

Clock0 Clock1 Clock2

Menene tushen shigar asynchronous share fage?

gui_output_re gister_aclr

BABU ACLR0 ACLR1

Menene tushen shigar da bayanan da ke aiki tare?

gui_output_re gister_sclr

BABU SCLR0 SCLR1

Ayyukan Adder

Wane aiki ya kamata a yi akan abubuwan da aka fitar na farko na masu ninkawa?

gui_multiplier 1_direction

KARA, SUB, MAI CANCANCI

Default Value 1
16

Bayani
Adadin masu yawa da za a haɗa tare. Ƙimar ita ce 1 har zuwa 4. Ƙayyade faɗin tashar tashar dataa[].

Ƙayyade faɗin tashar tashar bayanai[].

Ƙayyade nisa na tashar tashar [] sakamakon.

Kashe

Zaɓi wannan zaɓi don ƙirƙirar kunna agogo

ga kowane agogo.

Default Value

Bayani

Kashe agogo0
BABU KOWA

Zaɓi wannan zaɓi don ba da damar yin rijistar fitarwa na adder module.
Zaɓi Clock0, Clock1 ko Clock2 don kunnawa da tantance tushen agogo don rajistar fitarwa. Dole ne ku zaɓi fitarwar Rijista na sashin ƙara don kunna wannan siga.
Yana ƙayyade madaidaicin tushe mai tushe don rijistar fitarwar ƙara. Dole ne ku zaɓi fitarwar Rijista na sashin ƙara don kunna wannan siga.
Yana ƙayyade madaidaicin tushe mai daidaitawa don rijistar fitarwar ƙara. Dole ne ku zaɓi fitarwar Rijista na sashin ƙara don kunna wannan siga.

KARA

Zaɓi aikin ƙari ko ragi don aiwatarwa don abubuwan da aka fitar tsakanin masu haɓaka na farko da na biyu.
Zaɓi ADD don yin ƙarin aiki.
Zaɓi SUB don aiwatar da aikin ragewa.
Zaɓa VARIABLE don amfani da tashar addnsub1 don sarrafa ƙarawa / ragi mai ƙarfi.
ci gaba…

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Siga

IP Generated Parameter

Daraja

Yi rijistar shigar 'adnsub1'

gui_addnsub_ A kan multiplier_reg Kashe ister1

Menene tushen shigar agogo?

gui_addnsub_ multiplier_reg ister1_clock

Clock0 Clock1 Clock2

Menene tushen shigar asynchronous share fage?

gui_addnsub_ multiplier_aclr 1

BABU ACLR0 ACLR1

Menene tushen shigar da bayanan da ke aiki tare?

gui_addnsub_ multiplier_sclr 1

BABU SCLR0 SCLR1

Wane aiki ya kamata a yi a kan abubuwan da aka fitar na biyu na masu ninkawa?

gui_multiplier 3_direction

KARA, SUB, MAI CANCANCI

Yi rijistar shigar 'adnsub3'

gui_addnsub_ A kan multiplier_reg Kashe ister3

Menene tushen shigar agogo?

gui_addnsub_ multiplier_reg ister3_clock

Clock0 Clock1 Clock2

Default Value
Kashe Clock0 BABU WANI KARA
Kashe agogo0

Bayani
Lokacin da aka zaɓi ƙimar VARIABLE: · Fitar da siginar addnsub1 zuwa sama don
ƙarin aiki. · Fitar da siginar addnsub1 zuwa ƙasa don
aikin ragewa. Dole ne ku zaɓi fiye da masu ninka biyu don kunna wannan siga.
Zaɓi wannan zaɓi don kunna rajistar shigarwa don tashar addnsub1. Dole ne ku zaɓi VARIABLE don Wane aiki ya kamata a yi akan abubuwan da aka samo na farko na masu ninkawa don kunna wannan siga.
Zaɓi Clock0, Clock1 ko Clock2 don tantance siginar shigar agogon don rijistar addnsub1. Dole ne ku zaɓi shigarwar 'addnsub1' Rajista don kunna wannan sigar.
Yana ƙayyade madaidaicin tushe mai tushe don rajistar addnsub1. Dole ne ku zaɓi shigarwar 'addnsub1' Rajista don kunna wannan sigar.
Yana ƙayyade madaidaicin tushe mai daidaitawa don rijistar addnsub1. Dole ne ku zaɓi shigarwar 'addnsub1' Rajista don kunna wannan sigar.
Zaɓi aikin ƙari ko ragi don aiwatarwa don abubuwan da aka fitar tsakanin masu ninka na uku da na huɗu. Zaɓi ADD don yin ƙari
aiki. Zaɓi SUB don aiwatar da raguwa
aiki. Zaɓi VARIABLE don amfani da addnsub1
tashar jiragen ruwa don sarrafa ƙarawa / ragi mai ƙarfi. Lokacin da aka zaɓi ƙimar VARIABLE: · Fitar da siginar addnsub1 zuwa sama don ƙarin aiki. • Fitar da siginar addnsub1 zuwa ƙasa don aikin ragi. Dole ne ku zaɓi ƙimar 4 don Menene adadin masu yawa? don kunna wannan siga.
Zaɓi wannan zaɓi don kunna rajistar shigarwa don siginar addnsub3. Dole ne ku zaɓi VARIABLE don Wane aiki ya kamata a yi akan abubuwan da aka fitar na biyun na biyu don kunna wannan siga.
Zaɓi Clock0, Clock1 ko Clock2 don tantance siginar shigar agogon don rijistar addnsub3. Dole ne ku zaɓi shigarwar 'adnsub3' Rajista don kunna wannan sigar.
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Siga
Menene tushen shigar asynchronous share fage?

IP Generated Parameter

Daraja

gui_addnsub_ multiplier_aclr 3

BABU ACLR0 ACLR1

Menene tushen shigar da bayanan da ke aiki tare?

gui_addnsub_ multiplier_sclr 3

BABU SCLR0 SCLR1

Kunna Polarity 'amfani_subadd'

gui_use_sub Kunna

ƙara

Kashe

8.6.3. Multipliers Tab

Table 32. Multipliers Tab

Siga

IP Generated Parameter

Daraja

Menene

gui_wakili

tsarin wakilci ation_a

don shigar da Multipliers A?

SAHANNU, BA'A SALLAH, MAI CANCANCI

Shigar da 'signa'

gui_register_s Kunna

igna

Kashe

Menene tushen shigar agogo?

gui_register_s igna_clock

Clock0 Clock1 Clock2

Menene tushen shigar asynchronous share fage?

gui_register_s igna_aclr

BABU ACLR0 ACLR1

Menene tushen shigar da bayanan da ke aiki tare?

gui_register_s igna_sclr

BABU SCLR0 SCLR1

Menene

gui_wakili

tsarin wakilci ation_b

don shigar da Multipliers B?

SAHANNU, BA'A SALLAH, MAI CANCANCI

Yi rijistar shigar 'signb'

gui_register_s Kunna

ignb

Kashe

Default Value BABU
BABU

Bayani
Yana ƙayyade madaidaicin tushe mai tushe don rajistar addnsub3. Dole ne ku zaɓi shigarwar 'addnsub3' Rajista don kunna wannan sigar.
Yana ƙayyade madaidaicin tushe mai daidaitawa don rajistar addnsub3. Dole ne ku zaɓi shigar da 'adnsub3' Rajista don kunna wannan sigar.

Kashe

Zaɓi wannan zaɓi don juyawa aikin

na tashar shigar da addnsub.

Fitar da addnsub zuwa sama don aikin ragewa.

Fitar da addnsub zuwa ƙasa don ƙarin aiki.

Default Value

Bayani

BA a sanya hannu Ƙidaya tsarin wakilci don shigarwar mai yawa A.

Kashe

Zaɓi wannan zaɓi don kunna alamar

yin rijista.

Dole ne ku zaɓi ƙimar VARIABLE don Menene tsarin wakilcin abubuwan shigar da Multipliers A? siga don kunna wannan zaɓi.

Agogo0

Zaɓi Clock0, Clock1 ko Clock2 don kunna da ƙididdige siginar shigarwar agogo don rijistar sa hannun.
Dole ne ku zaɓi shigarwar 'signa' mai rijista don kunna wannan sigar.

BABU

Yana ƙayyade madaidaicin tushe mai tushe don rajistar alamar.
Dole ne ku zaɓi shigarwar 'signa' mai rijista don kunna wannan sigar.

BABU

Yana ƙayyade madaidaicin tushe mai daidaitawa don rijistar alamar.
Dole ne ku zaɓi shigarwar 'signa' mai rijista don kunna wannan sigar.

UNSIGNED Ƙayyade tsarin wakilci don shigarwar mai ninka B.

Kashe

Zaɓi wannan zaɓi don kunna signb

yin rijista.

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Siga

IP Generated Parameter

Daraja

Default Value

Menene tushen shigar agogo?

gui_register_s ignb_clock

Clock0 Clock1 Clock2

Agogo0

Menene tushen shigar asynchronous share fage?

gui_register_s ignb_aclr

BABU ACLR0 ACLR1

Menene tushen shigar da bayanan da ke aiki tare?

gui_register_s ignb_sclr

BABU SCLR0 SCLR1

Kanfigareshan shigarwa
Yi rijista shigarwar A na mai ninka
Menene tushen shigar agogo?

gui_input_reg Kunna

ina_a

Kashe

gui_input_reg ister_a_clock

Clock0 Clock1 Clock2

BABU KOWA
Kashe agogo0

Menene tushen shigar asynchronous share fage?

gui_input_reg ister_a_aclr

BABU ACLR0 ACLR1

Menene tushen shigar da bayanan da ke aiki tare?

gui_input_reg ister_a_sclr

BABU SCLR0 SCLR1

Yi rijistar shigarwar B na mai ninkawa
Menene tushen shigar agogo?

gui_input_reg Kunna

yar_b

Kashe

gui_input_reg ister_b_clock

Clock0 Clock1 Clock2

BABU KOWA A Agogo0

Menene tushen shigar asynchronous share fage?

gui_input_reg ister_b_aclr

BABU ACLR0 ACLR1

BABU

Menene tushen shigar da bayanan da ke aiki tare?

gui_input_reg ister_b_sclr

BABU SCLR0 SCLR1

BABU

Menene shigarwar A na mai ninka da aka haɗa zuwa?

gui_multiplier Multiplier shigar da Multiplier

_a_shigar

Duba shigarwar shigarwar sarkar

Bayani
Dole ne ku zaɓi ƙimar VARIABLE don Menene tsarin wakilcin abubuwan shigar da Multipliers B? siga don kunna wannan zaɓi.
Zaɓi Clock0, Clock1 ko Clock2 don kunna da ƙididdige siginar shigarwar agogon don rajistar sa hannu. Dole ne ku zaɓi shigarwar 'signb' Rajista don kunna wannan sigar.
Yana ƙayyade madaidaicin tushe mai tushe don rajistar alamar. Dole ne ku zaɓi shigarwar 'signb' Rajista don kunna wannan sigar.
Yana ƙayyade madaidaicin tushe mai aiki tare don rajistar alamar. Dole ne ku zaɓi shigarwar 'signb' Rajista don kunna wannan sigar.
Zaɓi wannan zaɓi don kunna rajistar shigarwa don bas ɗin shigar da bayanai.
Zaɓi Clock0, Clock1 ko Clock2 don kunna da ƙididdige siginar shigar agogon rajista don bas ɗin shigarwar bayanai. Dole ne ku zaɓi shigar da shigarwar A na mai ninka don kunna wannan siga.
Yana ƙayyade madaidaicin tushen rijista don bas ɗin shigar da bayanai. Dole ne ku zaɓi shigar da shigarwar A na mai ninka don kunna wannan siga.
Yana ƙayyade madaidaicin tushen rijistar don bas ɗin shigar da bayanai. Dole ne ku zaɓi shigar da shigarwar A na mai ninka don kunna wannan siga.
Zaɓi wannan zaɓi don kunna rajistar shigarwa don bas ɗin shigar da bayanai.
Zaɓi Clock0, Clock1 ko Clock2 don kunna da ƙididdige siginar shigar agogon rajista don bas ɗin shigar da bayanai. Dole ne ku zaɓi Rijista shigarwar B na mai ninka don kunna wannan siga.
Yana ƙayyade madaidaicin tushen rijistar don bas ɗin shigar da bayanai. Dole ne ku zaɓi Rijista shigarwar B na mai ninka don kunna wannan siga.
Yana ƙayyade madaidaicin tushen rijistar don bas ɗin shigar da bayanai. Dole ne ku zaɓi Rijista shigarwar B na mai ninka don kunna wannan siga.
Zaɓi tushen shigarwa don shigarwar A na mai ninka.
ci gaba…

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Siga

IP Generated Parameter

Daraja

Scanout A Kanfigareshan Rajista

Yi rijistar fitarwa na sarkar duba

gui_scanouta Kunna

_yi rijista

Kashe

Menene tushen shigar agogo?

gui_scanouta _register_clock k

Clock0 Clock1 Clock2

Menene tushen shigar asynchronous share fage?

gui_scanouta _register_aclr

BABU ACLR0 ACLR1

Menene tushen shigar da bayanan da ke aiki tare?

gui_scanouta _register_sclr

BABU SCLR0 SCLR1

8.6.4. Prereader Tab

Table 33. Preadder Tab

Siga

IP Generated Parameter

Daraja

Zaɓi yanayin predder

preadder_mo de

SAUKI, COEF, INPUT, SQUARE, na dindindin

Default Value

Bayani
Zaɓi shigarwar Multiplier don amfani da bas ɗin shigar da bayanai a matsayin tushen zuwa mai ninka. Zaɓi shigarwar sarkar Scan don amfani da bas ɗin shigar da scanin azaman tushen mai ninka kuma kunna bas ɗin fitarwa. Ana samun wannan siga lokacin da kuka zaɓi 2, 3 ko 4 don Menene adadin masu yawa? siga.

Kashe Clock0 BABU KODA

Zaɓi wannan zaɓi don kunna rajistar fitarwa don bas ɗin fitarwa na scanouta.
Dole ne ku zaɓi shigarwar sarkar Scan don Menene shigarwar A na mai ninka da aka haɗa zuwa? siga don kunna wannan zaɓi.
Zaɓi Clock0, Clock1 ko Clock2 don kunna da ƙididdige siginar shigar agogon rajista don bas ɗin fitarwa.
Dole ne ku kunna fitarwar rajista na ma'aunin sarkar duba don kunna wannan zaɓi.
Yana ƙayyade madaidaicin tushen rajistar don bas ɗin fitarwa na scanouta.
Dole ne ku kunna fitarwar rajista na ma'aunin sarkar duba don kunna wannan zaɓi.
Yana ƙayyade madaidaicin tushen rijistar don bas ɗin fitarwa na scanouta.
Dole ne ku zaɓi fitarwar rajista na ma'aunin sarkar duba don kunna wannan zaɓi.

Default Value
SAUKI

Bayani
Yana ƙayyadaddun yanayin aiki don ƙirar mai gabatarwa. SAUKI: Wannan yanayin yana ƙetare predder. Wannan shine yanayin tsoho. COEF: Wannan yanayin yana amfani da fitarwa na preadder da bas ɗin shigar da coefsel a matsayin abubuwan da ake shigar da su zuwa mai ninka. INPUT: Wannan yanayin yana amfani da fitarwa na preadder da bas ɗin shigar da bayanai a matsayin abubuwan da ake shigar da su zuwa mai ninka. SQUARE: Wannan yanayin yana amfani da fitarwa na predder a matsayin duka abubuwan da aka shigar zuwa mai ninka.
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Siga

IP Generated Parameter

Daraja

Zaɓi jagorar mai gabatarwa

gui_preadder ADD,

_magana

SUB

Yaya fadi ya kamata motocin shigar da C width_c su kasance?

1-256

Kanfigareshan Shigar Bayanai C

Yi rijistar shigar datac

gui_datac_inp Kunna

ut_yi rijista

Kashe

Menene tushen shigar agogo?

gui_datac_inp ut_register_cl ock

Clock0 Clock1 Clock2

Menene tushen shigar asynchronous share fage?

gui_datac_inp ut_register_a clr

BABU ACLR0 ACLR1

Menene tushen shigar da bayanan da ke aiki tare?

gui_datac_inp ut_register_sc lr

BABU SCLR0 SCLR1

Haɗin kai
Yaya fadi ya kamata fadin coef ɗin ya kasance?

fadi_coef

1-27

Kanfigareshan Rijistar Coef

Yi rijistar shigarwar coefsel

gui_coef_regi Kunna

ster

Kashe

Menene tushen shigar agogo?

gui_coef_regi ster_clock

Clock0 Clock1 Clock2

Default Value
KARA
16

Bayani
CONSTANT: Wannan yanayin yana amfani da bas ɗin shigar da bayanai tare da preadder da bas ɗin shigarwar coefsel a matsayin abubuwan shigar da masu ninkawa.
Ƙayyadaddun aiki na predder. Domin kunna wannan siga, zaɓi waɗannan abubuwan don Zaɓi yanayin Preadder: · COEF · INPUT · SQUARE ko · CONSTANT
Yana ƙayyade adadin rago don shigar da bas ɗin C. Dole ne ku zaɓi INPUT don Zaɓi yanayin prepreder don kunna wannan sigar.

A Clock0 BABU KOWA

Zaɓi wannan zaɓi don kunna rajistar shigarwa don bas ɗin shigarwar datac. Dole ne ku saita INPUT zuwa Zaɓi siginar yanayin prepreder don kunna wannan zaɓi.
Zaɓi Clock0, Clock1 ko Clock2 don ƙididdige siginar shigarwar agogo don rijistar shigarwar datac. Dole ne ku zaɓi shigar da bayanan da aka yi rajista don kunna wannan siga.
Yana ƙayyade madaidaicin tushe mai tushe don rajistar shigarwar bayanai. Dole ne ku zaɓi shigar da bayanan da aka yi rajista don kunna wannan siga.
Yana ƙayyade madaidaicin tushe mai aiki tare don rajistar shigarwar bayanai. Dole ne ku zaɓi shigar da bayanan da aka yi rajista don kunna wannan siga.

Yana ƙayyadadden adadin rago don

coefsel shigar bas.

Dole ne ku zaɓi COEF ko CONSTANT don yanayin prereader don kunna wannan siga.

A agogo 0

Zaɓi wannan zaɓi don kunna rajistar shigarwa don bas ɗin shigarwar coefsel. Dole ne ku zaɓi COEF ko CONSTANT don yanayin prereader don kunna wannan siga.
Zaɓi Clock0, Clock1 ko Clock2 don ƙididdige siginar shigarwar agogo don rajistar shigarwar coefsel. Dole ne ku zaɓi Rijista shigarwar coefsel don kunna wannan siga.
ci gaba…

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Siga
Menene tushen shigar asynchronous share fage?

IP Generated Parameter

Daraja

gui_coef_regi ster_aclr

BABU ACLR0 ACLR1

Menene tushen shigar da bayyanannen aiki tare

gui_coef_regi ster_sclr

BABU SCLR0 SCLR1

Coefficient_0 Kanfigareshan

coef0_0 zuwa coef0_7

0x00000 0xFFFFFF

Coefficient_1 Kanfigareshan

coef1_0 zuwa coef1_7

0x00000 0xFFFFFF

Coefficient_2 Kanfigareshan

coef2_0 zuwa coef2_7

0x00000 0xFFFFFF

Coefficient_3 Kanfigareshan

coef3_0 zuwa coef3_7

0x00000 0xFFFFFF

8.6.5. Accumulator Tab

Table 34. Accumulator Tab

Siga

IP Generated Parameter

Daraja

Kunna tarawa?

mai tarawa

E, A'A

Menene nau'in aikin tarawa?

accum_directi ADD,

SUB

Default Value BABU
BABU
0 x0000000
0 x0000000
0 x0000000
0 x0000000

Bayani
Yana ƙayyade madaidaicin tushe mai tushe don rajistar shigarwar coefsel. Dole ne ku zaɓi Rijista shigarwar coefsel don kunna wannan siga.
Yana ƙayyade madaidaicin tushe mai daidaitawa don rajistar shigarwar coefsel. Dole ne ku zaɓi Rijista shigarwar coefsel don kunna wannan siga.
Yana ƙayyadad da ƙididdiga masu ƙima don wannan mai yawa na farko. Dole ne adadin ragowa ya kasance daidai da ƙayyadaddun a Yaya faɗin coef ɗin ya zama? siga. Dole ne ku zaɓi COEF ko CONSTANT don yanayin prereader don kunna wannan siga.
Yana ƙayyadad da ƙididdiga masu ƙima don wannan mai yawa na biyu. Dole ne adadin ragowa ya kasance daidai da ƙayyadaddun a Yaya faɗin coef ɗin ya zama? siga. Dole ne ku zaɓi COEF ko CONSTANT don yanayin prereader don kunna wannan siga.
Yana ƙayyadad da ƙididdiga masu ƙima don wannan mai yawa na uku. Dole ne adadin ragowa ya kasance daidai da ƙayyadaddun a Yaya faɗin coef ɗin ya zama? siga. Dole ne ku zaɓi COEF ko CONSTANT don yanayin prereader don kunna wannan siga.
Yana ƙayyadad da ƙididdiga masu ƙima don wannan ninka na huɗu. Dole ne adadin ragowa ya kasance daidai da ƙayyadaddun a Yaya faɗin coef ɗin ya zama? siga. Dole ne ku zaɓi COEF ko CONSTANT don yanayin prereader don kunna wannan siga.

Default Value NO
KARA

Bayani
Zaɓi YES don kunna mai tarawa. Dole ne ku zaɓi Fitar da fitarwa na naúrar ƙara lokacin yin amfani da fasalin tarawa.
Yana ƙayyade aikin tarawa: · ADD don ƙarin aiki · SUB don aikin ragi. Dole ne ku zaɓi YES don Kunna tara tara? siga don kunna wannan zaɓi.
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Siga
Preload Constant Kunna ƙaddamarwa akai-akai

IP Generated Parameter

Daraja

gui_ena_prelo Kunna

ad_const

Kashe

Menene shigar da tashar tashar tara da aka haɗa zuwa?

gui_accumula ACCUM_SLOAD, te_port_select SLOAD_ACCUM

Zaɓi ƙima don ƙaddamarwa da farko loadconst_val 0 - 64

Menene tushen shigar agogo?

gui_accum_sl oad_register_ agogo

Clock0 Clock1 Clock2

Menene tushen shigar asynchronous share fage?

gui_accum_sl oad_register_ aclr

BABU ACLR0 ACLR1

Menene tushen shigar da bayanan da ke aiki tare?

gui_accum_sl oad_register_ sclr

BABU SCLR0 SCLR1

Kunna tara tara biyu

gui_biyu_a Kunna

kum

Kashe

Default Value

Bayani

Kashe

Kunna accum_sload ko

sload_accum sigina da shigar da rajista

don zabar shigarwar zuwa ga

mai tarawa.

Lokacin da accum_sload yayi ƙasa ko sload_accum, ana ciyar da fitarwa mai yawa a cikin mai tarawa.

Lokacin da accum_sload yayi girma ko sload_accum, mai amfani da aka ƙayyade akai-akai ana ciyar da shi a cikin mai tarawa.

Dole ne ku zaɓi YES don Kunna tara tara? siga don kunna wannan zaɓi.

ACCUM_SL OAD

Yana ƙayyadadden halayen siginar accum_sload/ sload_accum.
ACCUM_SLOAD: Fitar accum_sload ƙasa da ƙasa don loda fitarwa mai yawa zuwa mai tarawa.
SLOAD_ACCUM: Fitar da sload_accum mai tsayi don loda fitarwa mai yawa zuwa mai tarawa.
Dole ne ku zaɓi Kunna zaɓi na dindindin don kunna wannan siga.

Ƙimar da aka saita akai akai.

Wannan ƙimar na iya zama 2N inda N shine ƙimar da aka saita akai-akai.

Lokacin N=64, yana wakiltar sifili akai-akai.

Dole ne ku zaɓi Kunna zaɓi na dindindin don kunna wannan siga.

Agogo0

Zaɓi Clock0, Clock1 ko Clock2 don tantance siginar shigar agogon don rajistar accum_sload/sload_accum.
Dole ne ku zaɓi Kunna zaɓi na dindindin don kunna wannan siga.

BABU

Yana ƙayyade madaidaicin tushe mai tushe don rajistar accum_sload/sload_accum.
Dole ne ku zaɓi Kunna zaɓi na dindindin don kunna wannan siga.

BABU

Yana ƙayyade madaidaicin tushen tushe don rajistar accum_sload/sload_accum.
Dole ne ku zaɓi Kunna zaɓi na dindindin don kunna wannan siga.

Kashe

Yana kunna rijistar tarawa biyu.

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 54

Aika da martani

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8.6.6. Systolic/Chainout Tab

Table 35. Systolic/Chainout Adder Tab

Siga Kunna ƙara sarƙoƙi

IP Generated Parameter

Daraja

chainout_kara YES,

A'A

Menene nau'in aikin chainout adder?

chainout_kara ADD,

er_direction

SUB

Kunna shigarwar 'negate' don ƙarar sarƙoƙi?

Port_negate

PORT_USED, PORT_UNUSED

Shigar da 'babu'? negate_regist

BA a yi rijista ba, CLOCK0, CLOCK1, CLOCK2, CLOCK3

Menene tushen shigar asynchronous share fage?

negate_aclr

BABU ACLR0 ACLR1

Menene tushen shigar da bayanan da ke aiki tare?

negate_sclr

BABU SCLR0 SCLR1

Jinkirin systolic
Kunna rajistar jinkiri na systolic

gui_systolic_d Kunna

elay

Kashe

Menene tushen shigar agogo?

gui_systolic_d CLOCK0,

elay_clock

KYAUTA 1,

Default Value
A'A

Bayani
Zaɓi YES don kunna tsarin ƙarar sarƙoƙi.

KARA

Yana ƙayyadaddun aiki na chainout adder.
Don aikin ragi, dole ne a zaɓi SIGNED don Menene tsarin wakilcin abubuwan shigarwar Multipliers A? kuma Menene tsarin wakilci don abubuwan shigar da Multipliers B? a cikin Multipliers Tab.

PORT_UN AMFANI

Zaɓi PORT_USED don kunna siginar shigar da ba daidai ba.
Wannan sigar ba ta da inganci lokacin da aka kashe sarƙoƙin sarƙoƙi.

RASHIN rijista

Don kunna rajistar shigarwa don siginar shigarwar negate kuma tana ƙayyade siginar agogon shigarwa don rajistar negate.
Zaɓi BABU REGISTER idan ba a buƙatar rajistar shigarwar da ba a buƙata ba
Wannan sigar ba ta aiki lokacin da kuka zaɓi:
NO don Kunna ƙara sarƙoƙi ko
· PORT_UNUSED don Kunna shigar da 'negate' don ƙara sarkar? siga ko

BABU

Yana ƙayyadad da tushen asynchronous bayyananne don rajistar saƙo.
Wannan sigar ba ta aiki lokacin da kuka zaɓi:
NO don Kunna ƙara sarƙoƙi ko
· PORT_UNUSED don Kunna shigar da 'negate' don ƙara sarkar? siga ko

BABU

Yana ƙayyade madaidaicin tushe mai aiki tare don rajistar saƙo.
Wannan sigar ba ta aiki lokacin da kuka zaɓi:
NO don Kunna ƙara sarƙoƙi ko
· PORT_UNUSED don Kunna shigar da 'negate' don ƙara sarkar? siga ko

Kashe CLOCK0

Zaɓi wannan zaɓi don kunna yanayin systolic. Ana samun wannan siga lokacin da kuka zaɓi 2, ko 4 don Menene adadin masu yawa? siga. Dole ne ku kunna fitarwar Rijista na sashin ƙara don amfani da rajistar jinkiri na systolic.
Yana ƙayyade siginar agogon shigarwa don rajistar jinkiri na systolic.
ci gaba…

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Siga

IP Generated Parameter

Daraja

KYAUTA 2,

Menene tushen shigar asynchronous share fage?

gui_systolic_d elay_aclr

BABU ACLR0 ACLR1

Menene tushen shigar da bayanan da ke aiki tare?

gui_systolic_d elay_sclr

BABU SCLR0 SCLR1

Default Value
BABU
BABU

Bayani
Dole ne ku zaɓi kunna rajistan jinkiri na systolic don kunna wannan zaɓi.
Yana ƙayyade madaidaicin tushe mai tushe don rajistar jinkiri na systolic. Dole ne ku zaɓi kunna rajistan jinkiri na systolic don kunna wannan zaɓi.
Yana ƙayyade madaidaicin tushe mai daidaitawa don rajistar jinkiri na systolic. Dole ne ku zaɓi kunna rajistan jinkiri na systolic don kunna wannan zaɓi.

8.6.7. Tabbar bututun mai

Tebur 36. Tabbar bututun mai

Kanfigareshan Tsarukan Bututu

IP Generated Parameter

Daraja

Kuna so ku ƙara rajistar bututun zuwa shigarwar?

gui_pipelining A'a, Ee

Default Value
A'a

Da fatan za a saka

latency

adadin agogon latency

hawan keke

Kowane darajar da ta fi 0 fiye da 0

Menene tushen shigar agogo?

gui_input_late ncy_clock

CLOCK0, CLOCK1, CLOCK2

Menene tushen shigar asynchronous share fage?

gui_input_late ncy_aclr

BABU ACLR0 ACLR1

Menene tushen shigar da bayanan da ke aiki tare?

gui_input_late ncy_sclr

BABU SCLR0 SCLR1

CLOCK0 BABU KOWA

Bayani
Zaɓi Ee don ba da damar ƙarin matakin rajistar bututun zuwa siginar shigarwa. Dole ne ku saka ƙima sama da 0 don Da fatan za a saka adadin ma'auni na latency.
Yana ƙayyadadden jinkirin da ake so a cikin zagayowar agogo. Mataki ɗaya na rajistar bututu = latency 1 a cikin zagayowar agogo. Dole ne ku zaɓi YES don Kuna so ku ƙara rajistar bututun zuwa shigarwar? don kunna wannan zaɓi.
Zaɓi Clock0, Clock1 ko Clock2 don kunnawa da ƙididdige siginar shigar agogon rajistar bututun. Dole ne ku zaɓi YES don Kuna so ku ƙara rajistar bututun zuwa shigarwar? don kunna wannan zaɓi.
Yana ƙayyade madaidaicin tushen rijistar don ƙarin rajistar bututun mai. Dole ne ku zaɓi YES don Kuna so ku ƙara rajistar bututun zuwa shigarwar? don kunna wannan zaɓi.
Yana ƙayyade madaidaicin tushen rajistar don ƙarin rajistar bututun mai. Dole ne ku zaɓi YES don Kuna so ku ƙara rajistar bututun zuwa shigarwar? don kunna wannan zaɓi.

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 56

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683490 | 2020.10.05 Aika Ra'ayoyin

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core

Hankali:

Intel ya cire goyon bayan wannan IP a cikin Intel Quartus Prime Pro Edition 20.3. Idan ainihin IP ɗin da ke cikin ƙira ɗin ku ya yi niyya ga na'urori a cikin Intel Quartus Prime Pro Edition, zaku iya maye gurbin IP da LPM_MULT Intel FPGA IP ko sake ƙirƙira IP ɗin ku tattara ƙirarku ta amfani da Intel Quartus Prime Standard Edition software.

Ana amfani da ALTMEMMULT IP core don ƙirƙirar masu haɓaka tushen ƙwaƙwalwar ajiya ta amfani da tubalan ƙwaƙwalwar onchip da aka samo a cikin Intel FPGAs (tare da M512, M4K, M9K, da tubalan ƙwaƙwalwar MLAB). Wannan ainihin IP ɗin yana da amfani idan ba ku da isassun albarkatu don aiwatar da masu haɓakawa a cikin abubuwan dabaru (LEs) ko keɓaɓɓun albarkatu masu yawa.
AlTMEMMULT IP core aiki ne na aiki tare wanda ke buƙatar agogo. AlTMEMMULT IP core yana aiwatar da mai haɓakawa tare da mafi ƙarancin kayan aiki da latency mai yuwuwa don saitin sigogi da ƙayyadaddun bayanai.
Hoto mai zuwa yana nuna tashar jiragen ruwa na ALTMEMMULT IP core.

Hoto 21. ALTMEMMULT Ports

ALTMEMMULT

data_in[] sload_data coeff_in[]

sakamako[] sakamako_ingantacciyar load_yi

sload_coeff

sclr agogo
inst

Siffofin Bayani masu alaƙa a shafi na 71

9.1. Features
AlTMEMMULT IP core yana ba da fasalulluka masu zuwa: · Yana ƙirƙira masu haɓaka tushen ƙwaƙwalwar ajiya kawai ta amfani da tubalan ƙwaƙwalwar guntu da aka samu a ciki.
Intel FPGAs · Yana goyan bayan faɗin bayanai na 1 bits · Yana goyan bayan sa hannu da tsarin wakilcin bayanan da ba a sanya hannu ba · Yana goyan bayan bututun mai tare da tsayayyen fitarwa.

ISO 9001: 2015 Rajista

9. ALTMEMMULT (Memory tushen Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05
* Yana adana maɓalli masu yawa a cikin ƙwaƙwalwar shiga bazuwar (RAM)
· Yana ba da zaɓi don zaɓar nau'in block na RAM
· Yana goyan bayan fayyace mashigai na zaɓi na aiki tare da mashigai masu sarrafa kaya
9.2. Verilog HDL Prototype
Samfurin Verilog HDL mai zuwa yana cikin Tsarin Verilog File (.v) altera_mf.v a cikin eda synthesis directory.
module altmemmult #(parameter coeff_representation = "SIGNED", parameter coefficient0 = "UNUSED", parameter data_representation = "SIGNED", parameter meant_device_family = "ba a yi amfani da shi ba", parameter max_clock_cycles_per_result = 1, parameter number_of_lockefficients "AUSE parameter number_of_locks" total_latency = 1, siga width_c = 1, siga width_d = 1, siga width_r = 1, siga width_s = 1, siga lpm_type = "altmemmult", siga lpm_hint = "ba a yi amfani da shi ba") ( agogon shigarwa, waya shigarwa [nisa_c-1: 1]coeff_in, shigar da waya [width_d-0:1] data_in, fitarwa waya load_done, fitarwa waya [width_r-0:1] sakamakon, fitarwa waya sakamakon_valid, shigar da waya sclr, shigar da waya [width_s-0:1] sel, shigarwa waya sload_coeff, shigar da waya sload_data)/* kira syn_black_box = 0 */; endmodule
9.3. Bayanin Bangaren VHDL
Bayanin ɓangaren VHDL yana cikin Tsarin VHDL File (.vhd) altera_mf_components.vhd a cikin librariesvhdlaltera_mf directory.
bangaren altmemmult generic (coeff_representation: kirtani: = "SIGNED"; coefficient0: kirtani: = "UNUSED"; data_representation: kirtani: = "SIGNED"; nufin_device_family: kirtani : = "ba a yi amfani da shi"; max_clock_cycles_per_result = coefficient: 1 natural lamba: _natural lamba : = 1; ram_block_type: kirtani: = "AUTO"; total_latency: natural; width_c: natural; width_d: natural; width_r: natural; width_s: natural: = 1; lpm_hint: kirtani: = "UNUSED"; lpm_type: kirtani: = "altmemmult"); tashar jiragen ruwa (agogo: in std_logic; coeff_in: a cikin std_logic_vector (nisa_c-1 zuwa 0): = (wasu => '0'); data_in: in std_logic_vector (width_d-1 zuwa 0);

Jagorar Mai Amfani da Integer FPGA Integer IP Cores 58

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9. ALTMEMMULT (Memory tushen Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

load_yi: fita std_logic; sakamako: fita std_logic_vector (nisa_r-1 zuwa 0); result_valid: fita std_logic; sclr: a cikin std_logic: = '0'; sel: a cikin std_logic_vector (nisa_s-1 zuwa 0): = (sauran => '0'); sload_coeff: a cikin std_logic: = '0'; sload_data: a cikin std_logic: = '0'); bangaren ƙarshe;

9.4. Tashoshi

Tebura masu zuwa suna jera abubuwan shigarwa da tashar jiragen ruwa na ALTMEMMULT IP core.

Tebur 37. ALTMEMMULT Mashigai Mashigai

Sunan tashar jiragen ruwa

Da ake bukata

Bayani

agogo

Shigar da agogo zuwa mai ninka.

coeff_in[]

A'a

Ƙaddamarwa tashar shigar da bayanai don mai yawa. Girman tashar shigarwar ya dogara da ƙimar sigar WIDTH_C.

data_in[]

tashar shigar da bayanai zuwa mai yawa. Girman tashar shigarwar ya dogara da ƙimar sigar WIDTH_D.

sclr

A'a

Shigar da bayanan aiki tare. Idan ba a yi amfani da shi ba, ƙimar tsoho tana aiki babba.

sel[]

A'a

Kafaffen zaɓin ƙididdiga. Girman tashar shigarwar ya dogara da WIDTH_S

ƙimar siga.

sload_coeff

A'a

Tashar tashar shigar da madaidaicin nauyin nauyi. Yana maye gurbin ƙima da aka zaɓa na yanzu tare da ƙimar da aka ƙayyade a cikin shigarwar coeff_in.

sload_data

A'a

tashar shigar da bayanai na aiki tare. Alamar siginar da ke ƙayyadad da sabon aikin ninkawa kuma yana soke duk wani aiki na ninkawa da ke akwai. Idan ma'aunin MAX_CLOCK_CYCLES_PER_RESULT yana da darajar 1, ba a kula da tashar shigar da bayanan sload_data.

Tebura 38. ALTMEMMULT Mashigai na Fitowa

Sunan tashar jiragen ruwa

Da ake bukata

Bayani

sakamako[]

Multiplier fitarwa tashar jiragen ruwa. Girman tashar shigarwar ya dogara da ƙimar sigar WIDTH_R.

sakamako_mai inganci

Yana nuna lokacin da fitarwa shine ingantaccen sakamako na cikakken ninkawa. Idan ma'aunin MAX_CLOCK_CYCLES_PER_RESULT yana da darajar 1, ba a amfani da tashar fitarwa mai inganci.

kaya_yi

A'a

Yana nuna lokacin da sabuwar ƙididdiga ta gama lodi. Siginar load_done yana tabbatarwa lokacin da sabuwar ƙididdiga ta gama lodi. Sai dai idan siginar load_done ya yi girma, ba za a iya loda wata ƙimar ƙima cikin ƙwaƙwalwar ajiya ba.

9.5. Sigogi

Tebur mai zuwa yana lissafin sigogi don ALTMEMMULT IP core.

Tebur 39.
WIDTH_D WIDTH_C

Alamar ALTMEMMULT
Sunan Siga

Nau'in da ake buƙata

Bayani

Integer Ee

Yana ƙayyade faɗin tashar tashar data_in[].

Integer Ee

Yana ƙayyade faɗin tashar tashar coeff_in[]. ci gaba…

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Jagorar Mai Amfani da Integer FPGA Integer IP Cores 59

9. ALTMEMMULT (Memory tushen Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

Sigar Suna WIDTH_R WIDTH

Takardu / Albarkatu

intel FPGA Integer Arithmetic IP Cores [pdf] Jagorar mai amfani
FPGA Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙwararren Ƙadda ) na Ƙarƙatawa ne na Ƙarfafawa na Ƙiƙa na Ƙiƙa na Ƙiƙa na Ƙiƙa na Ƙiƙa na Ƙiƙa na Ƙiƙa na Ƙiƙa na Ƙiƙa na Ƙiƙa na Ƙiƙa na FPGA )

Magana

Manual mai amfani

FPGA Integer Rithmetic IP Cores

Takardu / Albarkatu

Magana

Bar sharhi

Soke amsa