GOWIN IPUG1174-1.0E USB 2.0 Host Controller IP

IMPORTANT INFORMATION

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Revision History

List of Figures

Figure 3-1 USB 2.0 Host Controller Block Diagram………………………………………………………………… 5
Figure 4-1 Timing Diagram of Host Controller Read Register ………………………………………………….. 9
Figure 4-2 Timing Diagram of Host Controller Write Register ………………………………………………….. 10
Figure 4-3 Timing Diagram of Host Controller DMA Read……………………………………………………….. 11
Figure 4-4 Timing Diagram of Host Controller DMA Write……………………………………………………….. 11
Figure 5-1 IP Core Generator ……………………………………………………………………………………………… 13
Figure 5-2 USB 2.0 Host Controller IP Core………………………………………………………………………….. 14
Figure 5-3 USB 2.0 Host Controller Configuration Interface ……………………………………………………. 14

List of Tables

Table 1-1 Terminology and Abbreviations ……………………………………………………………………………… 2
Table 2-1 Gowin USB 2.0 Host Controller IP Overview …………………………………………………………… 3
Table 2-2 Resource Utilization …………………………………………………………………………………………….. 4
Table 3-1 Internal Register Distribution of USB 2.0 Host Controller………………………………………….. 6
Table 3-2 MEMADDR Register ……………………………………………………………………………………………. 7
Table 3-3 DMACONFIG Register…………………………………………………………………………………………. 7
Table 4-1 Signal Definitions ………………………………………………………………………………………………… 8
Table 4-2 Timing Characteristics………………………………………………………………………………………….. 11

About This Guide

Purpose

The purpose of Gowin USB 2.0 Host Controller IP User Guide is to help you learn the features and usage of Gowin USB 2.0 Host Controller IP by providing functional description, signal description and interface configuration. The software screenshots in this manual are based on 1.9.9 Beta-6. As the software is subject to change without notice, some information may not remain relevant and may need to be adjusted according to the software that is in use.

Related Documents

The latest user guides are available on the GOWINSEMI Website.
You can find the related documents at www.gowinsemi.com/:

• DS100, GW1N series of FPGA Products Data Sheet
• DS117, GW1NR series of FPGA Products Data Sheet
• DS891, GW1NRF series of FPGA Products Data Sheet
• DS821, GW1NS series of FPGA Products Data Sheet
• DS871, GW1NSE series FPGA Products Data Sheet
• DS881, GW1NSER series FPGA Products Data Sheet
• DS861, GW1NSR series of FPGA Products Data Sheet
• DS102, GW2A series of FPGA Products Data Sheet
• DS226, GW2AR series of FPGA Products Data Sheet
• DS971, GW2AN-18X &9X Data Sheet
• DS976, GW2AN-55 Data Sheet
• DS981, GW5AT series of FPGA Products Data Sheet
• DS1103, GW5A series of FPGA Products Data Sheet
• DS981, GW5AST series of FPGA Products Data Sheet
• SUG100, Gowin Software User Guide

Terminology and Abbreviations

The terminology and abbreviations used in this manual are as shown in Table 1-1.

Table 1-1 Terminology and Abbreviations

Support and Feedback

Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: support@gowinsemi.com

Introduction

Overview

Universal Serial Bus, commonly known as USB, is an external bus used to standardize the connection and communication between computers and external devices.
Gowin USB 2.0 Host Controller IP is based on the EHCI protocol, supporting SRAM interface, allowing connection to any microprocessor supporting the SRAM interface. It also supports ULPI interface, allowing connection to any USB 2.0 transceiver supporting the ULPI interface. It includes an internal 24K RAM space for storing transmission descriptors and data.

Table 2-1 Gowin USB 2.0 Host Controller IP Overview

Note!
For the devices supported, you can click here to get the information.

Features

The features of Gowin USB 2.0 Host Controller IP are as follows:

• Supports high-speed (480 Mbps), full-speed (12Mbps), and low-speed (1.5Mbps)
• Supports device plug-and-play detection, reset, high-speed handshake, suspend, and wake-up
• Supports control transfer, bulk transfer, synchronous transfer, and interrupt transfer
• Supports split control transfer, split bulk transfer, split synchronous transfer, and split interrupt transfer
• Supports USB transceiver macrocell interface (ULPI)
• Supports SRAM interface as well as direct memory access (DMA) operations

Resource Utilization

Gowin USB 2.0 Host Controller IP can be implemented by Verilog language. Its performance and resource utilization may vary when the design is employed in different devices, or at different densities, speeds, or grades. Taking Gowin GW2AN-18 series of FPGA as an instance, the resource utilization of Gowin USB 2.0 Host Controller IP is as shown in Table 2-2.

Table 2-2 Resource Utilization

Functional Description

USB 2.0 Host Controller Structure

The USB 2.0 Host Controller is located between the microprocessor and downstream USB device. The USB 2.0 Host Controller links the microprocessor with downstream USB devices, receiving commands from the microprocessor, and facilitating data interaction between the microprocessor and the USB device. Figure 3-1 shows the block diagram of USB 2.0 host controller.

Figure 3-1 USB 2.0 Host Controller Block Diagram

Register Definition

This section introduces the internal register distribution of USB 2.0 Host Controller. The internal registers of the host controller include three categories: Capability registers, Operational registers, and DMA registers.

Table 3-1 Internal Register Distribution of USB 2.0 Host Controller

Capability Register

You can see the Section 2.2 of the Enhanced Host Controller Interface Specification for Universal Serial Bus protocol for the definitions of each field in the Capability registers.

Operational Register

You can see the Section 2.3 of the Enhanced Host Controller Interface Specification for Universal Serial Bus protocol for the definitions of each field in the Operational registers.

DMA Register

MEMADDR (DMA Start Address)

Address 54h
Size: 32 bits

This register is used to store the start address for each DMA read/write.

Table 3-2 MEMADDR Register

DMACONFIG (DMA Configuration)

Address 58h
Size:32 bits

This register is used to store each DMA read/write command.

Table 3-3 DMACONFIG Register

Signal Descriptions

Signal Definitions

Signal definitions of Gowin USB 2.0 Host Controller IP are as shown in Table 4-1.
Table 4-1 Signal Definition

Note!
[1] This interface is used to connect external ULPI PHY.

USB 2.0 Host Controller SDRAM Interface Timing

When the user needs to read register, set cs_n_i to 0 and addr_i to register address, and control rd_n_i to generate a negative pulse. The read data will be output to dat_io waiting for Toe after the falling edge of rd_n_i. When the user needs to write register, set cs_n_i to 0 and addr_i to register address, input the write data to dat_io, and control wr_n_i to generate a negative pulse. The write data will be written to the destination register waiting for Tadhw after the rising edge of wr_n_i.

Note!

• Each read and write operation to a register requires a unit of 4 bytes.
• For timing characteristics, see Table 4-2.

Figure 4-1 and Figure 4-2 are respectively the read and write register timing diagrams.
Figure 4-1 Timing Diagram of Host Controller Read Register

Figure 4-2 Timing Diagram of Host Controller Write Register

When the user needs to read or write internal RAM, it is necessary to initiate the process through the DMA method. If a DMA operation is required, the user first needs to write the start address to the MEMADDR register. Subsequently, the DMA write/read command along with the data length should be written to the DMACONFIG register, and the DMA enable field should be set to 1. Upon the host controller setting dreq_o to 1, the user sets dack_i to 0, entering DMA write/read mode.
During the DMA read process, the user controls rd_n_i to generate a negative pulse, and the host controller outputs the data in address order to the data bus waiting for Toe after each falling edge of rd_n_i.
During the DMA write process, the user controls wr_n_i to generate a negative pulse, and the host controller writes the data in address order to the internal RAM space on each rising edge of wr_n_i.
Throughout the DMA read/write process, the host controller calculates the number of wr_n_i/rd_n_i pulses. When the count reaches the byte length preset in DMACONFIG, the host controller sets dreq_o to 0, ending the current DMA operation.
Figure 4-3 and Figure 4-4 are respectively the DMA read and write timing diagrams.

Figure 4-3 Timing Diagram of Host Controller DMA Read

Figure 4-4 Timing Diagram of Host Controller DMA Write

Table 4-2 Timing Characteristics

Interface Configuration

You can click “Tools > IP Core Generator” in Gowin Software to call and configure USB 2.0 Host Controller.

1. Open IP Core Generator
   After creating the project, you can click the “Tools” tab in the upper-left corner, then click the “IP Core Generator” via the drop-down list, as shown in Figure 5-1.
   Figure 5-1 IP Core Generator
   
   
2. Open USB 2.0 Host Controller IP Core
   Select “Soft IP Core > Interface and Interconnect > USB 2.0 Host Controller IP”, as shown in Figure 5-2. Double-click to open the configuration interface.
   Figure 5-2 USB 2.0 Host Controller IP Core
   
   
3. USB 2.0 Host Controller IP Core Configuration Interface
   The USB 2.0 Host Controller IP core configuration interface is shown in Figure 5-3. The port diagram is on the left, and the options are on the right.
   • You can configure the generated file name in “File Name” text box.
   • You can configure the generated top module name in “Module Name” text box.
     Figure 5-3 USB 2.0 Host Controller Configuration Interface
     
     

Documents / Resources

GOWIN IPUG1174-1.0E USB 2.0 Host Controller IP [pdf] User Guide IPUG1174-1.0E Gowin USB 2.0 Host Controller IP, IPUG1174-1.0E, Gowin USB 2.0 Host Controller IP, USB 2.0 Host Controller IP, 2.0 Host Controller IP, Host Controller IP, Controller IP

References

• User Manual