Gowin 10G Serial Ethernet IP
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About This Guide
Purpose
The purpose of Gowin 10G Serial Ethernet IP User Guide is to help you learn the features and usage of Gowin 10G Serial Ethernet IP by providing the descriptions of functions, GUI, and reference design, etc. The software screenshots and the supported products listed in this manual are based on Gowin Software V1.9.9. As the software is subject to change without notice, some information may not remain relevant and may need to be adjusted according to the software that is in use.
Related Documents
The latest user guides are available on the GOWINSEMI website. You can find the related documents at www.gowinsemi.com:
- SUG100, Gowin Software User Guide
- DS981, GW5AT series of FPGA Products Data Sheet
- DS1103, GW5A series of FPGA Products Data Sheet
- DS1239, GW5AST series of FPGA Products Data Sheet
- DS1105, GW5AS series of FPGA Products Data Sheet
Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown in Table 1-1.
Table 1-1 Terminology and Abbreviations
Support and Feedback
Gowin Semiconductor provides customers with comprehensive technical support. If you have any questions, comments, or suggestions, please feel free to contact us directly using the information provided below.
- Website: www.gowinsemi.com
- E-mail: support@gowinsemi.com
Overview
Gowin 10G Serial Ethernet IP implements the functions described in IEEE 802.3 standard Clause 49 for 10GBASE-R, providing the functions of the Physical Medium Attachment (PMA) and Physical Coding Sublayer (PCS). It offers users an XGMII (10-Gigabit Media Independent Interface) in accordance with IEEE 802.3 Clause 46 definition. This IP can be integrated into devices that comply with 10GBASE-R serial Ethernet, commonly used in communication applications.
Table 2-1 Gowin 10G Serial Ethernet IP
Note!
For the devices supported, you can click here to get the information.
Features
- Supports IEEE802.3 Clause 49
- Supports 10GBASE-R PMA/PCS layer protocols
- Supports 10.3125Gbps
- Supports 64/66B decoding error block statistics (Only GW5AT-138/75 support this feature)
- Supports decoding error block statistics for 64/66B
- Supports serial data scrambling and descrambling
- Supports BER monitor (Only GW5AT-138/75 support this feature)
- Supports a user-side XGMII as defined by IEEE 802.3 Clause 46
- Supports RX clock elastic buffer
Operating Frequency
Gowin 10G Serial Ethernet IP operates internally at 161.2 MHz and 156.25 MHz, and the XGMII operates at 156.25 MHz.
Resource Utilization
Gowin 10G Serial Ethernet IP can be implemented by Verilog. Its performance and resource utilization may vary when the design is employed in different devices, or at different densities, speeds, or grades. Taking Gowin GW5AT series of FPGA as an instance, the resource utilization is as shown in Table 2-2. GW5AT-60/GW5AT-15 devices directly use SerDes hardcore-related functions, consuming almost no logic resources. For the resource utilization of other devices, please refer to later release information.
Table 2-2 Resource Utilization
Functional Description
Structure
The basic structure of Gowin 10G Serial Ethernet IP is shown in Figure 3-1, mainly including SerDes and PCS modules. 10G Serial Ethernet IP calls SerDes hardcore as the PMA of the protocol. Simultaneously, the IP implements the 10GBASE-R PCS protocol, providing users with an XGMII. Users can call Gowin 10G Ethernet MAC IP to interface with XGMII to implement a 10G Ethernet solution. Alternatively, they can independently design a 10G Ethernet MAC and interface it with the XGMII. The User Logic in the figure refers to the User Design in the FPGA. Externally, the FPGA can communicate with other devices using an SFP+ module.
Figure 3-1 Block Diagram of Gowin 10G Serial Ethernet IP
User Interface
Reset
GW5AT-138/75
The IP supports separate resets for RX and TX. rx_rstn_i is the asynchronous reset input for the RX, and tx_rstn_i is the asynchronous reset input for the TX. Both of these asynchronous reset signals are active low. The descriptions of reset signals are shown in Table 4-1.
GW5AT-60/15
No reset input control.
Clock
Users need to provide clocks and indicator signals that meet the requirements for the IP to ensure the correct operation of the IP. The descriptions of clock signals are shown in Table 4-1. The clock is a crucial condition for the normal operation of the IP. The recommended clock connection is as follows: GW5AT-138/75
SerDes input reference clock with 156.25 MHz
As shown in Figure 3-2, the ref_clk_o clock is the SerDes input reference clock with 156.25MHz. This output clock can be directly connected to xgmii_rx_clk_i and xgmii_tx_clk_i. xgmii_rx_clk_ready_i and xgmii_tx_clk_ready_i should be assigned constant value of 1.
Figure 3-2 Clock Connection Reference (ref_clk_o outputs a clock with 156.25MHz)
SerDes input reference clock is non-156.25 MHz, and take 125MHz as an example.
As shown in Figure 3-3, the ref_clk_o clock is SerDes input reference clock with 125 MHz. This output clock can generate a 156.25 MHz clock through a PLL, which is then used as the input for xgmii_rx_clk_i and xgmii_tx_clk_i. Both xgmii_rx_clk_ready_i and xgmii_tx_clk_ready_i should be connected to the PLL LOCK signal.
Figure 3-3 Clock Connection Reference (ref_clk_o outputs a clock with 125MHz)
GW5AT-60/15
SerDes input reference clock with 156.25 MHz
As shown Figure 3-4, the ref_clk_o output clock is the SerDes input reference clock with 156.25 MHz. This output clock can be directly connected to xgmii_rx_clk_i and xgmii_tx_clk_i.
Figure 3-4 Clock Connection Reference (ref_clk_o outputs a clock with 156.25MHz)
SerDes input reference clock is non-156.25 MHz, and take 125MHz as an example.
As shown in Figure 3-5, the ref_clk_o output clock is the SerDes input reference clock with 125 MHz. This output clock needs to be passed through a PLL to generate a 156.25 MHz clock, which serves as the input for xgmii_rx_clk_i and xgmii_tx_clk_i
XGMII
The IP provides users XGMII as defined by IEEE 802.3 Clause 46. The descriptions of the XGMII signals are as shown in Table 4-1. The XGMII encoding format can be found in IEEE 802.3 Clause 46. The IP provides a 64-bit XGMII for the user, sampled at the rising edge of its synchronous clock. In contrast, the XGMII defined by IEEE 802.3 Clause 46 is 32-bit and sampled at the dual edges of the clock. The correspondence between the two is shown in Table 3-1.
Table 3-1 Correspondence between IEEE802.3 XGMII and the IP
Status Interface
Table 4-1 lists the IP status output interface. Users can utilize such interfaces to monitor the internal and link status of the IP.
Debug Interface
The IP provides a set of Debug interfaces for users, as shown in Table 4-1.
AFE (Analog Front End)
AFE means the analog front-end, and the operating speed of Gowin 10G Serial Ethernet IP is 10.3125Gbps. Users can configure the analog parameters of the IP through the interface to ensure signal integrity.
Transmit
On the transmit side, users can configure the differential swing and FFE (Feed-Forward Equalization) parameters of the IP.
Transmit Differential Swing
As shown in Figure 3-6, the differential voltage of the TX signal is Vdiff = (V+) – (V-), and the differential signal swing is Vdiffpp = 2xVdiff. Users can configure Vdiffpp through the interface, with a range of 180mV to 900mV. Figure 3-6 Transmit Differential Signal Swing Vdiffpp
TX FFE
FFE stands for Feed-Forward Equalization. The IP supports automatic and manual adjustment of the TX FFE coefficients. When the user configures the FFE Mode as Auto, the IP automatically adjusts the FFE coefficients based on the hardware environment, and in this case, the configuration of Cm, C0, and C1 is invalid. When the user configures the FFE Mode as Manual, he can manually adjust the 3-tap coefficients to configure the pre-emphasis of the TX signal. As shown in Figure 3-7, when the user configures the FFE Mode as Manual, he can adjust the values of Cm, C0, and C1 to modify the voltage amplitudes of Va, Vb, and Vc. The calculation formula is as follows:
- Va=Vdiffpp *(-Cm+C0+C1)/40
- Vb=Vdiffpp *(-Cm+C0-C1)/40
- Vc=Vdiffpp *(Cm+C0-C1)/40
Receive
Receive Differential Signal Threshold
Users can configure the SD Threshold to adjust the voltage threshold for the RX signal. When the received differential signal is greater than the SD Threshold, the SerDes determines that valid data has been received. When the received differential signal is less than the SD Threshold, the \SerDes determines that valid data has not been received, and it enters the Electrical Idle state.
Port List
For GW5AT-138/75 devices, the I/O port of Gowin 10G Serial Ethernet IP is shown in Figure 4-1.
Figure 4-1 I/O Port Diagram of Gowin 10G Serial Ethernet IP (GW5AT-138/75)
For GW5AT-60/15 devices, the I/O port of Gowin 10G Serial Ethernet IP is shown in Figure 4-2.
For the IO descriptions of Gowin 10G Serial Ethernet IP, you can see Table 4-1.
Table 4-1 IO Port List of Gowin 10G Serial Ethernet IP
Parameter Configuration
You can configure the static parameters of Gowin 10G Serial Ethernet IP according to the design requirements, as shown in Table 5-1.
Table 5-1 Static Parameters of Gowin 10G Serial Ethernet IP
Interface Configuration
You can invoke and configure Gowin 10G Serial Ethernet IP using the IP Core Generator tool in the IDE.
- Open IP Core Generator.
After creating the project, click the “Tools” tab in the upper left, click “IP Core Generator” to open Gowin IP Core Generator via the drop-down list, as shown in Figure 6-1.
Figure 6-1 IP Core Generator
- Open SerDes IP Configuration Interface.
Select “SerDes” in IP Core Generator and open SerDes IP configuration interface, as shown in Figure 6-2.
- First, configure the “General” tab in the SerDes IP interface.
- Device, Device Version, Part Number: Used to set the part number, it is determined by the current project, and the user can not set it.
- Language: Support Verilog and VHDL, and you can choose the language as a requirement, and the default is Verilog.
- File Name, Module Name, Create In: SerDes file name, module name and the generated file path settings.
You can select the protocol in the “Protocol” option according to your needs. Click “the Create” button on the right to open the protocol configuration, and it displays the current protocols supported by SerDes IP and the corresponding Quad, PLL and Lane usage; on the right side, it displays the information about the selected protocol, including “Information”, “Summary”, and “Reference”.
- Open 10G Serial Ethernet IP Interface Configuration. Select “10G Serial Ethernet” in the “Protocol” option, and click the “Create” button to open the 10G Serial Ethernet IP configuration interface, as shown in Figure 6-3.
The left side of the configuration interface displays the port diagram of 10G Serial Ethernet IP, and on the right side, it shows parameter configuration options, which includes the PHY Configuration option and AFE option. For the configuration options, you can see Table 5-1. - IP Generation
After completing 10G Serial Ethernet IP configuration, click “OK” button at the bottom right corner of the interface to generate files of the 10G Serial Ethernet IP, and return to the SerDes IP configuration interface, then the SerDes IP configuration interface displays the current generated 10G Serial Ethernet IP and the corresponding Quad, PLL and Lane usage, as shown in Figure 6-4.
Then, click “OK” button at the bottom right corner of the interface to generate SerDes IP files and complete the whole 10G Serial Ethernet IP generation.
Reference Design
See Gowin 10G Serial Ethernet IP reference design for details at the Gowinsemi website. The hardware platform is as shown in Figure 7-1.
Figure 7-1 Hardware Platform and Diagram
This reference design takes
DK_START_GW5AT-LV138FPG676A_V2.0 development board as the hardware platform. As shown in the above figure, the FPGA connects to a 10G SFP+ module via SFP1 on the development board, serving as the channel for 10G Ethernet transmission. Additionally, a differential clock with a frequency of 156.25MHz is input to the SerDes as a reference clock through SMA (AA13 and AB13). In the reference design, XGMII Generator module is used to send XGMII-formatted data to the 10G Serial Ethernet IP, and the XGMII Monitor module is employed to monitor the data received by the 10G Serial Ethernet IP. Users can observe the transmitted and received XGMII data through GAO.
FAQ
- Q: Can I use the Gowin 10G Serial Ethernet IP with other software versions?
- A: The information provided in this manual is based on Gowin Software V1.9.9. It is recommended to adjust according to the software version in use as some details may vary.
- Q: What is the operating frequency of the Gowin 10G Serial Ethernet IP?
- A: The operating frequency is detailed in the user guide under the ‘Overview’ section.
Documents / Resources
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Gowin 10G Serial Ethernet IP [pdf] User Guide GW5AT-60, GW5AT-15, 10G Serial Ethernet IP, 10G Serial, Ethernet IP, IP |