ANALOG DEVICES LTM4640 20A Step Down DC to DC Module Regulator Owner's Manual

Connect your input power source to the LTM4640 and follow the guidelines provided in your specific application to utilize its complete solution features.

Maintenance:

Regularly check the LTM4640 for any signs of damage or wear and ensure proper cleaning to maintain optimal performance.

FAQ

Q: Can the LTM4640 be used for outdoor applications?
- A: The LTM4640 is designed for indoor use only and should not be exposed to outdoor elements.

Q: What is the input power range for the LTM4640?
- A: The recommended input power range for the LTM4640 is between X volts and Y volts. Please refer to the product manual for specific details.

Q: How do I troubleshoot if the LTM4640 is not functioning correctly?
- A: Check all connections, ensure proper input power, and refer to the troubleshooting section in the user manual for step-by-step guidance.

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FEATURES

Complete Solution in <1cm2 (Single-Sided PCB) or 0.5cm2 (Dual-Sided PCB)
Wide Input Voltage Range: 3.1V to 20V 0.6V to 3.3V Output Voltage Up to 20A DC output current ±1.5% Maximum Total DC Output Voltage Error Differential Remote Sensing Amplifier Fast Transient Response External Frequency Synchronization Multiphase Parallel Current Sharing with up
to 4 × LTM4640s Power Good Indicator Overvoltage and Overtemperature Protection 49-Pin, 6.25mm × 6.25mm × 5.07mm, BGA package Pin compatible with LTM4626, LTM4638, and
LTM4657

APPLICATIONS

Telecom, Datacom, Networking, and Industrial Equipment
Medical Diagnostic Equipment Data Storage Rack Units and Cards Test and Debug Systems

TYPICAL APPLICATION

GENERAL DESCRIPTION

The LTM4640 is a complete 20A step-down switching mode power µModule® (micromodule) regulator in a tiny 6.25mm × 6.25mm × 5.07mm BGA package. The package includes the switching controller, the power MOSFETs, an inductor, and the supporting components. Operating over an input voltage range of 3.1V to 20V, the LTM4640 supports an output voltage range of 0.6V to 3.3V, set by a single external resistor. Its high-efficiency design delivers up to 20A continuous output current. Only bulk input and output capacitors are needed.
The LTM4640 supports selectable discontinuous conduction mode (DCM) operation and output voltage tracking for supply rail sequencing. Its high switching frequency and controlled on-time valley current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. Fault protection features include overvoltage and overtemperature protection.
The LTM4640 is available with a RoHS-compliant terminal finish.

001
EFFICIENCY (%)
002

VIN 3.1V TO 20V

2 × 22µF 25V

PINS NOT USED IN THIS CIRCUIT:
CLKOUT, FREQ, PGOOD, PHMODE

VIN LTM4640 VOUT

RUN

VOSNS+

INTVCC

MODE/CLKIN

COMPa

VOSNS

COMPb

TRACK/SS

GND

15k

VOUT 1.0V, 20A
4 × 100µF 6.3V

0.1µF

Figure 1. 20A, 1VOUT DC-to-DC Step-Down µModule Regulator

90
85
80
75 VIN = 5V, 600kHz VIN = 12V, 600kHz
70 0 2 4 6 8 10 12 14 16 18 20 LOAD CURRENT (A)
Figure 2. 1VOUT Efficiency vs. Load Current

Rev. 0 One Analog Way, Wilmington, MA 01887-2356, U.S.A.

DOCUMENT FEEDBACK Tel: 781.329.4700

Data Sheet

SPECIFICATIONS

Table 1. Electrical Characteristics

(TA = 25°C. VIN = 12V per the typical application shown in Figure 1, unless otherwise specified.)

PARAMETER

SYMBOL

CONDITIONS

COMMENTS MIN TYP MAX UNITS

Switching Regulator Section (per Channel)

Input DC voltage

VIN

40°C TJ 125°C

3.1

Output voltage range

VOUT

40°C TJ 0.6 125°C

3.3

Output voltage, total variation with line and load

VOUT(DC)

RFB = 6.65k, MODE = INTVCC, IOUT = 0A to 15A 2 RFB = 6.65k, MODE = INTVCC,
IOUT = 0A to 20A

40°C TJ 1.477 1.50 1.523 125°C
1.477 1.50 1.523

V V

RUN pin ON threshold

VRUN

VRUN rising

1.15 1.25 1.35 V

Input supply bias current

IQ(VIN)

VIN = 12V, VOUT = 1.5V, MODE = INTVCC, IOUT = 0A VIN = 12V, VOUT = 1.5V, MODE = GND, IOUT = 0.1A

100

Shutdown, RUN = 0, VIN = 12V

µA

Input supply current

IS(VIN)

VIN = 12V, VOUT = 1.5V, IOUT = 20A

3.25

Output continuous current range Line regulation accuracy
Load regulation accuracy

IOUT(DC)
VOUT (Line)/VOUT
VOUT (Load)/VOUT

VIN = 12V, VOUT = 1.5V VOUT = 1.5V, VIN = 3.1V to 20V, IOUT = 0A VOUT = 1.5V, IOUT = 0A to 15A VOUT = 1.5V, IOUT = 0A to 20A

40°C TJ 125°C 40°C TJ 125°C

0.01 0.1 %/V

0.1 0.5 % 0.1 0.5 %

Turn-on overshoot

VOUT(START)

IOUT = 0A, COUT = 4 × 220µF ceramic, VIN = 12V, VOUT = 1.5V5

Turn-on time

tSTART

No load, TRACK/SS = 0.01µF, VIN = 12V, VOUT = 1.5V

Peak-to-peak

Load: 0% to 50% to 0% of full

output voltage deviation for dynamic load step

VOUTLS

load, 10A/µs slew rate, COUT = 4 × 220µF ceramic, VIN = 12V, VOUT = 1.5V 5

160

Load: 0% to 50% to 0% of full

Settling time for dynamic load step

tSETTLE

load, 10A/µs slew rate, COUT = 4 × 220µF ceramic, VIN = 12V, VOUT = 1.5V 5

µs

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Data Sheet

LTM4640

(TA = 25°C. VIN = 12V per the typical application shown in Figure 1, unless otherwise specified.)

PARAMETER Output current limit
Voltage at FB pin
Current at FB pin Resistor between VOSNS+ and FB pins Track pin soft start pull-up current VIN Undervoltage lockout Minimum on-time Minimum off-time
PGOOD trip level
PGOOD leakage PGOOD voltage low Internal VCC voltage Oscillator frequency

SYMBOL IOUTPK VFB IFB RFBHI ITRACK/SS VIN(UVLO) tON(MIN) tOFF(MIN)
VPGOOD
IPGOOD VPGL VINTVCC fOSC

CONDITIONS VIN = 12V, VOUT = 1.5V
IOUT = 0A, VOUT = 1.5V
3

COMMENTS MIN TYP MAX UNITS

40°C TJ 0.594 0.60 0.606

125°C

±30 nA

TRACK/SS = 0V
VIN falling VIN hysteresis
3
3
VFB with respect to set output VFB ramping negative
VFB with respect to set output VFB ramping positive
VPGOOD = INTVCC, VFB = 0.6V
IPGOOD = 1mA
VIN = 4V to 20V

6 10 µA

2.45 2.6 2.75 V

350

12 8 5

8 12

µA

0.02 0.1

3.2 3.3 3.4

600

kHz

The LTM4640, including the E-grade and I-grade parts (see Table 14), is tested under pulsed load conditions such as that TJ TA. The LTM4640E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the 40°C to 125°C internal operating temperature 1 range are assured by design, characterization, and correlation with statistical process controls. The LTM4640I is guaranteed to meet specifications over the full 40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated package thermal resistance, and
other environmental factors.

2 See Thermal Considerations and Output Current Derating for different VIN, VOUT, and TA conditions. 3 100% tested at wafer level.

The LTM4640, includes overtemperature protection that is intended to protect the device during momentary
4 overload conditions. The junction temperature exceeds 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair the device’s reliability.

5 Guaranteed by design. Validated from bench measurements.

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Data Sheet

LTM4640

ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise specified.
Table 2. Absolute Maximum Ratings

PARAMETER

RATING

VIN VOUT INTVCC RUN PGOOD, FREQ, COMPa, COMPb, PHMODE, CLKOUT, FB MODE/CLKIN, TRACK/SS VOSNS+ VOSNS Internal operating temperature range 1, 2 Storage temperature range Peak solder reflow body temperature

0.3V to 22V 0.3V to 3.6V 0.3V to 3.6V 0.3V to 20V
0.3V to 3.6V
0.3V to INTVCC 0.3V to 3.6V 0.3V to 0.3V
40°C to 125°C
55°C to 125°C
250°C

The LTM4640, includes overtemperature protection that is intended to protect the device during momentary
2 overload conditions. The junction temperature exceeds 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair the
device’s reliability.

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

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Data Sheet

LTM4640

Thermal Resistance
Thermal performance is directly linked to Printed Circuit Board (PCB) design and operating environment. Close attention to PCB thermal design is required.

Electrostatic Discharge (ESD)
The following ESD information is provided for handling of ESD-sensitive devices in an ESD-protected area only. Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Field-induced charged device model (FICDM) and charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.

ESD Ratings
Table 3. LTM4640 ESD Ratings
ESD MODEL HBM CDM

WITHSTAND THRESHOLD (V) ±2500 ±1250

CLASS 3A C3

ESD Caution

ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

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Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SW TSENSE
7 TSENSE+
6 PGOOD
VOUT 5

TOP VIEW

GND PHMODE

RUN 4
INTVCC 3
VOSNS 2
VOSNS+ 1
FB COMPa

ABCDE F G
BGA PACKAGE 49-PIN (6.25mm × 6.25mm × 5.07mm)

VIN
VOUT MODE/CLKIN TRACK/SS
CLKOUT
COMPb FREQ

003

TJMAX = 125°C, JCtop = 10.1°C/W, JCbottom = 3.9°C/W, JA = 16°C/W

VALUES ARE DETERMINED BY SIMULATION PER JESD51 CONDITIONS, WEIGHT 660mg.
JA VALUE IS OBTAINED WITH DEMO BOARD. SEE THE APPLICATIONS INFORMATION SECTION FOR LAB MEASUREMENT
AND DERATING INFORMATION.
Figure 3. Pinout Configuration

LTM4640

Pin Descriptions
Table 4. Pin Descriptions

PIN CFG 1

NAME

A1A5, F3, G1G3

VOUT

A6 A7 B1 B2, B6, C3 C7, D5D7, E5E7, F5 F7, G6G7

TSENSE+ TSENSE
VOSNS+
GND

DESCRIPTION
Power Output Pins of the Switching Mode Regulator. Apply output load between these pins and GND. Recommend placing output decoupling capacitance directly between these pins and the GND. See the Applications Information section for paralleling outputs. Temperature Monitor Pin. An internal diode-connected NPN transistor is placed between TSENSE+ and TSENSE pins. See the Applications Information section for details. Low-Side of the Internal Temperature Monitor. Positive Input to the Differential Remote Sense Amplifier. Internally, this pin is connected to the FB pin with a 10k ±0.5% precision resistor. See the Applications Information section for details.
Power Ground Pins for Both Input and Output Returns. Use large PCB copper areas to connect the GND pins together.

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Data Sheet

LTM4640

PIN CFG 1 B3 B4 B5 B7
C1
C2
D1
D2
D3D4, E3 E4, F4, G4
E1 E2

NAME INTVCC RUN PGOOD
SW FB VOSNS COMPa
MODE/CLKIN
VIN FREQ TRACK/SS

DESCRIPTION
Internal 3.3V Regulator Output of the Switching Mode Regulator Channel. The internal power drivers and control circuits are powered by this voltage. The LTM4640 has an internal 2.2µF decoupling capacitor. No external decoupling capacitor is required. Run Control Input Pin. Enable regulator operation by connecting the RUN pin above 1.35V. Connecting it below 1.1V shuts down the specific regulator channel. Output Power Good Pin with Open-Drain Logic. The PGOOD pin is pulled to ground when the voltage on the FB pin is out of ±8% of the internal 0.6V reference. Switching node of each channel that is used for testing purposes. Also, an R-C snubber network is applied to reduce or eliminate switch node ringing. Otherwise, leave it floating. See the Applications Information section for details. The Negative Input of the Error Amplifier for the Switching Mode Regulator. This pin is internally connected to VOSNS+ with a 10k precision resistor. The output voltage is programmed with an additional resistor between FB and VOSNS pins. In a PolyPhase® operation, connect the FB pins together to allow for a parallel operation. See the Applications Information section for details. Negative Input to the Differential Remote Sense Amplifier. Connect an external resistor between FB and VOSNS pins to set the output voltage of the specific channel. See the Applications Information section for details. Current control threshold and error amplifier compensation point of the switching mode regulator channel. The internal current comparator threshold is linearly proportional to this voltage. Connect the COMPa pins from different channels together for a parallel operation. The device is internally compensated. Connect to the COMPb pin to use the internal compensation. Or connect to a Type-II C-R-C network to use customized compensation. Discontinuous Mode Select Pin and External Synchronization Input to Phase Detector. Connect MODE/CLKIN to GND for discontinuous-conduction mode (DCM) operation. Floating MODE/CLKIN or connecting it to a voltage above 1V selects forced continuous mode (FCM). Furthermore, connecting MODE/CLKIN to an external clock synchronizes the system clock to the external clock and puts the part in FCM. See the Applications Information section for details. Power input pins connect to the drain of the internal top MOSFET, and the signal VIN to the internal 3.3V regulator for the control circuitry for each switching mode regulator channel. Apply input voltages between these pins and GND pins. Recommend placing input decoupling capacitance directly between each of the VIN pins and the GND pins. Switching Frequency Program Pin. The frequency is set internally to 600kHz. An external resistor is placed from this pin to GND to increase frequency, or from this pin to INTVCC to reduce frequency. See the Applications Information section for frequency adjustment. Output Tracking and Soft Start Pin of the Switching Mode Regulator. The TRACK/SS pin allows the user to control the rise time of the output voltage. Putting a voltage below 0.6V on this pin bypasses the internal reference input to the error amplifier, instead it servos the FB pin to the TRACK voltage. Above 0.6V, the tracking function

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Data Sheet

LTM4640

PIN CFG 1
F1 F2
G5

NAME
COMPb CLKOUT PHMODE

DESCRIPTION
stops, and the internal reference resumes control of the error amplifier. There’s an internal 6µA pull-up current from INTVCC on this pin, putting a capacitor here provides a soft start function. See the Applications Information section for details. Internal Loop Compensation Network. Connect to COMPa pin to use the internal compensation in the majority of applications. Output Clock Signal for PolyPhase Operation. The phase of CLKOUT with respect to CLKIN is determined by the state of the respective PHMODE pin. CLKOUT’s peak-topeak amplitude is INTVCC to GND. See the Applications Information section for details. Control Input to the Phase Selector of the Switching Mode Regulator. It determines the phase relationship between the internal oscillator and CLKOUT. Connect it to INTVCC for a 2-phase operation, connect it to GND for a 3-phase operation, and connect it to INTVCC/2 for a 4-phase operation. See the Applications Information section for details.

Table 5. LTM4640 Component BGA Pinout

PIN ID A1G4
A1 B1 C1 D1 E1 F1 G1 A5G7 A5 B5 C5 D5 E5 F5 G5

FUNCTION
VOUT VOSNS+
FB COMPa FREQ COMPb
VOUT
VOUT PGOOD
GND GND GND GND PHMODE

PIN ID
A2 B2 C2 D2 E2 F2 G2
A6 B6 C6 D6 E6 F6 G6

FUNCTION
VOUT GND VOSNS MODE/CLKIN TRACK/SS CLKOUT VOUT
TSENSE+ GND GND GND GND GND GND

PIN ID
A3 B3 C3 D3 E3 F3 G3
A7 B7 C7 D7 E7 F7 G7

FUNCTION
VOUT INTVCC GND
VIN VIN VOUT VOUT
TSENSE SW GND GND GND GND GND

PIN ID
A4 B4 C4 D4 E4 F4 G4

FUNCTION
VOUT RUN GND VIN VIN VIN VIN

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Data Sheet

LTM4640

005

TYPICAL PERFORMANCE CHARACTERISTICS

EFFICIENCY (%)

100

1.0VOUT, 600kHz

1.2VOUT, 600kHz

1.5VOUT, 600kHz

1.8VOUT, 600kHz

2.5VOUT, 600kHz

0 2 4 6 8 10 12 14 16 18 20

LOAD CURRENT (A)

Figure 4. Efficiency vs. Load Current from 3.3VIN

100

1.0VOUT, 600kHz

1.2VOUT, 700kHz

1.5VOUT, 800kHz

1.8VOUT, 900kHz

2.5VOUT, 1000kHz

3.3VOUT, 1000kHz

70 0 2 4 6 8 10 12 14 16 18 20

LOAD CURRENT (A)

Figure 6. Efficiency vs. Load Current from 12VIN

004
EFFICIENCY (%)

100

1.0VOUT, 600kHz

1.2VOUT, 700kHz

1.5VOUT, 800kHz

1.8VOUT, 800kHz

2.5VOUT, 800kHz

3.3VOUT, 800kHz

70 0 2 4 6 8 10 12 14 16 18 20

LOAD CURRENT (A)

Figure 5. Efficiency vs. Load Current from 5VIN

VOUT AC-COUPLED
100mV/DIV
LOAD STEP CURRENT 5A/DIV
100µs/DIV VIN = 12V, VOUT = 1V, fSW = 600kHz COUT = 4 × 220µF + 2 × 2.2µF + 1µF CERAMIC CAPACITOR INTERNAL COMPENSATION, COMPa CONNECT TO COMPb, CFF = 100pF, 10A ~ 15A (25%) LOAD STEP 10A/s SLEW RATE
Figure 7. 1VOUT Transient Response

EFFICIENCY (%)

007

008 006

VOUT AC-COUPLED
100mV/DIV
LOAD STEP CURRENT 5A/DIV 100µs/DIV VIN = 12V, VOUT = 1.5V, fSW = 800kHz COUT = 4 × 220µF + 2 × 2.2µF + 1µF CERAMIC CAPACITOR INTERNAL COMPENSATION, COMPa CONNECT TO COMPb, CFF = 100pF, 10A ~ 15A (25%) LOAD STEP 10A/s SLEW RATE
Figure 8. 1.5VOUT Transient Response
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VOUT AC-COUPLED
100mV/DIV
LOAD STEP CURRENT 5A/DIV 100µs/DIV VIN = 12V, VOUT = 2.5V, fSW = 1MHz COUT = 4 × 220µF + 2 × 2.2µF + 1µF CERAMIC CAPACITOR INTERNAL COMPENSATION, COMPa CONNECT TO COMPb, CFF = 100pF, 10A ~ 15A (25%) LOAD STEP 10A/s SLEW RATE
Figure 9. 2.5VOUT Transient Response
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009

Data Sheet

LTM4640

VOUT AC-COUPLED
100mV/DIV
LOAD STEP CURRENT 5A/DIV
100µs/DIV VIN = 12V, VOUT = 3.3V, fSW = 1MHz COUT = 4 × 220µF + 2 × 2.2µF + 1µF CERAMIC CAPACITOR INTERNAL COMPENSATION, COMPa CONNECT TO COMPb, CFF = 100pF, 10A ~ 15A (25%) LOAD STEP 10A/s SLEW RATE
Figure 10. 3.3VOUT Transient Response

010

RUN 10V/DIV
PGOOD 5V/DIV
VOUT 1V/DIV
INPUT CURRENT 500mA/DIV
5ms/DIV VIN = 12V, VOUT = 1.5V, fSW = 800kHz COUT = 4 × 220µF + 2 × 2.2µF + 1µF CERAMIC CAPACITOR INTERNAL COMPENSATION, COMPa CONNECT TO COMPb, CFF = 100pF, CSS = 0.1µF
Figure 11. Startup Waveform without Load Current

011

RUN 10V/DIV PGOOD
5V/DIV
VOUT 1V/DIV
INPUT CURRENT
2A/DIV
5ms/DIV VIN = 12V, VOUT = 1.5V, fSW = 800kHz COUT = 4 × 220µF + 2 × 2.2µF + 1µF CERAMIC CAPACITOR INTERNAL COMPENSATION, COMPa CONNECT TO COMPb, CFF = 100pF, CSS = 0.1µF
Figure 12. Startup Waveform with 20A Load Current

012

INPUT CURRENT
1A/DIV
VOUT 1V/DIV
200µs/DIV VIN = 12V, VOUT = 1.5V, fSW = 800kHz COUT = 4 × 220µF + 2 × 2.2µF + 1µF CERAMIC CAPACITOR INTERNAL COMPENSATION, COMPa CONNECT TO COMPb, CFF = 100pF
Figure 13. Output Short-Circuit Waveform without Load Current Applied

013

INPUT CURRENT
1A/DIV
VOUT 1V/DIV
200µs/DIV VIN = 12V, VOUT = 1.5V, fSW = 800kHz COUT = 4 × 220µF + 2 × 2.2µF + 1µF CERAMIC CAPACITOR INTERNAL COMPENSATION, COMPa CONNECT TO COMPb, CFF = 100pF
Figure 14. Output Short-Circuit Waveform with 20A Load Current Applied

014

RUN 10V/DIV PGOOD
5V/DIV
VOUT 2V/DIV
INPUT CURRENT 500mA/DIV
5ms/DIV VIN = 12V, VOUT = 3.3V, fSW = 800kHz COUT = 4 × 220µF + 2 × 2.2µF + 1µF CERAMIC CAPACITOR INTERNAL COMPENSATION, COMPa CONNECT TO COMPb, CFF = 100pF, CSS = 0.1µF
Figure 15. Startup into Prebiased Output

015

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Data Sheet

LTM4640

VOUT AC-COUPLED
10mV/DIV

016

20MHz BANDWIDTH LIMIT
500ns/DIV VIN = 12V, VOUT = 1.5V, fSW = 800kHz, NO LOAD, CCM COUT = 4 × 220µF + 2 × 2.2µF + 1µF CERAMIC CAPACITOR INTERNAL COMPENSATION, COMPa CONNECT TO COMPb, CFF = 100pF
Figure 16. Steady-State Output Voltage Ripple

THEORY OF OPERATION
LTM4640 Overview
The LTM4640 is a standalone non-isolated switch mode DC-to-DC power supply. The LTM4640 can deliver up to 20A DC output current with few external input and output capacitors. This µModule provides precisely regulated output voltage adjustable between 0.6V to 3.3V through one external resistor over an input voltage range of 3.1V to 20V. A typical application schematic is shown in Figure 37.
The LTM4640 contains an integrated controlled on-time valley current mode controller, the power MOSFETs, an inductor, and other supporting discrete components. The default switching frequency is 600kHz. For noisesensitive applications, the switching frequency can be adjusted by external resistors, and the Module regulator can be externally synchronized to a clock within ±30% of the set frequency. See the Applications Information section for details.
With current mode control and internal feedback loop compensation, the LTM4640 has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all the ceramic output capacitors.
Current mode control provides cycle-by-cycle fast current limiting. Internal output overvoltage and undervoltage comparators pull the open-drain PGOOD output low if the output feedback voltage exits a ±8% window around the regulation point. Continuous operation is forced during overvoltage and undervoltage conditions, except during startup when the TRACK pin is ramping up to 0.6V.
Furthermore, to protect the internal power MOSFET devices against transient voltage spikes, the LTM4640 constantly monitors the VIN pin for an overvoltage condition. When VIN rises above 24.5V, the regulator suspends operation by shutting off both power MOSFETs. Once VIN drops below 21.5V, the regulator immediately resumes normal operation. The regulator does not execute its soft start function when exiting an overvoltage condition.
A multiphase operation can easily be employed with the synchronization and phase mode controls. Up to four phases can be cascaded to run simultaneously with respect to each other by programming the PHMODE pin to

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Data Sheet

LTM4640

different levels. The LTM4640 has MODE/CLKIN and CLKOUT pins for PolyPhase operation of multiple devices or frequency synchronization.

Pulling the RUN pin to GND forces the controller into its shutdown state, turning off both power MOSFETs and most of the internal control circuitry. At light load currents, discontinuous-conduction mode (DCM) operation can be enabled to achieve higher efficiency compared to continuous-conduction mode (CCM) by pulling the MODE/CLKIN pin to GND. The TRACK/SS pin is used for power supply tracking and soft start programming. See the Applications Information section for details.

Simplified Block Diagram
LTM4640

INTVCC MODE/CLKIN

2.2µF

PGOOD
VIN 0.1µF

10k

INTVCC

CIN 22µF
25V

VIN 3.1V TO 20V

CLKOUT PHMODE

POWER CONTROL

0.18µH

VOUT
1µF GND

COUT 3 × 100µF
6.3V

VOUT 1.5V,
20A

0.1µF VIN

TRACK/SS
RUN COMPa COMPb
INTERNAL COMP

DIFF AMP

INTERNAL FILTER
274k FREQ

GND

VOSNS
FB 10k ±0.5% VOSNS+
TSENSE+

RFB 15k

TSENSE

017

Figure 17. LTM4640 Simplified Block Diagram

Decoupling Requirements
Table 6. Decoupling Requirements

SYMBOL PARAMETER

CONDITIONS MIN

TYP

MAX UNITS

CIN

External input capacitor requirement

IOUT = 20A

µF

(VIN = 3.1V to 20V, VOUT = 1.5V)

COUT

External output capacitor requirement

IOUT = 20A

330 1

470 1

µF

(VIN = 3.1V to 20V, VOUT = 1.5V)

1Additional capacitance may be required under extreme temperature and/or capacitor bias voltage conditions

because of the variation of the actual capacitance over bias voltage and temperature.

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Data Sheet

LTM4640

APPLICATIONS INFORMATION

The typical LTM4640 application circuit is shown in Figure 37. The external component selection is primarily determined by the input voltage, output voltage, load transient, and maximum load current. See Table 12 for specific external capacitor requirements for a particular application.

VIN to VOUT Step-Down Ratios
There are restrictions on the maximum VIN and VOUT step-down ratios that can be achieved for a given input voltage because of the minimum off-time and minimum on-time limits of the regulator. The minimum off-time limit imposes a maximum duty cycle which is calculated with Equation 1.

= 1 – (() × )

(1)

where tOFF(MIN) is the minimum off-time, typically 50ns for LTM4640, and fSW (Hz) is the switching frequency. Conversely, the minimum on-time limit imposes a minimum duty cycle of the converter which is calculated with Equation 2.

= () ×

(2)

where tON(MIN) is the minimum on-time, typically 25ns for LTM4640. In the rare cases where the minimum duty cycle is surpassed, the output voltage remains in regulation, but the switching frequency decreases from its programmed value. Note that additional thermal derating may be applied. See the Thermal Considerations and Output Current Derating section.

Output Voltage Programming

The pulse-width modulation (PWM) controller has an internal 0.6V reference voltage. As shown in Figure 17 (Simplified Block Diagram), a 10k internal feedback resistor connects the VOSNS+ and the FB pins. Adding a resistor, RFB, from FB pin to VOSNS pin programs the output voltage given by Equation 3.

0.6 – 0.6

(3)

Table 7 summarizes the RFB values required for some of the typical output voltage applications.

Table 7. RFB Resistor Table vs. Various Output Voltages

VOUT (V)

0.6

1.0

1.2

1.5

1.8

2.5

3.3

RFB (k)

OPEN

6.65

4.99

3.16

2.21

For parallel operation of multiple channels, the same feedback setting resistor is used for the parallel design. This is done by connecting the VOSNS+ to the output, as shown in Figure 18, thus connecting one of the internal 10k resistors to the output. All the VFB pins connect with one programming resistor, as shown in Figure 18. See Figure 39
for an example of a parallel operation.

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Rev. 0 15 of 38

Data Sheet

LTM4640

COMPa LTM4640 VOUT

COMPb

VOSNS+

TRACK/SS

VOSNS

CLKOUT

1.2V, 40A

MODE/CLKIN

COMPa LTM4640 VOUT

COMPb

VOSNS+

TRACK/SS 0.1µF

VOSNS

RFB 10k

018

Figure 18. 2-Phase Parallel Configurations
Input Decoupling Capacitors
The LTM4640 should be connected to a low AC impedance DC source. For the regulator, a 22µF input ceramic capacitor is required for root mean square (RMS) ripple current decoupling. Bulk input capacitance is only needed when the input source impedance is compromised by long inductive leads, traces, or not enough source capacitance. The bulk capacitor is an aluminum electrolytic capacitor or polymer capacitor.

Without considering the inductor ripple current, the RMS current of the input capacitor is estimated with Equation 4.

()

() %

( 2

–

)

(4)

where % is the estimated efficiency of the power Module regulator.
Output Decoupling Capacitors
With an optimized high frequency, high bandwidth design, only a single low equivalent series resistance (ESR) output ceramic capacitor is required for the LTM4640 to achieve low output ripple voltage and very good transient response. In extreme cold or hot temperatures, or high output voltage cases, an additional ceramic capacitor or a tantalum-polymer capacitor is required because of the variation of the actual capacitance over bias voltage and temperature. Table 12 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 5A load-step transient. Additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. The Analog Devices LTpowerCAD® design tool is available to download online for output ripple, stability, and transient response analysis for further optimization.
Discontinuous-Conduction Mode
In applications where low output ripple and high efficiency at intermediate current are desired, discontinuousconduction mode (DCM) should be used by connecting the MODE/CLKIN pin to GND. At light loads, the internal current comparator may remain tripped for several cycles and force the top MOSFET to stay off for several cycles, thus skipping cycles. The inductor current does not reverse in this mode.

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Rev. 0 16 of 38

Data Sheet

LTM4640

Forced Continuous Mode
In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, FCM operation should be used. FCM operation can be enabled by connecting the MODE/CLKIN pin to INTVCC. In this mode, the inductor current can reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During startup, FCM is disabled, and the inductor current is prevented from reversing until the LTM4640’s output voltage is in regulation.

Operating Frequency
The operating frequency of the LTM4640 is optimized to achieve the compact package size and the minimum output ripple voltage while keeping high efficiency. The default operating frequency is 600kHz. In most applications, no additional frequency adjustment is required.

If an operating frequency other than 600kHz is required by the application, the operating frequency is increased by adding a resistor, RFSET, between the FREQ pin and GND, as shown in Figure 38, or is decreased by adding a resistor between the FREQ pin and INTVCC. The RFSET resistance value is calculated with Equation 5.

1.67 × 1011 × – 600
2.72 × 1011 × { 600 –

( (

> <

600) 600)

(5)

The programmable operating frequency range is from 400kHz to 3MHz.

Frequency Synchronization and Clock In
The LTM4640 has a phase-locked loop comprised of an internal voltage-controlled oscillator and a phase detector. This allows the internal top MOSFET turn-on to be locked to the rising edge of the external clock. The external clock frequency range must be within ±30% around the operating frequency set by the RFSET resistor. A pulse detection circuit detects a clock on the CLKIN pin to turn on the phase-locked loop. The pulse width of the clock must be at least 100ns. The clock’s high level must be above 1V and the clock’s low level below 0.3V. During the startup of the regulator, the phase-locked loop function is disabled.

Multiphase Operation
For output loads that demand more than 20A of current, multiple LTM4640s are paralleled to run out-of-phase to provide more output current without increasing input and output voltage ripples.

The CLKOUT signal is connected to the MODE/CLKIN pin of the following LTM4640 stage to line up both the frequency and the phase of the entire system. Connecting the PHMODE pin to INTVCC, GND, or FLOAT generates a phase difference (between CLKIN and CLKOUT) of 180°, 120°, or 90°, respectively, which corresponds to 2-phase, 3phase, or 4-phase operation. Figure 39 shows a 2-phase design. For a 3-phase or a 4-phase operation to achieve the best performance, it is recommended to use an external clock integrated circuit (IC) to provide the desired phase difference for each LTM4640. An optional low-pass filter is added to each external clock signal before it is fed to the LTM4640. Figure 19 shows a 4-phase design in such a way. Interleaving among more than four phases is not recommended.

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Rev. 0 17 of 38

Data Sheet

LTM4640

Table 8. PHMODE Pin Status and Corresponding Phase Relationship (Relative to CLKIN)

PHMODE

INTVCC

GND

CLKOUT

180°

120°

FLOAT 90°

1k
68pF 0° MODE/CLKIN
LTM4640
VOUT

LTC6902

CLK1

CLK4

CLK2

CLK3

68pF 90° MODE/CLKIN
LTM4640
VOUT

68pF 180° MODE/CLKIN
LTM4640
VOUT

1k
68pF 270° MODE/CLKIN
LTM4640
VOUT

RMS INPUT RIPPLE CURRENT DC LOAD CURRENT
020 019

PHASE 1

PHASE 2

PHASE 3

PHASE 4

Figure 19. 4-Phase Operation with an External Clock IC and Low-Pass Filters
A multiphase power supply significantly reduces the amount of ripple current in both the input and the output capacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (if the input voltage exceeds the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used when all the outputs are connected to achieve a single high output current design.

The LTM4640 is an inherently current mode-controlled device, which ensures good current sharing in parallel operation. This balances the thermals on the design. Connect the RUN, TRACK/SS, FB, and COMPa pins of each paralleling channel together. Figure 39 shows an example of a parallel operation and the pins connection.

Input RMS Ripple Current Cancellation
Analog Devices Application Note 77 provides a detailed explanation of a multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved phases. Figure 20 shows this graph.

0.60

1-PHASE

2-PHASE

0.55

3-PHASE

4-PHASE

0.50

6-PHASE

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (VOUT/VIN)
Figure 20. The RMS Input Ripple Current to DC Load Current Ratio as a Function of the Duty Cycle

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Rev. 0 18 of 38

Data Sheet

LTM4640

Soft Start and Output Voltage Tracking
The TRACK/SS pin provides a means to either soft start the regulator or track it to a different power supply. A capacitor on the TRACK/SS pin programs the ramp rate of the output voltage. An internal 6µA current source charges up the external soft start capacitor towards INTVCC voltage. When the TRACK/SS voltage is below 0.6V, it takes over the internal 0.6V reference voltage to control the output voltage. The total soft start time is calculated with Equation 6.

0.6

6µ

(6)

where CSS is the capacitance on the TRACK/SS pin. Current foldback and FCM are disabled during the soft start process.

Output voltage tracking can also be externally programmed using the TRACK/SS pin. The output is tracked up and
down with another regulator. Figure 21 and Figure 22 show examples of a waveform and the schematic of ratio metric tracking where the subordinate regulator’s output slew rate is proportional to the main device.

MAIN OUTPUT SUBORDINATE OUTPUT

OUTPUT VOLTAGE
021 022

VIN 3.1V TO 20V

TIME
Figure 21. Output Ratio Metric Tracking Waveform

2 × 22µF 25V

VIN LTM4640 VOUT

RUN

VOSNS+

INTVCC

MODE/CLKIN

COMPa

VOSNS

COMPb

TRACK/SS

GND

RFB(MAIN) 6.65k

4 × 100µF 6.3V

VOUT(MAIN) 1.5V, 20A

RTR(TOP) 10k

RTR(BOT) 6.65k

2 × 22µF 25V

VIN LTM4640 VOUT

RUN

VOSNS+

INTVCC

MODE/CLKIN

COMPa

VOSNS

COMPb

TRACK/SS

GND

RFB(SUB) 10k

4 × 100µF 6.3V

VOUT(SUB) 1.2V, 20A

Figure 22. Example Schematic of Ratio Metric Output Voltage Tracking

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Rev. 0 19 of 38

Data Sheet

LTM4640

Since the subordinate regulator’s TRACK/SS is connected to the main device output through an R R TR(TOP)/ TR(BOT) resistor divider, and its voltage is used to regulate the subordinate device output voltage when TRACK/SS voltage is below 0.6V, the subordinate device output voltage and the main device output voltage should satisfy Equation 7 during startup.

()

() () + 10

()

() () + ()

(7)

The RFB(SUB) is the feedback resistor, and the RTR(TOP)/RTR(BOT) is the resistor divider on the TRACK/SS pin of the subordinate regulator, as shown in Figure 22.

Following Equation 7, the ratio of the main device output slew rate (MR) to the subordinate device output slew rate (SR) is given by Equation 8.

()(+1) 0
()

(8)

() + ()

For example, VOUT(MAIN) = 1.5V, MR = 1.5V/1ms and VOUT(SUB) = 1.2V, SR = 1.2V/1ms. From Equation 8, we could solve that RTR(TOP) = 10k and RTR(BOT) = 6.65k are a good combination for the ratio metric tracking.
The TRACK/SS pin has the 6µA current source on when a resistive divider implements tracking on the subordinate regulator. This imposes an offset on the TRACK/SS pin input. Smaller value resistors with the same ratios as the resistor values calculated from Equation 8 are recommended to mitigate such impact. For example, where the 10k is used, then a 5k is used to reduce the TRACK/SS pin offset to a negligible value.
Coincident output tracking is recognized as a special ratio metric output tracking in which the main device output slew rate (MR) is the same as the subordinate device output slew rate (SR), waveform as shown in Figure 23.

MAIN OUTPUT SUBORDINATE OUTPUT

OUTPUT VOLTAGE
023

TIME
Figure 23. Output Coincident Tracking Waveform

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Rev. 0 20 of 38

Data Sheet

LTM4640

From Equation 8, we could easily find that, in coincident tracking, the subordinate regulator’s TRACK/SS pin resistor divider is always the same as its feedback divider (Equation 9).

() () + 10

() () + ()

(9)

For example, RTR(TOP) = 10k and RTR(BOT) = 10k is a good combination for coincident tracking for a VOUT(MAIN) = 1.5V and VOUT(SUB) = 1.2V application.
Power Good
The PGOOD pin is an open-drain pin that can be used to monitor valid output voltage regulation. This pin is pulled low when the output voltage exceeds a ±8% window around the regulation point. To prevent unwanted PGOOD glitches during transients or dynamic VOUT changes, the LTM4640’s PGOOD falling edge includes a blanking delay of approximately 25 switching cycles.

RUN Enable
Pulling the RUN pin to ground forces the LTM4640 into the shutdown state, turning off both power MOSFETs and most of its internal control circuitry. Bringing the RUN pin above 0.6V turns on the internal reference only, while keeping the power MOSFETs off. Increasing the RUN pin voltage above 1.35V turns on the entire device.

Prebiased Output Startup
There may be situations that require the power supply to start up with some charge on the output capacitors. The LTM4640 can safely power up into a prebiased output without discharging it.

The LTM4640 accomplishes this by forcing discontinuous-conduction mode (DCM) operation until the TRACK/SS pin voltage reaches 0.6V reference voltage. This prevents the bottom FET from turning on during the prebiased output startup, which would discharge the output.

SW Pins and Optional Snubber Circuit
The SW pin is generally for testing purposes. The SW pin can also be used to dampen out switch node ringing caused by the LC parasitic in the switched current path using a series R-C snubber circuit. The resistor dampens the resonance, and the capacitor is chosen to only affect the high-frequency ringing across the resistor. The snubber circuit is optional, as the LTM4640 can operate well with proper PCB layout. If needed, below are suggestions regarding snubber circuit design.

If the stray inductance or capacitance can be measured or approximated, then it is possible to use an analytical technique to select the snubber values. The inductance is usually easier to predict. It combines the power path board inductance in combination with the MOSFET interconnect bond wire inductance.

First, the SW pin is monitored with a wide bandwidth scope with a high frequency scope probe. The ring frequency is measured for its value. The impedance ZL is calculated with Equation 10.

= 2 × f × L

(10)

where f is the resonant frequency of the ring, and L is the total parasitic inductance in the switch path. If a resistor is selected that is equal to ZL, then the ringing should be dampened. The snubber capacitor value is chosen so that its impedance is equal to the resistor at the ring frequency. This is calculated with Equation 11.

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Rev. 0 21 of 38

Data Sheet

LTM4640

1 ×f

(11)

These values are a good place to start. Modifications to these components should be made to attenuate the ringing with the least amount of power loss.

Stability Compensation
The LTM4640 has already been internally compensated for all output voltages and capacitor combinations, including all ceramic capacitor applications when COMPb is connected to COMPa. Note that a 22pF to 100pF feedforward capacitor (CFF) is required for connecting from VOUT to VFB pins for all ceramic output capacitor applications to achieve high bandwidth control loop compensation with enough phase margin. Table 12 provides most of the application requirements using optimized internal compensation.
For specific optimized requirements, disconnect COMPb from COMPa and apply a Type II compensation network from COMPa to GND to achieve external compensation. Choose the components of the Type-II network dependent on the desired output response for line and load variations as well as loop stability parameters–phase margin and gain margin of the feedback loop. In general, selecting a low capacitance and a high resistance for the Type-II network at COMPa pin leads to a fast transient response but may adversely affect the loop stability parameters.
The LTpowerCAD design tool is available to download online to perform specific control loop optimization and to analyze the control stability and load transient performance.

Differential Remote Sense Amplifier
An accurate differential remote sense amplifier is built into the LTM4640 to sense output voltages accurately at the remote load points. This is especially true for high current loads. It is important that the VOSNS+ and VOSNS pins are connected properly at the remote output sense point, and that the feedback resistor, RFB, is connected between the VFB and VOSNS pins (see Figure 37).
In a multiphase single output application, only one set of differential sensing amplifiers and one set of feedback resistors is required, while connecting RUN, TRACK/SS, VOUT, VFB, and COMPa of different channels together. See Figure 39 for an example of a paralleling application.

Input Overvoltage Protection
To protect the internal power MOSFET devices against transient voltage spikes, the LTM4640 constantly monitors the VIN pin for an overvoltage condition. When the VIN rises above 24.5V, the regulator suspends operation by shutting off both power MOSFETs on the corresponding channel. Once VIN drops below 21.5V, the regulator immediately resumes normal operation. The regulator executes its soft start function when exiting an overvoltage condition.

Output Current Limit
Under overload or short-circuit conditions, the output current is no higher than the specified output current limit. The LTM4640 may still be switching, but the output voltage regulation is not guaranteed, which is dependent on the load resistance under such conditions. Continuous operation under such conditions is not recommended, as this may cause the maximum operating junction temperature to be exceeded, which may impair the device’s reliability.

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Rev. 0 22 of 38

Data Sheet

LTM4640

Temperature Monitoring
Measuring the absolute temperature of a diode is possible due to the relationship between current, voltage, and temperature described by the classic diode Equation 12.

= × ×

(12)

where ID is the diode current, VD is the diode voltage, is the ideality factor (typically close to 1), and IS (saturation current) is a process-dependent parameter. The VT is broken out with Equation 13.

× q

(13)

where T is the diode junction temperature in Kelvin, q is the electron charge, and K is Boltzmann’s constant. The VT is approximately 26mV at room temperature (298K) and scales linearly with Kelvin temperature. It is this linear temperature relationship that makes diodes suitable temperature sensors. The IS term in Equation 13 is the extrapolated current through a diode junction when the diode has zero volts across the terminals. The IS term varies from process to process, varies with temperature, and must always be less than ID. Combining all the constants into one term (see Equation 14).

(14)

where KD = 8.62 × 10-5 V/K, assuming the ideality factor is 1 and knowing ln (ID/IS) is always positive because ID is always greater than IS, leaves us with the results given in Equation 15.

()

(15)

It should be noted that as the temperature increases, the IS term increases more quickly, and thus, the ln (ID/IS) absolute value reduces faster, yielding a negative coefficient of diode voltage vs. temperature, which is an approximate 2mV/°C temperature relationship as shown in Figure 24.
0.8

0.7

DIODE VOLTAGE (V)
024

0.6

0.5

0.4

0.3

TEMPERATURE (°C)

100

125

Figure 24. Diode Voltage VD vs. Temperature T(°C)

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Rev. 0 23 of 38

Data Sheet

LTM4640

To obtain a linear voltage proportional to the temperature, we cancel the IS variable in the natural logarithm term to remove the IS dependency from Equation 15. This is accomplished by measuring the diode voltage at two currents: I1 and I2, where I1 = 10 × I2, and subtracting is given in Equation 16.

()

–

()

(16)

Combining like terms, and then simplifying the natural log terms yields Equation 17.

= () × × (10)

(17)

and redefining the constant is given in Equation 18.

yields Equation 19.

(10)

198

(18)

= × ()

(19)

Equation 20 solves for temperature.

()

(20)

(°) = () – 273.15

Where 300.15K = 27°C is an example.
If we take the difference in voltage across the diode measured at two currents with a ratio of 10, the resulting voltage is 198V per Kelvin of the junction with a zero intercept at 0 Kelvin.
The internal diode-connected NPN transistor between TSENSE+ and TSENSE pins is used to monitor the internal temperature of the LTM4640.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configurations and Function Descriptions section are consistent with those parameters defined by JESD5112 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board. The motivation for providing these thermal coefficients is found in JESD5112 (Guidelines for Reporting and Using Electronic Package Thermal Information).
Many designers may use laboratory equipment and a test vehicle, such as an evaluation (demo) board, to anticipate the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to complement any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configurations and Function Descriptions section are, in and of themselves, not relevant to providing guidance on thermal performance; instead, the derating curves provided in Figure 29 through Figure 34 can be used in a manner that yields insight and guidance about the user’s application and can be adapted to correlate thermal performance to the user’s application.

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Rev. 0 24 of 38

Data Sheet

LTM4640

The Pin Configurations and Function Descriptions section gives three thermal coefficients explicitly defined in JESD5112; these coefficients are quoted or paraphrased as follows.
1. JA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in one cubic foot sealed enclosure. This environment is sometimes referred to as “still air”, although natural convection causes the air to move. This value is determined with the part mounted to a 95mm × 76mm PCB with four layers.

2. JCbottom, the thermal resistance from the junction to the bottom of the product case, is determined with all the component power dissipation flowing through the bottom of the package. In the typical µModule
regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into
the ambient environment. As a result, this thermal resistance value may be useful for comparing packages, but the test conditions don’t generally match the user’s application.

3. JCtop, the thermal resistance from the junction to the top of the product case, is determined with nearly all the component’s power dissipation flowing through the top of the package. As the electrical connections
of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of JCbottom, this value may be useful for comparing packages, but the test conditions don’t generally match the user’s
application.

A graphical representation of the thermal resistances is given in Figure 25; blue resistances are contained within the Module regulator, whereas green resistances are external to the µModule package.

µModule DEVICE
JCtop JUNCTION-TO-CASE (TOP) RESISTANCE

JA JUNCTION-TO-AMBIENT RESISTANCE

CASE (TOP)-TO-AMBIENT RESISTANCE

JUNCTION

JB JUNCTION-TO-BOARD RESISTANCE

JCbot JUNCTION-TO-CASE (BOTTOM) RESISTANCE

CASE (BOTTOM)-TO-BOARD RESISTANCE

BOARD-TO-AMBIENT RESISTANCE

AMBIENT

025

Figure 25. Graphical Representation of JESD5112 Thermal Coefficients
As a practical matter, it should be clear to the user that no individual or sub-group of the three thermal resistance parameters defined by JESD5112 or provided in the Pin Configurations and Function Descriptions section replicates or conveys normal operating conditions of a Module regulator. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conducts exclusively through the top or exclusively through the bottom of the µModule package–as the standard defines for JCtop and JCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package–granted, in the absence of a heat sink and airflow, most of the heat flow is into the board.
Airflow and Heat Sinking
Within the LTM4640, be aware that there are multiple power devices and components dissipating power with a consequence that the thermal resistances relative to different junctions of components or dies are not exactly linear with respect to the total package power loss. To reconcile this complication without sacrificing modeling

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Rev. 0 25 of 38

Data Sheet

LTM4640

simplicity–but also, not ignoring practical realities–an approach has been taken by using FEA software modeling and laboratory testing in a controlled environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software accurately builds the mechanical geometry of the LTM4640 and the specified PCB with all of the correct material coefficients and accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JSED5112 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDECdefined thermal resistance values; (3) the model and FEA software evaluates the LTM4640 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples within a controlled environment chamber while operating the device at the same power loss as the one which was simulated. An outcome of this process and due diligence yields the set of derating curves shown in Figure 29 through Figure 34. After these laboratory tests have been performed and correlated to the LTM4640, then the JB and BA are summed together to provide a value that should closely equal the JA value because approximately 100% of power loss flows from the junction through the board into ambient with no airflow or top mounted heat sink.
The 1V, 1.5V, and 3.3V power loss curves in Figure 26 through Figure 28 can be used in coordination with the load current derating curves in Figure 29 through Figure 34 for calculating an approximate JA thermal resistance for the LTM4640 with various airflow conditions. The power loss curves are taken at room temperature and are increased with a multiplicative factor according to the ambient temperature. This approximate factor is 1.2 for 120°C, at junction temperature. The maximum load current is achievable while increasing ambient temperature if the junction temperature is less than 120°C, which is a 5°C guard band from a maximum junction temperature of 125°C. When the ambient temperature reaches a point where the junction temperature is 120°C, then the load current is lowered to maintain the junction at 120°C, while increasing ambient temperature up to 120°C. The derating curves are plotted with the output current starting at 20A and the ambient temperature at 30°C. The output voltages are 1V, 1.5V, and 3.3V. These are chosen to include the lower and higher output voltage ranges to correlate the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber and thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at 120°C maximum while lowering output current or power with increasing ambient temperature.
The decreased output current decreases the internal µModule loss as the ambient temperature is increased. The monitored junction temperature of 120°C minus the ambient operating temperature specifies how much µModule temperature rise can be allowed. For example, in Figure 30, the load current is derated to ~10A at ~95°C with no airflow or heat sink, and the power loss for the 12V to 1V at 10A output is about 1.8W. The 1.8W loss is calculated with the ~1.5W room temperature loss from the 12V to 1V power loss curve at 10A, and the 1.2 multiplying factor at 120°C junction temperature. If the 95°C ambient temperature is subtracted from the 120°C junction temperature, then the difference of 25°C divided by 1.8W equals a 13.9°C/W JA thermal resistance. Table 9 specifies a 14°C/W value, which is very close. Table 10 and Table 11 provide equivalent thermal resistances for 1.5V and 3.3V outputs with and without airflow and heat sinking. The derived thermal resistances in Table 9, Table 10, and Table 11 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with the previous ambient temperature multiplicative factors. The printed circuit board is a 1.6mm thick 6-layer board with twoounce copper for all six layers. The PCB dimensions are 90mm × 90mm.

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Rev. 0 26 of 38

Data Sheet

TA = 25°C, unless otherwise noted.
4.0 SW = 600k
.5

WER L SS W

2.5

2.0

1.5

1.0

0.5

= 5

= 12

0 0246

10 12 14 16 1 20

L A C RRE A

Figure 26. Power Loss at 1V Output

LTM4640
Figure 27. Power Loss at 1.5V Output

Figure 28. Power Loss at 3.3V Output

Figure 29. 5V to 1V Derating Curve, No Heat Sink

Figure 30. 12V to 1V Derating Curve, No Heat Sink

Figure 31. 5V to 1.5V Derating Curve, No Heat Sink

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Rev. 0 27 of 38

Data Sheet

LTM4640

Figure 32. 12V to 1.5V Derating Curve, No Heat Sink

Figure 33. 5V to 3.3V Derating Curve, No Heat Sink

Figure 34. 12V to 3.3V Derating Curve, No Heat Sink

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Rev. 0 28 of 38

Data Sheet

LTM4640

Figure 35 shows a thermal capture of LTM4640 with 12V input, 1V output at 20A, 600kHz, 21°C ambient temperature, without airflow and heat sink conditions.

Figure 35. Thermal Image at 12VIN, 1VOUT at 20A, 600kHz, 21°C Ambient Temperature, without Airflow and Heat Sinking

Table 9. 1V Output
DERATING CURVE Figure 29, Figure 30 Figure 29, Figure 30 Figure 29, Figure 30

VIN (V)
5, 12 5, 12 5, 12

POWER LOSS CURVE
Figure 26 Figure 26 Figure 26

AIRFLOW (LFM)
0 200 400

HEAT SINK
None None None

JA (°C/W) 14 11 10

Table 10. 1.5V Output

DERATING CURVE
Figure 31, Figure 32 Figure 31, Figure 32 Figure 31, Figure 32

VIN (V)
5, 12 5, 12 5, 12

POWER LOSS CURVE
Figure 27 Figure 27 Figure 27

AIRFLOW (LFM)
0 200 400

HEAT SINK
None None None

JA (°C/W) 14 11 10

Table 11. 3.3V Output

VIN

DERATING CURVE

(V)

Figure 33, Figure 34

5, 12

Figure 33, Figure 34

5, 12

Figure 33, Figure 34

5, 12

POWER LOSS CURVE
Figure 28 Figure 28 Figure 28

AIRFLOW (LFM)
0 200 400

HEAT SINK
None None None

JA (°C/W) 15 12 11

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Rev. 0 29 of 38

Data Sheet

LTM4640

Table 12. Output Voltage Response vs. Component Matrix (See Figure 37)

COUT1 VENDORS
Murata

PART NUMBER

DESCRIPTION

GRM32EC70J107ME15L 100µF, 6.3V, X7S, 1210

COUT2 VENDORS
Panasonic

PART NUMBER EEF-GX0E471L

Taiyo Yuden JMK325AC7107MM

100µF, 6.3V, X7S, 1210

TDK

C3225X6S0J107M250AC 100µF, 6.3V, X6S, 1210

Murata

GRM31CR60J227ME11L 220µF, 6.3V, X5R, 1206

DESCRIPTION 470µF, 2.5V, 3m

All Ceramic Output Capacitors

VOUT

VIN

RFB

(V) (V) (k)

1.5

6.65

1.5

6.65

2.5

3.16

2.5

3.16

3.3

2.21

3.3

2.21

fSW (kHz) 600 600 800 800 800 1000 800 1000

COUT1 (CERAMIC
CAP) 4 × 220µF
4 × 220µF
4 × 220µF
4 × 220µF
4 × 220µF
4 × 220µF
4 × 220µF
4 × 220µF

COUT2 (BULK CAP) None
None
None
None
None
None
None
None

COMPa (pF)
Short to COMPb Short to COMPb Short to COMPb Short to COMPb Short to COMPb Short to COMPb Short to COMPb Short to COMPb

RTH ON CTH ON COMPa COMPa
(k) (pF) None None
None None
None None
None None
None None
None None
None None
None None

LOAD PK-PK RECOVERY

STEP DEVIATION TIME

(A) (mV)

(µs)

100

110

114

121

124

Safety Considerations

The LTM4640 does not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current must be provided to protect the unit from catastrophic failure. The device does support thermal shutdown.

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Data Sheet

LTM4640

Layout Checklist/Example
The high integration of LTM4640 makes the printed circuit board (PCB) layout very simple and easy to use. However, to optimize its electrical and thermal performance, some layout considerations are still necessary.
1. Use large PCB copper areas for high current paths, including VIN, GND, and VOUT. It helps to minimize the PCB conduction loss and thermal stress.
2. To minimize noise coupling on the output, reduce the copper area border between VIN and VOUT, and separate them with GND copper.
3. Place high-frequency ceramic input and output capacitors next to the VIN, PGND, and VOUT pins to minimize high-frequency noise.
4. Place a dedicated power ground layer underneath the unit.
5. To minimize the via conduction loss and reduce the µModule thermal stress, use multiple vias for interconnection between the top layer and other power layers.
6. Do not put vias directly on the pad unless they are capped or plated over.
7. Bring out test points on the signal pins for monitoring.
8. Keep separation between CLKIN, CLKOUT, and FREQ pin-traces to minimize the possibility of noise due to crosstalk between these signals.
Figure 36 gives a good example of the recommended PCB layout.

VOUT VIN
GND

036

Figure 36. Recommended PCB Layout

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Rev. 0 31 of 38

Data Sheet

LTM4640

Typical Applications
VIN 3.1V TO 20V

2 × 22µF 25V

VIN LTM4640 VOUT

RUN

VOSNS+

INTVCC

MODE/CLKIN

COMPa COMPb

VOSNS TRACK/SS

GND

33pF 15k

5 × 100µF 6.3V

VOUT 1.0V, 20A

0.1µF

PINS NOT USED IN THIS CIRCUIT: CLKOUT, INTVCC, PGOOD, PHMODE
Figure 37. 3.1VIN to 20VIN, 1V Output at 20A Design

037 038

VIN 5V TO 20V

2 × 22µF 25V
1MHz CLOCK

VIN LTM4640 VOUT

RUN

VOSNS+

MODE/CLKIN

COMPa

412k

COMPb FREQ

VOSNS TRACK/SS

GND

2 × 47µF + 6.3V

VOUT 470µF 3.3V, 20A 6.3V

2.21k

0.1µF

PINS NOT USED IN THIS CIRCUIT: CLKOUT, INTVCC, PGOOD, PHMODE
Figure 38. 5VIN to 20VIN, 3.3V Output with 1MHz External Clock

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Rev. 0 32 of 38

Data Sheet

LTM4640

VIN 3.1V TO 20V

4 × 22µF 25V
0.1µF

VIN RUN

VOUT VOSNS+
LTM4640

INTVCC PHMODE TRACK/SS PGOOD

COMPa COMPb
FB
VOSNS

GND

CLKOUT

33pF

VOUT 1.5V, 40A
10 × 100µF 6.3V

VIN RUN

MODE/CLKIN
VOUT VVOOSSNNSS++
LTM4640

INTVCC PHMODE

COMPa COMPb

TRACK/SS

PGOOD

GND

VOSNS

6.65k

Figure 39. 3.1VIN to 20VIN, Two Phases, 1.5V at 40A Design

040 039

VIN 3.1V TO 20V

4 × 22µF 25V

VIN LTM4640 VOUT

RUN

VOSNS+

INTVCC

MODE/CLKIN

COMPa COMPb

VOSNS TRACK/SS

GND

33pF 6.65k

5 × 100µF 6.3V

VOUT1 1.5V, 20A

0.1µF

PINS NOT USED IN THIS CIRCUIT:
CLKOUT, FREQ, PGOOD, PHMODE

VIN LTM4640 VOUT

RUN

VOSNS+

INTVCC

MODE/CLKIN

COMPa

VOSNS

COMPb

TRACK/SS

GND

33pF 10k

VOUT2 1.2V, 20A 5 × 100µF 6.3V VOUT1
10k

10k

Figure 40. 3.1VIN to 20VIN, 1.2V and 1.5V with Coincident Tracking

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Rev. 0 33 of 38

Data Sheet

LTM4640

Related Parts
Table 13.Related Parts

PART NUMBER DESCRIPTION

COMMENT

LTM4657 LTM4626 LTM4638 LTM4702 LTM4703 LTM4707 LTM4622

8A µModule regulator, pin compatible with 3.1V VIN 20V, 0.6V VOUT 5.5V,

LTM4626, LTM4638 and LTM4640

6.25mm × 6.25mm × 3.87mm BGA

12A µModule regulator, pin compatible with 3.1V VIN 20V, 0.6V VOUT 5.5V,

LTM4657, LTM4638 and LTM4640

6.25mm × 6.25mm × 3.87mm BGA

15A µModule regulator, pin compatible with 3.1V VIN 20V, 0.6V VOUT 5.5V,

LTM4657, LTM4626 and LTM4640

6.25mm × 6.25mm × 5.02mm BGA

10A Silent Switcher 3 µModule regulator, 3V VIN 16V, 0.3V VOUT 6V,

pin compatible with LTM4703 and LTM4707 6.25mm × 6.25mm × 5.07mm BGA

12A Silent Switcher 3 µModule regulator, 3V VIN 16V, 0.3V VOUT 6V,

pin compatible with LTM4702 and LTM4707 6.25mm × 6.25mm × 5.07mm BGA

15A Silent Switcher 3 µModule regulator, 3V VIN 16V, 0.3V VOUT 6V,

pin compatible with LTM4702 and LTM4703 6.25mm × 6.25mm × 5.07mm BGA

Dual 2.5A or single 5A µModule regulator 3.6V VIN 20V, 0.6V VOUT 5.5V,

LTM4705
LTM4646
LTM4630/ LTM4630A

Dual 5A or single 10A µModule regulator
Dual 10A or single 20A µModule regulator
Dual 18A or single 36A µModule regulator, pin compatible with LTM4650

6.25mm × 6.25mm × 1.82mm (LGA) or 2.42mm (BGA) 3.1V VIN 20V, 0.6V VOUT 5.5V,
6.25mm × 7.5mm × 3.22mm BGA 4.5V VIN 20V, 0.6V VOUT 5.5V,
11.25mm × 15mm × 5.01mm BGA 4.5V VIN 15V (18V for LTM4630A), 0.6V VOUT 1.8V
(8V for LTM4630A), 16mm × 16mm × 4.41mm (LGA)

LTM4650/ LTM4650A

Dual 25A or single 50A µModule regulator, pin compatible with LTM4630

or 5.01mm (BGA) 4.5V VIN 15V (16V for LTM4650A), 0.6V VOUT 1.8V
(5.5V for LTM4650A), 16mm × 16mm × 4.41mm (LGA)

LTM4668/ LTM4668A LTM4643
LTM4644

Configurable quad 1.2A µModule regulator
Configurable quad 3A µModule regulator, Pin compatible with LTM4644 Configurable quad 4A µModule regulator, pin compatible with LTM4643

or 5.01mm (BGA) 2.7V VIN 17V, 0.6V VOUT 1.8V (5.5V for
LTM4668A), 6.25mm × 6.25mm × 2.1mm BGA 4V VIN 20V, 0.6V VOUT 3.3V,
9mm × 15mm × 1.82mm LGA, 2.42mm BGA 4V VIN 14V, 0.6V VOUT 5.5V,
9mm × 15mm × 5.01mm BGA

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Rev. 0 34 of 38

OUTLINE DIMENSIONS

LTM4640

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Figure 41. 49-Pin, 6.25mm × 6.25mm × 5.07mm, BGA

Rev. 0 35 of 38

Data Sheet

LTM4640

ORDERING GUIDE

Table 14.Ordering Guide

TEMPERATURE PACKAGE

MODEL

RANGE 1 DESCRIPTION*

PACKAGE OPTION

LTM4640EY#PBF

40°C to 125°C Part marking: 4640, 49-Pin, 6.25mm × 6.25mm × 5.07mm, BGA

SAC305 (RoHS) ball package.

finish, e1 finish code,

moisture sensitivity

level (MSL 4) rated

LTM4640IY#PBF

device. 40°C to 125°C Part marking: 4640, 49-Pin, 6.25mm × 6.25mm × 5.07mm, BGA

SAC305 (RoHS) ball package.

finish, e1 finish code,

moisture sensitivity

level (MSL 4) rated

device.

The LTM4640, including E-grade and I-grade parts (see Table 14), is tested under pulsed load conditions such that TJ TA. The LTM4640E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the 40°C to 125°C internal operating temperature range are

assured by design, characterization, and correlation with statistical process controls. The LTM4640I is guaranteed to meet specifications over the full 40°C to 125°C internal operating temperature range. Note

that the maximum ambient temperature consistent with these specifications is determined by specific

operating conditions in conjunction with board layout, the rated package thermal resistance, and other

environmental factors.

Contact the factory for parts specified with wider operating temperature ranges. *Ball finish code is per IPC/JEDEC J-STD-609. The temperature grade is identified by a label on the shipping container.

Recommended LGA and BGA PCB assembly and manufacturing procedures.

LGA and BGA package and tray drawings.

Table 15. Evaluation Boards PART NUMBER DC3107A

DESCRIPTION 20VIN, 20A Step-Down DC-to-DC µModule Regulator evaluation (demo) board.

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Rev. 0 36 of 38

Data Sheet
SELECTOR GUIDE
Package Photos

LTM4640

(Part marking is laser mark)

Design Resources
Table 16. Design Resources

SUBJECT

DESCRIPTION

µModule Design and Manufacturing Resources

Design:
Selector guides Evaluation (demo)
boards and Gerber files Free simulation tools

Manufacturing:
Quick start guide PCB design, assembly, and
manufacturing guidelines Package and board level
reliability

µModule Regulator Products Search

Sort table of products by parameters and download the result
as a spread sheet. Search using the Quick Power Search parametric table.

Digital Power System Management

The Analog Devices family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging.

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Rev. 0 37 of 38

Data Sheet

LTM4640

ALL INFORMATION CONTAINED HEREIN IS PROVIDED “AS IS” WITHOUT REPRESENTATION OR WARRANTY. NO RESPONSIBILITY IS ASSUMED BY ANALOG DEVICES FOR ITS USE, NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THIRD PARTIES THAT MAY RESULT FROM ITS USE. SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. NO LICENCE, EITHER EXPRESSED OR IMPLIED, IS GRANTED UNDER ANY ADI PATENT RIGHT, COPYRIGHT, MASK WORK RIGHT, OR ANY OTHER ADI INTELLECTUAL PROPERTY RIGHT RELATING TO ANY COMBINATION, MACHINE, OR PROCESS, IN WHICH ADI PRODUCTS OR SERVICES ARE USED. TRADEMARKS AND REGISTERED TRADEMARKS ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS. ALL ANALOG DEVICES PRODUCTS CONTAINED HEREIN ARE SUBJECT TO RELEASE AND AVAILABILITY.

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Documents / Resources

ANALOG DEVICES LTM4640 20A Step Down DC to DC Module Regulator [pdf] Owner's Manual
LTM4640 20A Step Down DC to DC Module Regulator, LTM4640, 20A Step Down DC to DC Module Regulator, Down DC to DC Module Regulator, Module Regulator, Regulator

References

User Manual

ANALOG DEVICES LTM4640 20A Step Down DC to DC Module Regulator

Product Usage Instructions

FAQ

FEATURES

GENERAL DESCRIPTION

SPECIFICATIONS

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

APPLICATIONS INFORMATION

Safety Considerations

OUTLINE DIMENSIONS

ORDERING GUIDE

Documents / Resources

References

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