Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi

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I-FPGA Integer Arithmetic IP Cores

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi
Ibuyekezelwe i-Intel® Quartus® Prime Design Suite: 20.3

Inguqulo Ye-inthanethi Thumela Impendulo

UG-01063

I-ID: 683490 Inguqulo: 2020.10.05

Okuqukethwe
Okuqukethwe
1. Intel FPGA Integer Arithmetic IP Cores……………………………………………………………….. 5
2. LPM_COUNTER (Counter) IP Core……………………………………………………………………….. 7 2.1. Izici…………………………………………………………………………………………………….7 2.2. I-Verilog HDL Prototype……………………………………………………………………………….. 8 2.3. I-VHDL Component Declaration………………………………………………………………………….8 2.4. I-VHDL LIBRARY_USSE Declaration…………………………………………………………………………………………………………………………………………………………………………… 9 2.5. Amachweba ………………………………………………………………………………………………………..9 2.6. Amapharamitha……………………………………………………………………………………………………………
3. LPM_DIVIDE (Divider) Intel FPGA IP Core………………………………………………………….. 12 3.1. Izici………………………………………………………………………………………………………. 12 3.2. I-Verilog HDL Prototype…………………………………………………………………………………… 12 3.3. I-VHDL Component Declaration……………………………………………………………………….. 13 3.4. I-VHDL LIBRARY_USE Declaration………………………………………………………………………. 13 3.5. Amachweba ………………………………………………………………………………………………………………………………………………………………………………………………………… Amapharamitha………………………………………………………………………………………………………
4. LPM_MULT (Multiplier) IP Core……………………………………………………………………………. 16 4.1. Izici………………………………………………………………………………………………………. 16 4.2. I-Verilog HDL Prototype…………………………………………………………………………………… 17 4.3. I-VHDL Component Declaration……………………………………………………………………….. 17 4.4. I-VHDL LIBRARY_USE Declaration………………………………………………………………………. 17 4.5. Amasignali……………………………………………………………………………………………………………………………………………………………………………………………… 18 4.6. Amapharamitha we-Stratix V, i-Arria V, i-Cyclone V, ne-Intel Cyclone 10 LP Amadivayisi……………… 18 4.6.1. Ithebhu evamile………………………………………………………………………………………18 4.6.2. Okujwayelekile 2 Ithebhu…………………………………………………………………………………… 19 4.6.3. Ithebhu yokufaka amapayipi …………………………………………………………………………………… 19 4.7. Amapharamitha we-Intel Stratix 10, Intel Arria 10, kanye ne-Intel Cyclone 10 GX Amadivayisi ……….. 20 4.7.1. Ithebhu evamile……………………………………………………………………………………20 4.7.2. Okujwayelekile 2 Ithebhu…………………………………………………………………………………… 20 4.7.3. Ukufakwa kwamapayipi ………………………………………………………………………………………
5. LPM_ADD_SUB (I-Adder/Subtractor)……………………………………………………………………… 22 5.1. Izici………………………………………………………………………………………………………. 22 5.2. I-Verilog HDL Prototype…………………………………………………………………………………… 23 5.3. I-VHDL Component Declaration……………………………………………………………………….. 23 5.4. I-VHDL LIBRARY_USE Declaration………………………………………………………………………. 23 5.5. Amachweba …………………………………………………………………………………………………………………………………………………………………………………………………… Amapharamitha…………………………………………………………………………………………………… 23
6. LPM_COMPARE (Isiqhathanisi)………………………………………………………………………………… 26 6.1. Izici………………………………………………………………………………………………………. 26 6.2. I-Verilog HDL Prototype…………………………………………………………………………………… 27 6.3. I-VHDL Component Declaration……………………………………………………………………….. 27 6.4. I-VHDL LIBRARY_USE Declaration………………………………………………………………………. 27 6.5. Amachweba ……………………………………………………………………………………………………………………………………………………………………………………………………… Amapharamitha………………………………………………………………………………………………… 27

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7. I-ALTECC (Ikhodi Yokulungisa Iphutha: Isifaki khodi/Isikhiphi) IP Core…………………………………………… 30
7.1. Izici Zesifaki khodi se-ALTECC……………………………………………………………………………..31 7.2. I-Verilog HDL Prototype (ALTECC_ENCODER)…………………………………………………………. 32 7.3. I-Verilog HDL Prototype (ALTECC_DECODER)…………………………………………………………. 32 7.4. I-VHDL Component Declaration (ALTECC_ENCODER)………………………………………………33 7.5. Isimemezelo Sengxenye Ye-VHDL (ALTECC_DECODER)………………………………………………33 7.6. I-VHDL LIBRARY_USE Declaration………………………………………………………………………. 33 7.7. Izimbobo ze-Encoder…………………………………………………………………………………………………………………………………………………………………………………… 33 7.8. Izimbobo zedikhoda…………………………………………………………………………………………… Amapharamitha wesifaki khodi……………………………………………………………………………………… 34 7.9. Amapharamitha edikhoda ……………………………………………………………………………………
8. I-Intel FPGA Multiply Adder IP Core…………………………………………………………………………. 36
8.1. Izici………………………………………………………………………………………………………. 37 8.1.1. I-pre-adder………………………………………………………………………………….. 38 8.1.2. Irejista yokubambezeleka kwe-Systolic…………………………………………………………………….. 40 8.1.3. I-Pre-load Constant……………………………………………………………………………… I-Double Accumulator………………………………………………………………………… 43
8.2. I-Verilog HDL Prototype…………………………………………………………………………………… 44 8.3. I-VHDL Component Declaration……………………………………………………………………….. 44 8.4. I-VHDL LIBRARY_USE Declaration………………………………………………………………………. 44 8.5. Amasignali…………………………………………………………………………………………………………………………………………………………………………………………………… 44 8.6. Amapharamitha……………………………………………………………………………………………… 47
8.6.1. Ithebhu evamile…………………………………………………………………………………47 8.6.2. Ithebhu yamamodi engeziwe………………………………………………………………………….. 47 8.6.3. Ithebhu Yeziphindaphinda…………………………………………………………………………….. 49 8.6.4. Ithebhu Ye-Preadder……………………………………………………………………………………. 51 8.6.5. Ithebhu Ye-accumulator…………………………………………………………………………….. 53 8.6.6. Ithebhu ye-Systolic/Chainout………………………………………………………………………. 55 8.6.7. Ithebhu yokufaka amapayipi …………………………………………………………………………………… 56
9. I-ALTMEMMULT (I-Memory-based Constant Coefficient Multiplier) IP Core……………………… 57
9.1. Izici………………………………………………………………………………………………………. 57 9.2. I-Verilog HDL Prototype…………………………………………………………………………………… 58 9.3. I-VHDL Component Declaration……………………………………………………………………….. 58 9.4. Amachweba ……………………………………………………………………………………………………………………………………………………………………………………………………………… Amapharamitha………………………………………………………………………………………………… 59
10. ALTMULT_ACCUM (Phindekisa-Buthelela) I-IP Core………………………………………………… 61
10.1. Izici………………………………………………………………………………………………….. 62 10.2. I-Verilog HDL Prototype……………………………………………………………………………..62 10.3. I-VHDL Component Declaration………………………………………………………………………………… I-VHDL LIBRARY_USSE Declaration……………………………………………………………………………63 10.4. Amachweba …………………………………………………………………………………………………………………………………………………… 63 10.5. Amapharamitha………………………………………………………………………………………………. 63
11. ALTMULT_ADD (I-Multiply-Adder) IP Core……………………………………………………………..69
11.1. Izici………………………………………………………………………………………………….. 71 11.2. I-Verilog HDL Prototype……………………………………………………………………………..72 11.3. I-VHDL Component Declaration…………………………………………………………………………… 72 11.4. I-VHDL LIBRARY_USE Declaration………………………………………………………………………72

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11.5. Amachweba …………………………………………………………………………………………………………………………………………………… 72 11.6. Amapharamitha………………………………………………………………………………………………. 73
12. ALTMULT_COMPLEX (I-Complex Multiplier) IP Core………………………………………………… 86 12.1. Ukuphindaphinda Okuyinkimbinkimbi………………………………………………………………………………. 86 12.2. Ukumelwa kweCanonical……………………………………………………………………………… 87 12.3. Ukumelela Okuvamile……………………………………………………………………… 87 12.4. Izici……………………………………………………………………………………………….. 88 12.5. I-Verilog HDL Prototype………………………………………………………………………………..88 12.6. I-VHDL Component Declaration……………………………………………………………………………… I-VHDL LIBRARY_USSE Declaration………………………………………………………………………89 12.7. Amasignali………………………………………………………………………………………………………………………………………………. 89 12.8. Amapharamitha………………………………………………………………………………………………. 89
13. ALTSQRT (Integer Square Root) IP Core………………………………………………………………92 13.1. Izici……………………………………………………………………………………………….. 92 13.2. I-Verilog HDL Prototype……………………………………………………………………………..92 13.3. I-VHDL Component Declaration………………………………………………………………………………… I-VHDL LIBRARY_USSE Declaration…………………………………………………………………………93 13.4. Amachweba …………………………………………………………………………………………………………………………………………………… 93 13.5. Amapharamitha………………………………………………………………………………………………. 93
14. PARALLEL_ADD (Parallel Adder) IP Core………………………………………………………….. 95 14.1. Isici……………………………………………………………………………………………….95 14.2. I-Verilog HDL Prototype………………………………………………………………………………..95 14.3. I-VHDL Component Declaration……………………………………………………………………………… I-VHDL LIBRARY_USSE Declaration…………………………………………………………………………96 14.4. Amachweba …………………………………………………………………………………………………………………………………………………… 96 14.5. Amapharamitha………………………………………………………………………………………………. 96
15. I-Integer Arithmetic IP Cores User Guide Document Archives …………………………………… 98
16. Umlando Wokubuyekezwa Kombhalo we-Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi…. 99

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 4

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683490 | 2020.10.05 Thumela Impendulo

1. Intel FPGA Integer Arithmetic IP Cores

Ungasebenzisa i-Intel® FPGA integer IP cores ukwenza imisebenzi yezibalo ekwakhiweni kwakho.

Le misebenzi ihlinzeka ngokuhlanganiswa okunengqondo okusebenza kahle kakhulu nokusebenzisa idivayisi kunokubhala ngekhodi imisebenzi yakho. Ungenza ngokwezifiso ama-IP cores ukuze ahlangabezane nezidingo zakho zedizayini.

I-Intel integer arithmetic IP cores ihlukaniswe yaba izigaba ezimbili ezilandelayo: · Umtapo wolwazi wamamojula anepharamitha (LPM) IP cores · Intel-specific (ALT) IP cores

Ithebula elilandelayo lifaka uhlu lwezinombolo ze-IP cores ze-arithmetic.

Ithebula 1.

Uhlu lwama-IP Cores

IP Cores

I-LPM IP cores

LPM_COUNTER

LPM_DIVIDE

LPM_MULT

LPM_ADD_SUB
LPM_COMPARE
Intel-specific (ALT) IP cores ALTECC

Umsebenzi Uphelileview I-Counter Divider Multiplier
I-Adder noma i-subtractor Comparator
I-ECC Encoder/Decoder

Idivayisi Esekelwe
I-Arria® II GX, i-Arria II GZ, i-Arria V, i-Intel Arria 10, i-Cyclone® IV E, i-Cyclone IV GX, i-Cyclone V, i-Intel Cyclone 10 LP,
I-Intel Cyclone 10 GX, MAX® II, MAX V, MAX 10, Stratix® IV, Stratix V
I-Arria II GX, i-Arria II GZ, i-Arria V, i-Intel Arria 10, i-Cyclone IV E, i-Cyclone IV GX,
I-Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
I-Arria II GX, i-Arria II GZ, i-Arria V, i-Intel Arria 10, i-Cyclone IV E, i-Cyclone IV GX,
I-Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
I-Arria II GX, i-Arria II GZ, i-Arria V, i-Intel Arria 10, i-Cyclone IV E, i-Cyclone IV GX,
I-Cyclone V,Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, i-Stratix IV, i-Stratix V iqhubekile…

Inkampani ye-Intel Wonke Amalungelo Agodliwe. I-Intel, ilogo ye-Intel, nezinye izimpawu ze-Intel yizimpawu zokuthengisa ze-Intel Corporation noma izinkampani ezingaphansi kwayo. I-Intel iqinisekisa ukusebenza kwe-FPGA yayo kanye nemikhiqizo yesemiconductor ekucacisweni kwamanje ngokuvumelana newaranti evamile ye-Intel, kodwa igodla ilungelo lokwenza izinguquko kunoma imiphi imikhiqizo namasevisi nganoma yisiphi isikhathi ngaphandle kwesaziso. I-Intel ayithathi mthwalo noma isikweletu esivele ngenxa yesicelo noma ukusetshenziswa kwanoma yiluphi ulwazi, umkhiqizo, noma isevisi echazwe lapha ngaphandle kwalapho okuvunyelwene ngakho ngokubhaliwe yi-Intel. Amakhasimende e-Intel ayelulekwa ukuthi athole inguqulo yakamuva yokucaciswa kwedivayisi ngaphambi kokuthembela kunoma yiluphi ulwazi olushicilelwe nangaphambi kokufaka ama-oda emikhiqizo noma amasevisi. *Amanye amagama namabhrendi angafunwa njengempahla yabanye.

I-ISO 9001:2015 Ibhalisiwe

1. Intel FPGA Integer Arithmetic IP Cores 683490 | 2020.10.05

IP Cores Intel FPGA Multiply Adder noma ALTERA_MULT_ADD ALTMEMMULT
ALTMULT_ACCUM ALTMULT_ADD ALTMULT_COMPLEX
ALTSQRT
PARALLEL_ADD

Umsebenzi Uphelileview I-Multiplier-Adder
I-Memory-based Constant Coefficient Multiplier
I-Multiplier-Accumulator Multiplier-Adder
Isiphindaphinda esiyinkimbinkimbi
I-Integer Square-Root
I-Parallel Adder

Idivayisi Esekelwe
Arria V, Stratix V, Cyclone V, Intel Stratix 10, Intel Arria 10, Intel Cyclone
10 GX
Arria II GX, Arria II GZ, Arria V, Intel Arria 10 (Intel Quartus® Prime Standard Edition), Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
I-Cyclone 10 LP, MAX II, MAX V, MAX 10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX,Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
I-Arria II GX, i-Arria II GZ, i-Intel Arria 10, i-Arria V, i-Arria V GZ, i-Cyclone IV E, i-Cyclone IV GX, i-Cyclone V, i-Intel
I-Cyclone 10 GX, Intel Cyclone 10 LP, MAX 10, Stratix V, Intel Stratix 10
I-Arria II GX, i-Arria II GZ, i-Arria V, i-Intel Arria 10, i-Cyclone IV E, i-Cyclone IV GX,
I-Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V
I-Arria II GX, i-Arria II GZ, i-Arria V, i-Intel Arria 10, i-Cyclone IV E, i-Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP,Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V

Ulwazi Oluhlobene
· I-Intel FPGAs kanye Namanothi Okukhishwa Kwamadivayisi Ahlelekayo
· Isingeniso se-Intel FPGA IP Cores Sinikeza ulwazi olwengeziwe mayelana ne-Intel FPGA IP Cores.
· Umhlahlandlela Womsebenzisi Wezingqikithi Ze-IP Entantayo Inikeza ulwazi olwengeziwe mayelana nama-Intel FPGA Floating-Point IP cores.
· Isethulo ku-Intel FPGA IP Cores Inikeza ulwazi olujwayelekile mayelana nawo wonke ama-Intel FPGA IP cores, okuhlanganisa ukwenza ipharamitha, ukukhiqiza, ukuthuthukisa, kanye nokulingisa ama-IP cores.
· Ukudala Inguqulo Ezimele Ye-IP Nezikripthi Zokulingisa ze-Qsys Dala izikripthi zokulingisa ezingadingi ukubuyekezwa mathupha kwesofthiwe noma ukuthuthukiswa kwenguqulo ye-IP.
· Ukuphathwa Kwephrojekthi Imihlahlandlela Yemikhuba Engcono Kakhulu yokuphatha kahle nokuphatheka kwephrojekthi yakho ne-IP files.
· I-Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi Wokugcina Izingobo Zomlando ekhasini 98 Ihlinzeka ngohlu lwemihlahlandlela yabasebenzisi yezinguqulo zangaphambilini ze-Integer Arithmetic IP cores.

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 6

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2. LPM_COUNTER (Isibali) IP Core

Umfanekiso 1.

I-LPM_COUNTER IP core iyisibali kanambambili esakha izinto zokubala eziphezulu, zokubala ezansi neziphezulu noma ezansi ezinemiphumela efinyelela kumabhithi angu-256 ububanzi.

Isibalo esilandelayo sibonisa izimbobo ze-LPM_COUNTER IP core.

LPM_COUNTER Izimbobo

LPM_COUNTER

ssclr sload idatha yesethi[]

q[]

phezulu phansi

i-cout

aclr aload asset

clk_zu cnt_zu cin
inst

2.1. Izici
I-LPM_COUNTER IP core inikeza izici ezilandelayo: · Ikhiqiza izinto zokubala eziphezulu, phansi, naphezulu/phansi · Ikhiqiza izinhlobo zokubala ezilandelayo:
- I-Plain kanambambili- ikhawunta yekhawunta iqala ku-zero noma i-decrements iqala ku-255
- I-Modulus-ikhawunta yekhawunta iya noma iyancipha ukusuka enanini lemodulus elishiwo umsebenzisi bese iphinda
· Isekela okukhethwa kukho kokuvumelanisa okucacile, ukulayisha, nokusetha izimbobo zokufaka · Isekela izimbobo zokufakwayo ozikhethelayo ezicacile, layisha, futhi usethe okokufaka · Isekela ukubala kokuzikhethela vumela futhi iwashi linike amandla izimbobo zokufaka · Isekela izimbobo zokungena neziphumayo ozikhethela

I-ISO 9001:2015 Ibhalisiwe

2. LPM_COUNTER (Isibali) IP Core
683490 | 2020.10.05
2.2. I-Verilog HDL Prototype
Lesi sibonelo esilandelayo se-Verilog HDL sitholakala ku-Verilog Design File (.v) lpm.v ku i-edasynthesis directory.
module lpm_counter ( q, idatha, iwashi, cin, cout, clk_en, cnt_en, updown, aset, aclr, aload, sset, sclr, sload, eq ); ipharamitha lpm_type = “lpm_counter”; ipharamitha lpm_width = 1; ipharamitha lpm_modulus = 0; ipharamitha lpm_direction = “OKUNGASETSHENZISWA”; ipharamitha lpm_avalue = “OKUNGASETSHENZISWA”; ipharamitha lpm_svalue = “OKUNGASETSHENZISWA”; ipharamitha lpm_pvalue = “OKUNGASETSHENZISIWE”; ipharamitha lpm_port_updown = “PORT_CONNECTIVITY”; ipharamitha lpm_hint = “OKUNGASETSHENZISWA”; okukhiphayo [lpm_width-1:0] q; ukuphuma kokukhishwa; okukhiphayo [15:0] eq; i-cin input; okokufaka [lpm_width-1:0] idatha; iwashi lokufaka, clk_en, cnt_zu, phezulu; i-asethi yokufaka, aclr, aload; isethi yokufaka, sclr, sload; endmodule
2.3. Isimemezelo Sengxenye Ye-VHDL
Isimemezelo sengxenye ye-VHDL sitholakala ku-VHDL Design File (.vhd) LPM_PACK.vhd ku librariesvhdllpm directory.
ingxenye LPM_COUNTER ejwayelekile ( LPM_WIDTH : yemvelo; LPM_MODULUS : yemvelo := 0; LPM_DIRECTION : string := "AKUSETSHENZISWA"; LPM_AVALUE : uchungechunge := "OKUNGASETSHENZISIWE"; LPM_SVALUE : uchungechunge := "OKUNGASETSHENZISIWE"; LPM_PORTIVPD : LPM_PORTIV ; LPM_PVALUE : iyunithi yezinhlamvu := “OKUNGASETSHENZISIWE”; LPM_TYPE : string := L_COUNTER; LPM_HINT : string := “AKUSETSHENZISWA”); port (IDATHA : in std_logic_vector(LPM_WIDTH-1 downto 0):= (OTHERS =>
'0'); IWASHI : ku-std_logic ; CLK_EN : ku-std_logic := '1'; CNT_EN : ku-std_logic := '1'; OKUSHA : ku-std_logic := '1'; SLOAD : ku-std_logic := '0'; I-SSET : ku-std_logic := '0'; I-SCLR : ku-std_logic := '0'; I-ALOAD : ku-std_logic := '0'; I-ASET : ku-std_logic := '0'; I-ACLR : ku-std_logic := '0'; I-CIN : ku-std_logic := '1'; I-COUT : out std_logic := '0'; Q : out std_logic_vector(LPM_WIDTH-1 downto 0); I-EQ : out std_logic_vector(15 downto 0));
ingxenye yokugcina;

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2.4. I-VHDL LIBRARY_USE Isimemezelo
Isimemezelo se-VHDL LIBRARY-USE asidingeki uma usebenzisa Isimemezelo Sengxenye Ye-VHDL.
I-LIBRARY lpm; SEBENZISA i-lpm.lpm_components.all;

2.5. Amachweba

Amathebula alandelayo aklelisa izimbobo zokufaka neziphumayo ze-LPM_COUNTER IP core.

Ithebula 2.

LPM_COUNTER Izimbobo Zokufaka

Igama Lembobo

Kudingeka

Incazelo

idatha[]

Cha

Ukufakwa kwedatha ehambisanayo kwikhawunta. Usayizi wembobo yokufaka uncike enanini lepharamitha ye-LPM_WIDTH.

iwashi

Yebo

Okokufaka kwewashi elicushwe kahle.

clk_zu

Cha

Iwashi linika amandla okokufaka ukuze unike amandla yonke imisebenzi ehambisanayo. Uma ikhishiwe, inani elizenzakalelayo lingu-1.

cnt_zu

Cha

Ukubala vumela okokufaka ukuze ukhubaze ukubala uma kuthiwa kuphansi ngaphandle kokuthinta i-sload, i-sset, noma i-sclr. Uma ikhishiwe, inani elizenzakalelayo lingu-1.

phezulu phansi

Cha

Ilawula isiqondiso sokubala. Uma kugonyelwa phezulu (1), isiqondiso sokubala siphezulu, futhi uma kuthiwa siphansi (0), isiqondiso sokubala siphansi. Uma ipharamitha ye-LPM_DIRECTION isetshenziswa, imbobo ebheke phezulu ayikwazi ukuxhunywa. Uma i-LPM_DIRECTION ingasetshenziswa, imbobo ebheke phezulu ingakhethwa. Uma ikhishiwe, inani elizenzakalelayo liphezulu (1).

cin

Cha

Ngena ku-bit ye-oda eliphansi. Ezibalini eziphezulu, ukuziphatha kwe-cin input kungukuthi

kufana nokuziphatha kokokufaka kwe-cnt_en. Uma ikhishiwe, inani elizenzakalelayo ngu-1

(VCC).

aclr

Cha

Okokufaka okucacile okungahambisani. Uma kokubili i-asethi ne-aclr kusetshenziswa futhi kushiwo, i-aclr ikhipha i-asethi. Uma ikhishiwe, inani elizenzakalelayo lingu-0 (likhutshaziwe).

impahla

Cha

Okokufaka kwesethi engavumelanisi. Icacisa okukhishwayo okungu-q[] njengawo wonke u-1, noma inani elishiwo ipharamitha ye-LPM_AVALUE. Uma zombili izimbobo ze-asethi ne-aclr zisetshenziswa futhi kushiwo, inani lembobo ye-aclr leqa inani lembobo ye-asethi. Uma ikhishiwe, inani elizenzakalelayo ngu-0, likhutshaziwe.

layisha

Cha

Okokufaka kokulayisha okungavumelaniyo okulayisha ngokulinganayo ikhawunta enenani lokokufaka idatha. Uma imbobo yokulayisha isetshenziswa, imbobo yedatha[] kufanele ixhumeke. Uma ikhishiwe, inani elizenzakalelayo ngu-0, likhutshaziwe.

sclr

Cha

Okokufaka okucacile okuvumelanayo okusula ikhawunta emaphethelweni ewashi asebenzayo alandelayo. Uma zombili izimbobo ze-sset ne-sclr zisetshenziswa futhi kushiwo, inani lembobo ye-sclr leqa inani lembobo ye-sset. Uma ikhishiwe, inani elizenzakalelayo ngu-0, likhutshaziwe.

isethi

Cha

Okokufaka kwesethi ehambisanayo esetha isibali onqenqemeni lwewashi elilandelayo elisebenzayo. Icacisa inani lemiphumela engu-q njengabo bonke o-1, noma inani elishiwo ipharamitha ye-LPM_SVALUE. Uma zombili izimbobo ze-sset ne-sclr zisetshenziswa futhi zigonyelwa,
inani lembobo ye-sclr leqa inani lembobo ye-sset. Uma ikhishiwe, inani elizenzakalelayo lingu-0 (likhutshaziwe).

layisha

Cha

Okokufaka kokulayisha okuvumelanisiwe okulayisha isibali ngedatha[] onqenqemeni lwewashi elisebenzayo elilandelayo. Uma imbobo ye-sload isetshenziswa, imbobo yedatha[] kufanele ixhunywe. Uma ikhishiwe, inani elizenzakalelayo lingu-0 (likhutshaziwe).

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 9

2. LPM_COUNTER (Isibali) IP Core 683490 | 2020.10.05

Ithebula 3.

LPM_COUNTER Izimbobo zokuphuma

Igama Lembobo

Kudingeka

Incazelo

q[]

Cha

Okukhipha idatha kusuka kukhawunta. Usayizi wembobo yokuphumayo uncike ku-

LPM_WIDTH inani lepharamitha. Kungaba i-q[] noma okungenani imbobo eyodwa ye-eq[15..0]

kumele ixhunywe.

i-eq[15..0]

Cha

I-Counter decode okukhiphayo. Imbobo ye-eq[15..0] ayifinyeleleki kumhleli wepharamitha ngoba ipharamitha isekela i-AHDL kuphela.
Imbobo ye-q[] noma i-eq[] imbobo kufanele ixhumeke. Kuze kufike kumachweba we-c eq angasetshenziswa (0 <= c <= 15). Amanani wokubala aphansi angu-16 kuphela akhishwa ikhodi. Uma inani lokubala lingu-c, okukhiphayo kwe-eqc kuthiwa kuphezulu (1). Okwesiboneloampi-le, uma isibalo singu-0, eq0 = 1, uma isibalo singu-1, eq1 = 1, futhi uma isibalo singu-15, i-eq 15 = 1. Okukhiphayo okunqunyiwe kwamanani wokubala ka-16 noma ngaphezulu kudinga ukuqoshwa kwangaphandle. Okuphumayo kwe-eq[15..0] ku-asynchronous kuya ku-q[] okukhiphayo.

i-cout

Cha

Khipha imbobo ye-MSB bit yekhawunta. Ingasetshenziselwa ukuxhuma kwenye ikhawunta ukuze udale ikhawunta enkulu.

2.6. Amapharamitha

Ithebula elilandelayo libala imingcele ye-LPM_COUNTER IP core.

Ithebula 4.

LPM_COUNTER Amapharamitha

Igama lepharamitha

Uhlobo

LPM_WIDTH

Inombolo ephelele

LPM_DIRECTION

Intambo

LPM_MODULUS LPM_AVALUE

Inombolo ephelele
Inombolo ephelele/ Intambo

LPM_SVALUE LPM_HINT

Inombolo ephelele/ Intambo
Intambo

LPM_TYPE

Intambo

Kudingeka Yebo Cha Cha Cha
Cha No
Cha

Incazelo
Icacisa ububanzi bedatha[] kanye nezimbobo ze-q[], uma zisetshenziswa.
Amanani PHEZULU, PHANSI, futhi AKASETSHENZISWA. Uma ipharamitha ye-LPM_DIRECTION isetshenziswa, imbobo ebheke phezulu ayikwazi ukuxhunywa. Uma imbobo eya phezulu ingaxhumekile, inani elizenzakalelayo lepharamitha LPM_DIRECTION LIPHEZULU.
Isibalo esiphezulu, kanye nokukodwa. Inombolo yezimo ezihlukile kumjikelezo wekhawunta. Uma inani lomthwalo likhulu kunepharamitha ye-LPM_MODULUS, ukuziphatha kwekhawunta akucacisiwe.
Inani eliqhubekayo elilayishwayo lapho i-asethi kuthiwa iphezulu. Uma inani elishiwo likhulu noma lilingana nalo , ukuziphatha kwekhawunta kuyizinga lengqondo elingachazwanga (X), lapho yi-LPM_MODULUS, uma ikhona, noma 2 ^ LPM_WIDTH. I-Intel incoma ukuthi ucacise leli nani njengenombolo yedesimali yemiklamo ye-HDL.
Inani eliqhubekayo elilayishwa onqenqemeni olukhuphukayo lwembobo yewashi lapho imbobo ye-sset kuthiwa iphakeme. I-Intel incoma ukuthi ucacise leli nani njengenombolo yedesimali yemiklamo ye-HDL.
Uma uqinisekisa ukuthi umtapo wezincwadi wamamojula anepharamitha (LPM) usebenza Kudizayini ye-VHDL File (.vhd), kufanele usebenzise ipharamitha ye-LPM_HINT ukuze ucacise ipharamitha eqondene ne-Intel. Okwesiboneloample: LPM_HINT = “CHAIN_SIZE = 8, ONE_INPUT_IS_CONSTANT = YEBO”
Inani elizenzakalelayo AKUSETSHENZISWA.
Ihlonza igama lebhizinisi lebhizinisi lamamojula we-parameterized (LPM) emtatsheni we-VHDL files.
waqhubeka...

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 10

Thumela Impendulo

2. LPM_COUNTER (Isibali) IP Core 683490 | 2020.10.05

Igama lepharamitha INTENDED_DEVICE_FAMILY CARRY_CNT_EN
LABWIDE_SCLR
LPM_PORT_UPDOWN

Thayipha Intambo Yezintambo
Intambo
Intambo

Inombolo edingekayo
Cha
Cha

Incazelo
Le parameter isetshenziselwa izinjongo zokulingisa nokuziphatha. Le parameter isetshenziselwa izinjongo zokulingisa nokuziphatha. Umhleli wepharamitha ubala inani lale pharamitha.
Ipharamitha ethize ye-Intel. Kufanele usebenzise ipharamitha ye-LPM_HINT ukuze ucacise ipharamitha ye-CARRY_CNT_EN kumklamo we-VHDL files. Amanani A-SMART, VULIWE, VALIWE, futhi AKASETSHENZISWA. Inika amandla umsebenzi we-LPM_COUNTER ukuze usakaze isignali ye-cnt_en ngochungechunge lokuthwala. Kwezinye izimo, isilungiselelo sepharamitha ye-CARRY_CNT_EN singase sibe nomthelela omncane esivinini, ngakho-ke ungase ufune ukusivala. Inani elizenzakalelayo yi-SMART, ehlinzeka ngokuhwebelana okungcono kakhulu phakathi kosayizi nesivinini.
Ipharamitha ethize ye-Intel. Kufanele usebenzise ipharamitha ye-LPM_HINT ukuze ucacise ipharamitha ye-LABWIDE_SCLR kumklamo we-VHDL files. Amanani AVULIWE, AVALIWE, noma AKASETSHENZISWA. Inani elizenzakalelayo LIVULIWE. Ikuvumela ukuthi ukhubaze ukusetshenziswa kwesici se-LABwide sclr esitholakala emindenini yamadivayisi aphelelwe yisikhathi. Ukuvala le nketho kukhulisa amathuba okusebenzisa ngokugcwele ama-LAB agcwaliswe kancane, futhi ngaleyo ndlela kungase kuvumele ukuminyana okunengqondo okuphezulu lapho i-SCLR ingasebenzi ku-LAB ephelele. Le pharamitha iyatholakala ukuze ihambisane nemuva, futhi i-Intel incoma ukuthi ungasebenzisi le pharamitha.
Icacisa ukusetshenziswa kwembobo yokufaka eyehlayo. Uma kukhishiwe inani elizenzakalelayo lingu-PORT_CONNECTIVITY. Uma inani lembobo lisethelwe ku-PORT_USED, imbobo iphathwa njengesetshenzisiwe. Uma inani lembobo lisethelwe ku-PORT_UNUSED, imbobo ithathwa njengengasetshenzisiwe. Uma inani lembobo lisethelwe ku-PORT_CONNECTIVITY, ukusetshenziswa kwembobo kunqunywa ngokuhlola ukuxhumeka kwembobo.

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 11

683490 | 2020.10.05 Thumela Impendulo

3. LPM_DIVIDE (Isihlukanisi) Intel FPGA IP Core

Umfanekiso 2.

I-LPM_DIVIDE Intel FPGA IP core isebenzisa isihlukanisi ukuze kuhlukaniswe inani lokokufaka lenombolo ngenani lokokufaka eliyidinominetha ukuze kukhiqizwe i-quotient nensalela.

Isibalo esilandelayo sibonisa izimbobo ze-LPM_DIVIDE IP core.

LPM_DIVIDE Izimbobo

LPM_DIVIDE

inombolo[] denom[] iwashi

i-quotient[] hlala[]

cela aclr

inst

3.1. Izici
I-LPM_DIVIDE IP core inikeza izici ezilandelayo: · Ikhiqiza isihlukanisi esihlukanisa inani lokufakwayo lenumerator ngokokufaka kwedenominator
inani lokukhiqiza i-quotient kanye nensalela. · Isekela ububanzi bedatha yamabhithi ayi-1. · Isekela ifomethi yokumelwa kwedatha esayiniwe nengasayiniwe kukho kokubili inombolo
kanye namanani edinomineyitha. · Isekela indawo noma ukwenziwa kwesivinini. · Inikeza inketho yokucacisa okusele okuphozithivu. · Isekela ukubambezeleka kokuphuma kwamapayipi okulungisekayo. · Isekela ozikhethela Asynchronous ecacile futhi iwashi ukunika amandla amachweba.

3.2. I-Verilog HDL Prototype
Lesi sibonelo esilandelayo se-Verilog HDL sitholakala ku-Verilog Design File (.v) lpm.v ku i-edasynthesis directory.
module lpm_divide ( quotient, hlala, inombolo, idenom, iwashi, clken, aclr); ipharamitha lpm_type = “lpm_divide”; ipharamitha lpm_widthn = 1; ipharamitha lpm_widthd = 1; ipharamitha lpm_nrepresentation = “AKUSAYINWE”; ipharamitha lpm_drepresentation = “AKUSAYINWE”; ipharamitha lpm_remainderpositive = “TRUE”; ipharamitha lpm_pipeline = 0;

I-ISO 9001:2015 Ibhalisiwe

3. LPM_DIVIDE (Isihlukanisi) Intel FPGA IP Core 683490 | 2020.10.05

ipharamitha lpm_hint = “OKUNGASETSHENZISWA”; iwashi lokufaka; i-clken yokufaka; okokufaka aclr; okokufaka [lpm_widthn-1:0] inombolo; okokufaka [lpm_widthd-1:0] idinom; okukhiphayo [lpm_widthn-1:0] i-quotient; okuphumayo [lpm_widthd-1:0] kusele; endmodule

3.3. Isimemezelo Sengxenye Ye-VHDL
Isimemezelo sengxenye ye-VHDL sitholakala ku-VHDL Design File (.vhd) LPM_PACK.vhd ku librariesvhdllpm directory.
ingxenye LPM_DIVIDE generic (LPM_WIDTHN : yemvelo; LPM_WIDTHD : eyemvelo;
LPM_NREPRESENTATION : string := "OKUNGASAYINWE"; LPM_DREPRESENTATION : string := "OKUNGASAYINWE"; LPM_PIPELINE : okwemvelo := 0; LPM_TYPE : string := L_DIVIDE; LPM_HINT : string := "OKUNGASETSHENZISWA"); imbobo (NUMER : in std_logic_vector(LPM_WIDTHN-1 downto 0); DENOM : in std_logic_vector(LPM_WIDTHD-1 downto 0); ACLR : in std_logic := '0'; CLOCK : in std_logic := '0logic: Cd'; := '1'; QUOTIENT : out std_logic_vector(LPM_WIDTHN-1 downto 0); REMAIN : out std_logic_vector(LPM_WIDTHD-1 downto 0)); ingxenye yokugcina;

3.4. I-VHDL LIBRARY_USE Isimemezelo
Isimemezelo se-VHDL LIBRARY-USE asidingeki uma usebenzisa Isimemezelo Sengxenye Ye-VHDL.
I-LIBRARY lpm; SEBENZISA i-lpm.lpm_components.all;

3.5. Amachweba

Amathebula alandelayo aklelisa okokufaka nezimbobo ze-LPM_DIVIDE IP core.

Ithebula 5.

LPM_DIVIDE Izimbobo Zokufaka

Igama Lembobo

Kudingeka

inombolo[]

Yebo

idenomu[]

Yebo

Incazelo
Okokufaka kwedatha yenumera. Usayizi wembobo yokufaka uncike enanini lepharamitha ye-LPM_WIDTHN.
Okokufaka kwedatha ye-Denominator. Usayizi wembobo yokufaka uncike enanini lepharamitha ye-LPM_WIDTHD.
waqhubeka...

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 13

3. LPM_DIVIDE (Isihlukanisi) Intel FPGA IP Core 683490 | 2020.10.05

Port Name clock clken
aclr

Inombolo edingekayo
Cha

Incazelo
Okokufaka kwewashi ukuze kusetshenziswe amapayipi. Kumanani we-LPM_PIPELINE ngaphandle kuka-0 (okuzenzakalelayo), imbobo yewashi kufanele inikwe amandla.
Iwashi livumela ukusetshenziswa kwamapayipi. Lapho i-clken port kuthiwa iphakeme, umsebenzi wokuhlukanisa uyenzeka. Uma isignali iphansi, akukho msebenzi owenzekayo. Uma ikhishiwe, inani elizenzakalelayo lingu-1.
Imbobo ecacile engavumelanisiwe esetshenziswa noma nini ukusetha kabusha ipayipi kuwo wonke ama-'0 ngokuhambisana nokokufaka kwewashi.

Ithebula 6.

LPM_DIVIDE Izimbobo Zokukhiphayo

Igama Lembobo

Kudingeka

Incazelo

i-quotient[]

Yebo

Okukhipha idatha. Usayizi wembobo yokuphumayo uncike ku-LPM_WIDTHN

inani lepharamitha.

hlala[]

Yebo

Okukhipha idatha. Usayizi wembobo yokuphumayo uncike ku-LPM_WIDTHD

inani lepharamitha.

3.6. Amapharamitha

Ithebula elilandelayo libala amapharamitha we-LPM_DIVIDE Intel FPGA IP core.

Igama lepharamitha

Uhlobo

Kudingeka

Incazelo

LPM_WIDTHN

Inombolo ephelele

Yebo

Icacisa ububanzi benombolo[] kanye

quotient[] izimbobo. Amanani angu-1 kuya ku-64.

LPM_WIDTHD

Inombolo ephelele

Yebo

Icacisa ububanzi be-denom[] kanye

hlala[] amachweba. Amanani angu-1 kuye ku-64.

I-LPM_NREPRESENTATION LPM_DREPRESENTATION

Intambo Yezintambo

Cha

Ukumelwa kwesignali kokokufaka kwenombolo.

Amanani ESAYINWE futhi AKASAYINWE. Lapho lokhu

ipharamitha isethwe ukuze ithi SIGINWE, isihlukanisi

ihumusha okokufaka kwenombolo[] njengokusayiniwe okubili

umphelelisi.

Cha

Ukumelwa kwesignali kokufakwayo kwedinomineyitha.

Amanani ESAYINWE futhi AKASAYINWE. Lapho lokhu

ipharamitha isethwe ukuze ithi SIGINWE, isihlukanisi

ihumusha okokufaka kwe-denom[] njengokusayiniwe okubili

umphelelisi.

LPM_TYPE

Intambo

Cha

Ihlonza umtapo wolwazi wamapharamitha

amamojula (LPM) igama lebhizinisi ekwakhiweni kwe-VHDL

files (.vhd).

LPM_HINT

Intambo

Cha

Uma wenza umtapo wolwazi we

umsebenzi wamamojula wepharamitha (LPM) ku-a

I-VHDL Design File (.vhd), kufanele usebenzise i

LPM_HINT ipharamitha yokucacisa i-Intel-

ipharamitha ethile. Okwesiboneloample: LPM_HINT

= “CHAIN_SIZE = 8,

ONE_INPUT_IS_CONSTANT = YEBO” The

inani elizenzakalelayo AKUSETSHENZISWA.

LPM_REMAINDERPOSITIVE

Intambo

Cha

Ipharamitha ethize ye-Intel. Kufanele usebenzise i-

LPM_HINT ipharamitha yokucacisa i

LPM_REMAINDERPOSITIVE ipharamitha ku

Umklamo we-VHDL files. Amanani AYIQINISO noma AMANGA.

Uma le pharamitha isethwe ukuze ithi TRUE, khona-ke i

inani lembobo[] esele kumelwe ibe nkulu

waqhubeka...

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 14

Thumela Impendulo

3. LPM_DIVIDE (Isihlukanisi) Intel FPGA IP Core 683490 | 2020.10.05

Igama lepharamitha

Uhlobo

MAXIMIZE_SPEED

Inombolo ephelele

LPM_PIPELINE

Inombolo ephelele

INTENDED_DEVICE_FAMILY SKIP_BITS

I-String Integer

Inombolo edingekayo
Cha Cha Cha

Incazelo
kuno noma okulingana noziro. Uma le pharamitha isethwe ukuze ithi TRUE, inani lembobo[] esele lingaba uziro, noma inani liwuphawu olufanayo, oluphozithivu noma olunegethivu, njengenani lembobo yenombolo. Ukuze kwehliswe indawo futhi kuthuthukiswe isivinini, i-Intel incoma ukusetha le pharamitha kokuthi TRUE emisebenzini lapho okusele kufanele kube phozithivu noma lapho okusele kungabalulekile.
Ipharamitha ethize ye-Intel. Kufanele usebenzise ipharamitha ye-LPM_HINT ukuze ucacise ipharamitha engu-MAXIMIZE_SPEED kumklamo we-VHDL files. Amanani angu-[0..9]. Uma isetshenziswa, isofthiwe ye-Intel Quartus Prime izama ukuthuthukisa isenzakalo esithile somsebenzi we-LPM_DIVIDE ngesivinini kunokusebenziseka, futhi ikhipha ukulungiselelwa kwenketho ye-Optimization Technique logic. Uma i-MAXIMIZE_SPEED ingasetshenziswa, kusetshenziswa inani lenketho ye-Optimization Technique. Uma inani le-MAXIMIZE_SPEED lingu-6 noma ngaphezulu, I-Compiler ithuthukisa i-LPM_DIVIDE IP core ngesivinini esiphezulu ngokusebenzisa amaketango okuthwala; uma inani lingu-5 noma ngaphansi, umhlanganisi usebenzisa umklamo ngaphandle kwamaketanga okuthwala.
Icacisa inani lemijikelezo yewashi yokubambezeleka ehlotshaniswa ne-quotient[] kanye nokusele[] kokuphumayo. Inani likaziro (0) libonisa ukuthi akukho ukubambezeleka okukhona, nokuthi umsebenzi wokuhlanganiswa kuphela uyaqiniswa. Uma ikhishiwe, inani elizenzakalelayo lingu-0 (alinapayipi). Awukwazi ukucacisa inani lepharamitha ye-LPM_PIPELINE ephakeme kune-LPM_WIDTHN.
Le parameter isetshenziselwa izinjongo zokulingisa nokuziphatha. Umhleli wepharamitha ubala inani lale pharamitha.
Ivumela ukwahlukaniswa kwebhithi okusebenza kahle kakhudlwana ukuze kuthuthukiswe ingqondo kumabhithi aholayo ngokunikeza inombolo ye-GND eholayo kumongo we-LPM_DIVIDE we-IP. Cacisa inombolo ye-GND ehamba phambili ekukhishweni kwe-quotient kule pharamitha.

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 15

683490 | 2020.10.05 Thumela Impendulo

4. LPM_MULT (Multiplier) IP Core

Umfanekiso 3.

I-LPM_MULT IP core isebenzisa isiphindaphinda ukuze siphindaphinde amanani edatha yokufaka amabili ukuze kukhiqizwe umkhiqizo njengokuphumayo.

Umfanekiso olandelayo ubonisa izimbobo ze-LPM_MULT IP core.

LPM_Mult Ports

Idatha yewashi ye-LPM_MULT[] umphumela[] idathab[] aclr/sclr clken
inst

Izici Zokwaziswa Okuhlobene ekhasini 71

4.1. Izici
I-LPM_MULT IP core inikeza izici ezilandelayo: · Ikhiqiza isiphindaphinda esiphindaphinda amanani edatha yokufaka amabili · Isekela ububanzi bedatha yamabhithi ayi-1 · Isekela ifomethi yokumelela idatha engasayiniwe nengabhalisiwe · Isekela ukwenziwa ngcono kwendawo noma isivinini · Isekela ukulayishwa kwamapayipi ngokubambezeleka kokuphumayo okulungisekayo · Inikeza inketho yokuqaliswa ekusetshenzisweni kwesignali yedijithali (DSP)
i-block circuitry noma i-logic elements (LEs) Qaphela: Uma wakha iziphindaphinda ezinkulu kunosayizi osekelwe ngokomdabu kungase/
kuzoba nomthelela wokusebenza ovela ekuqhumeni kwamabhulokhi e-DSP. · Isekela okukhethwa kukho okucacile okungavumelaniyo futhi iwashi linika amandla amachweba okokufaka · Isekela ukuvumelanisa okungakhethwa ngokusobala kumadivayisi we-Intel Stratix 10, Intel Arria 10 kanye ne-Intel Cyclone 10 GX

I-ISO 9001:2015 Ibhalisiwe

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05
4.2. I-Verilog HDL Prototype
Lesi sibonelo esilandelayo se-Verilog HDL sitholakala ku-Verilog Design File (.v) lpm.v ku i-edasynthesis directory.
module lpm_mult ( umphumela, idathaa, idathab, isamba, iwashi, clken, aclr ) ipharamitha lpm_type = “lpm_mult”; ipharamitha lpm_widtha = 1; ipharamitha lpm_widthb = 1; ipharamitha lpm_widths = 1; ipharamitha lpm_widthp = 1; ipharamitha lpm_representation = “AKUSAYINWE”; ipharamitha lpm_pipeline = 0; ipharamitha lpm_hint = “OKUNGASETSHENZISWA”; iwashi lokufaka; i-clken yokufaka; okokufaka aclr; okokufaka [lpm_widtha-1:0] idatha; okokufaka [lpm_widthb-1:0] idathab; okokufaka [lpm_widths-1:0] isamba; umphumela [lpm_widthp-1:0]; endmodule
4.3. Isimemezelo Sengxenye Ye-VHDL
Isimemezelo sengxenye ye-VHDL sitholakala ku-VHDL Design File (.vhd) LPM_PACK.vhd ku librariesvhdllpm directory.
ingxenye LPM_MULT generic ( LPM_WIDTHA : natural; LPM_WIDTHB : natural; LPM_WIDTHS : natural := 1; LPM_WIDTHP : natural;
LPM_REPRESENTATION : string := "OKUNGASAYINWE"; LPM_PIPELINE : okwemvelo := 0; LPM_TYPE: iyunithi yezinhlamvu := L_MULT; LPM_HINT : string := "OKUNGASETSHENZISWA"); port ( DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0); IDATHAB : ku std_logic_vector(LPM_WIDTHB-1 downto 0); ACLR : in std_logic := '0'; CLOCK : in std_logic := '0: logic'; CLOCK := '1'; I-SUM : ku-std_logic_vector(LPM_WIDTHS-1 kwehle ku-0) := (OTHERS => '0'); Umphumela : kuphume std_logic_vector(LPM_WIDTHP-1 phansi kokuthi 0)); ingxenye yokugcina;
4.4. I-VHDL LIBRARY_USE Isimemezelo
Isimemezelo se-VHDL LIBRARY-USE asidingeki uma usebenzisa Isimemezelo Sengxenye Ye-VHDL.
I-LIBRARY lpm; SEBENZISA i-lpm.lpm_components.all;

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 17

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

4.5. Amasignali

Ithebula 7.

Izimpawu Zokufaka ze-LPM_MULT

Igama Lesignali

Kudingeka

Incazelo

idatha[]

Yebo

Okokufaka kwedatha.

Kumadivayisi e-Intel Stratix 10, Intel Arria 10, kanye ne-Intel Cyclone 10 GX, usayizi wesiginali yokufaka uncike enanini lepharamitha yobubanzi be-Dataa.

Kumadivayisi amadala ne-Intel Cyclone 10 LP, usayizi wesiginali yokufaka uncike enanini lepharamitha ye-LPM_WIDTHA.

idathab[]

Yebo

Okokufaka kwedatha.

Kumadivayisi e-Intel Stratix 10, Intel Arria 10, kanye ne-Intel Cyclone 10 GX, usayizi wesiginali yokufaka uncike enanini lepharamitha yobubanzi be-Datab.

Kumadivayisi amadala ne-Intel Cyclone 10 LP, usayizi wesiginali yokufaka uncike

kunani lepharamitha ye-LPM_WIDTHB.

iwashi

Cha

Okokufaka kwewashi ukuze kusetshenziswe amapayipi.

Kumadivayisi amadala ne-Intel Cyclone 10 LP, isignali yewashi kufanele inikwe amandla amanani e-LPM_PIPELINE ngaphandle kuka-0 (okuzenzakalelayo).

Kumadivayisi e-Intel Stratix 10, Intel Arria 10, kanye ne-Intel Cyclone 10 GX, isignali yewashi kufanele inikwe amandla uma inani le-Latency lingaphandle kuka-1 (okuzenzakalelayo).

klekani

Cha

Iwashi livumela ukusetshenziswa kwamapayipi. Lapho isignali ye-clken igonyelwa phezulu, i

ukusebenza kwe-adder/subtractor kuyenzeka. Uma isignali iphansi, akukho msebenzi

kwenzeka. Uma ikhishiwe, inani elizenzakalelayo lingu-1.

aclr scl

Cha

Isiginali ecacile ehambisanayo esetshenziswa nganoma yisiphi isikhathi ukusetha kabusha ipayipi kuwo wonke ama-0s,

ngokuhambisana nesignali yewashi. Ipayipi liqalisa kokungachazwanga (X)

izinga le-logic. Okuphumayo kuyinani elingaguquki, kodwa alilona uziro.

Cha

Isignali ecacile ehambisanayo esetshenziswa noma nini ukusetha kabusha ipayipi kuwo wonke ama-0s,

ngokuhambisana nesignali yewashi. Ipayipi liqalisa kokungachazwanga (X)

izinga le-logic. Okuphumayo kuyinani elingaguquki, kodwa alilona uziro.

Ithebula 8.

LPM_MULT Amasignali okukhiphayo

isignali Igama

Kudingeka

Incazelo

umphumela[]

Yebo

Okukhipha idatha.

Kumadivayisi amadala ne-Intel Cyclone 10 LP, usayizi wesiginali yokukhiphayo uncike enanini lepharamitha ye-LPM_WITDHP. Uma i-LPM_WIDTHP < ubuningi (LPM_WIDTHA + LPM_WIDTHB, LPM_WIDTHS) noma (LPM_WIDTHA + LPM_WIDTHS), kuphela ama-MSB e-LPM_WIDTHP akhona.

Ku-Intel Stratix 10, Intel Arria 10 ne-Intel Cyclone 10 GX, usayizi wamasiginali okukhiphayo uncike kupharamitha yobubanzi bomphumela.

4.6. Amapharamitha we-Stratix V, i-Arria V, i-Cyclone V, ne-Intel Cyclone 10 LP Devices

4.6.1. Ithebhu Ejwayelekile

Ithebula 9.

Ithebhu evamile

Ipharamitha

Inani

Ukucushwa Kweziphindaphinda

Phindaphinda ukufakwa kwe-'data' ngokufaka kwe-'datab'

Inani elizenzakalelayo

Incazelo

Phindaphinda ukufakwa kwe-'data' ngokufaka kwe-'datab'

Khetha ukucushwa okufunayo kwesiphindaphinda.
waqhubeka...

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 18

Thumela Impendulo

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

Ipharamitha
Ingabe okokufaka 'kwedatha' kufanele kube ububanzi obungakanani? Ingabe okokufaka 'kwedatha' kufanele kube ububanzi obungakanani? Kufanele bunqunywe kanjani ububanzi bomphumela 'womphumela'? Khawulela ububanzi

Inani
Phindaphinda ufake 'idatha' ngokwayo (ukusebenza kwe-squaring)
1 - 256 amabhithi

Inani elizenzakalelayo

Incazelo

8 amabhithi

Cacisa ububanzi bembobo yedatha[].

1 - 256 amabhithi

8 amabhithi

Cacisa ububanzi bembobo yedathab[].

Bala ngokuzenzakalelayo ububanzi Khawulela ububanzi
1 - 512 amabhithi

Ngokuzenzakalelayo y bala ububanzi

Khetha indlela oyifunayo ukuze unqume ububanzi bembobo yomphumela[].

16 amabhithi

Cacisa ububanzi bomphumela[] imbobo.
Leli nani lizosebenza kuphela uma ukhetha okuthi Khawulela ububanzi kupharamitha Yohlobo.

4.6.2. Okujwayelekile 2 Ithebhu

Ithebula 10. Okujwayelekile 2 Ithebhu

Ipharamitha

Inani

Okokufaka Kwedatha

Ingabe ibhasi le-'datab' linenani elingaguquki?

Cha Yebo

Uhlobo Lokuphindaphinda

Iluphi uhlobo

Akusayiniwe

uyafuna ukuphindaphinda? Isayiniwe

Ukuqaliswa

Yikuphi ukuqaliswa kokuphindaphinda okufanele kusetshenziswe?

Sebenzisa ukufakwa okuzenzakalelayo
Sebenzisa i-multiplier circuitry (Ayitholakali kuyo yonke imindeni)
Sebenzisa izinto ezinengqondo

Inani elizenzakalelayo

Incazelo

Cha

Khetha Yebo ukuze ucacise inani elingaguquki le-

`datab' ibhasi lokufaka, uma likhona.

Akusayiniwe

Cacisa ifomethi yokumelela kwakho kokubili okokufaka kwedatha[] kanye nedathab[].

Sebenzisa i-ion yokuqalisa ezenzakalelayo

Khetha indlela oyifunayo ukuze unqume ububanzi bembobo yomphumela[].

4.6.3. Ithebhu yokufaka amapayipi

Ithebula 11. Ithebhu yokufaka amapayipi

Ipharamitha

Ingabe ufuna ukufaka iphayiphi i-No

umsebenzi?

Yebo

Inani

Dala i-'aclr'

—

imbobo ecacile engavumelanisiwe

Inani elizenzakalelayo

Incazelo

Cha

Khetha Yebo ukuze unike amandla irejista yamapayipi ku-

okukhiphayo kokuphindaphinda futhi ucacise okufunayo

ukubambezeleka kokuphuma kumjikelezo wewashi. Ivumela i-

irejista yepayipi yengeza ukubambezeleka okwengeziwe ku

okukhiphayo.

Akuhloliwe

Khetha le nketho ukuze unike amandla imbobo ye-aclr ukusebenzisa i-asynchronous clear kurejista yamapayipi.
waqhubeka...

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 19

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

Ipharamitha
Dala iwashi le-'clken' elinika amandla iwashi
Ukuthuthukisa
Iluphi uhlobo lokuthuthukisa olufunayo?

Inani -
Indawo Yesivinini Esizenzakalelayo

Inani elizenzakalelayo

Incazelo

Akuhloliwe

Icacisa amandla ewashi aphezulu asebenzayo embobeni yewashi yerejista yamapayipi

Okuzenzakalelayo

Cacisa ukulungiselelwa okufunayo kwe-IP core.
Khetha Okuzenzakalelayo ukuze uvumele isofthiwe ye-Intel Quartus Prime ukuthi inqume ukulungiselelwa okungcono kakhulu kwe-IP core.

4.7. Amapharamitha we-Intel Stratix 10, Intel Arria 10, kanye ne-Intel Cyclone 10 GX Devices

4.7.1. Ithebhu Ejwayelekile

Ithebula 12. Ithebhu evamile

Ipharamitha

Inani

Inani elizenzakalelayo

Incazelo

Uhlobo Lokucushwa Kweziphindaphinda
Ububanzi Bembobo Yedatha

Phindaphinda ukufakwa kwe-'data' ngokufaka kwe-'datab'
Phindaphinda ufake 'idatha' ngokwayo (ukusebenza kwe-squaring)

Phindaphinda ukufakwa kwe-'data' ngokufaka kwe-'datab'

Khetha ukucushwa okufunayo kwesiphindaphinda.

Ububanzi bedatha

1 - 256 amabhithi

8 amabhithi

Cacisa ububanzi bembobo yedatha[].

Ububanzi bedatha

1 - 256 amabhithi

8 amabhithi

Cacisa ububanzi bembobo yedathab[].

Kufanele bunqunywe kanjani ububanzi bomphumela 'womphumela'?

Uhlobo

Bala ububanzi ngokuzenzakalelayo
Khawulela ububanzi

Ngokuzenzakalelayo y bala ububanzi

Khetha indlela oyifunayo ukuze unqume ububanzi bembobo yomphumela[].

Inani

1 - 512 amabhithi

16 amabhithi

Cacisa ububanzi bomphumela[] imbobo.
Leli nani lizosebenza kuphela uma ukhetha okuthi Khawulela ububanzi kupharamitha Yohlobo.

Ububanzi bomphumela

1 - 512 amabhithi

—

Ibonisa ububanzi obusebenzayo bembobo yomphumela[].

4.7.2. Okujwayelekile 2 Ithebhu

Ithebula 13. Okujwayelekile 2 Ithebhu

Ipharamitha

Okokufaka Kwedatha

Ingabe ibhasi le-'datab' linenani elingaguquki?

Cha Yebo

Inani

Inani elizenzakalelayo

Incazelo

Cha

Khetha Yebo ukuze ucacise inani elingaguquki le-

`datab' ibhasi lokufaka, uma likhona.

waqhubeka...

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 20

Thumela Impendulo

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

Ipharamitha

Inani

Noma yiliphi inani elikhulu kuno-0

Uhlobo Lokuphindaphinda

Iluphi uhlobo

Akusayiniwe

uyafuna ukuphindaphinda? Isayiniwe

Isitayela Sokusebenzisa

Yikuphi ukuqaliswa kokuphindaphinda okufanele kusetshenziswe?

Sebenzisa ukufakwa okuzenzakalelayo
Sebenzisa i-multiplier circuitry ezinikele
Sebenzisa izinto ezinengqondo

Inani elizenzakalelayo

Incazelo

Cacisa inani elingaguquki lembobo yedathab[].

Akusayiniwe

Cacisa ifomethi yokumelela kwakho kokubili okokufaka kwedatha[] kanye nedathab[].

Sebenzisa i-ion yokuqalisa ezenzakalelayo

Khetha indlela oyifunayo ukuze unqume ububanzi bembobo yomphumela[].

4.7.3. Ukufakwa kwamapayipi

Ithebula 14. Ithebhu yokufaka amapayipi

Ipharamitha

Inani

Ingabe ufuna ukuphayiphisa umsebenzi?

Ipayipi

Cha Yebo

Uhlobo Lwesiginali Olucacile Ukubambezeleka

Noma yiliphi inani elikhulu kuno-0.
AKUKHO ACLR SCLR

Dala iwashi 'clken'

—

vumela iwashi

Iluphi uhlobo lokuthuthukisa olufunayo?

Uhlobo

Indawo Yesivinini Esizenzakalelayo

Inani elizenzakalelayo

Incazelo

Cha 1 AKEKHO
—

Khetha Yebo ukuze unike amandla irejista yamapayipi ekuphumeni komphindi. Ukunika amandla irejista yamapayipi kungeza ukubambezeleka okwengeziwe kokuphumayo.
Cacisa ukubambezeleka okukhiphayo okufunayo kumjikelezo wewashi.
Cacisa uhlobo lokusetha kabusha irejista yamapayipi. Khetha LUTHO uma ungasebenzisi noma iyiphi irejista yamapayipi. Khetha i-ACLR ukuze usebenzise i-asynchronous clear kurejista yamapayipi. Lokhu kuzokhiqiza imbobo ye-ACLR. Khetha i-SCLR ukuze usebenzise i-synchronous clear kurejista yamapayipi. Lokhu kuzokhiqiza imbobo ye-SCLR.
Icacisa amandla ewashi aphezulu asebenzayo embobeni yewashi yerejista yamapayipi

Okuzenzakalelayo

Cacisa ukulungiselelwa okufunayo kwe-IP core.
Khetha Okuzenzakalelayo ukuze uvumele isofthiwe ye-Intel Quartus Prime ukuthi inqume ukulungiselelwa okungcono kakhulu kwe-IP core.

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 21

683490 | 2020.10.05 Thumela Impendulo

5. LPM_ADD_SUB (I-Adder/Subtractor)

Umfanekiso 4.

I-LPM_ADD_SUB IP core ikuvumela ukuthi usebenzise i-adder noma i-subtractor ukuze wengeze noma ukhiphe amasethi edatha ukuze ukhiqize okukhiphayo okuqukethe isamba noma umehluko wamanani okokufaka.

Umfanekiso olandelayo ubonisa izimbobo ze-LPM_ADD_SUB IP core.

LPM_ADD_SUB Izimbobo

LPM_ADD_SUB add_sub cin

idatha[]

iwashi clken datab[] aclr

umphumela[] wokuchichima kokuphuma

inst

5.1. Izici
I-LPM_ADD_SUB IP core inikeza izici ezilandelayo: · Ikhiqiza i-adder, subtractor, kanye ne-adder/subtractor elungisekayo
imisebenzi. · Isekela ububanzi bedatha yamabhithi ayi-1. · Isekela ifomethi yokumelwa kwedatha njengokusayinwa nokungasayiniwe. · Isekela ozikhethela ukuthwala (borrow-out), asynchronous ecacile, futhi iwashi ukunika amandla
izimbobo zokufaka. · Isekela ukuphuma kokuzithandela (ukuboleka) kanye namachweba okukhiphayo okuchichimayo. · Inikeza noma elinye lamabhasi edatha okokufaka njalo. · Isekela ukufakwa kwamapayipi ngokulibaziseka kokuphumayo okulungisekayo.

I-ISO 9001:2015 Ibhalisiwe

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05
5.2. I-Verilog HDL Prototype
Lesi sibonelo esilandelayo se-Verilog HDL sitholakala ku-Verilog Design File (.v) lpm.v ku i-edasynthesis directory.
module lpm_add_sub ( umphumela, cout, ukuchichima, add_sub, cin, dataa, datab, clock, clken, aclr ); ipharamitha lpm_type = “lpm_add_sub”; ipharamitha lpm_width = 1; ipharamitha lpm_direction = “OKUNGASETSHENZISWA”; ipharamitha lpm_representation = “SAYINWE”; ipharamitha lpm_pipeline = 0; ipharamitha lpm_hint = “OKUNGASETSHENZISWA”; okokufaka [lpm_width-1:0] idatha, idathab; okokufaka add_sub, cin; iwashi lokufaka; i-clken yokufaka; okokufaka aclr; umphumela [lpm_width-1:0]; ukuphuma kokukhishwa, ukuchichima; endmodule
5.3. Isimemezelo Sengxenye Ye-VHDL
Isimemezelo sengxenye ye-VHDL sitholakala ku-VHDL Design File (.vhd) LPM_PACK.vhd ku librariesvhdllpm directory.
ingxenye LPM_ADD_SUB generic (LPM_WIDTH : yemvelo;
LPM_DIRECTION : string := "OKUNGASETSHENZISWA"; LPM_REPRESENTATION: iyunithi yezinhlamvu := “ISAYINIWE”; LPM_PIPELINE : okwemvelo := 0; LPM_TYPE : string := L_ADD_SUB; LPM_HINT : string := "OKUNGASETSHENZISWA"); port (IDATAA : ku-std_logic_vector(LPM_WIDTH-1 downto 0); IDATHAB : ku-std_logic_vector(LPM_WIDTH-1 downto 0); ACLR : ku-std_logic := '0'; IWASHI : ku-std_logic := '0' ku-CLK_logic ku-CLK_logic; := '1'; CIN : in std_logic := 'Z'; ADD_SUB : in std_logic := '1'; Umphumela : out std_logic_vector(LPM_WIDTH-1 downto 0); COUT : out std_logic; PHUMELA : out std_logic); ingxenye yokugcina;
5.4. I-VHDL LIBRARY_USE Isimemezelo
Isimemezelo se-VHDL LIBRARY-USE asidingeki uma usebenzisa Isimemezelo Sengxenye Ye-VHDL.
I-LIBRARY lpm; SEBENZISA i-lpm.lpm_components.all;
5.5. Amachweba
Amathebula alandelayo aklelisa okokufaka nezimbobo ze-LPM_ADD_SUB IP core.

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 23

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05

Ithebula 15. LPM_ADD_SUB IP Core Input Ports

Igama Lembobo

Kudingeka

Incazelo

cin

Cha

Ngena ku-bit ye-oda eliphansi. Ngemisebenzi yokwengeza, inani elimisiwe ngu-0. For

imisebenzi yokukhipha, inani elizenzakalelayo ngu-1.

idatha[]

Yebo

Okokufaka kwedatha. Usayizi wembobo yokufaka uncike enanini lepharamitha ye-LPM_WIDTH.

idathab[]

Yebo

Okokufaka kwedatha. Usayizi wembobo yokufaka uncike enanini lepharamitha ye-LPM_WIDTH.

add_sub

Cha

Imbobo yokufaka yokuzikhethela ukuze unike amandla ukushintsha okuguquguqukayo phakathi kwe-adder ne-subtractor

imisebenzi. Uma ipharamitha ye-LPM_DIRECTION isetshenziswa, i-add_sub ayikwazi ukusetshenziswa. Uma

kukhishiwe, inani elizenzakalelayo lithi ADD. I-Intel incoma ukuthi usebenzise i-

Ipharamitha ye-LPM_DIRECTION yokucacisa ukusebenza komsebenzi we-LPM_ADD_SUB,

esikhundleni sokunikeza okungaguquki embobeni ye-add_sub.

iwashi

Cha

Okokufaka ukuze kusetshenziswe amapayipi. Imbobo yewashi inikeza okokufaka kwewashi kwepayipi

ukusebenza. Kumanani e-LPM_PIPELINE ngaphandle kuka-0 (okuzenzakalelayo), imbobo yewashi kufanele ibe

inikwe amandla.

klekani

Cha

Iwashi livumela ukusetshenziswa kwamapayipi. Lapho ichweba le-clken lithi liphakeme, i-adder/

ukusebenza kwe-subtractor kuyenzeka. Uma isignali iphansi, akukho msebenzi owenzekayo. Uma

isusiwe, inani elizenzakalelayo ngu-1.

aclr

Cha

Asynchronous clear ukuze isetshenziswe ngamapayipi. Ipayipi liqalisa kokungachazwanga (X)

izinga le-logic. Imbobo ye-aclr ingasetshenziswa nganoma yisiphi isikhathi ukusetha kabusha ipayipi kuwo wonke ama-0s,

ngokuhambisana nesignali yewashi.

Ithebula 16. LPM_ADD_SUB IP Core Output Ports

Igama Lembobo

Kudingeka

Incazelo

umphumela[]

Yebo

Okukhipha idatha. Usayizi wembobo yokuphumayo uncike kupharamitha ye-LPM_WIDTH

inani.

i-cout

Cha

Ukukhipha (ukuboleka) kwebhithi ebaluleke kakhulu (MSB). Imbobo ye-cout inomzimba

Ukutolika njengokwenziwa (ukuboleka) kwe-MSB. Imbobo ye-cout iyathola

ukuchichima emisebenzini ENGATHIWE. I-out port isebenza ngendlela efanayo

Imisebenzi ESAYINWE futhi AYISAYINWE.

phuphuma

Cha

Okukhiphayo ongakukhetha kokuchichimayo. Imbobo echichimayo inokuhumusha ngokomzimba njenge

i-XOR yokuyisa ku-MSB ngokukhipha i-MSB. Imbobo yokuchichima

igomela lapho imiphumela yeqa ukunemba okutholakalayo, futhi isetshenziswa kuphela uma i-

LPM_REPRESENTATION inani lepharamitha SIGNED.

5.6. Amapharamitha

Ithebula elilandelayo libala amapharamitha angumongo we-LPM_ADD_SUB.

Ithebula 17. LPM_ADD_SUB IP Core Parameters

Igama lepharamitha LPM_WIDTH

Thayipha inombolo ephelele

Kudingeka Yebo

Incazelo
Icacisa ububanzi bedatha[], idathab[], nezimbobo zomphumela[].

LPM_DIRECTION

Intambo

Cha

Amanani ADD, SUB, kanye OKUNGASETSHENZISIWE. Uma ikhishiwe, inani elizenzakalelayo lithi DEFAULT, eliqondisa ipharamitha ukuthi ithathe inani layo ku-add_sub port. Imbobo ye-add_sub ayikwazi ukusetshenziswa uma i-LPM_DIRECTION isetshenziswa. I-Intel incoma ukuthi usebenzise ipharamitha ye-LPM_DIRECTION ukuze ucacise ukusebenza komsebenzi we-LPM_ADD_SUB, kunokuba unikeze okungaguquki embobeni ye-add_sub.
waqhubeka...

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 24

Thumela Impendulo

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05

Igama lepharamitha LPM_REPRESENTATION LPM_PIPELINE LPM_HINT LPM_TYPE ONE_INPUT_IS_CONSTANT MAXIMIZE_SPEED
INTENDED_DEVICE_FAMILY

Thayipha I-String Integer String String Integer
Intambo

Iyadingeka Cha Cha Cha Cha Cha Cha Cha
Cha

Incazelo
Icacisa uhlobo lokwengeza okwenziwe. Amanani ESAYINWE futhi AKASAYINWE. Uma likhishiwe, inani elizenzakalelayo LISAYINWE. Uma le pharamitha isethelwe KUSAYINWE, i-adder/i-subtractor ihumusha okokufaka kwedatha njengokuphelelisa okubili okusayiniwe.
Icacisa inani lemijikelezo yewashi lewashi elihambisana nomphumela[] ophumayo. Inani likaziro (0) libonisa ukuthi akukho ukubambezeleka okukhona, nokuthi umsebenzi wokuhlanganiswa kuphela uzoqiniswa. Uma ikhishiwe, inani elizenzakalelayo ngu-0 (alipayipi).
Ikuvumela ukuthi ucacise amapharamitha aqondene ne-Intel ekwakhiweni kwe-VHDL files (.vhd). Inani elizenzakalelayo AKUSETSHENZISWA.
Ihlonza igama lebhizinisi lebhizinisi lamamojula we-parameterized (LPM) emtatsheni we-VHDL files.
Ipharamitha ethize ye-Intel. Kufanele usebenzise ipharamitha ye-LPM_HINT ukuze ucacise ipharamitha ye-ONE_INPUT_IS_CONSTANT kumklamo we-VHDL files. Amanani athi YEBO, CHA, futhi AKASETSHENZISWA. Inikeza ukulungiselelwa okukhulu uma okokufaka okukodwa kungashintshi. Uma ikhishiwe, inani elizenzakalelayo lithi CHA.
Ipharamitha ethize ye-Intel. Kufanele usebenzise ipharamitha ye-LPM_HINT ukuze ucacise ipharamitha engu-MAXIMIZE_SPEED kumklamo we-VHDL files. Ungacacisa inani eliphakathi kuka-0 no-10. Uma isetshenziswa, isofthiwe ye-Intel Quartus Prime izama ukuthuthukisa isenzakalo esithile somsebenzi we-LPM_ADD_SUB ukuze uthole isivinini esikhundleni sokusebenziseka, futhi ikhipha ukulungiselelwa kwenketho ye-Optimization Technique. Uma i-MAXIMIZE_SPEED ingasetshenziswa, kusetshenziswa inani lenketho ye-Optimization Technique. Uma isilungiselelo se-MAXIMIZE_SPEED siyi-6 noma ngaphezulu, I-Compiler ithuthukisa i-LPM_ADD_SUB IP core ngesivinini esiphezulu isebenzisa amaketango okuthwala; uma isilungiselelo singu-5 noma ngaphansi, i-Compiler isebenzisa umklamo ngaphandle kwamaketanga okuthwala. Le pharamitha kufanele icaciswe kumadivayisi e-Cyclone, Stratix, ne-Stratix GX kuphela uma imbobo ye-add_sub ingasetshenziswa.
Le parameter isetshenziselwa izinjongo zokulingisa nokuziphatha. Umhleli wepharamitha ubala inani lale pharamitha.

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 25

683490 | 2020.10.05 Thumela Impendulo

6. LPM_COMPARE (Isiqhathanisi)

Umfanekiso 5.

I-LPM_COMPARE IP core iqhathanisa inani lamasethi amabili edatha ukuze kunqunywe ubudlelwano phakathi kwawo. Ngendlela yayo elula, ungasebenzisa isango elingu-NOMA elikhethekile ukuze unqume ukuthi izingcezu ezimbili zedatha ziyalingana yini.

Isibalo esilandelayo sibonisa izimbobo ze-LPM_COMPARE IP core.

LPM_COMPARE Izimbobo

LPM_COMPARE

klekani

alb

aeb

idatha[]

agb

idathab[]

iminyakab

iwashi

aneb

aclr

aleb

inst

6.1. Izici
I-LPM_COMPARE IP core inikeza izici ezilandelayo: · Ikhiqiza umsebenzi wokuqhathanisa ukuze uqhathanise amasethi amabili edatha · Isekela ububanzi bedatha obungamabhithi ayi-1 · Isekela ifomethi yokumelela idatha njengokusayinwa nokungasayiniwe · Ikhiqiza izinhlobo ezilandelayo zokuphuma:
— i-alb (okufakwayo A kungaphansi kunokokufaka B) — aeb (okufakiwe A kulingana nokokufaka B) — agb (okufakiwe A kukhulu kunokokufaka B) — i-ageb (okufakwayo A kukhulu noma kulingana nokokufaka B) — aneb ( okokufaka A akulingani nokufakwayo B) — i-aleb (okufakwayo A kungaphansi noma kulingana nokokufaka B) · Isekela ukuzikhethela okucacile okuvumelanayo futhi iwashi livumela izimbobo zokufakwayo · Inikeza okokufaka kwedathab[] kokungaguquki · Isekela ukubhobhoza kwamapayipi ngokubambezeleka kokuphumayo okulungisekayo

I-ISO 9001:2015 Ibhalisiwe

6. LPM_COMPARE (Isiqhathanisi) 683490 | 2020.10.05
6.2. I-Verilog HDL Prototype
Lesi sibonelo esilandelayo se-Verilog HDL sitholakala ku-Verilog Design File (.v) lpm.v ku i-edasynthesis directory.
imojuli lpm_compare ( alb, aeb, agb, aleb, aneb, ageb, dataa, datab, clock, clken, aclr ); ipharamitha lpm_type = “lpm_compare”; ipharamitha lpm_width = 1; ipharamitha lpm_representation = “AKUSAYINWE”; ipharamitha lpm_pipeline = 0; ipharamitha lpm_hint = “OKUNGASETSHENZISWA”; okokufaka [lpm_width-1:0] idatha, idathab; iwashi lokufaka; i-clken yokufaka; okokufaka aclr; okukhiphayo alb, aeb, agb, aleb, aneb, ageb; endmodule
6.3. Isimemezelo Sengxenye Ye-VHDL
Isimemezelo sengxenye ye-VHDL sitholakala ku-VHDL Design File (.vhd) LPM_PACK.vhd ku librariesvhdllpm directory.
ingxenye LPM_COMPARE ejwayelekile (LPM_WIDTH : yemvelo;
LPM_REPRESENTATION : string := "OKUNGASAYINWE"; LPM_PIPELINE : okwemvelo := 0; LPM_TYPE: iyunithi yezinhlamvu := L_COMPARE; LPM_HINT : string := "OKUNGASETSHENZISWA"); port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0); IDATHAB : ku-std_logic_vector(LPM_WIDTH-1 downto 0); ACLR : in std_logic := '0'; IWASHI : ku-std_logic := '0' ku-CLK_logic ku-CLD_logic; := '1'; AGB : out std_logic; AGEB : out std_logic; AEB : out std_logic; ANEB : out std_logic; ALB : out std_logic; ALEB : out std_logic); ingxenye yokugcina;
6.4. I-VHDL LIBRARY_USE Isimemezelo
Isimemezelo se-VHDL LIBRARY-USE asidingeki uma usebenzisa Isimemezelo Sengxenye Ye-VHDL.
I-LIBRARY lpm; SEBENZISA i-lpm.lpm_components.all;
6.5. Amachweba
Amathebula alandelayo aklelisa okokufaka nokuphumayo kwe-LMP_COMPARE IP core.

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 27

6. LPM_COMPARE (Isiqhathanisi) 683490 | 2020.10.05

Ithebula 18. LPM_COMPARE IP core Input Ports

Igama Lembobo

Kudingeka

Incazelo

idatha[]

Yebo

Okokufaka kwedatha. Usayizi wembobo yokufaka uncike enanini lepharamitha ye-LPM_WIDTH.

idathab[]

Yebo

Okokufaka kwedatha. Usayizi wembobo yokufaka uncike enanini lepharamitha ye-LPM_WIDTH.

iwashi

Cha

Okokufaka kwewashi ukuze kusetshenziswe amapayipi. Imbobo yewashi inikeza okokufaka kwewashi kwepayipi

ukusebenza. Kumanani e-LPM_PIPELINE ngaphandle kuka-0 (okuzenzakalelayo), imbobo yewashi kufanele ibe

inikwe amandla.

klekani

Cha

Iwashi livumela ukusetshenziswa kwamapayipi. Lapho i-clken port igonyelwa phezulu, i

umsebenzi wokuqhathanisa uyenzeka. Uma isignali iphansi, akukho msebenzi owenzekayo. Uma

isusiwe, inani elizenzakalelayo ngu-1.

aclr

Cha

Asynchronous clear ukuze isetshenziswe ngamapayipi. Ipayipi liqalisa kungqondongqondo engachazwanga (X).

izinga. Imbobo ye-aclr ingasetshenziswa nganoma yisiphi isikhathi ukusetha kabusha ipayipi kuwo wonke ama-0s,

ngokuhambisana nesignali yewashi.

Ithebula 19. LPM_COMPARE IP core Output Ports

Igama Lembobo

Kudingeka

Incazelo

alb

Cha

Imbobo yokuphuma yesiqhanisi. Kuyagonyelwa uma okokufaka A kungaphansi kunokokufaka B.

aeb

Cha

Imbobo yokuphuma yesiqhanisi. Kuyagonyelwa uma okokufaka A kulingana nokokufaka B.

agb

Cha

Imbobo yokuphuma yesiqhanisi. Kuyagonyelwa uma okokufaka A kukhulu kunokokufaka B.

iminyakab

Cha

Imbobo yokuphuma yesiqhanisi. Kuyagonyelwa uma okokufaka A kukukhulu noma kulingana nokokufaka

aneb

Cha

Imbobo yokuphuma yesiqhanisi. Kuyagonyelwa uma okokufaka A kungalingani nokokufaka B.

aleb

Cha

Imbobo yokuphuma yesiqhanisi. Kuyagonyelwa uma okokufaka A kungaphansi noma kulingana nokokufaka B.

6.6. Amapharamitha

Ithebula elilandelayo libala imingcele ye-LPM_COMPARE IP core.

Ithebula 20. LPM_COMPARE IP core Parameters

Igama lepharamitha

Uhlobo

Kudingeka

LPM_WIDTH

Inombolo ephelele Yebo

LPM_REPRESENTATION

Intambo

Cha

LPM_PIPELINE

Inombolo ephelele

LPM_HINT

Intambo

Cha

Incazelo
Icacisa ububanzi bedathaa[] nezimbobo zedathab[].
Icacisa uhlobo lokuqhathanisa okwenziwe. Amanani ESAYINWE futhi AKASAYINWE. Uma likhishiwe, inani elizenzakalelayo AKUSAYINWE. Uma leli nani lepharamitha lisethelwe KUSAYINWE, isiqhathanisi sitolika okokufaka kwedatha njengokuphelelisa okubili okusayiniwe.
Icacisa inombolo yemijikelezo yewashi yokubambezeleka ehlotshaniswa ne-alb, i-aeb, i-agb, i-ageb, i-aleb, noma i-aneb okukhiphayo. Inani likaziro (0) libonisa ukuthi akukho ukubambezeleka okukhona, nokuthi umsebenzi wokuhlanganiswa kuphela uzoqiniswa. Uma ikhishiwe, inani elizenzakalelayo lingu-0 (alinapayipi).
Ikuvumela ukuthi ucacise amapharamitha aqondene ne-Intel ekwakhiweni kwe-VHDL files (.vhd). Inani elizenzakalelayo AKUSETSHENZISWA.
waqhubeka...

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 28

Thumela Impendulo

6. LPM_COMPARE (Isiqhathanisi) 683490 | 2020.10.05
Igama lepharamitha LPM_TYPE INTENDED_DEVICE_FAMILY
ONE_INPUT_IS_CONSTANT

Thayipha Intambo Yezintambo
Intambo

Inombolo edingekayo
Cha

Incazelo
Ihlonza igama lebhizinisi lebhizinisi lamamojula we-parameterized (LPM) emtatsheni we-VHDL files.
Le parameter isetshenziselwa izinjongo zokulingisa nokuziphatha. Umhleli wepharamitha ubala inani lale pharamitha.
Ipharamitha ethize ye-Intel. Kufanele usebenzise ipharamitha ye-LPM_HINT ukuze ucacise ipharamitha ye-ONE_INPUT_IS_CONSTANT kumklamo we-VHDL files. Amanani athi YEBO, CHA, noma OKUNGASETSHENZISIWE. Inikeza ukulungiselelwa okukhulu uma okokufaka kungashintshi. Uma ikhishiwe, inani elizenzakalelayo lithi CHA.

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 29

683490 | 2020.10.05 Thumela Impendulo

7. I-ALTECC (Ikhodi Yokulungisa Iphutha: Isifaki khodi/Isikhiphi) I-IP Core

Umfanekiso 6.

I-Intel inikeza i-ALTECC IP core ukuze iqalise ukusebenza kwe-ECC. I-ECC ithola idatha eyonakele eyenzeka ngasohlangothini lomamukeli phakathi nokudluliswa kwedatha. Le ndlela yokulungisa iphutha ifaneleka kakhulu ezimweni lapho amaphutha enzeke ngokungahleliwe kunokuqhuma.

I-ECC ithola amaphutha ngenqubo yokufaka ikhodi nokuqopha idatha. Okwesiboneloample, lapho i-ECC isetshenziswa kuhlelo lokusebenza lokudlulisela, idatha efundwa kumthombo ibhalwa ngekhodi ngaphambi kokuthunyelwa kumamukeli. Okukhiphayo (igama lekhodi) elisuka kusifaki khodi liqukethe idatha eluhlaza exhunywe nenani lamabhithi okulingana. Inani eliqondile lamabhithi okulingana afakiwe lincike enanini lamabhithi edatha yokufaka. Igama lekhodi elakhiwe libe selidluliselwa endaweni okuyiwa kuyo.

Umamukeli uthola igama lekhodi futhi alihlukanise. Ulwazi olutholwe yi-decoder lunquma ukuthi iphutha litholakele yini. Idekhoda ithola amaphutha ebhithi eyodwa kanye ne-double-bit, kodwa ingalungisa kuphela amaphutha ebhithi eyodwa kudatha eyonakele. Lolu hlobo lwe-ECC wukuthola iphutha elilodwa lokulungiswa kwephutha eliphindwe kabili (SECDED).

Ungalungiselela imisebenzi yesifaki khodi neyesikhiphi core ye-ALTECC IP. Okokufaka kwedatha kusifaki khodi kubhalwa ngekhodi ukuze kukhiqizwe igama lekhodi eliyinhlanganisela yokokufaka kwedatha namabhithi okulingana akhiqiziwe. Igama lekhodi elakhiwe lidluliselwa kumojula yesikhiphi sekhodi ukuze kuqoshwe amakhodi ngaphambi nje kokuba ifike endaweni okuyiwa kuyo. Idekhoda ikhiqiza i-syndrome vector ukuze inqume ukuthi likhona yini iphutha egameni lekhodi elamukelwe. Idikhoda ilungisa idatha kuphela uma iphutha lebhithi elilodwa lisuka kumabhithi edatha. Ayikho isignali ehlatshwa umkhosi uma iphutha lebhithi eyodwa lisuka kumabhithi okulingana. Idikhoda futhi inezimpawu zefulegi ukukhombisa isimo sedatha etholiwe kanye nesenzo esithathwe idikhoda, uma sikhona.

Izibalo ezilandelayo zibonisa izimbobo ze-ALTECC IP core.

I-ALTECC Encoder Ports

ALTECC_ENCODER

idatha[]

q[]

iwashi

aclr

inst

I-ISO 9001:2015 Ibhalisiwe

7. I-ALTECC (Ikhodi Yokulungisa Iphutha: Isifaki khodi/Isikhiphi) IP Core 683490 | 2020.10.05

Umfanekiso 7. I-ALTECC Decoder Ports

ALTECC_DECODER

idatha[] iwashi lewashi

q[] iphutha_lithole iphutha_elilungisiwe
iphutha_elibulalayo

aclr

inst

7.1. Izici ze-ALTECC Encoder

I-ALTECC encoder IP core inikeza izici ezilandelayo: · Yenza umbhalo wedatha usebenzisa i-Hamming Coding scheme · Isekela ububanzi bedatha wamabhithi angu-2 · Isekela ifomethi yokumelela idatha engasayiniwe nengasayiniwe · Isekela ukufakwa kwamapayipi ngokubambezeleka kokuphuma komjikelezo wewashi owodwa noma emibili · Isekela ngokuzithandela i-asynchronous clear futhi iwashi linika amandla izimbobo

I-ALTECC encoder IP core ithatha futhi ibhale ngekhodi idatha kusetshenziswa uhlelo lwe-Haming Coding. Uhlelo lwe-Hamming Coding luthola amabhithi okulingana futhi luwahlanganise kudatha yasekuqaleni ukuze kukhiqizwe igama lekhodi yokuphumayo. Inani lamabhithi okulingana afakiwe lincike kububanzi bedatha.

Ithebula elilandelayo libala inani lamabhithi okulingana anezelwe kububanzi obuhlukahlukene bobubanzi bedatha. Ikholomu Yamabhithi Ephelele imelela isamba senani lamabhithi edatha yokufaka namabhithi alinganisiwe angeziwe.

Ithebula 21.

Inombolo yamabhithi okulingana nekhodi yegama ngokuya ngobubanzi bedatha

Ububanzi Bedatha

Inombolo ye-Parity Bits

Isamba samabhithi (Ikhodi yegama)

2-4

3+1

6-8

5-11

4+1

10-16

12-26

5+1

18-32

27-57

6+1

34-64

58-64

7+1

66-72

I-parity bit derivation isebenzisa ukuhlola okulinganayo. Ibhithi engu-1 eyengeziwe (ekhonjiswe kuthebula njengokuthi +1) yengezwe kumabhithi wokulinganisa njenge-MSB yegama lekhodi. Lokhu kuqinisekisa ukuthi igama lekhodi linenombolo elinganayo ka-1's. Okwesiboneloampi-le, uma ububanzi bedatha bungamabhithi angu-4, amabhithi wokulingana angu-4 anezelwa kudatha ukuze abe igama lekhodi elinenani lamabhithi angu-8. Uma amabhithi angu-7 asuka ku-LSB egama lekhodi engu-8 enenombolo eyinqaba ka-1, ibhithi yesi-8 (MSB) yegama lekhodi ingu-1 okwenza inani eliphelele lika-1 egameni lekhodi lilingane.
Isibalo esilandelayo sibonisa igama lekhodi elakhiwe kanye nokuhlelwa kwamabhithi okulingana namabhithi edatha kokokufaka kwedatha engu-8-bit.

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 31

7. I-ALTECC (Ikhodi Yokulungisa Iphutha: Isifaki khodi/Isikhiphi) IP Core 683490 | 2020.10.05

Umfanekiso 8.

I-Parity Bits Ukuhlelwa Kwebhithi Yedatha Ku-8-Bit Yekhodi Ekhiqizwayo Izwi

MSB

I-LSB

4 izingcezu zokulinganisa

4 izingcezu zedatha

I-ALTECC encoder IP core yamukela kuphela ububanzi bokufakwayo kwamabhithi angu-2 ukuya kwangu-64 ngesikhathi esisodwa. Ububanzi bokufaka bamabhithi angu-12, amabhithi angu-29, namabhithi angu-64, afaneleka kahle kumadivayisi e-Intel, akhiqiza imiphumela yamabhithi angu-18, amabhithi angu-36, namabhithi angu-72 ngokulandelana. Ungakwazi ukulawula umkhawulo we-bitselection kusihleli sepharamitha.

7.2. I-Verilog HDL Prototype (ALTECC_ENCODER)
Lesi sibonelo esilandelayo se-Verilog HDL sitholakala ku-Verilog Design File (.v) lpm.v ku i-edasynthesis directory.
module altecc_encoder #( ipharamitha aimed_device_family = “engasetshenzisiwe”, ipharamitha lpm_pipeline = 0, ipharamitha width_codeword = 8, ipharamitha width_dataword = 8, ipharamitha lpm_type = “altecc_encoder”, ipharamitha lpm_hint = “unused wireclr, iwashi lokufaka, i-input input iwashi locingo, intambo yokufaka [width_dataword-1:0] idatha, intambo yokuphumayo [width_codeword-1:0] q); endmodule

7.3. I-Verilog HDL Prototype (ALTECC_DECODER)
Lesi sibonelo esilandelayo se-Verilog HDL sitholakala ku-Verilog Design File (.v) lpm.v ku i-edasynthesis directory.
imojuli altecc_decoder #( ipharamitha target_device_family = “engasetshenzisiwe”, ipharamitha lpm_pipeline = 0, ipharamitha width_codeword = 8, ipharamitha width_dataword = 8, ipharamitha lpm_type = “altecc_decoder”, ipharamitha lpm_hint = “unused wireclr, iwashi lokufaka, iwashi lokufaka iwashi locingo, intambo yokufaka [width_codeword-1:0] idatha, intambo ephumayo err_corrected, outout wire err_detected, outout wire err_fatal, outout wire [width_dataword-1:0] q); endmodule

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 32

Thumela Impendulo

7. I-ALTECC (Ikhodi Yokulungisa Iphutha: Isifaki khodi/Isikhiphi) IP Core 683490 | 2020.10.05
7.4. I-VHDL Component Declaration (ALTECC_ENCODER)
Isimemezelo sengxenye ye-VHDL sitholakala ku-VHDL Design File (.vhd) altera_mf_components.vhd ku librariesvhdlaltera_mf directory.
ingxenye ye-altecc_encoder generic ( target_device_family:string := "engasetshenzisiwe"; lpm_pipeline:natural := 0; width_codeword:natural := 8; width_dataword:natural := 8; lpm_hint:string := "UNUSED":cclpalpte ”); port( aclr:in std_logic := '0'; iwashi:ku-std_logic := '0'; iwashi:ku-std_logic := '1'; idatha:ku-std_logic_vector(width_dataword-1 downto 0); q:out std_logic_vector(width_codeword -1 kwehle kuye ku-0)); ingxenye yokugcina;
7.5. I-VHDL Component Declaration (ALTECC_DECODER)
Isimemezelo sengxenye ye-VHDL sitholakala ku-VHDL Design File (.vhd) altera_mf_components.vhd ku librariesvhdlaltera_mf directory.
ingxenye altecc_decoder generic ( target_device_family:string := "engasetshenziswanga"; lpm_pipeline:natural := 0; width_codeword:natural := 8; width_dataword:natural := 8; lpm_hint:string := "UNUSED":cclpalte" ”); port( aclr:in std_logic := '0'; iwashi:ku-std_logic := '0'; iwashi:ku-std_logic := '1'; idatha:ku-std_logic_vector(width_codeword-1 downto 0); iphutha_lilungisiwe: out std_logic; iphutha_litholakele : out std_logic; q:out std_logic_vector(width_dataword-1 downto 0); syn_e : out std_logic); ingxenye yokugcina;
7.6. I-VHDL LIBRARY_USE Isimemezelo
Isimemezelo se-VHDL LIBRARY-USE asidingeki uma usebenzisa Isimemezelo Sengxenye Ye-VHDL.
I-LIBRARY alter_mf; SEBENZISA i-altera_mf.altera_mf_components.all;
7.7. Izimbobo zesifaki khodi
Amathebula alandelayo aklelisa izimbobo zokufakwayo neziphumayo ze-ALTECC encoder IP core.

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 33

7. I-ALTECC (Ikhodi Yokulungisa Iphutha: Isifaki khodi/Isikhiphi) IP Core 683490 | 2020.10.05

Ithebula 22. Izimbobo Zokufaka Encoder ze-ALTECC

Igama Lembobo

Kudingeka

Incazelo

idatha[]

Yebo

Imbobo yokufaka idatha. Usayizi wembobo yokufaka uncike ku-WIDTH_DATAWORD

inani lepharamitha. Imbobo yedatha[] iqukethe idatha eluhlaza okufanele ibhalwe ngekhodi.

iwashi

Yebo

Imbobo yokufaka iwashi enikeza isignali yewashi ukuvumelanisa umsebenzi wombhalo wekhodi.

Imbobo yewashi iyadingeka uma inani le-LPM_PIPELINE likhulu kuno-0.

iwashi

Cha

Iwashi livula amandla. Uma ikhishiwe, inani elizenzakalelayo lingu-1.

aclr

Cha

Okokufaka okucacile okungahambisani. Isiginali ye-aclr ephezulu esebenzayo ingasetshenziswa noma kunini ukuze

sula amarejista ngokulinganayo.

Ithebula 23. I-ALTECC Encoder Output Ports

Igama Lembobo q[]

Kudingeka Yebo

Incazelo
Imbobo yokukhipha idatha enekhodi. Usayizi wembobo yokukhiphayo uncike enanini lepharamitha engu-WIDTH_CODEWORD.

7.8. I-Decoder Ports

Amathebula alandelayo aklelisa izimbobo zokufaka nokuphumayo ze-ALTECC decoder IP core.

Ithebula 24. I-ALTECC Decoder Ports Input

Igama Lembobo

Kudingeka

Incazelo

idatha[]

Yebo

Imbobo yokufaka idatha. Usayizi wembobo yokufaka uncike enanini lepharamitha engu-WIDTH_CODEWORD.

iwashi

Yebo

Imbobo yokufaka iwashi enikeza isignali yewashi ukuvumelanisa umsebenzi wombhalo wekhodi. Imbobo yewashi iyadingeka uma inani le-LPM_PIPELINE likhulu kuno-0.

iwashi

Cha

Iwashi livula amandla. Uma ikhishiwe, inani elizenzakalelayo lingu-1.

aclr

Cha

Okokufaka okucacile okungahambisani. Isiginali ye-aclr ephezulu esebenzayo ingasetshenziswa noma nini ukusula amarejista ngokulinganayo.

Ithebula 25. I-ALTECC Decoder Output Ports

Igama Lembobo q[]

Kudingeka Yebo

Incazelo
Imbobo yokukhipha idatha eqoshwe ikhodi. Usayizi wembobo yokuphumayo uncike enanini lepharamitha engu-WIDTH_DATAWORD.

iphutha_kutholiwe Yebo

Hlaba umkhosi ukuze ubonise isimo sedatha etholiwe futhi ucacise noma imaphi amaphutha atholiwe.

iphutha_lungisa Yebo d

Hlaba umkhosi ukuze ubonise isimo sedatha etholiwe. Isho iphutha lebhithi elilodwa elitholiwe futhi lalungiswa. Ungasebenzisa idatha ngoba isivele ilungisiwe.

iphutha_elibulalayo

Yebo

Hlaba umkhosi ukuze ubonise isimo sedatha etholiwe. Isho iphutha le-double-bit elitholiwe, kodwa alilungiswanga. Akumele usebenzise idatha uma lesi siginali igonyelwa.

syn_e

Cha

Isignali yokuphumayo ezoya phezulu noma nini lapho kutholwa iphutha lebhithi elilodwa ekulinganeni

izingcezu.

7.9. Amapharamitha wesifaki khodi
Ithebula elilandelayo libala imingcele ye-ALTECC encoder IP core.

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 34

Thumela Impendulo

7. I-ALTECC (Ikhodi Yokulungisa Iphutha: Isifaki khodi/Isikhiphi) IP Core 683490 | 2020.10.05

Ithebula 26. I-ALTECC Encoder Parameters

Igama lepharamitha

Uhlobo

Kudingeka

Incazelo

WIDTH_DATAWORD

Inombolo ephelele Yebo

Icacisa ububanzi bedatha eluhlaza. Amanani asuka ku-2 kuye ku-64. Uma ekhishiwe, inani elimisiwe ngu-8.

WIDTH_CODEWORD

Inombolo ephelele Yebo

Icacisa ububanzi begama lekhodi elihambisanayo. Amanani avumelekile asuka ku-6 kuye ku-72, ngaphandle kuka-9, 17, 33, no-65. Uma ekhishiwe, inani elizenzakalelayo lingu-13.

LPM_PIPELINE

Inombolo ephelele

Icacisa ipayipi lesekhethi. Amanani asuka ku-0 kuye ku-2. Uma inani lingu-0, izimbobo azibhalisiwe. Uma inani lingu-1, izimbobo zokukhiphayo zibhalisiwe. Uma inani lingu-2, izimbobo zokufaka nokuphumayo zibhalisiwe. Uma ikhishiwe, inani elizenzakalelayo lingu-0.

7.10. Amapharamitha wedekhoda

Ithebula elilandelayo libala amapharamitha angumongo wesikhiphikhodi se-ALTECC.

Ithebula 27. Amapharamitha we-ALTECC Decoder

Igama lepharamitha WIDTH_DATAWORD

Thayipha inombolo ephelele

Kudingeka

Incazelo

Yebo

Icacisa ububanzi bedatha eluhlaza. Amanani angu-2 kuya ku-64

inani elizenzakalelayo lingu-8.

WIDTH_CODEWORD

Inombolo ephelele

Yebo

Icacisa ububanzi begama lekhodi elihambisanayo. Amanani angu-6

kuya ku-72, ngaphandle kuka-9, 17, 33, kanye no-65. Uma kukhishiwe, inani elimisiwe

ngi 13.

LPM_PIPELINE

Inombolo ephelele

Cha

Icacisa irejista yesekethe. Amanani asuka ku-0 kuye ku-2. Uma i

inani ngu-0, akukho rejista esetshenziswayo. Uma inani lingu-1, i-

okukhiphayo kubhalisiwe. Uma inani lingu-2, kokubili okokufaka kanye ne-

okukhiphayo zibhalisiwe. Uma inani likhulu kuno-2, lingeziwe

amarejista asetshenziswa lapho kuphuma khona okungeziwe

ukubambezeleka. Uma ikhishiwe, inani elizenzakalelayo lingu-0.

Dala imbobo ethi 'syn_e'

Inombolo ephelele

Cha

Vula le pharamitha ukuze udale imbobo ye-sync_e.

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 35

683490 | 2020.10.05 Thumela Impendulo

8. Intel FPGA Multiply Adder IP Core

Umfanekiso 9.

I-Intel FPGA Multiply Adder (Intel Stratix 10, Intel Arria 10, kanye namadivayisi we-Intel Cyclone 10 GX) noma i-ALTERA_MULT_ADD (Amadivayisi we-Arria V, Stratix V, kanye ne-Cyclone V) i-IP core ikuvumela ukuthi usebenzise i-multiplier-adder.

Isibalo esilandelayo sibonisa izimbobo ze-Intel FPGA Multiply Adder noma i-ALTERA_MULT_ADD IP core.

I-Intel FPGA Multiply Adder noma ALTERA_MULT_ADD Ports

I-Intel FPGA Multiply Adder noma ALTERA_MULT_ADD

idathaa[] uphawu lwedathab[] uphawu lwedathac[] coefsel0[] coefsel1[] coefsel2[] coefsel3[] addnsub1 addnsub3 aclr/sclr[] scanina[] iwashi0 iwashi1 iwashi2 ena0 ena1 ena2 sload_accum
i-accum_sload chain[]

scanouta[] umphumela[]

acl0 acl1

inst
I-multiplier-adder yamukela amapheya okokufaka, iphindaphinde amanani ndawonye bese yengeza noma isuse emikhiqizweni yawo wonke amanye amapheya.
Uma bonke ububanzi bedatha yokufaka buyi-9-bits ububanzi noma buncane, umsebenzi usebenzisa ukulungiselelwa kokuphindaphinda okokufaka okungu-9 x 9 bit kubhulokhi ye-DSP kumadivayisi asekela ukulungiselelwa kwe-9 x 9. Uma kungenjalo, ibhulokhi ye-DSP isebenzisa iziphindaphindi zokufaka ezingu-18 × 18-bit ukucubungula idatha enobubanzi obuphakathi kwamabhithi angu-10 no-18. Uma ama-Intel FPGA Multiply Adder amaningi noma ALTERA_MULT_ADD IP cores zenzeka esakhiweni, imisebenzi isatshalaliswa ngokuthi

I-ISO 9001:2015 Ibhalisiwe

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05
amabhulokhi amaningi e-DSP ahlukene ngangokunokwenzeka ukuze umzila oya kulawa mabhulokhi uvumelane nezimo. Iziphindaphindi ezimbalwa ngebhulokhi ngayinye ye-DSP zivumela ukukhetha okuningi komzila kubhulokhi ngokunciphisa izindlela eziya kulo lonke idivayisi.
Amarejista kanye namarejista engeziwe ephayiphi lamasignali alandelayo afakwa ngaphakathi kwebhulokhi ye-DSP: · Ukufakwa kwedatha · Khetha okusayiniwe noma okungasayiniwe · Engeza noma ukhiphe okukhethiwe · Imikhiqizo yeziphindaphinda.
Endabeni yomphumela wokuphumayo, irejista yokuqala ifakwa kubhulokhi ye-DSP. Kodwa-ke amarejista engeziwe e-latency afakwa ezintweni ezinengqondo ngaphandle kwebhulokhi. I-peripheral yebhulokhi ye-DSP, okuhlanganisa okokufaka kwedatha kusiphindaphindi, okokufaka kwesignali yokulawula, nokuphumayo kwe-adder, sebenzisa umzila ovamile ukuze uxhumane nayo yonke idivayisi. Konke ukuxhumana emsebenzini kusebenzisa umzila ozinikele ngaphakathi kwebhulokhi ye-DSP. Lo mzila ozinikele uhlanganisa amaketango erejista yeshifu lapho ukhetha inketho yokususa idatha yokufaka ebhalisiwe yesiphindaphindi isuke kusiphindaphindi esisodwa iye kwesiphindaphinda esiseduze.
Ukuze uthole ulwazi olwengeziwe mayelana namabhulokhi e-DSP kunoma yiluphi uchungechunge lwedivayisi ye-Stratix V, kanye ne-Arria V, bheka isahluko se-DSP Blocks sezincwadi ezilandelanayo ekhasini elithi Literature and Technical Documentation.
Ulwazi Oluhlobene AN 306: Ukusebenzisa Iziphindaphinda kumadivayisi e-FPGA
Inikeza ulwazi olwengeziwe mayelana nokusebenzisa iziphindaphinda kusetshenziswa i-DSP namabhulokhi enkumbulo kumadivayisi we-Intel FPGA.
8.1. Izici
I-Intel FPGA Multiply Adder noma ALTERA_MULT_ADD IP core inikeza izici ezilandelayo: · Ikhiqiza isiphindaphinda ukuze yenze imisebenzi yokuphindaphinda yezinto ezimbili eziyinkimbinkimbi.
izinombolo Qaphela: Uma wakha iziphindaphinda ezinkulu kunosayizi osekelwe ngokomdabu kungase/
kuzoba nomthelela wokusebenza ovela ekuqhumeni kwamabhulokhi e-DSP. · Isekela ububanzi bedatha wamabhithi angu-1 256 · Isekela ifomethi yokumelela idatha esayiniwe nengabhalisiwe · Isekela ukufakwa kwamapayipi nge-latency okokufaka okulungisekayo · Inikeza inketho yokushintsha ngokuguquguqukayo phakathi kokusekelwa kwedatha esayiniwe nokungasayiniwe · Inikeza inketho yokushintsha ngamandla phakathi kokungeza nokukhipha ukusebenza · Isekela ngokuzikhethela okuvumelanayo nokuvumelanayo okucacile kanye newashi kunika amandla amachweba okokufaka · Isekela imodi yerejista yokubambezeleka kwe-systolic · Isekela i-adder yangaphambili ngama-coefficients alayishwa ngaphambili angu-8 ngesiphindaphinda ngasinye · Isekela ukulayisha kwangaphambili okungaguquki ukuze kuhambisane nempendulo ye-accumulator

Thumela Impendulo

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

8.1.1. I-Pre-adder
Nge-pre-adder, ukwengeza noma ukususa kwenziwa ngaphambi kokuphakela isiphindaphindi.
Kunezinhlobo ezinhlanu ze-pre-adder: · Imodi elula · Imodi ye-coefficient · Imodi yokufaka · Imodi yesikwele · Imodi eqhubekayo

Qaphela:

Uma kusetshenziswa i-pre-adder (imodi ye-pre-adder/input/square), konke okokufaka kwedatha kusiphindaphindi kufanele kube nesilungiselelo sewashi esifanayo.

8.1.1.1. Imodi Elula Ye-Pre-adder

Kule modi, womabili ama-operands aphuma kuzimbobo zokufaka futhi i-pre-adder ayisetshenziswa noma yeqiwa. Lena imodi ezenzakalelayo.

Umfanekiso 10. Imodi Elula Yangaphambili Ye-adder
a0 b0

Mult0

umphumela

8.1.1.2. Imodi ye-Pre-adder Coefficient
Kule modi, i-operand eyodwa yokuphindaphinda iphuma ku-pre-adder, kanti enye i-operand iphuma kusitoreji se-coefficient yangaphakathi. Isitoreji se-coefficient sivumela ama-constants angafika kwangu-8 asethiwe. Izimpawu zokukhetha i-coefficient ziyi-coefsel[0..3].
Le modi iboniswa esibalweni esilandelayo.

Okulandelayo kubonisa imodi ye-coefficient yangaphambili yesiphindi.

Umfanekiso 11. Imodi ye-Pre-adder Coefficient

Preadder

Mult0

+/-

umphumela

coefsel0 inkomo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 38

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05
8.1.1.3. Imodi Yokufaka I-Pre-adder Kule modi, i-operand eyodwa yesiphindaphinda iphuma ku-pre-adder, kanti enye i-operand iphuma ku-datac[] port input. Le modi iboniswa esibalweni esilandelayo.

Okulandelayo kubonisa imodi yokufaka ye-pre-adder yesiphindaphinda.

Umfanekiso 12. Imodi Yokufaka I-Pre-adder
a0 b0

Mult0

+/-

umphumela

8.1.1.4. Imodi yesikwele ye-pre-adder Le modi ivezwe ngesibalo esilandelayo.

Okulandelayo kubonisa imodi yesikwele yangaphambi kwe-adder yeziphindaphinda ezimbili.

Umfanekiso 13. I-Pre-adder Square Mode
a0 b0

Mult0

+/-

umphumela

8.1.1.5. I-Pre-adder Constant Mode
Kule modi, i-operand eyodwa yesiphindaphinda iphuma kumbobo yokufaka, kanti enye i-operand iphuma kusitoreji se-coefficient yangaphakathi. Isitoreji se-coefficient sivumela ama-constants angafika kwangu-8 asethiwe. Izimpawu zokukhetha i-coefficient ziyi-coefsel[0..3].
Le modi iboniswa esibalweni esilandelayo.

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Isibalo esilandelayo sibonisa imodi yangaphambi kwe-adder engaguquki yesiphindaphinda.

Umfanekiso 14. I-Pre-adder Constant Mode
a0

Mult0

umphumela

isiqephu0
inkomo
8.1.2. Irejista yokubambezeleka kwe-Systolic
Ku-systolic architecture, idatha yokufaka ifakwa kuchungechunge lwamarejista asebenza njengesilondolozi sedatha. Irejista ngayinye iletha okokufaka sample kusiphindaphinda lapho siphindaphindwa khona nge-coefficient efanele. I-chain adder igcina imiphumela ehlanganiswe kancane kancane evela kusiphindaphindi kanye nomphumela obhaliswe ngaphambilini osuka kumbobo yokufaka ye-chainin[] ukwenza umphumela wokugcina. Isici ngasinye sokwengeza ngokuphindaphinda kufanele sibambezeleke ngomjikelezo owodwa ukuze imiphumela ivunyelaniswe ngokufanelekile lapho ihlanganiswa ndawonye. Ukubambezeleka ngakunye okulandelanayo kusetshenziselwa ukubhekana nakho kokubili inkumbulo ye-coefficient kanye nesigcinalwazi sedatha yezinto zazo eziphindaphindayo ngokulandelana kwazo. Okwesiboneloample, ukubambezeleka okukodwa kwesici sokwengeza okuphindaphindekayo kwesibili, ukubambezeleka okubili kwesici sesithathu sokuphindaphinda, nokunye.
Umfanekiso 15. Amarejista e-Systolic
Amarejista e-Systolic

x(t) c(0)

S -1

c(1)

S -1

c(2)

S -1

c(N-1)

S -1

S -1 y(t)

x(t) imele imiphumela evela emfudlaneni oqhubekayo wokokufaka sampi-les kanye no-y(t)
imele ukufinyezwa kwesethi yokufaka samples, futhi ngokuhamba kwesikhathi, anda ngabo
ama-coefficients afanele. Kokubili okokufaka nemiphumela kugeleza ukusuka kwesokunxele kuye kwesokudla. I-c(0) ukuya ku-c(N-1) ichaza ama-coefficients. Amarejista okulibaziseka kwe-systolic achazwa ngu-S-1, kanti u-1 umele ukubambezeleka kwewashi elilodwa. Amarejista okulibaziseka kwe-Systolic ayengezwa ku
okokufaka kanye nemiphumela yokufaka amapayipi ngendlela eqinisekisa imiphumela evela ku
i-multiplier operand kanye nezibalo eziqoqiwe zihlala zihambisana. Le nto yokucubungula
iphindwaphindwa ukuze yakhe isekethe ehlanganisa umsebenzi wokuhlunga. Lolu hlelo lokusebenza
kuvezwe kuzibalo ezilandelayo.

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 40

Thumela Impendulo

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

U-N umele inani lemijikelezo yedatha engene kusiqoqiwe, u-y(t) umelela okukhiphayo ngesikhathi t, A(t) umele okokufaka ngesikhathi t, futhi B(i) ama-coefficient. U-t kanye no-i kusilinganiso kuhambisana nesikhathi esithile, ngakho-ke ukubala okukhiphayo sample y(t) ngesikhathi t, iqoqo lokokufaka sampkancane ngamaphoyinti angu-N ahlukene ngesikhathi, noma u-A(n), A(n-1), A(n-2), … A(n-N+1) uyadingeka. Iqembu lokufakwayo kuka-N sampama-les aphindaphindwa ngama-coefficient angu-N futhi afingqwe ndawonye ukuze enze umphumela wokugcina y.
I-systolic register architecture itholakala kuphela ku-sum-of-2 kanye ne-sum-of-4 modes. Kuzo zombili izindlela zokwakheka kwerejista ye-systolic, isignali yokuqala ye-chainin idinga ukuboshwa ku-0.
Isibalo esilandelayo sibonisa ukuqaliswa kwerejista yokubambezeleka kwe-systolic yeziphindaphinda ezi-2.
Umfanekiso 16. Irejista Yokubambezeleka kwe-Systolic Ukuqaliswa Kweziphindaphinda ze-2
i-chainin

Mult0

+/-

Mult1

+/-

umphumela
Isamba seziphindaphinda ezimbili zivezwa esibalweni esilandelayo.
Isibalo esilandelayo sibonisa ukuqaliswa kwerejista yokubambezeleka kwe-systolic yeziphindaphinda ezi-4.

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 41

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Umfanekiso 17. Irejista Yokubambezeleka kwe-Systolic Ukuqaliswa Kweziphindaphinda ze-4
i-chainin

Mult0

+/-

Mult1

+/-

Mult2

+/-

Mult3

+/-

umphumela
Isamba seziphindaphinda ezine zivezwe kusibalo esilandelayo. Umfanekiso 18. Isamba seziphindaphinda ezi-4
Okulandelayo kuklelisa i-advantagukuqaliswa kwerejista ye-systolic: · Yehlisa ukusetshenziswa kwensiza ye-DSP · Inika amandla ukuhlelwa kwemephu okuphumelelayo kubhulokhi ye-DSP kusetshenziswa isakhiwo se-adder seketango.

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 42

Thumela Impendulo

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

8.1.3. Layisha ngaphambilini Constant
I-pre-load njalo ilawula i-accumulator operand futhi igcwalise impendulo ye-accumulator. Ububanzi obuvumelekile be-LOADCONST_VALUE busuka ku-0. Inani elingaguquki lilingana no-64N, lapho N = LOADCONST_VALUE. Uma i-LOADCONST_VALUE isethelwe ku-2, inani elingashintshi lilingana no-64. Lo msebenzi ungasetshenziswa njengokusondeza okuchemile.
Isibalo esilandelayo sibonisa ukuqaliswa kokulayisha kwangaphambilini njalo.
Umfanekiso 19. Ukulayisha kwangaphambilini njalo

Impendulo ye-Accumulator

njalo

Mult0

+/-

Mult1

+/b1

umphumela

accum_sload sload_accum

Bheka ama-IP cores alandelayo ngokunye ukusetshenziswa kwesiphindaphinda: · ALTMULT_ACCUM · ALTMEMMULT · LPM_MULT
8.1.4. I-Accumulator Ekabili
Isici se-accumulator esiphindwe kabili sengeza irejista eyengeziwe endleleni yempendulo ye-accumulator. Irejista ye-accumulator ephindwe kabili ilandela irejista yokukhiphayo, ehlanganisa iwashi, ukunika amandla iwashi, kanye ne-aclr. Irejista eyengeziwe ye-accumulator ibuyisela umphumela ngokubambezeleka komjikelezo owodwa. Lesi sici sikwenza ukwazi ukuba namashaneli amabili e-accumulator anenani elifanayo lensiza.
Isibalo esilandelayo sibonisa ukusetshenziswa kwe-accumulator ephindwe kabili.

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 43

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Umfanekiso 20. I-Double Accumulator

Irejista ye-Accu mulator

I-Accu mulator impendulo ck

Mult0

+/-

Mult1

+/b1

Umphumela Wokuphuma Irejista

8.2. I-Verilog HDL Prototype
Ungathola i-Intel FPGA Multiply Adder noma i-ALTERA_MULT_ADD Verilog HDL prototype file (altera_mult_add_rtl.v) ku imitapo yolwazi yemisebenzi eminingi.
8.3. Isimemezelo Sengxenye Ye-VHDL
Isimemezelo sengxenye ye-VHDL sitholakala kokuthi altera_lnsim_components.vhd ku- libraryvhdl altera_lnsim directory.
8.4. I-VHDL LIBRARY_USE Isimemezelo
Isimemezelo se-VHDL LIBRARY-USE asidingeki uma usebenzisa Isimemezelo Sengxenye Ye-VHDL.
I-LIBRARY alter_mf; SEBENZISA i-altera_mf.altera_mf_components.all;

8.5. Amasignali

Amathebula alandelayo aklelisa amasiginali okokufaka nokuphumayo kwe-Multiply Adder Intel FPGA IPor ALTERA_MULT_ADD IP core.

Ithebula 28. Phindaphinda I-Adder Intel FPGA IPor ALTERA_MULT_ADD Izimpawu Zokufaka

Isiginali

Kudingeka

Incazelo

idathaa_0[]/dataa_1[]/

Yebo

idathaa_2[]/dataa_3[]

Okokufaka kwedatha kusiphindaphindi. Imbobo yokufaka [NUMBER_OF_MULTIPLIERS * WIDTH_A – 1 … 0] ububanzi
waqhubeka...

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 44

Thumela Impendulo

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Iwashi ledathab_0[]/datab_1[]/ idathab_2[]/datab_3[] /datac_0[]/ idathac_1[]/datac_2[] [3:1] aclr[0:1] sclr[0:1] ena[0:1] uphawu
uphawu
scanina[] accum_sload

Kudingeka Yebo Cha
Cha Cha Cha Cha Cha Cha
Cha
Cha No

Incazelo
Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kulawa masignali. Uma unikeza inani le-X kulawa masignali, inani le-X lisakazwa kumasignali okukhiphayo.
Okokufaka kwedatha kusiphindaphindi. Isignali yokokufaka [NUMBER_OF_MULTIPLIERS * WIDTH_B – 1 … 0] ububanzi Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kulawa masignali. Uma unikeza inani elingu-X kulawa masignali, inani le-X liyasakazwa kumasignali okukhiphayo.
Okokufaka kwedatha kusiphindaphindi. Isignali yokokufaka [NUMBER_OF_MULTIPLIERS * WIDTH_C – 1, … 0] ububanzi Khetha INPUT ukuze Khetha ipharamitha yemodi yepreadder ukuze unike lawa masignali amandla. Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kulawa masignali. Uma unikeza inani elingu-X kulawa masignali, inani le-X liyasakazwa kumasignali okukhiphayo.
Imbobo yokufaka iwashi kurejista ehambisanayo. Lesi siginali singasetshenziswa yinoma iyiphi irejista kumongo we-IP. Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kulawa masignali. Uma unikeza inani elingu-X kulawa masignali, inani le-X liyasakazwa kumasignali okukhiphayo.
Okokufaka okucacile okungahambisani nerejista ehambisanayo. Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kulawa masignali. Uma unikeza inani elingu-X kulawa masignali, inani le-X liyasakazwa kumasignali okukhiphayo.
Okokufaka okucacile okuvumelanayo kurejista ehambisanayo. Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe elingu-X kulawa masignali. Uma unikeza inani elingu-X kulawa masignali, inani le-X liyasakazwa kumasignali okukhiphayo
Nika amandla okokufaka kwesignali kurejista ehambisanayo. Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kulawa masignali. Uma unikeza inani elingu-X kulawa masignali, inani le-X liyasakazwa kumasignali okukhiphayo.
Icacisa ukumelwa kwezinombolo kokokufaka okuphindaphindayo A. Uma isignali yesiginali iphezulu, isiphindaphinda siphatha isiphindaphinda sesiginali A njengenombolo esayiniwe. Uma isignali yesignesha iphansi, isiphindaphinda siphatha isiphindaphinda esingu-A isignali njengenombolo engasayiniwe. Khetha okuthi VARIABLE kokuthi Ithini ifomethi yokumelela Iziphindaphinda A ipharamitha yokokufaka ukuze unike le siginali amandla. Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kule siginali. Uma unikeza inani elingu-X kulokhu okokufaka, inani le-X liyasakazwa kumasignali okukhiphayo.
Icacisa ukumelwa kwezinombolo kwesiginali engu-B yokuphindaphinda. Uma isignali yophawu iphezulu, isiphindaphinda siphatha isiphindaphinda esingu-B isignali njengenombolo ehambisanayo yamabili asayiniwe. Uma isignali yophawu iphansi, isiphindaphinda siphatha isiphindaphinda esingu-B isignali njengenombolo engasayiniwe. Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kule siginali. Uma unikeza inani elingu-X kulokhu okokufaka, inani le-X liyasakazwa kumasignali okukhiphayo.
Okokufaka kochungechunge lokuskena A. Isignali yokokufaka [WIDTH_A – 1, … 0] ububanzi. Uma ipharamitha ye-INPUT_SOURCE_A inenani le-SCANA, isignali ye-scanina iyadingeka.
Icacisa ngokunamandla ukuthi ingabe inani le-accumulator lihlala njalo. Uma isignali ye-accum_sload iphansi, umphumela wokuphindaphinda ulayishwa ku-accumulator. Ungayisebenzisi i-accum_sload ne-sload_accum kanyekanye.
waqhubeka...

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Isiginali sload_accum
i-chainin[] addnsub1
addnsub3
coefsel0[] coefsel1[] coefsel2[] coefsel3[]

Inombolo edingekayo
Cha No
Cha
Cha Cha Cha Cha Cha

Incazelo
Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kule siginali. Uma unikeza inani elingu-X kulokhu okokufaka, inani le-X liyasakazwa kumasignali okukhiphayo.
Icacisa ngokunamandla ukuthi ingabe inani le-accumulator lihlala njalo. Uma isignali ye-sload_acum iphezulu, khona-ke okukhiphayo okuphindaphindayo kulayishwa ku-accumulator. Ungayisebenzisi i-accum_sload ne-sload_accum kanyekanye. Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kule siginali. Uma unikeza inani elingu-X kulokhu okokufaka, inani le-X liyasakazwa kumasignali okukhiphayo.
Ibhasi lokufaka umphumela we-adder kusukela ku-s eyanduleletage. Isignali yokokufaka [WIDTH_CHAININ – 1, … 0] ububanzi.
Enza ukwengeza noma ukususa kokuphumayo kusukela kupheya yokuqala yeziphindaphindi. Okokufaka 1 kusiginali ye-addnsub1 ukuze wengeze okuphumayo kusukela kupheya yokuqala yeziphindaphindi. Faka u-0 kusiginali ye-addnsub1 ukuze ususe okuphumayo kupheya yokuqala yeziphindaphindi. Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kule siginali. Uma unikeza inani elingu-X kulokhu okokufaka, inani le-X liyasakazwa kumasignali okukhiphayo.
Enza ukwengeza noma ukususa kokuphumayo kusukela kupheya yokuqala yeziphindaphindi. Okokufaka 1 kusiginali ye-addnsub3 ukuze wengeze imiphumela evela kupheya yesibili yeziphindaphindi. Okokufaka 0 kusiginali ye-addnsub3 ukuze ususe okuphumayo kupheya yokuqala yeziphindaphindi. Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kule siginali. Uma unikeza inani elingu-X kulokhu okokufaka, inani le-X liyasakazwa kumasignali okukhiphayo.
Isiginali yokufaka i-coefficient[0:3] kusiphindaphinda sokuqala. Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kule siginali. Uma unikeza inani elingu-X kulokhu okokufaka, inani le-X liyasakazwa kumasignali okukhiphayo.
Isiginali yokufaka i-coefficient[0:3]kuya kusiphindaphindi sesibili. Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kule siginali. Uma unikeza inani elingu-X kulokhu okokufaka, inani le-X liyasakazwa kumasignali okukhiphayo.
Isignali yokufaka i-coefficient[0:3]kuya kusiphindaphindi sesithathu. Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kule siginali. Uma unikeza inani elingu-X kulokhu okokufaka, inani le-X liyasakazwa kumasignali okukhiphayo.
Isiginali yokufaka i-coefficient [0:3] ukuya kusiphindaphindi sesine. Imodeli yokulingisa yale IP isekela inani lokufaka elinganqunyiwe (X) kule siginali. Uma unikeza inani elingu-X kulokhu okokufaka, inani le-X liyasakazwa kumasignali okukhiphayo.

Ithebula 29. Phindaphinda Izimpawu Zokukhipha I-Adder Intel FPGA IP

Isiginali

Kudingeka

Incazelo

umphumela []

Yebo

Isignali yokuphuma okuningi. Isignali yokuphumayo [WIDTH_RESULT – 1 … 0] ububanzi

Imodeli yokulingisa yale IP isekela inani lokuphumayo elinganqunyiwe (X). Uma unikeza inani elingu-X njengokufakwayo, inani le-X liyasakazwa kule siginali.

scanouta []

Cha

Okukhiphayo kochungechunge lokuskena A. Isignali yokuphumayo [WIDTH_A – 1..0] ububanzi.

Khetha okungaphezulu kuka-2 ukuze uthole izinombolo zeziphindaphinda bese ukhetha okokufaka kweketango lokuskena kokuthi Iyini i-A yesiphindi exhunywe kupharamitha ukuze unike le siginali amandla.

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 46

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8.6. Amapharamitha

8.6.1. Ithebhu Ejwayelekile

Ithebula 30. Ithebhu evamile

Ipharamitha

IP Ekhiqizwe Ipharamitha

Inani

Ithini inombolo yeziphindaphinda?

inombolo_ye_m 1 – 4 ama-ultipliers

Kufanele abe ububanzi obungakanani amabhasi okufaka u-A ububanzi_a?

1 – 256

Kufanele abe ububanzi obungakanani amabhasi okokufaka B width_b?

1 – 256

Kufanele ibe banzi kangakanani ibhasi eliphumayo 'lomphumela'?

ububanzi_umphumela

1 – 256

Dala iwashi elihlobene vumela iwashi ngalinye

gui_associate On d_clock_enable Valiwe e

8.6.2. Ithebhu yamamodi engeziwe

Ithebula 31. Ithebhu yamamodi engeziwe

Ipharamitha

IP Ekhiqizwe Ipharamitha

Inani

Ukucushwa Kwemiphumela

Bhalisa ukuphuma kweyunithi ye-adder

gui_output_re Vuliwe

gister

Valiwe

Uyini umthombo wokufakwa kwewashi?

gui_output_re gister_clock

Iwashi0 Iwashi1 Iwashi2

Uyini umthombo wokufaka okucacile kwe-asynchronous?

gui_output_re gister_aclr

AKUKHO ACLR0 ACLR1

Uyini umthombo wokufaka okucacile okuvumelanayo?

gui_output_re gister_sclr

AKUKHO SCLR0 SCLR1

Ukusebenza kwe-adder

Yimuphi umsebenzi okufanele wenziwe kokuphumayo kwepheya yokuqala yeziphindaphinda?

gui_multiplier 1_direction

ADD, SUB, VARIABLE

Inani elizenzakalelayo 1
16

Incazelo
Inani leziphindaphinda ezizokwengezwa ndawonye. Amanani angu-1 ukuya ku-4. Cacisa ububanzi bembobo yedathaa[].

Cacisa ububanzi bembobo yedathab[].

Cacisa ububanzi bomphumela[] imbobo.

Valiwe

Khetha le nketho ukuze udale amandla wewashi

ngewashi ngalinye.

Inani elizenzakalelayo

Incazelo

Iwashi elivaliwe0
AKUKHO LUTHO

Khetha le nketho ukuze unike amandla irejista yokuphumayo yemojuli ye-adder.
Khetha Iwashi0 , Iwashi1 noma Iwashi2 ukuze unike amandla futhi ucacise umthombo wewashi wamarejista okukhiphayo. Kufanele ukhethe ukubhalisa okukhiphayo kweyunithi ye-adder ukuze unike amandla le parameter.
Icacisa umthombo ocacile ongavumelanisiwe werejista yokuphuma kwe-adder. Kufanele ukhethe ukubhalisa okukhiphayo kweyunithi ye-adder ukuze unike amandla le parameter.
Icacisa umthombo ocacile wokuvumelanisa werejista yokukhipha i-adder. Kufanele ukhethe ukubhalisa okukhiphayo kweyunithi ye-adder ukuze unike amandla le parameter.

ENGEZA

Khetha umsebenzi wokwengeza noma wokukhipha ukuze wenzele okuphumayo phakathi kwesiphindaphindi sokuqala nesesibili.
· Khetha okuthi ADD ukwenza umsebenzi wokwengeza.
· Khetha i-SUB ukuze wenze umsebenzi wokukhipha.
· Khetha okuthi VARIABLE ukuze usebenzise imbobo ye-adnsub1 ukuze uthole ukulawula okunamandla kokungeza/ukukhipha.
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Ipharamitha

IP Ekhiqizwe Ipharamitha

Inani

Bhalisa okokufaka kwe-'addnsub1'

gui_addnsub_ Ku-multiplier_reg Vala ister1

Uyini umthombo wokufakwa kwewashi?

gui_addnsub_ multiplier_reg ister1_clock

Iwashi0 Iwashi1 Iwashi2

Uyini umthombo wokufaka okucacile kwe-asynchronous?

gui_addnsub_ multiplier_aclr 1

AKUKHO ACLR0 ACLR1

Uyini umthombo wokufaka okucacile okuvumelanayo?

gui_addnsub_ multiplier_sclr 1

AKUKHO SCLR0 SCLR1

Yimuphi umsebenzi okufanele wenziwe kokuphumayo kweziphindaphinda ezimbili?

gui_multiplier 3_direction

ADD, SUB, VARIABLE

Bhalisa okokufaka kwe-'addnsub3'

gui_addnsub_ Ku-multiplier_reg Vala ister3

Uyini umthombo wokufakwa kwewashi?

gui_addnsub_ multiplier_reg ister3_clock

Iwashi0 Iwashi1 Iwashi2

Inani elizenzakalelayo
Iwashi elivaliwe0 AKUKHO ONGEZIWE
Iwashi elivaliwe0

Incazelo
Uma kukhethwa inani elingu-VARIABLE: · Shayela isiginali ye-addnsub1 iye phezulu ukuze
umsebenzi wokwengeza. · Shayela isignali ye-addnsub1 iye phansi ukuze
ukusebenza kokukhipha. Kufanele ukhethe iziphindaphindi ezingaphezu kwezimbili ukuze unike amandla le pharamitha.
Khetha le nketho ukuze unike amandla irejista yokufaka yembobo ye-addnsub1. Kumelwe ukhethe okuthi VARIABLE kokuthi Yimuphi umsebenzi okufanele wenziwe kokuphumayo kweziphindaphindi ezimbili zokuqala ukuze le pharamitha isebenze.
Khetha Iwashi0 , Iwashi1 noma Iwashi2 ukuze ucacise isignali yewashi lokufaka lerejista ye-adnsub1. Kufanele ukhethe okuthi Bhalisa okuthi 'addnsub1' ukuze unike amandla le pharamitha.
Icacisa umthombo ocacile ongavumelanisiwe werejista ye-adnsub1. Kufanele ukhethe okuthi Bhalisa okuthi 'addnsub1' ukuze unike amandla le pharamitha.
Icacisa umthombo ocacile wokuvumelanisa werejista ye-addnsub1. Kufanele ukhethe okuthi Bhalisa okuthi 'addnsub1' ukuze unike amandla le pharamitha.
Khetha umsebenzi wokwengeza noma wokukhipha ukuze wenzele okuphumayo phakathi kweziphindaphindi zesithathu nezesine. · Khetha ADD ukwenza ukwengeza
ukusebenza. · Khetha i-SUB ukuze ususe
ukusebenza. · Khetha VARIABLE ukusebenzisa addnsub1
ichweba lokulawula ukwengeza/ukususa okuguquguqukayo. Uma kukhethwa inani elingu-VARIABLE: · Shayela isignali ye-addnsub1 iye phezulu ukuze uthole umsebenzi wokwengeza. · Shayela isignali ye-addnsub1 iye phansi ukuze usebenze ngokukhipha. Kufanele ukhethe inani 4 elithi Ithini inombolo yeziphindaphinda? ukuze unike amandla le parameter.
Khetha le nketho ukuze unike amandla irejista yokufaka yesiginali ye-addnsub3. Kumelwe ukhethe okuthi VARIABLE kokuthi Yimuphi umsebenzi okufanele wenziwe kokuphumayo kwepheya yesibili yeziphindaphinda ukuze unike amandla le pharamitha.
Khetha Iwashi0 , Iwashi1 noma Iwashi2 ukuze ucacise isignali yewashi lokufaka lerejista ye-adnsub3. Kufanele ukhethe okuthi Bhalisa okuthi 'addnsub3′ ukuze unike amandla le pharamitha.
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Ipharamitha
Uyini umthombo wokufaka okucacile kwe-asynchronous?

IP Ekhiqizwe Ipharamitha

Inani

gui_addnsub_ multiplier_aclr 3

AKUKHO ACLR0 ACLR1

Uyini umthombo wokufaka okucacile okuvumelanayo?

gui_addnsub_ multiplier_sclr 3

AKUKHO SCLR0 SCLR1

I-polarity Nika amandla `use_subadd'

gui_use_subn On

engeza

Valiwe

8.6.3. Ithebhu Yokuphindaphinda

Ithebula 32. Ithebhu Yokuphindaphinda

Ipharamitha

IP Ekhiqizwe Ipharamitha

Inani

Yini i

gui_represent

ifomethi yokumelela_a

okokufaka kwe-Multipliers A?

ISAyiniwe, AKUSAYINWE, IYASHINTSHA

Bhalisa `uphawu' okokufaka

gui_register_s Vuliwe

igna

Valiwe

Uyini umthombo wokufakwa kwewashi?

gui_register_s igna_clock

Iwashi0 Iwashi1 Iwashi2

Uyini umthombo wokufaka okucacile kwe-asynchronous?

gui_register_s igna_aclr

AKUKHO ACLR0 ACLR1

Uyini umthombo wokufaka okucacile okuvumelanayo?

gui_register_s igna_sclr

AKUKHO SCLR0 SCLR1

Yini i

gui_represent

ifomethi yokumelela_b

okokufaka kwe-Multipliers B?

ISAyiniwe, AKUSAYINWE, IYASHINTSHA

Bhalisa okuthi `signb' okokufaka

gui_register_s Vuliwe

igb

Valiwe

Inani elizenzakalelayo LAYIKHO
AKUKHO

Incazelo
Icacisa umthombo ocacile ongavumelanisiwe werejista ye-adnsub3. Kufanele ukhethe okuthi Bhalisa okuthi 'addnsub3' ukuze unike amandla le pharamitha.
Icacisa umthombo ocacile wokuvumelanisa werejista ye-addnsub3. Kufanele ukhethe okuthi Bhalisa okuthi 'addnsub3′ ukuze unike amandla le pharamitha.

Valiwe

Khetha le nketho ukuze uhlehlise umsebenzi

yembobo yokufaka ye-addnsub.

Shayela i-adnsub ukuya phezulu ukuze usebenze ngokukhipha.

Shayela i-adnsub iye kokuphansi ukuze uthole umsebenzi wokwengeza.

Inani elizenzakalelayo

Incazelo

AKUSAYINWE Cacisa ifomethi yokumelela okokufaka okuphindaphindayo A.

Valiwe

Khetha le nketho ukuze unike amandla isignali

bhalisa.

Kufanele ukhethe ivelu eVARIABLE yokuthi Ithini ifomethi yokumelela okokufaka kwama-Multipliers A? ipharamitha ukuze unike amandla le nketho.

Isikhathi C0

Khetha Iwashi0 , Iwashi1 noma Iwashi2 ukuze unike amandla futhi ucacise isignali yewashi yokufaka yerejista yesignali.
Kufanele ukhethe okuthi Bhalisa `uphawu' ukuze unike amandla le parameter.

AKUKHO

Icacisa umthombo ocacile ongavumelanisiwe werejista yesiginali.
Kufanele ukhethe okuthi Bhalisa `uphawu' ukuze unike amandla le parameter.

AKUKHO

Icacisa umthombo ocacile ovumelanisiwe werejista yesiginali.
Kufanele ukhethe okuthi Bhalisa `uphawu' ukuze unike amandla le parameter.

AKUSAYINWE Cacisa ifomethi yokumelela okokufaka kuka-B okuphindaphindayo.

Valiwe

Khetha le nketho ukuze unike amandla uphawu

bhalisa.

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Ipharamitha

IP Ekhiqizwe Ipharamitha

Inani

Inani elizenzakalelayo

Uyini umthombo wokufakwa kwewashi?

gui_register_s ignb_clock

Iwashi0 Iwashi1 Iwashi2

Isikhathi C0

Uyini umthombo wokufaka okucacile kwe-asynchronous?

gui_register_s ignb_aclr

AKUKHO ACLR0 ACLR1

Uyini umthombo wokufaka okucacile okuvumelanayo?

gui_register_s ignb_sclr

AKUKHO SCLR0 SCLR1

Okokufaka Ukucushwa
Bhalisa okokufaka A kwesiphindaphindayo
Uyini umthombo wokufakwa kwewashi?

gui_input_reg Vuliwe

ister_a

Valiwe

gui_input_reg ister_a_clock

Iwashi0 Iwashi1 Iwashi2

AKUKHO LUTHO
Iwashi elivaliwe0

Uyini umthombo wokufaka okucacile kwe-asynchronous?

gui_input_reg ister_a_aclr

AKUKHO ACLR0 ACLR1

Uyini umthombo wokufaka okucacile okuvumelanayo?

gui_input_reg ister_a_sclr

AKUKHO SCLR0 SCLR1

Bhalisa okokufaka B kwesiphindaphinda
Uyini umthombo wokufakwa kwewashi?

gui_input_reg Vuliwe

ister_b

Valiwe

gui_input_reg ister_b_clock

Iwashi0 Iwashi1 Iwashi2

AKUKHO NONE Off Clock0

Uyini umthombo wokufaka okucacile kwe-asynchronous?

gui_input_reg ister_b_aclr

AKUKHO ACLR0 ACLR1

AKUKHO

Uyini umthombo wokufaka okucacile okuvumelanayo?

gui_input_reg ister_b_sclr

AKUKHO SCLR0 SCLR1

AKUKHO

Kuyini okokufaka okungu-A kwesiphindaphinda esixhunywe kukho?

gui_multiplier Multiplier Okokufaka Okuphindaphindayo

_okufakiwe

Okokufaka kweketango lokuskena

Incazelo
Kufanele ukhethe VARIABLE inani lokuthi Ithini ifomethi yokumelela okokufaka kwama-Multipliers B? ipharamitha ukuze unike amandla le nketho.
Khetha Iwashi0 , Iwashi1 noma Iwashi2 ukuze uvule futhi ucacise isignali yewashi yokufaka yerejista yezimpawu. Kufanele ukhethe okuthi Bhalisa `uphawu' ukuze unike amandla le parameter.
Icacisa umthombo ocacile ongavumelanisiwe werejista yophawu. Kufanele ukhethe okuthi Bhalisa `uphawu' ukuze unike amandla le parameter.
Icacisa umthombo ocacile ovunyelanisiwe werejista yophawu. Kufanele ukhethe okuthi Bhalisa `uphawu' ukuze unike amandla le parameter.
Khetha le nketho ukuze unike amandla irejista yokufaka yebhasi lokufaka idatha.
Khetha Iwashi0 , Iwashi1 noma Iwashi2 ukuze unike amandla futhi ucacise isignali yewashi yokufaka yerejista yebhasi yokufaka idatha. Kufanele ukhethe okuthi Bhalisa okokufaka A kwesiphindaphindayo ukuze unike amandla le pharamitha.
Icacisa umthombo ocacile werejista webhasi lokufaka idatha. Kufanele ukhethe okuthi Bhalisa okokufaka A kwesiphindaphindayo ukuze unike amandla le pharamitha.
Icacisa umthombo ocacile werejista webhasi lokufaka idatha. Kufanele ukhethe okuthi Bhalisa okokufaka A kwesiphindaphindayo ukuze unike amandla le pharamitha.
Khetha le nketho ukuze unike amandla irejista yokufaka yebhasi yokufaka idathab.
Khetha Iwashi0 , Iwashi1 noma Iwashi2 ukuze unike amandla futhi ucacise isignali yewashi yokufaka yerejista yebhasi yokufaka idathab. Kufanele ukhethe Bhalisa okokufaka B kwesiphindaphinda ukuze unike amandla le parameter.
Icacisa umthombo ocacile werejista webhasi lokufaka ledathab. Kufanele ukhethe Bhalisa okokufaka B kwesiphindaphinda ukuze unike amandla le parameter.
Icacisa umthombo ocacile werejista webhasi lokufaka ledathab. Kufanele ukhethe Bhalisa okokufaka B kwesiphindaphinda ukuze unike amandla le parameter.
Khetha umthombo wokufaka wokufaka A kwesiphindaphindayo.
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Ipharamitha

IP Ekhiqizwe Ipharamitha

Inani

Ukucushwa kwe-Scanout A Register

Bhalisa okukhiphayo kochungechunge lokuskena

gui_scanouta Vuliwe

_bhalisa

Valiwe

Uyini umthombo wokufakwa kwewashi?

gui_scanouta _register_clock k

Iwashi0 Iwashi1 Iwashi2

Uyini umthombo wokufaka okucacile kwe-asynchronous?

gui_scanouta _register_aclr

AKUKHO ACLR0 ACLR1

Uyini umthombo wokufaka okucacile okuvumelanayo?

gui_scanouta _register_sclr

AKUKHO SCLR0 SCLR1

8.6.4. Ithebhu Ye-Preadder

Ithebula 33. Ithebhu Ye-Preadder

Ipharamitha

IP Ekhiqizwe Ipharamitha

Inani

Khetha imodi ye-preadder

preadder_mo de

OKULULA, I-COEF, OKUFAKAYO, ISIkwele, OKUQHUBEKAYO

Inani elizenzakalelayo

Incazelo
Khetha okokufaka kokuphindaphinda ukuze usebenzise ibhasi lokufaka idatha njengomthombo wesiphindaphindi. Khetha okokufaka kochungechunge lokuskena ukuze usebenzise ibhasi lokufaka i-scanin njengomthombo wesiphindaphindi futhi unike amandla ibhasi eliphumayo lokuskena. Le parameter iyatholakala uma ukhetha 2, 3 noma 4 for Ithini inombolo yeziphindaphinda? ipharamitha.

Iwashi elivaliwe0 LUTHO LUTHO

Khetha le nketho ukuze unike amandla irejista yokuphumayo yebhasi eliphumayo le-scanouta.
Kufanele ukhethe okokufaka kweketango lokuskena kokuthi Yini okokufaka A kwesiphindaphindayo esixhunywe kuso? ipharamitha ukuze unike amandla le nketho.
Khetha Iwashi0 , Iwashi1 noma Iwashi2 ukuze unike amandla futhi ucacise isignali yewashi yokufaka yerejista yebhasi eliphumayo le-scanouta.
Kumelwe uvule ukubhalisa okukhiphayo kwepharamitha yechungechunge lokuskena ukuze unike amandla le nketho.
Icacisa umthombo ocacile werejista webhasi eliphumayo le-scanouta.
Kumelwe uvule ukubhalisa okukhiphayo kwepharamitha yechungechunge lokuskena ukuze unike amandla le nketho.
Icacisa umthombo ocacile werejista webhasi lokuphumayo le-scanouta.
Kufanele ukhethe Bhalisa okukhiphayo kwepharamitha yeketango lokuskena ukuze unike amandla le nketho.

Inani elizenzakalelayo
OKULULA

Incazelo
Icacisa imodi yokusebenza yemojuli yepreadder. OKULULA: Le modi yeqa i-preadder. Lena imodi ezenzakalelayo. I-COEF: Le modi isebenzisa okukhiphayo kwe-preadder kanye nebhasi yokufaka i-coefsel njengokufakwa kusiphindaphinda. OKUFAKAYO: Le modi isebenzisa okukhiphayo kwe-preadder kanye nebhasi yokufaka yedathac njengokufakwayo kusiphindaphindi. I-SQUARE: Le modi isebenzisa okukhiphayo kwepredida njengako kokubili okokufaka kusiphindaphindi.
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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Ipharamitha

IP Ekhiqizwe Ipharamitha

Inani

Khetha isiqondiso se-preadder

gui_preadder ADD,

_indlela

SUB

Kufanele abe ububanzi obungakanani amabhasi okokufaka we-C width_c?

1 – 256

Ukucushwa kwerejista yokufaka yedatha C

Bhalisa okokufaka kwedatha

gui_datac_inp Vuliwe

ut_bhalisa

Valiwe

Uyini umthombo wokufakwa kwewashi?

gui_datac_inp ut_register_cl ock

Iwashi0 Iwashi1 Iwashi2

Uyini umthombo wokufaka okucacile kwe-asynchronous?

gui_datac_inp ut_register_a clr

AKUKHO ACLR0 ACLR1

Uyini umthombo wokufaka okucacile okuvumelanayo?

gui_datac_inp ut_register_sc lr

AKUKHO SCLR0 SCLR1

Ama-Coefficients
Ububanzi bekhofu kufanele bube banzi kangakanani?

wide_coef

1 – 27

Ukulungiswa Kwerejista Ye-Coef

Bhalisa okokufaka kwe-coefsel

gui_coef_regi Vuliwe

ster

Valiwe

Uyini umthombo wokufakwa kwewashi?

gui_coef_regi ster_clock

Iwashi0 Iwashi1 Iwashi2

Inani elizenzakalelayo
ENGEZA
16

Incazelo
I-CONSTANT: Le modi isebenzisa ibhasi lokufakwayo kwedatha eline-preadder elidlule kanye nebhasi lokufaka le-coefsel njengokufakwa kusiphindaphindi.
Icacisa ukusebenza kwepredida. Ukuze unike amandla le parameter, khetha okulandelayo ukuze Khetha imodi yepreadder: · COEF · INPUT · SQUARE noma · CONSTANT
Icacisa inani lamabhithi ebhasi lokufaka elingu-C. Kufanele ukhethe i-INPUT ye-Khetha imodi ye-preadder ukuze unike amandla le pharamitha.

Ngewashi0 NONE NONE

Khetha le nketho ukuze unike amandla irejista yokufaka yebhasi lokufaka idathac. Kumelwe usethe INPUT ukuze Khetha ipharamitha yemodi ye-preadder ukuze unike amandla le nketho.
Khetha Iwashi0 , Iwashi1 noma Iwashi2 ukuze ucacise isignali yewashi yokufaka yerejista yokufaka idathac. Kufanele ukhethe Bhalisa okokufaka kwedatha ukuze unike amandla le pharamitha.
Icacisa umthombo ocacile ongavumelanisiwe werejista yokufaka yedatha. Kufanele ukhethe Bhalisa okokufaka kwedatha ukuze unike amandla le pharamitha.
Icacisa umthombo ocacile wokuvumelanisa werejista yokufaka yedatha. Kufanele ukhethe Bhalisa okokufaka kwedatha ukuze unike amandla le pharamitha.

Icacisa inani lamabhithi e

ibhasi lokufaka i-coefsel.

Kufanele ukhethe i-COEF noma i-CONSTANT yemodi ye-preadder ukuze unike amandla le pharamitha.

Ngewashi0

Khetha le nketho ukuze unike amandla irejista yokufaka yebhasi lokufaka i-coefsel. Kufanele ukhethe i-COEF noma i-CONSTANT yemodi ye-preadder ukuze unike amandla le pharamitha.
Khetha Iwashi0 , Iwashi1 noma Iwashi2 ukuze ucacise isignali yewashi yokufaka yerejista yokufaka ye-coefsel. Kufanele ukhethe Bhalisa okokufaka kwe-coefsel ukuze unike amandla le pharamitha.
waqhubeka...

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 52

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Ipharamitha
Uyini umthombo wokufaka okucacile kwe-asynchronous?

IP Ekhiqizwe Ipharamitha

Inani

gui_coef_regi ster_aclr

AKUKHO ACLR0 ACLR1

Uyini umthombo wokufaka okucacile okuvumelanayo

gui_coef_regi ster_sclr

AKUKHO SCLR0 SCLR1

I-Coefficient_0 Ukucushwa

i-coef0_0 kuya ku-coef0_7

0x00000 0xFFFFFF

I-Coefficient_1 Ukucushwa

i-coef1_0 kuya ku-coef1_7

0x00000 0xFFFFFF

I-Coefficient_2 Ukucushwa

i-coef2_0 kuya ku-coef2_7

0x00000 0xFFFFFF

I-Coefficient_3 Ukucushwa

i-coef3_0 kuya ku-coef3_7

0x00000 0xFFFFFF

8.6.5. Ithebhu ye-Accumulator

Ithebula 34. Ithebhu Ye-accumulator

Ipharamitha

IP Ekhiqizwe Ipharamitha

Inani

Nika amandla i-accumulator?

i-accumulator

YEBO CHA

Luyini uhlobo lomsebenzi we-accumulator?

accum_directi ADD,

SUB

Inani elizenzakalelayo LAYIKHO
AKUKHO
0x0000000 0
0x0000000 0
0x0000000 0
0x0000000 0

Incazelo
Icacisa umthombo ocacile ongavumelanisiwe werejista yokufaka ye-coefsel. Kufanele ukhethe Bhalisa okokufaka kwe-coefsel ukuze unike amandla le pharamitha.
Icacisa umthombo ocacile wokuvumelanisa werejista yokufaka ye-coefsel. Kufanele ukhethe Bhalisa okokufaka kwe-coefsel ukuze unike amandla le pharamitha.
Icacisa amanani e-coefficient alesi siphindaphindi sokuqala. Inombolo yamabhithi kufanele ifane naleyo eshiwo kokuthi Ububanzi bekhofu kufanele bube bukhulu kangakanani? ipharamitha. Kufanele ukhethe i-COEF noma i-CONSTANT yemodi ye-preadder ukuze unike amandla le pharamitha.
Icacisa amanani e-coefficient alesi siphindaphindi sesibili. Inombolo yamabhithi kufanele ifane naleyo eshiwo kokuthi Ububanzi bekhofu kufanele bube bukhulu kangakanani? ipharamitha. Kufanele ukhethe i-COEF noma i-CONSTANT yemodi ye-preadder ukuze unike amandla le pharamitha.
Icacisa amanani e-coefficient alesi siphindaphindi sesithathu. Inombolo yamabhithi kufanele ifane naleyo eshiwo kokuthi Ububanzi bekhofu kufanele bube bukhulu kangakanani? ipharamitha. Kufanele ukhethe i-COEF noma i-CONSTANT yemodi ye-preadder ukuze unike amandla le pharamitha.
Icacisa amanani e-coefficient alesi siphindaphindi sesine. Inombolo yamabhithi kufanele ifane naleyo eshiwo kokuthi Ububanzi bekhofu kufanele bube bukhulu kangakanani? ipharamitha. Kufanele ukhethe i-COEF noma i-CONSTANT yemodi ye-preadder ukuze unike amandla le pharamitha.

Inani elizenzakalelayo NO
ENGEZA

Incazelo
Khetha okuthi YEBO ukuze unike amandla i-accumulator. Kufanele ukhethe Bhalisa okukhiphayo kweyunithi ye-adder uma usebenzisa isici se-accumulator.
Icacisa ukusebenza kwe-accumulator: · ENGEZA umsebenzi wokwengeza · SUB ukuze usebenze ngokukhipha. Kufanele ukhethe okuthi YEBO ukuze uvule i-accumulator? ipharamitha ukuze unike amandla le nketho.
waqhubeka...

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 53

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Ipharamitha
Layisha ngaphambilini Constant Vumela ukulayisha kuqala okungaguquki

IP Ekhiqizwe Ipharamitha

Inani

gui_ena_prelo On

isikhangiso_const

Valiwe

Kuyini okokufaka kwembobo enqwabelene exhunywe kuyo?

gui_accumula ACCUM_SLOAD, te_port_select SLOAD_ACCUM

Khetha inani lokulayisha kuqala i-loadconst_val 0 – 64

njalo

Uyini umthombo wokufakwa kwewashi?

gui_accum_sl oad_register_ iwashi

Iwashi0 Iwashi1 Iwashi2

Uyini umthombo wokufaka okucacile kwe-asynchronous?

gui_accum_sl oad_register_ aclr

AKUKHO ACLR0 ACLR1

Uyini umthombo wokufaka okucacile okuvumelanayo?

gui_acum_sl oad_register_ sclr

AKUKHO SCLR0 SCLR1

Nika amandla i-accumulator ekabili

gui_double_a Vuliwe

ccm

Valiwe

Inani elizenzakalelayo

Incazelo

Valiwe

Nika amandla i-accum_sload noma

sload_accum amasignali kanye nerejista yokufaka

ukuze ukhethe ngokushintshayo okokufaka ku

i-accumulator.

Uma i-accum_sload iphansi noma i-sload_accum, okokukhiphayo kwesiphindaphindayo kufakwa ku-accumulator.

Uma i-accum_sload iphezulu noma i-sload_acum, umsebenzisi oshiwo ukulayisha kuqala okungaguquki kuphakela ku-accumulator.

Kufanele ukhethe okuthi YEBO ukuze uvule i-accumulator? ipharamitha ukuze unike amandla le nketho.

ACCUM_SL OAD

Icacisa ukuziphatha kwesignali ye-accum_sload/sload_accum.
ACCUM_SLOAD: Shayela i-accum_sload low ukuze ulayishe okukhiphayo kwesiphindaphindayo ku-accumulator.
SLOAD_ACCUM: Shayela sload_accum phezulu ukuze ulayishe okukhiphayo okuphindaphindayo ku-accumulator.
Kufanele ukhethe Vumela inketho yokulayisha kuqala engaguquki ukuze unike amandla le pharamitha.

Cacisa inani elimisiwe eliqhubekayo.

Leli nani lingaba ngu-2N lapho okuthi N kuyinani elingaguquki elisethiwe kusengaphambili.

Uma i-N=64, imele uziro ongashintshi.

Kufanele ukhethe Vumela inketho yokulayisha kuqala engaguquki ukuze unike amandla le pharamitha.

Isikhathi C0

Khetha Iwashi0 , Iwashi1 noma Iwashi2 ukuze ucacise isignali yewashi yokufaka yerejista ye-accum_sload/sload_accum.
Kufanele ukhethe Vumela inketho yokulayisha kuqala engaguquki ukuze unike amandla le pharamitha.

AKUKHO

Icacisa umthombo ocacile ongavumelanisiwe werejista ye-accum_sload/sload_accum.
Kufanele ukhethe Vumela inketho yokulayisha kuqala engaguquki ukuze unike amandla le pharamitha.

AKUKHO

Icacisa umthombo ocacile ovumelanisiwe werejista ye-accum_sload/sload_accum.
Kufanele ukhethe Vumela inketho yokulayisha kuqala engaguquki ukuze unike amandla le pharamitha.

Valiwe

Inika amandla irejista ye-accumulator ekabili.

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 54

Thumela Impendulo

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

8.6.6. Ithebhu ye-Systolic/Chainout

Ithebula 35. Ithebhu ye-Systolic/Chainout Adder

Ipharamitha Vumela i-chainout adder

IP Ekhiqizwe Ipharamitha

Inani

chainout_engeza YEBO,

CHA

Luyini uhlobo lwe-chainout adder?

chainout_engeza ADD,

er_direction

SUB

Nika amandla okokufaka `kokuphika' kwe-adder ye-chainout?

I-Port_negate

PORT_USED, PORT_UNUSED

Bhalisa `ukuphika' okokufaka? negate_regist er

AYIBHALISIWE, IWASHI0, IWASHI1, IWASHI2, IWASHI3

Uyini umthombo wokufaka okucacile kwe-asynchronous?

negate_aclr

AKUKHO ACLR0 ACLR1

Uyini umthombo wokufaka okucacile okuvumelanayo?

negate_sclr

AKUKHO SCLR0 SCLR1

Ukubambezeleka kwe-Systolic
Nika amandla amarejista okulibaziseka kwe-systolic

gui_systolic_d Vuliwe

ela

Valiwe

Uyini umthombo wokufakwa kwewashi?

gui_systolic_d IWASHI0,

elay_clock

IWASHI1,

Inani elizenzakalelayo
CHA

Incazelo
Khetha okuthi YEBO ukuze unike amandla imojula ye-adder ye-chainout.

ENGEZA

Icacisa ukusebenza kwe-adder ye-chainout.
Ngomsebenzi wokukhipha, SAYINWE kufanele kukhethelwe Iyiphi ifomethi yokumelela okokufaka kwe-Multipliers A? futhi Ithini ifomethi yokumelela okokufaka kwe-Multipliers B? kuthebhu Yokuphindaphinda.

PORT_UN USED

Khetha i-PORT_USED ukuze unike amandla isignali yokufaka yokuphika.
Le pharamitha ayivumelekile uma i-chainout adder ivaliwe.

Susa ukubhalisa u-ERED

Ukuze unike amandla irejista yokufaka yesiginali yokufaka ephambene futhi ucacise isignali yewashi yokufaka yerejista ephikayo.
Khetha OKUNGABHALISI uma irejista yokufaka yokuphika ingadingeki
Le parameter ayivumelekile uma ukhetha:
· CHA ukuze Vumela i-chainout adder noma
· PORT_UNUSED yokunika amandla okokufaka kwe-'negate' kwe-chainout adder? ipharamitha noma

AKUKHO

Icacisa umthombo ocacile ongavumelanisiwe werejista ephikayo.
Le parameter ayivumelekile uma ukhetha:
· CHA ukuze Vumela i-chainout adder noma
· PORT_UNUSED yokunika amandla okokufaka kwe-'negate' kwe-chainout adder? ipharamitha noma

AKUKHO

Icacisa umthombo ocacile ovumelanisiwe werejista ephikayo.
Le parameter ayivumelekile uma ukhetha:
· CHA ukuze Vumela i-chainout adder noma
· PORT_UNUSED yokunika amandla okokufaka kwe-'negate' kwe-chainout adder? ipharamitha noma

Iwashi elivaliwe0

Khetha le nketho ukuze unike amandla imodi ye-systolic. Le parameter iyatholakala uma ukhetha 2, noma 4 for What is the number of multipliers? ipharamitha. Kufanele uvumele ukukhishwa kweRejista yeyunithi ye-adder ukuze usebenzise amarejista okulibaziseka kwe-systolic.
Icacisa isignali yewashi lokufaka lerejista yokubambezeleka kwe-systolic.
waqhubeka...

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 55

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Ipharamitha

IP Ekhiqizwe Ipharamitha

Inani

IWASHI2,

Uyini umthombo wokufaka okucacile kwe-asynchronous?

gui_systolic_d elay_aclr

AKUKHO ACLR0 ACLR1

Uyini umthombo wokufaka okucacile okuvumelanayo?

gui_systolic_d elay_sclr

AKUKHO SCLR0 SCLR1

Inani elizenzakalelayo
AKUKHO
AKUKHO

Incazelo
Kufanele ukhethe ukunika amandla amarejista okulibaziseka kwe-systolic ukuze unike amandla le nketho.
Icacisa umthombo ocacile ongavumelanisiwe werejista yokubambezeleka kwe-systolic. Kufanele ukhethe ukunika amandla amarejista okulibaziseka kwe-systolic ukuze unike amandla le nketho.
Icacisa umthombo ocacile wokuvumelanisa werejista yokubambezeleka kwe-systolic. Kufanele ukhethe ukunika amandla amarejista okulibaziseka kwe-systolic ukuze unike amandla le nketho.

8.6.7. Ithebhu yokufaka amapayipi

Ithebula 36. Ithebhu yokufaka amapayipi

Ukucushwa Kokufakwa Kwepharamitha

IP Ekhiqizwe Ipharamitha

Inani

Uyafuna ukwengeza irejista yamapayipi kokokufaka?

gui_pipelining Cha, Yebo

Inani elizenzakalelayo
Cha

Sicela ucacise i

ukubambezeleka

inombolo yewashi lewashi

imijikelezo

Noma yiliphi inani elikhulu kuno-0

Uyini umthombo wokufakwa kwewashi?

gui_input_late ncy_clock

IWASHI0, IWASHI1, IWASHI2

Uyini umthombo wokufaka okucacile kwe-asynchronous?

gui_input_late ncy_aclr

AKUKHO ACLR0 ACLR1

Uyini umthombo wokufaka okucacile okuvumelanayo?

gui_input_late ncy_sclr

AKUKHO SCLR0 SCLR1

IWASHI0 LUTHO LUTHO

Incazelo
Khetha Yebo ukuze unike amandla izinga elengeziwe lerejista yamapayipi kumasignali okokufaka. Kumelwe ucacise inani elikhulu kuno-0 kokuthi Sicela ucacise inombolo yepharamitha yemijikelezo yewashi lokubambezeleka.
Icacisa ukubambezeleka okufunayo emijikelezweni yewashi. Ileveli eyodwa yerejista yamapayipi = ukubambezeleka okungu-1 kumjikelezo wewashi. Kufanele ukhethe okuthi YEBO kokuthi Ingabe ufuna ukwengeza irejista yamapayipi kokufakwayo? ukuze unike amandla le nketho.
Khetha Iwashi0 , Iwashi1 noma Iwashi2 ukuze unike amandla futhi ucacise isignali yewashi yokufaka irejista yephayiphi. Kufanele ukhethe okuthi YEBO kokuthi Ingabe ufuna ukwengeza irejista yamapayipi kokufakwayo? ukuze unike amandla le nketho.
Icacisa irejista yomthombo ocacile ongavumelanisiwe werejista yamapayipi eyengeziwe. Kufanele ukhethe okuthi YEBO kokuthi Ingabe ufuna ukwengeza irejista yamapayipi kokufakwayo? ukuze unike amandla le nketho.
Icacisa irejista yomthombo ocacile ovumelanayo werejista yamapayipi eyengeziwe. Kufanele ukhethe okuthi YEBO kokuthi Ingabe ufuna ukwengeza irejista yamapayipi kokufakwayo? ukuze unike amandla le nketho.

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 56

Thumela Impendulo

683490 | 2020.10.05 Thumela Impendulo

9. I-ALTMEMMULT (I-Memory-based Constant Coefficient Multiplier) IP Core

Qaphela:

I-Intel isuse ukusekelwa kwale IP ku-Intel Quartus Prime Pro Edition 20.3. Uma i-IP eyinhloko eklanyweni yakho iqondise amadivayisi aku-Intel Quartus Prime Pro Edition, ungakwazi esikhundleni se-IP ufake i-LPM_MULT Intel FPGA IP noma ukhiqize kabusha i-IP futhi uhlanganise umklamo wakho usebenzisa isofthiwe ye-Intel Quartus Prime Standard Edition.

I-ALTMEMMULT IP core isetshenziselwa ukwakha iziphindaphinda ezisekelwe kumemori kusetshenziswa amabhulokhi ememori ye-onchip atholakala ku-Intel FPGAs (ene-M512, M4K, M9K, ne-MLAB memory block). Lo mnyombo we-IP uwusizo uma ungenazo izinsiza ezanele zokuqalisa iziphindaphindi kuzinto ezinengqondo (ama-LE) noma izinsiza zokuphindaphinda ezizinikele.
I-ALTMEMMULT IP core iwumsebenzi wokuvumelanisa odinga iwashi. I-ALTMEMMULT IP core isebenzisa isiphindaphinda esinomthamo omncane kakhulu nokubambezeleka okungaba khona kusethi enikeziwe yamapharamitha kanye nokucaciswa.
Umfanekiso olandelayo ubonisa izimbobo ze-ALTMEMMULT IP core.

Umfanekiso 21. Amachweba we-ALTMEMMULT

I-ALTMEMMULT

idatha_in[] sload_data coeff_in[]

umphumela[] umphumela_ulayishiwe_ovumelekile

sload_coeff

iwashi le-sclr
inst

Izici Zokwaziswa Okuhlobene ekhasini 71

9.1. Izici
I-ALTMEMMULT IP core inikeza izici ezilandelayo: · Idala kuphela iziphindaphinda ezisekelwe kumemori isebenzisa amabhulokhi ememori e-on-chip atholakala ku-
Intel FPGAs · Isekela ububanzi bedatha obungamabhithi angu-1 · Isekela ifomethi yokumelela idatha engasayiniwe nengabhalisiwe · Isekela ukufakwa kwamapayipi ngokubambezeleka okungaguquki

I-ISO 9001:2015 Ibhalisiwe

9. I-ALTMEMMULT (I-Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05
· Igcina ama-multiples constants kumemori yokufinyelela okungahleliwe (RAM)
· Inikeza inketho yokukhetha uhlobo lwe-RAM block
· Isekela izimbobo zokufaka ezicacile ezivumelanayo ozikhethelayo nezilawula umthwalo
9.2. I-Verilog HDL Prototype
Lesi sibonelo esilandelayo se-Verilog HDL sitholakala ku-Verilog Design File (.v) i-altera_mf.v ku eda synthesis directory.
module altmemmult #( ipharamitha coeff_representation = “ISAYINIWE”, ipharamitha coefficient0 = “OKUNGASETSHENZISIWE”, ipharamitha_representation yedatha = “SIGNED”, ipharamitha target_device_family = “engasetshenzisiwe”, ipharamitha max_clock_cycles_per_result = 1, ipharamitha yepharamitha =1, ipharamitha_uhlobo_lwesivimbeli =1, ipharamitha_uhlobo_lwesivimbeli =1, ipharamitha_uhlobo olufanele total_latency = 1, ipharamitha ububanzi_c = 1, ububanzi bepharamitha_d = 1, ipharamitha ububanzi_r = 1, ububanzi bepharamitha_s = 0, ipharamitha lpm_type = “altmemmult”, ipharamitha lpm_hint = “engasetshenzisiwe”) ( iwashi lentambo yokufaka, intambo yokufaka [width_c-1: 0]i-coeff_in, i-input wire [width_d-1:0] data_in, i-output wire load_yenziwe, umphumela wentambo yokukhiphayo [width_r-1:0] umphumela, i-output wire result_valid, i-input wire sclr, i-input wire [width_s-1:XNUMX] sel, input wire sload_coeff, wire wire sload_data)/* synthesis syn_black_box=XNUMX */; endmodule
9.3. Isimemezelo Sengxenye Ye-VHDL
Isimemezelo sengxenye ye-VHDL sitholakala ku-VHDL Design File (.vhd) altera_mf_components.vhd ku librariesvhdlaltera_mf directory.
ingxenye ye-altmemmult generic ( coeff_representation:string := “SIGNED”; coefficient0:string := “AKUSETSHENZISWA”; data_representation:string := “SIGNED”; intention_device_family:string := “unused”; max_clock_cycles_per_result:_result_1 := 1; ram_block_type:string := “AUTO”; total_latency:natural; width_c:natural; width_d:natural; width_r:natural; wide_s:natural := 1; lpm_hint:string := "AKUSUSEKIWE"; lpm_type:string := "altmemmult"); port( iwashi:ku-std_logic; coeff_in:in std_logic_vector(width_c-1 downto 0) := (abanye => '0'); idatha_in:ku-std_logic_vector(width_d-1 downto 0);

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 58

Thumela Impendulo

9. I-ALTMEMMULT (I-Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

load_done:out std_logic; umphumela: out std_logic_vector(width_r-1 downto 0); umphumela_uvumelekile:out std_logic; sclr:in std_logic := '0'; sel:ku-std_logic_vector(width_s-1 downto 0) := (abanye => '0'); sload_coeff:in std_logic := '0'; sload_data:in std_logic := '0'); ingxenye yokugcina;

9.4. Amachweba

Amathebula alandelayo aklelisa izimbobo zokufaka neziphumayo ze-ALTMEMMULT IP core.

Ithebula 37. I-ALTMEMMULT Izimbobo Zokufaka

Igama Lembobo

Kudingeka

Incazelo

iwashi

Yebo

Okokufaka kwewashi kusiphindaphindi.

coeff_in[]

Cha

Imbobo yokufaka ye-coefficient yesiphindaphindi. Usayizi wembobo yokufaka uncike enanini lepharamitha engu-WIDTH_C.

idatha_ku[]

Yebo

Imbobo yokufaka idatha kuya kusiphindaphinda. Usayizi wembobo yokufaka uncike enanini lepharamitha engu-WIDTH_D.

sclr

Cha

Okokufaka okucacile okuvumelanayo. Uma ingasetshenziswanga, inani elizenzakalelayo liphezulu.

sel[]

Cha

Ukukhethwa kwe-coefficient engashintshi. Usayizi wembobo yokufaka uncike ku-WIDTH_S

inani lepharamitha.

sload_coeff

Cha

Imbobo yokufaka ye-coefficient yokulayisha ehambisanayo. Ifaka esikhundleni senani le-coefficient elikhethiwe lamanje ngenani elishiwo kokokufaka kwe-coeff_in.

idatha_ye-sload

Cha

Imbobo yokufaka idatha yokulayisha evumelanisiwe. Isiginali ecacisa umsebenzi omusha wokuphindaphinda futhi ikhansela noma yimuphi umsebenzi okhona wokuphindaphinda. Uma ipharamitha engu-MAX_CLOCK_CYCLES_PER_RESULT inenani elingu-1, imbobo yokufaka ye-sload_data ishaywa indiva.

Ithebula 38. ATMEMMULT Izimbobo Zokuphuma

Igama Lembobo

Kudingeka

Incazelo

umphumela[]

Yebo

Imbobo yokukhipha ephindaphindayo. Usayizi wembobo yokufaka uncike enanini lepharamitha engu-WIDTH_R.

umphumela_uvumelekile

Yebo

Ibonisa lapho okukhiphayo kuwumphumela ovumelekile wokuphindaphinda okuphelele. Uma ipharamitha engu-MAX_CLOCK_CYCLES_PER_RESULT inenani elingu-1, imbobo yokukhiphayo evumelekile ayisetshenziswa.

layisha_kwenziwe

Cha

Ibonisa ukuthi i-coefficient entsha iqedile nini ukulayisha. Isiginali ye-load_done igomela lapho i-coefficient entsha iqedile ukulayisha. Ngaphandle uma isignali ye-load_done iphezulu, alikho elinye inani le-coefficient elingalayishwa kumemori.

9.5. Amapharamitha

Ithebula elilandelayo libala imingcele ye-ALTMEMMULT IP core.

Ithebula 39.
WIDTH_D WIDTH_C

Amapharamitha we-ALTMEMMULT
Igama lepharamitha

Uhlobo Oludingekayo

Incazelo

Inombolo ephelele Yebo

Icacisa ububanzi bembobo yedatha_in[].

Inombolo ephelele Yebo

Icacisa ububanzi bembobo ye-coeff_in[]. waqhubeka...

Thumela Impendulo

Intel FPGA Integer Arithmetic IP Cores Umhlahlandlela Womsebenzisi 59

9. I-ALTMEMMULT (I-Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

Igama lepharamitha WIDTH_R WIDTH

Amadokhumenti / Izinsiza

Intel FPGA Integer Arithmetic IP Cores [pdf] Umhlahlandlela Womsebenzisi
I-FPGA Integer Arithmetic IP Cores, Integer Arithmetic IP Cores, Arithmetic IP Cores, IP Cores

Izithenjwa

Imaniwali yosebenzisayo

I-FPGA Integer Arithmetic IP Cores

Amadokhumenti / Izinsiza

Izithenjwa

Shiya amazwana

Khansela impendulo

I-FPGA Integer Arithmetic IP Cores

Amadokhumenti / Izinsiza

Izithenjwa

Okuthunyelwe Okuhlobene

Shiya amazwana

Khansela impendulo