intel FPGA Integer Arithmetic IP ohun kohun olumulo Itọsọna

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FPGA Integer Arithmetic IP ohun kohun

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Intel FPGA Integer Iṣiro Itọnisọna Olumulo Awọn ohun kohun IP
Imudojuiwọn fun Intel® Quartus® Prime Design Suite: 20.3

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ID: 683490 Ẹya: 2020.10.05

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1. Intel FPGA Integer Awọn ohun kohun IP Iṣiro………………………………………………………………………………………….. 5
2. LPM_COUNTER (Otaju) IP Core……………………………………………………………………………………………………….. 7 2.1. Awọn ẹya …………………………………………………………………………………………………………………………………… 7 2.2. Verilog HDL Afọwọkọ……………………………………………………………………………………………………….. 8 2.3. Ikede paati VHDL……………………………………………………………………………………………….8 2.4. Ìkéde VHDL LIBRARY_USE……………………………………………………………………………………………………………… Awọn ibudo ………………………………………………………………………………………………………………………………………………….9 2.5. Awọn paramita …………………………………………………………………………………………………………………………………………………………………………………………
3. LPM_DIVIDE (Olupin) Intel FPGA IP Core……………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Awọn ẹya ………………………………………………………………………………………………………………………… 12 3.1. Verilog HDL Afọwọkọ……………………………………………………………………………………………………………………………… Ikede paati VHDL……………………………………………………………………………………….. 12 3.2. VHDL LIBRARY_Ipolongo………………………………………………………………………………………… 12 3.3. Awọn ibudo ………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Awọn paramita …………………………………………………………………………………………………………………………………………………………………………………………………
4. LPM_MULT (Ipo pupọ) IP Core………………………………………………………………………………………………………………………. 16 4.1. Awọn ẹya ………………………………………………………………………………………………………………………… 16 4.2. Verilog HDL Afọwọkọ……………………………………………………………………………………………………………………………………… 17 4.3. Ikede paati VHDL……………………………………………………………………………………….. 17 4.4. VHDL LIBRARY_Ipolongo………………………………………………………………………………………… 17 4.5. Awọn ifihan agbara……………………………………………………………………………………………………………………………………………………………………………………………………………… Awọn paramita fun Stratix V, Arria V, Cyclone V, ati Intel Cyclone 18 LP Awọn ẹrọ………………… 4.6 10. Taabu Gbogbogbo………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Gbogbogbo 18 Taabu……………………………………………………………………………………………………………………………………………… Taabu Pipin ………………………………………………………………………………………………………………………………………… Awọn paramita fun Intel Stratix 4.6.1, Intel Arria 18, ati Intel Cyclone 4.6.2 GX Awọn ẹrọ……….. 2 19. Taabu Gbogbogbo………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Gbogbogbo 4.6.3 Taabu……………………………………………………………………………………………………………………………………… 19 4.7. Pipelin …………………………………………………………………………………………………………………………………………………
5. LPM_ADD_SUB (Adder/Subtractor)………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Awọn ẹya ………………………………………………………………………………………………………………………… 22 5.1. Verilog HDL Afọwọkọ……………………………………………………………………………………………………………………………………………… 22 5.2. Ikede paati VHDL……………………………………………………………………………………….. 23 5.3. Ìkéde VHDL LIBRARY_LILO …………………………………………………………………………………………………. 23 5.4. Awọn ibudo ………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Awọn paramita …………………………………………………………………………………………………………………………………………………………………………………………
6. LPM_COMPARE (Comparator)………………………………………………………………………………………………………………………………………………………………………………….26 6.1. Awọn ẹya ………………………………………………………………………………………………………………………… 26 6.2. Verilog HDL Afọwọkọ……………………………………………………………………………………………………………………………………… 27 6.3. Ikede paati VHDL……………………………………………………………………………………….. 27 6.4. VHDL LIBRARY_Ipolongo………………………………………………………………………………………… 27 6.5. Awọn ibudo ………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Awọn paramita …………………………………………………………………………………………………………………………………………………………………………………………

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 2

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7. ALTECC (Koodu Atunse Aṣiṣe: Encoder/Decoder) IP Core……………………………………………… 30
7.1. ALTECC Awọn ẹya ara ẹrọ koodu………………………………………………………………………………………………………..31 7.2. Verilog HDL Afọwọkọ (ALTECC_ENCODER)………………………………………………………………………………. 32 7.3. Verilog HDL Afọwọkọ (ALTECC_DECODER)………………………………………………………………………………. 32 7.4. Ikede paati VHDL (ALTECC_ENCODER)……………………………………………………………………………………… Ikede paati VHDL (ALTECC_DECODER)……………………………………………………………………………… Ìkéde VHDL LIBRARY_LILO …………………………………………………………………………………………………. 33 7.5. Awọn ibudo koodu ……………………………………………………………………………………………………………………… 33 7.6. Awọn ibudo Decoder ………………………………………………………………………………………………………………………………………………………… 33 7.7. Awọn paramita koodu……………………………………………………………………………………………………………………… 33 7.8. Awọn paramita Decoder …………………………………………………………………………………………………………………………………
8. Intel FPGA isodipupo Adder IP Core…………………………………………………………………………………………………………………. 36
8.1. Awọn ẹya ………………………………………………………………………………………………………………………… 37 8.1.1. Pre-adder……………………………………………………………………………………………………………………….. 38 8.1.2. Iforukọsilẹ Idaduro Systolic……………………………………………………………………………………….. 40 8.1.3. Ibakan ti a ti gbe-iṣaaju………………………………………………………………………………………………………………… 43 8.1.4. Akojo meji …………………………………………………………………………………………………………………………
8.2. Verilog HDL Afọwọkọ……………………………………………………………………………………………………………………………… 44 8.3. Ikede paati VHDL……………………………………………………………………………………….. 44 8.4. VHDL LIBRARY_Ipolongo………………………………………………………………………………………… 44 8.5. Awọn ifihan agbara………………………………………………………………………………………………………………………………………………………………………………………………………………………… Awọn paramita …………………………………………………………………………………………………………………………………………………………………………………………
8.6.1. Gbogbogbo taabu ............................................................................................................ Awọn ọna afikun Taabu……………………………………………………………………………………….. 47 8.6.2. Taabu Multipliers………………………………………………………………………………………………………….. 47 8.6.3. Taabu Preader……………………………………………………………………………………………………………… 49 8.6.4. Taabu Akojo………………………………………………………………………………………….. 51 8.6.5. Systolic/Chainout Taabu………………………………………………………………………………………………………. 53 8.6.6. Taabu Pipin …………………………………………………………………………………………………………………………………………………………………………………………………
9. ALTMEMMULT (Isọdipúpọ Ibakan ti o da lori iranti) IP Core……………………………… 57
9.1. Awọn ẹya ………………………………………………………………………………………………………………………… 57 9.2. Verilog HDL Afọwọkọ……………………………………………………………………………………………………………………………………… 58 9.3. Ikede paati VHDL……………………………………………………………………………………….. 58 9.4. Awọn ibudo ………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Awọn paramita …………………………………………………………………………………………………………………………………………………………………………………………………………
10. ALTMULT_ACCUM (Pipo-Ikojọpọ) IP Core……………………………………………………… 61
10.1. Awọn ẹya………………………………………………………………………………………………………………….. 62 10.2. Verilog HDL Afọwọkọ………………………………………………………………………………………………………..62 10.3. Ikede paati VHDL……………………………………………………………………………………………… 63 10.4. Ìkéde VHDL LIBRARY_LILO…………………………………………………………………………………………………….63 10.5. Awọn ibudo …………………………………………………………………………………………………………………………. 63 10.6. Awọn paramita……………………………………………………………………………………………………………………… 64
11. ALTMULT_ADD (Pọpọlọpọ-Adder) IP Core………………………………………………………………………………………..69
11.1. Awọn ẹya………………………………………………………………………………………………………………….. 71 11.2. Verilog HDL Afọwọkọ………………………………………………………………………………………………………..72 11.3. Ikede paati VHDL……………………………………………………………………………………………… 72 11.4. Ìkéde VHDL LIBRARY_USE………………………………………………………………………………

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Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 3

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11.5. Awọn ibudo …………………………………………………………………………………………………………………………. 72 11.6. Awọn paramita……………………………………………………………………………………………………………………… 73
12. ALTMULT_COMPLEX (Epo Multiplier) IP Core……………………………………………………………… 86 12.1. Ilọpo Idipọ………………………………………………………………………………………………………………… 86 12.2. Aṣoju Canonical……………………………………………………………………………………………………… 87 12.3. Aṣoju Iṣeduro …………………………………………………………………………………………………………. 87 12.4. Awọn ẹya ………………………………………………………………………………………………………………………….. 88 12.5. Verilog HDL Afọwọkọ………………………………………………………………………………………………………..88 12.6. Ikede paati VHDL……………………………………………………………………………………………………… 89 12.7. Ìkéde VHDL LIBRARY_LILO …………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Awọn ifihan agbara ………………………………………………………………………………………………………………………… 89 12.8. Awọn paramita……………………………………………………………………………………………………………………… 89
13. ALTSQRT (Integer Square Root) IP Core………………………………………………………………………………………………… Awọn ẹya………………………………………………………………………………………………………………….. 92 13.1. Verilog HDL Afọwọkọ……………………………………………………………………………………………………………….92 13.2. Ikede paati VHDL……………………………………………………………………………………………… 92 13.3. Ìkéde VHDL LIBRARY_LILO ………………………………………………………………………………………………………………………………………………………………………………………………………………………………………………… Awọn ibudo …………………………………………………………………………………………………………………………. 93 13.4. Awọn paramita……………………………………………………………………………………………………………………… 93
14. PARALLEL_ADD (Parallel Adder) IP Core……………………………………………………………………………….. 95 14.1. Ẹya……………………………………………………………………………………………………………………………………….95 14.2. Verilog HDL Afọwọkọ………………………………………………………………………………………………………..95 14.3. Ikede paati VHDL……………………………………………………………………………………………………… 96 14.4. Ìkéde VHDL LIBRARY_LILO ………………………………………………………………………………………………… Awọn ibudo …………………………………………………………………………………………………………………………. 96 14.5. Awọn paramita……………………………………………………………………………………………………………………… 96
15. Integer Arithmetic IP Cores Itọnisọna Olumulo Iwe Ipamọ Awọn iwe ipamọ ………………………………………… 98
16. Itan Atunyẹwo iwe fun Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP…. 99

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 4

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1. Intel FPGA Integer Arithmetic IP ohun kohun

O le lo awọn ohun kohun IP integer Intel® FPGA lati ṣe awọn iṣẹ ṣiṣe mathematiki ninu apẹrẹ rẹ.

Awọn iṣẹ wọnyi nfunni ni iṣelọpọ imọ-jinlẹ daradara diẹ sii ati imuse ẹrọ ju ifaminsi awọn iṣẹ tirẹ lọ. O le ṣe akanṣe awọn ohun kohun IP lati gba awọn ibeere apẹrẹ rẹ.

Awọn ohun kohun IP iṣiro integer ti pin si awọn ẹka meji wọnyi: · Library of parameterized modules (LPM) IP cores · Intel-specific (ALT) IP kores

Tabili ti o tẹle yii ṣe atokọ awọn ohun kohun IP odidi isiro.

Tabili 1.

Akojọ ti awọn IP ohun kohun

IP ohun kohun

LPM IP ohun kohun

LPM_COUNTER

LPM_DIVIDE

LPM_MULT

LPM_ADD_SUB
LPM_COMPARE
Intel-kan pato (ALT) IP ohun kohun ALTECC

Isẹ pariview Counter Divider Multiplier
Adder tabi subtractor Comparator
ECC Encoder/Decoder

Ẹrọ atilẹyin
Arria® II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone® IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP,
Intel Cyclone 10 GX, MAX® II, MAX V, MAX 10, Stratix® IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V tẹsiwaju…

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn ami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.

ISO 9001: 2015 forukọsilẹ

1. Intel FPGA Integer Arithmetic IP ohun kohun 683490 | 2020.10.05

IP Cores Intel FPGA Multiply Adder tabi ALTERA_MULT_ADD ALTMEMMULT
ALTMULT_ACCUM ALTMULT_ADD ALTMULT_COMPLEX
ALTSQRT
PARALLEL_ADD

Isẹ pariview Multiplier-Adder
Olupilẹṣẹ Ibakan ti o da lori iranti
Multiplier-Accumulator Multiplier-Adder
eka Multiplier
Odidi Square-Root
Parallel parallel

Ẹrọ atilẹyin
Arria V, Stratix V, Cyclone V, Intel Stratix 10, Intel Arria 10, Intel Cyclone
10 GX
Arria II GX, Arria II GZ, Arria V, Intel Arria 10 (Intel Quartus® Prime Standard Edition), Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Cyclone 10 LP, MAX II, MAX V, MAX 10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Intel Arria 10, Arria V, Arria V GZ, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Cyclone 10 GX, Intel Cyclone 10 LP, MAX 10, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V

Alaye ti o jọmọ
· Awọn FPGA Intel ati Awọn ẹrọ Itumọ Awọn Akọsilẹ
· Ifihan si Intel FPGA IP Cores Pese alaye siwaju sii nipa Intel FPGA IP Cores.
· Itọsọna olumulo Awọn Cores IP Lilefoofo-Point Pese alaye siwaju sii nipa Intel FPGA Lilefoofo-Point IP ohun kohun.
Ifihan si Intel FPGA IP Cores Pese alaye gbogbogbo nipa gbogbo awọn ohun kohun Intel FPGA IP, pẹlu parameterizing, ti ipilẹṣẹ, igbegasoke, ati simulating IP kohun.
Ṣiṣẹda Version-Ominira IP ati awọn iwe afọwọkọ Simulation Qsys Ṣẹda awọn iwe afọwọkọ iṣeṣiro ti ko nilo awọn imudojuiwọn afọwọṣe fun sọfitiwia tabi awọn iṣagbega ẹya IP.
· Iṣakoso Ise agbese Awọn ilana Awọn adaṣe to dara julọ fun iṣakoso daradara ati gbigbe ti iṣẹ akanṣe ati IP rẹ files.
· Integer Arithmetic IP Cores Itọsọna Olumulo Awọn iwe ipamọ iwe ni oju-iwe 98 Pese atokọ ti awọn itọsọna olumulo fun awọn ẹya ti tẹlẹ ti awọn ohun kohun IP Oniṣiriṣi Integer.

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 6

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2. LPM_COUNTER (Oju) IP mojuto

Olusin 1.

LPM_COUNTER IP mojuto jẹ counter alakomeji ti o ṣẹda awọn iṣiro soke, awọn iṣiro isalẹ ati awọn iṣiro oke tabi isalẹ pẹlu awọn abajade ti o to awọn bit 256 fifẹ.

Nọmba atẹle yii fihan awọn ebute oko oju omi fun LPM_COUNTER IP mojuto.

Awọn ibudo LPM_COUNTER

LPM_COUNTER

ssclr sload data []

q[]

imudojuiwọn

kootu

aclr fifuye aset

clk_en cnt_en cin
inst

2.1. Awọn ẹya ara ẹrọ
LPM_COUNTER IP mojuto nfunni ni awọn ẹya wọnyi: · Ṣe ipilẹṣẹ soke, isalẹ, ati awọn iṣiro oke/isalẹ · Ṣe ipilẹṣẹ awọn oriṣi counter wọnyi:
- Alakomeji pẹtẹlẹ – awọn iṣiro counter ti o bẹrẹ lati odo tabi awọn idinku ti o bẹrẹ lati 255
- Modulus – counter ti n pọ si tabi dinku lati iye modulus ti olumulo ti ṣalaye ati tun ṣe
Atilẹyin iyan amuṣiṣẹpọ ko o, fifuye, ati ṣeto awọn ibudo igbewọle · Atilẹyin iyan asynchronous ko o, fifuye, ati ṣeto awọn ibudo igbewọle · Atilẹyin iyan kika sise ati aago jeki igbewọle ebute oko · Atilẹyin iyan gbe-in ati ki o gbe-jade ebute oko

ISO 9001: 2015 forukọsilẹ

2. LPM_COUNTER (Oju) IP mojuto
683490 | 2020.10.05
2.2. Verilog HDL Afọwọkọ
Afọwọkọ Verilog HDL atẹle wa ni Apẹrẹ Verilog File (.v) lpm.v ninu awọn edasynthesis liana.
module lpm_counter (q, data, aago, cin, cout, clk_en, cnt_en, updown, aset, aclr, aload, sset, sclr, sload, eq); paramita lpm_type = "lpm_counter"; paramita lpm_width = 1; paramita lpm_modul = 0; paramita lpm_direction = “UNUSED”; paramita lpm_avalue = “UNUSED”; paramita lpm_svalue = "UNUSED"; paramita lpm_pvalue = “UNUSED”; paramita lpm_port_updown = "PORT_CONNECTIVITY"; paramita lpm_hint = “A ko lo”; igbejade [lpm_width-1:0] q; jade cout; àbájáde [15:0] eq; cin input; igbewọle [lpm_width-1: 0] data; aago titẹ sii, clk_en, cnt_en, updown; aset input, aclr, fifuye; igbewọle sset, sclr, sload; endmodule
2.3. Ikede paati VHDL
Ìkéde paati VHDL wa ninu Apẹrẹ VHDL File (.vhd) LPM_PACK.vhd ninu awọn librariesvhdllpm liana.
paati LPM_COUNTER jeneriki ( LPM_WIDTH: adayeba; LPM_MODULUS: adayeba: = 0; LPM_DIRECTION: okun: = "A ko lo"; LPM_AVALUE : okun : = "A ko lo"; LPM_SVALUE : okun : = "UNUSED" : OPIN PORT CONTROL : = "UNUSED" ; ; LPM_PVALUE : okun: = "A ko lo"; LPM_TYPE : okun : = L_COUNTER; ibudo (DATA : ninu std_logic_vector(LPM_WIDTH-1 titi de 0):= (OTHERS =>
'0'); Aago: ni std_logic; CLK_EN: ni std_logic: = '1'; CNT_EN: ni std_logic: = '1'; Igbesoke: ni std_logic: = '1'; SLOAD: ni std_logic: = '0'; SSET: ni std_logic: = '0'; SCLR: ni std_logic: = '0'; ALOAD: ni std_logic: = '0'; ASET: ni std_logic: = '0'; ACLR: ni std_logic: = '0'; CIN: ni std_logic: = '1'; COUT: jade std_logic: = '0'; Q: jade std_logic_vector (LPM_WIDTH-1 si isalẹ 0); EQ: jade std_logic_vector (15 si isalẹ 0));
paati ipari;

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 8

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2. LPM_COUNTER (Oju) IP mojuto 683490 | 2020.10.05

2.4. Ìkéde VHDL LIBRARY_USE
Ìkéde VHDL LIBRARY-LILO ko nilo ti o ba lo Ikede paati VHDL.
IKÚN Lpm; LO lpm.lpm_components.all;

2.5. Awọn ibudo

Awọn tabili atẹle ṣe atokọ awọn igbewọle ati awọn ebute agbejade fun LPM_COUNTER IP mojuto.

Tabili 2.

Awọn ibudo igbewọle LPM_COUNTER

Orukọ Port

Ti beere fun

Apejuwe

data[]

Rara

Iṣagbewọle data ti o jọra si counter. Iwọn ibudo titẹ sii da lori iye paramita LPM_WIDTH.

aago

Bẹẹni

Iṣagbewọle aago eti-daadaa.

clk_en

Rara

Aago mu titẹ sii ṣiṣẹ lati mu gbogbo awọn iṣẹ amuṣiṣẹpọ ṣiṣẹ. Ti o ba yọkuro, iye aiyipada jẹ 1.

cnt_en

Rara

Kika mu titẹ sii ṣiṣẹ lati mu kika naa kuro nigbati o ba sọ pe o lọ silẹ lai ni ipa lori sload, sset, tabi sclr. Ti o ba yọkuro, iye aiyipada jẹ 1.

imudojuiwọn

Rara

Ṣiṣakoso itọsọna ti kika. Nigbati a ba sọ pe o ga (1), itọsọna kika wa ni oke, ati nigbati o ba sọ pe kekere (0), itọsọna kika wa ni isalẹ. Ti a ba lo paramita LPM_DIRECTION, ibudo oke ko le sopọ. Ti a ko ba lo LPM_DIRECTION, ibudo oke jẹ iyan. Ti o ba yọkuro, iye aiyipada yoo wa ni oke (1).

cin

Rara

Gbe-ni si kekere-ibere bit. Fun awọn iṣiro soke, ihuwasi ti titẹ sii cin jẹ

aami si awọn ihuwasi ti cnt_en input. Ti o ba yọkuro, iye aiyipada jẹ 1

(VCC).

aclr

Rara

Iṣagbewọle ko o Asynchronous. Ti o ba jẹ pe aset ati aclr mejeeji ti lo ati fi idi rẹ mulẹ, aclr dojuti aset. Ti o ba yọkuro, iye aiyipada jẹ 0 (alaabo).

asese

Rara

Iṣagbewọle ṣeto asynchronous. Ntọkasi awọn abajade q[] bi gbogbo awọn 1s, tabi si iye ti a tọka nipasẹ paramita LPM_AVALUE. Ti o ba jẹ pe aset ati awọn ebute oko oju omi aclr mejeeji ti wa ni lilo ati fi idi rẹ mulẹ, iye ti ibudo aclr dojuiwọn iye ti ibudo dukia. Ti o ba yọkuro, iye aiyipada jẹ 0, alaabo.

fifuye

Rara

Iṣagbewọle fifuye Asynchronous ti o ṣe asynchronously kojọpọ counter pẹlu iye lori titẹ sii data. Nigbati o ba ti lo ibudo ẹru, ibudo data[] gbọdọ wa ni asopọ. Ti o ba yọkuro, iye aiyipada jẹ 0, alaabo.

sclr

Rara

Iṣagbewọle ko o Amuṣiṣẹpọ ti o ko counter lori eti aago ti nṣiṣe lọwọ atẹle. Ti o ba jẹ pe awọn sset ati awọn ebute oko oju omi sclr mejeeji ti wa ni lilo ati fi idi rẹ mulẹ, iye ti ibudo sclr yoo bori iye ti ibudo sset. Ti o ba yọkuro, iye aiyipada jẹ 0, alaabo.

ṣeto

Rara

Iṣagbewọle eto amuṣiṣẹpọ ti o ṣeto counter lori eti aago ti nṣiṣe lọwọ atẹle. Ni pato iye awọn abajade q bi gbogbo awọn 1s, tabi si iye ti a tọka nipasẹ paramita LPM_SVALUE. Ti o ba jẹ pe mejeeji sset ati awọn ebute oko oju omi sclr ti lo ati fi idi rẹ mulẹ,
iye ti ibudo sclr danu iye ti ibudo sset. Ti o ba yọkuro, iye aiyipada jẹ 0 (alaabo).

sload

Rara

Iṣagbewọle fifuye amuṣiṣẹpọ ti o gbe counter pẹlu data[] ni eti aago ti nṣiṣe lọwọ atẹle. Nigbati o ba ti lo sload ibudo, data[] ibudo gbọdọ wa ni ti sopọ. Ti o ba yọkuro, iye aiyipada jẹ 0 (alaabo).

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 9

2. LPM_COUNTER (Oju) IP mojuto 683490 | 2020.10.05

Tabili 3.

Awọn ibudo Ijade LPM_COUNTER

Orukọ Port

Ti beere fun

Apejuwe

q[]

Rara

Data o wu lati counter. Awọn iwọn ti awọn wu ibudo da lori awọn

LPM_WIDTH iye paramita. Boya q[] tabi o kere ju ọkan ninu awọn ibudo eq [15..0].

gbọdọ wa ni ti sopọ.

ek[15]

Rara

Counter iyipada koodu. Ibudo eq[15..0] ko wa ninu olootu paramita nitori paramita nikan ṣe atilẹyin AHDL.
Boya ibudo q[] tabi eq[] gbọdọ wa ni asopọ. Titi di awọn ebute oko oju omi c eq le ṣee lo (0 <= c <= 15). Awọn iye kika 16 ti o kere julọ nikan ni o jẹ iyipada. Nigbati iye kika ba jẹ c, abajade eqc jẹ wi pe o ga (1). Fun example, nigbati awọn kika ni 0, eq0 = 1, nigbati awọn kika ni 1, eq1 = 1, ati nigbati awọn kika ni 15, eq 15 = 1. Decoded o wu fun awọn iye kika ti 16 tabi o tobi beere ita iyipada. Awọn abajade eq [15..0] jẹ asynchronous si abajade q[].

kootu

Rara

Gbe-jade ibudo ti awọn counter ká MSB bit. O le ṣee lo lati sopọ si counter miiran lati ṣẹda counter nla kan.

2.6. Awọn ipin

Tabili ti o tẹle yii ṣe atokọ awọn paramita fun LPM_COUNTER IP mojuto.

Tabili 4.

Awọn paramita LPM_COUNTER

Orukọ paramita

Iru

LPM_WIDTH

Odidi

LPM_DIRECTION

Okun

LPM_MODULUS LPM_AVALUE

Odidi
Odidi / Okun

LPM_SVALUE LPM_HINT

Odidi / Okun
Okun

LPM_TYPE

Okun

Ti beere Bẹẹni Bẹẹkọ Bẹẹkọ
Rara Bẹẹkọ
Rara

Apejuwe
Pato awọn iwọn ti data[] ati q[] ibudo, ti wọn ba lo.
Awọn iye ti wa ni oke, isalẹ, ati Ailolo. Ti a ba lo paramita LPM_DIRECTION, ibudo oke ko le sopọ. Nigbati ibudo oke ko ba ti sopọ, LPM_DIRECTION paramita aiyipada iye ni UP.
Iwọn ti o pọju, pẹlu ọkan. Nọmba ti oto ipinle ni counter ká ọmọ. Ti iye fifuye ba tobi ju paramita LPM_MODULUS, ihuwasi counter ko ni pato.
Iye ibakan ti o jẹ ti kojọpọ nigbati dukia ti jẹri ga. Ti iye pàtó kan ba tobi ju tabi dogba si , ihuwasi ti counter jẹ ẹya aisọye (X) kannaa ipele, ibi ti jẹ LPM_MODULUS, ti o ba wa, tabi 2 ^ LPM_WIDTH. Intel ṣeduro pe ki o pato iye yii gẹgẹbi nọmba eleemewa fun awọn apẹrẹ AHDL.
Ibakan iye ti o ti wa ni ti kojọpọ lori awọn nyara eti ti awọn ibudo aago nigbati awọn sset ibudo ti wa ni wi ga. Intel ṣeduro pe ki o pato iye yii gẹgẹbi nọmba eleemewa fun awọn apẹrẹ AHDL.
Nigbati o ba tẹ ile-ikawe ti awọn modulu parameterized (LPM) ṣiṣẹ ni Apẹrẹ VHDL kan File (.vhd), o gbọdọ lo LPM_HINT paramita lati tokasi ohun Intel-kan pato paramita. Fun example: LPM_HINT = "CHAIN_SIZE = 8, ONE_INPUT_IS_CONSTANT = BẸẸNI"
Awọn aiyipada iye ti wa ni Ailolo.
Ṣe idanimọ ile-ikawe ti awọn modulu parameterized (LPM) orukọ nkan ni apẹrẹ VHDL files.
tesiwaju…

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 10

Fi esi ranṣẹ

2. LPM_COUNTER (Oju) IP mojuto 683490 | 2020.10.05

Orukọ paramita INTENDED_DEVICE_FAMILY CARRY_CNT_EN
LABWIDE_SCLR
LPM_PORT_UPDOWN

Tẹ Okun Okun
Okun
Okun

Ti beere fun Bẹẹkọ
Rara
Rara

Apejuwe
A lo paramita yii fun apẹrẹ ati awọn idi kikopa ihuwasi. A lo paramita yii fun apẹrẹ ati awọn idi kikopa ihuwasi. Olootu paramita ṣe iṣiro iye fun paramita yii.
paramita kan pato Intel. O gbọdọ lo paramita LPM_HINT lati ṣe pato paramita CARRY_CNT_EN ni apẹrẹ VHDL files. Awọn iye jẹ SMART, ON, PA, ati LAILO. Mu iṣẹ LPM_COUNTER ṣiṣẹ lati tan ifihan agbara cnt_en nipasẹ ẹwọn gbigbe. Ni awọn igba miiran, eto paramita CARRY_CNT_EN le ni ipa diẹ lori iyara, nitorina o le fẹ lati paa. Iwọn aiyipada jẹ SMART, eyiti o pese iṣowo-pipa ti o dara julọ laarin iwọn ati iyara.
paramita kan pato Intel. O gbọdọ lo paramita LPM_HINT lati ṣe pato paramita LABWIDE_SCLR ni apẹrẹ VHDL files. Awọn iye wa ni TAN, PA, tabi Ailolo. Awọn aiyipada iye ti wa ni ON. Gba ọ laaye lati mu lilo ẹya LABwide sclr ti a rii ni awọn idile ẹrọ ti o ti bajẹ. Pa aṣayan yii pọ si awọn aye lati lo awọn LAB ti o kun ni kikun, ati nitorinaa o le gba iwuwo oye ti o ga julọ nigbati SCLR ko kan LAB pipe. Paramita yii wa fun ibaramu sẹhin, ati Intel ṣeduro rẹ lati ma lo paramita yii.
Ntọkasi lilo ibudo igbewọle updown. Ti o ba yọkuro iye aiyipada ni PORT_CONNECTIVITY. Nigbati iye ibudo ti ṣeto si PORT_USED, a tọju ibudo naa bi lilo. Nigbati iye ibudo ti ṣeto si PORT_UNUSED, a tọju ibudo naa bi a ko lo. Nigbati iye ibudo ti ṣeto si PORT_CONNECTIVITY, lilo ibudo naa jẹ ipinnu nipasẹ ṣiṣe ayẹwo Asopọmọra ibudo.

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 11

683490 | 2020.10.05 Firanṣẹ esi

3. LPM_DIVIDE (Divide) Intel FPGA IP mojuto

Olusin 2.

LPM_DIVIDE Intel FPGA IP mojuto n ṣe imuse olupin kan lati pin iye igbewọle numerator nipasẹ iye igbewọle iyeida kan lati ṣe agbejade ipin ati iyoku kan.

Nọmba atẹle yii fihan awọn ebute oko oju omi fun LPM_DIVIDE IP mojuto.

Awọn ibudo LPM_DIVIDE

LPM_DIVIDE

numer[] denom[] aago

iye to ku[]

clken aclr

inst

3.1. Awọn ẹya ara ẹrọ
LPM_DIVIDE IP mojuto n funni ni awọn ẹya wọnyi: · Ṣe ipilẹṣẹ alapin ti o pin iye igbewọle numerator nipasẹ igbewọle iyeida
iye lati gbejade iye ati iyokù. · Atilẹyin data iwọn ti 1 die-die. · Ṣe atilẹyin ọna kika aṣoju data ti a fowo si ati ti a ko fowo si fun oni nọmba mejeeji
ati iyeida iyeida. · Atilẹyin agbegbe tabi iyara ti o dara ju. · Pese ohun aṣayan lati pato kan rere aloku o wu. · Atilẹyin pipelining Configurable o wu lairi. · Atilẹyin iyan asynchronous ko o ati aago jeki ebute oko.

3.2. Verilog HDL Afọwọkọ
Afọwọkọ Verilog HDL atẹle wa ni Apẹrẹ Verilog File (.v) lpm.v ninu awọn edasynthesis liana.
module lpm_divide (iye, ku, numer, denom, aago, klken, aclr); paramita lpm_type = "lpm_divide"; paramita lpm_widthn = 1; paramita lpm_widthd = 1; paramita lpm_nrepresentation = "UNSIGNED"; paramita lpm_drepresentation = "UNSIGNED"; paramita lpm_remainderpositive = "TÒÓTỌ"; paramita lpm_pipeline = 0;

ISO 9001: 2015 forukọsilẹ

3. LPM_DIVIDE (Divide) Intel FPGA IP mojuto 683490 | 2020.10.05

paramita lpm_hint = “A ko lo”; aago titẹ sii; klken igbewọle; igbewọle aclr; igbewọle [lpm_widthn-1: 0] nomba; igbewọle [lpm_widthd-1: 0] denom; ojade [lpm_widthn-1: 0] iye; iṣẹjade [lpm_widthd-1: 0] ku; endmodule

3.3. Ikede paati VHDL
Ìkéde paati VHDL wa ninu Apẹrẹ VHDL File (.vhd) LPM_PACK.vhd ninu awọn librariesvhdllpm liana.
paati LPM_DIVIDE jeneriki (LPM_WIDTHN: adayeba; LPM_WIDTHD: adayeba;
LPM_NASEJU : okun : = "A ko fi orukọ silẹ"; LPM_DREPRESENTATION : okun: = "A ko forukọsilẹ"; LPM_PIPELINE: adayeba:= 0; LPM_TYPE: okun: = L_DIVIDE; LPM_HINT: okun: = "A ko lo"); ibudo (NUMER : ni std_logic_vector (LPM_WIDTHN-1 si isalẹ 0); DENOM : ni std_logic_vector (LPM_WIDTHD-1 si isalẹ 0); ACLR : ni std_logic: = '0'; CLOCK : ni std_logic: CL 'std : = '0'; QUOTIENT: jade std_logic_vector (LPM_WIDTHN-1 si isalẹ 1); jade std_logic_vector (LPM_WIDTHD-0 si isalẹ 1)); paati ipari;

3.4. Ìkéde VHDL LIBRARY_USE
Ìkéde VHDL LIBRARY-LILO ko nilo ti o ba lo Ikede paati VHDL.
IKÚN Lpm; LO lpm.lpm_components.all;

3.5. Awọn ibudo

Awọn tabili atẹle ṣe atokọ igbewọle ati awọn ebute agbejade fun LPM_DIVIDE IP mojuto.

Tabili 5.

LPM_DIVIDE Awọn ibudo igbewọle

Orukọ Port

Ti beere fun

nomba[]

Bẹẹni

denom[]

Bẹẹni

Apejuwe
Iṣagbewọle data numerator. Iwọn ibudo titẹ sii da lori iye paramita LPM_WIDTHN.
Iṣagbewọle data iyeida. Iwọn ibudo titẹ sii da lori iye paramita LPM_WIDTHD.
tesiwaju…

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 13

3. LPM_DIVIDE (Divide) Intel FPGA IP mojuto 683490 | 2020.10.05

Ibudo Name aago klken
aclr

Ti beere fun Bẹẹkọ
Rara

Apejuwe
Iṣagbewọle aago fun lilo pipeline. Fun awọn iye LPM_PIPELINE yatọ si 0 (aiyipada), ibudo aago gbọdọ wa ni mu ṣiṣẹ.
Aago jeki lilo pipelined. Nigbati ibudo klken ba ni idaniloju giga, iṣẹ pipin naa waye. Nigbati ifihan ba lọ silẹ, ko si iṣẹ kan. Ti o ba yọkuro, iye aiyipada jẹ 1.
Ibudo mimọ Asynchronous ti a lo nigbakugba lati tun opo gigun ti epo pada si gbogbo awọn '0' ni asynchronously si titẹ sii aago.

Tabili 6.

Awọn ibudo Ijade LPM_DIVIDE

Orukọ Port

Ti beere fun

Apejuwe

oro[]

Bẹẹni

Ijade data. Iwọn ibudo ti njade da lori LPM_WIDTHN

paramita iye.

wà[]

Bẹẹni

Ijade data. Iwọn ibudo ti njade da lori LPM_WIDTHD

paramita iye.

3.6. Awọn ipin

Tabili ti o tẹle ṣe atokọ awọn aye fun LPM_DIVIDE Intel FPGA IP mojuto.

Orukọ paramita

Iru

Ti beere fun

Apejuwe

LPM_WIDTHN

Odidi

Bẹẹni

Sọ awọn iwọn ti nọmba [] ati

opoiye[] ibudo. Awọn iye jẹ 1 si 64.

LPM_WIDTHD

Odidi

Bẹẹni

Sọ awọn iwọn ti denom[] ati

wà [] ibudo. Awọn iye jẹ 1 si 64.

LPM_NAsọtẹlẹ LPM_DREPRESENTATION

Okun Okun

Rara

Ami asoju ti igbewọle oni nọmba.

Awọn iye ti wa ni fọwọsi ati ti ko forukọsilẹ. Nigbati eyi

paramita ti ṣeto si SIGNED, pin

tumọ nomba [] igbewọle bi meji ti fowo si

iranlowo.

Rara

Ami asoju ti igbewọle iyeida.

Awọn iye ti wa ni fọwọsi ati ti ko forukọsilẹ. Nigbati eyi

paramita ti ṣeto si SIGNED, pin

tumọ titẹ sii denom[] bi meji ti a fọwọsi

iranlowo.

LPM_TYPE

Okun

Rara

Ṣe idanimọ ile-ikawe ti parameterized

module (LPM) nkankan orukọ ninu VHDL oniru

files (.vhd).

LPM_HINT

Okun

Rara

Nigba ti o ba instantiate a ìkàwé ti

parameterized modulu (LPM) iṣẹ ni a

Apẹrẹ VHDL File (.vhd), o gbọdọ lo awọn

paramita LPM_HINT lati pato Intel-

paramita kan pato. Fun example: LPM_HINT

= "CHAIN_SIZE = 8,

ONE_INPUT_IS_CONSTANT = BẸẸNI” Awọn

aiyipada iye ti wa ni UNUSED.

LPM_REMAINDERPOSITIVE

Okun

Rara

paramita kan pato Intel. O gbọdọ lo awọn

paramita LPM_HINT lati pato awọn

paramita LPM_REMAINDERPOSITIVE ni

VHDL apẹrẹ files. Awọn iye jẹ ODODO tabi IRO.

Ti a ba ṣeto paramita yii si TÒÓTỌ, lẹhinna ni

iye ibudo to ku[] gbọdọ jẹ ti o tobi ju

tesiwaju…

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 14

Fi esi ranṣẹ

3. LPM_DIVIDE (Divide) Intel FPGA IP mojuto 683490 | 2020.10.05

Orukọ paramita

Iru

MAXIMIZE_SPEED

Odidi

LPM_PIPELINE

Odidi

INTENDED_DEVICE_FAMILY SKIP_BITS

Okun Integer

Ti beere No
Bẹẹkọ Bẹẹkọ

Apejuwe
ju tabi dogba si odo. Ti a ba ṣeto paramita yii si TÒÓTỌ, iye ti ibudo to ku[] jẹ boya odo, tabi iye naa jẹ ami kanna, boya rere tabi odi, gẹgẹbi iye ibudo nomba. Lati le dinku agbegbe ati ilọsiwaju iyara, Intel ṣe iṣeduro ṣeto paramita yii si TÒÓTỌ ni awọn iṣẹ ṣiṣe nibiti iyoku gbọdọ jẹ rere tabi nibiti iyoku ko ṣe pataki.
paramita kan pato Intel. O gbọdọ lo paramita LPM_HINT lati sọ pato MAXIMIZE_SPEED paramita ni apẹrẹ VHDL files. Awọn iye jẹ [0..9]. Ti o ba lo, sọfitiwia Intel Quartus Prime ngbiyanju lati mu apẹẹrẹ kan pato ti iṣẹ LPM_DIVIDE pọ si fun iyara dipo ipa-ọna, ati pe o dojukọ eto aṣayan ọgbọn Imọ-ẹrọ Imudara dara julọ. Ti MAXIMIZE_SPEED ko ba lo, iye aṣayan Imọ-ẹrọ Iṣapeye lo dipo. Ti iye MAXIMIZE_SPEED jẹ 6 tabi ju bẹẹ lọ, Olupilẹṣẹ ṣe iṣapeye LPM_DIVIDE IP mojuto fun iyara ti o ga julọ nipa lilo awọn ẹwọn gbigbe; ti iye naa ba jẹ 5 tabi kere si, olupilẹṣẹ ṣe apẹrẹ laisi awọn ẹwọn gbigbe.
Ntọkasi nọmba awọn iyipo aago ti aiduro ti o ni nkan ṣe pẹlu iye-iye [] ati ku[] awọn abajade. Iye kan ti odo (0) tọkasi pe ko si idaduro to wa, ati pe iṣẹ apapọ kan jẹ lẹsẹkẹsẹ. Ti o ba ti yọkuro, iye aiyipada jẹ 0 (ti kii ṣe pipelin). O ko le pato iye kan fun paramita LPM_PIPELINE ti o ga ju LPM_WIDTHN.
A lo paramita yii fun apẹrẹ ati awọn idi kikopa ihuwasi. Olootu paramita ṣe iṣiro iye fun paramita yii.
Faye gba laaye fun pipin ipin-diẹ daradara diẹ sii lati mu ọgbọn pọ si lori awọn die-die asiwaju nipa pipese nọmba GND asiwaju si LPM_DIVIDE IP mojuto. Pato nọmba GND ti o jẹ asiwaju lori abajade iye si paramita yii.

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 15

683490 | 2020.10.05 Firanṣẹ esi

4. LPM_MULT (Multiplier) IP mojuto

Olusin 3.

LPM_MULT IP mojuto n ṣe imuse isodipupo lati ṣe isodipupo awọn iye data titẹ sii meji lati gbejade ọja kan bi iṣelọpọ.

Nọmba atẹle yii fihan awọn ebute oko oju omi fun LPM_MULT IP mojuto.

Awọn ibudo LPM_Mult

LPM_MULT aago dataa[] esi[] datab[] aclr/sclr klken
inst

Alaye ti o jọmọ Awọn ẹya ara ẹrọ loju iwe 71

4.1. Awọn ẹya ara ẹrọ
LPM_MULT IP core nfunni ni awọn ẹya wọnyi: · Ṣe ipilẹṣẹ isodipupo ti o ṣe isodipupo awọn iye data titẹ sii meji · Atilẹyin iwọn data ti awọn bits 1 · Atilẹyin ti a fowo si ati ọna kika aṣoju data ti a ko fowo si · Atilẹyin agbegbe tabi iṣapeye iyara · Atilẹyin pipelining pẹlu lairi iṣelọpọ atunto · Pese ohun aṣayan fun imuse ni iyasọtọ ifihan agbara oni nọmba (DSP)
Àkọsílẹ circuitry tabi kannaa eroja (LEs) Akiyesi: Nigbati o ba kọ multipliers o tobi ju awọn abinibi ni atilẹyin iwọn le /
yoo jẹ ipa iṣẹ ṣiṣe ti o waye lati cascading ti awọn bulọọki DSP. Ṣe atilẹyin ko o asynchronous iyan ati aago mu awọn ebute titẹ sii ṣiṣẹ · Ṣe atilẹyin imuṣiṣẹpọ iyan ko o fun Intel Stratix 10, Intel Arria 10 ati Intel Cyclone 10 GX awọn ẹrọ

ISO 9001: 2015 forukọsilẹ

4. LPM_MULT (Multiplier) IP mojuto 683490 | 2020.10.05
4.2. Verilog HDL Afọwọkọ
Afọwọkọ Verilog HDL atẹle wa ni Apẹrẹ Verilog File (.v) lpm.v ninu awọn edasynthesis liana.
module lpm_mult (esi, dataa, datab, apao, aago, klken, aclr ) paramita lpm_type = "lpm_mult"; paramita lpm_widtha = 1; paramita lpm_widthb = 1; paramita lpm_widths = 1; paramita lpm_widthp = 1; paramita lpm_representation = "UNSIGNED"; paramita lpm_pipeline = 0; paramita lpm_hint = “A ko lo”; aago titẹ sii; klken igbewọle; igbewọle aclr; igbewọle [lpm_widtha-1: 0] data; igbewọle [lpm_widthb-1: 0] datab; igbewọle [lpm_widths-1: 0] apao; abajade [lpm_widthp-1: 0]; endmodule
4.3. Ikede paati VHDL
Ìkéde paati VHDL wa ninu Apẹrẹ VHDL File (.vhd) LPM_PACK.vhd ninu awọn librariesvhdllpm liana.
paati LPM_MULT jeneriki ( LPM_WIDTHA: adayeba; LPM_WIDTHB: adayeba; LPM_WIDTHS: adayeba: = 1; LPM_WIDTHP: adayeba;
LPM_Aṣoju : okun: = "A ko forukọsilẹ"; LPM_PIPELINE: adayeba:= 0; LPM_TYPE: okun: = L_MULT; LPM_HINT: okun: = "A ko lo"); ibudo (DATAA: ni std_logic_vector (LPM_WIDTHA-1 si isalẹ 0); DATAB: ni std_logic_vector (LPM_WIDTHB-1 si isalẹ 0); ACLR: ni std_logic: = '0'; CLOCK: ni std_logic: CL 'std := '0'; SUM : ninu std_logic_vector(LPM_WIDTHS-1 downto 1) := (OTHERS => '0'); paati ipari;
4.4. Ìkéde VHDL LIBRARY_USE
Ìkéde VHDL LIBRARY-LILO ko nilo ti o ba lo Ikede paati VHDL.
IKÚN Lpm; LO lpm.lpm_components.all;

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 17

4. LPM_MULT (Multiplier) IP mojuto 683490 | 2020.10.05

4.5. Awọn ifihan agbara

Tabili 7.

LPM_MULT Awọn ifihan agbara igbewọle

Orukọ ifihan agbara

Ti beere fun

Apejuwe

data[]

Bẹẹni

Iṣagbewọle data.

Fun Intel Stratix 10, Intel Arria 10, ati awọn ẹrọ Intel Cyclone 10 GX, iwọn ifihan agbara titẹ sii da lori iye paramita iwọn Dataa.

Fun agbalagba ati awọn ẹrọ Intel Cyclone 10 LP, iwọn ifihan agbara titẹ sii da lori iye paramita LPM_WIDTHA.

data[]

Bẹẹni

Iṣagbewọle data.

Fun Intel Stratix 10, Intel Arria 10, ati awọn ẹrọ Intel Cyclone 10 GX, iwọn ifihan agbara titẹ sii da lori iye paramita iwọn iwọn Datab.

Fun agbalagba ati awọn ẹrọ Intel Cyclone 10 LP, iwọn ifihan agbara titẹ sii da

lori iye paramita LPM_WIDTHB.

aago

Rara

Iṣagbewọle aago fun lilo pipeline.

Fun agbalagba ati Intel Cyclone 10 LP awọn ẹrọ, ifihan aago gbọdọ wa ni sise fun LPM_PIPELINE iye miiran ju 0 (aiyipada).

Fun Intel Stratix 10, Intel Arria 10, ati Intel Cyclone 10 GX awọn ẹrọ, ifihan aago gbọdọ ṣiṣẹ ti iye Latency jẹ miiran ju 1 (aiyipada).

klken

Rara

Ṣiṣẹ aago fun lilo pipeline. Nigba ti klken ifihan agbara ti wa ni wi ga, awọn

paramọlẹ / subtractor isẹ ti gba ibi. Nigbati ifihan ba lọ silẹ, ko si iṣẹ

waye. Ti o ba yọkuro, iye aiyipada jẹ 1.

aclr sclr

Rara

Ifihan agbara asynchronous ti a lo nigbakugba lati tun opo gigun ti epo si gbogbo awọn 0s,

asynchronously to aago ifihan agbara. Opo opo gigun ti epo naa bẹrẹ si aisọye (X)

ipele kannaa. Awọn abajade jẹ deede, ṣugbọn iye ti kii ṣe odo.

Rara

Ifihan agbara amuṣiṣẹpọ ti a lo nigbakugba lati tun opo gigun ti epo si gbogbo awọn 0s,

ni iṣọkan si ifihan aago aago. Opo opo gigun ti epo naa bẹrẹ si aisọye (X)

ipele kannaa. Awọn abajade jẹ deede, ṣugbọn iye ti kii ṣe odo.

Tabili 8.

LPM_MULT Awọn ifihan agbara Ijade

ifihan agbara Name

Ti beere fun

Apejuwe

abajade[]

Bẹẹni

Ijade data.

Fun agbalagba ati Intel Cyclone 10 LP awọn ẹrọ, iwọn ifihan agbara da lori iye paramita LPM_WIDTHP. Ti LPM_WIDTHP <max (LPM_WIDTHA + LPM_WIDTHB, LPM_WIDTHS) tabi (LPM_WIDTHA + LPM_WIDTHS), LPM_WIDTHP MSB nikan lo wa.

Fun Intel Stratix 10, Intel Arria 10 ati Intel Cyclone 10 GX, iwọn awọn ifihan agbara jade da lori paramita iwọn Abajade.

4.6. Awọn paramita fun Stratix V, Arria V, Cyclone V, ati Intel Cyclone 10 LP Awọn ẹrọ

4.6.1. Gbogbogbo Taabu

Tabili 9.

Gbogbogbo Taabu

Paramita

Iye

Iṣeto Multiplier

Ṣe isodipupo titẹ 'data' nipasẹ titẹ sii 'datab'

Aiyipada Iye

Apejuwe

Ṣe isodipupo titẹ 'data' nipasẹ titẹ sii 'datab'

Yan iṣeto ti o fẹ fun multiplier.
tesiwaju…

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 18

Fi esi ranṣẹ

4. LPM_MULT (Multiplier) IP mojuto 683490 | 2020.10.05

Paramita
Bawo ni igbewọle 'data' yẹ ki o jẹ jakejado? Bawo ni igbewọle 'datab' yẹ ki o gbooro? Bawo ni o yẹ ki o pinnu iwọn ti abajade 'esi'? Ni ihamọ iwọn

Iye
Ṣe isodipupo titẹ 'data' funrararẹ (iṣiṣẹ onigun)
1-256 die-die

Aiyipada Iye

Apejuwe

8 die-die

Pato awọn iwọn ti dataa[] ibudo.

1-256 die-die

8 die-die

Pato awọn iwọn ti datab[] ibudo.

Ni adaṣe ṣe iṣiro iwọn naa Ni ihamọ iwọn naa
1-512 die-die

Laifọwọyi y ṣe iṣiro iwọn naa

Yan ọna ti o fẹ lati pinnu iwọn abajade [] ibudo.

16 die-die

Pato iwọn abajade [] ibudo.
Iye yii yoo munadoko nikan ti o ba yan Fi ihamọ iwọn ni paramita Iru.

4.6.2. Gbogbogbo 2 Tab

Table 10. Gbogbogbo 2 Tab

Paramita

Iye

Igbewọle Data

Ṣe ọkọ akero igbewọle 'datab' ni iye igbagbogbo bi?

Bẹẹkọ Bẹẹni

Orisi isodipupo

Iru iru

Ti ko fowo si

isodipupo ṣe o fẹ? Ti fowo si

imuse

Eyi ti imuse multiplier yẹ ki o ṣee lo?

Lo imuse aiyipada
Lo Circuit isodipupo iyasọtọ (Ko wa fun gbogbo awọn idile)
Lo awọn eroja ọgbọn

Aiyipada Iye

Apejuwe

Rara

Yan Bẹẹni lati pato iye igbagbogbo ti

`datab' igbewọle akero, ti o ba eyikeyi.

Ti ko fowo si

Pato ọna kika aṣoju fun dataa[] ati datab[] mejeeji.

Lo ion aiyipada imuse

Yan ọna ti o fẹ lati pinnu iwọn abajade [] ibudo.

4.6.3. Pipelining Tab

Table 11. Pipelining Tab

Paramita

Ṣe o fẹ lati pa opo gigun ti epo No

iṣẹ?

Bẹẹni

Iye

Ṣẹda 'aclr' kan

—

asynchronous ko o ibudo

Aiyipada Iye

Apejuwe

Rara

Yan Bẹẹni lati jeki iforukọsilẹ opo gigun ti epo si awọn

multiplier ká o wu ki o si pato awọn ti o fẹ

o wu lairi ni aago ọmọ. Muu ṣiṣẹ naa

Forukọsilẹ oniho afikun lairi si awọn

jade.

Ti ko ni ayẹwo

Yan aṣayan yii lati mu ibudo aclr ṣiṣẹ lati lo asynchronous ko o fun iforukọsilẹ opo gigun ti epo.
tesiwaju…

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 19

4. LPM_MULT (Multiplier) IP mojuto 683490 | 2020.10.05

Paramita
Ṣẹda aago 'clken' mu aago ṣiṣẹ
Imudara julọ
Iru iṣapeye wo ni o fẹ?

Iye -
Agbegbe Iyara Aiyipada

Aiyipada Iye

Apejuwe

Ti ko ni ayẹwo

Ni pato ṣiṣẹ aago giga ti nṣiṣe lọwọ fun ibudo aago ti iforukọsilẹ opo gigun ti epo

Aiyipada

Pato iṣapeye ti o fẹ fun ipilẹ IP.
Yan Aiyipada lati jẹ ki sọfitiwia Intel Quartus Prime lati pinnu iṣapeye ti o dara julọ fun ipilẹ IP.

4.7. Awọn paramita fun Intel Stratix 10, Intel Arria 10, ati Intel Cyclone 10 GX Awọn ẹrọ

4.7.1. Gbogbogbo Taabu

Table 12. Gbogbogbo Tab

Paramita

Iye

Aiyipada Iye

Apejuwe

Multiplier iṣeto ni Iru
Awọn iwọn Port Data

Ṣe isodipupo titẹ 'data' nipasẹ titẹ sii 'datab'
Ṣe isodipupo titẹ 'data' funrararẹ (iṣiṣẹ onigun)

Ṣe isodipupo titẹ 'data' nipasẹ titẹ sii 'datab'

Yan iṣeto ti o fẹ fun multiplier.

Iwọn data

1-256 die-die

8 die-die

Pato awọn iwọn ti dataa[] ibudo.

Iwọn data

1-256 die-die

8 die-die

Pato awọn iwọn ti datab[] ibudo.

Bawo ni o yẹ ki o pinnu iwọn ti abajade 'esi'?

Iru

Ni adaṣe ṣe iṣiro iwọn naa
Ni ihamọ iwọn

Laifọwọyi y ṣe iṣiro iwọn naa

Yan ọna ti o fẹ lati pinnu iwọn abajade [] ibudo.

Iye

1-512 die-die

16 die-die

Pato iwọn abajade [] ibudo.
Iye yii yoo munadoko nikan ti o ba yan Fi ihamọ iwọn ni paramita Iru.

Iwọn abajade

1-512 die-die

—

Ṣe afihan iwọn imunadoko ti abajade [] ibudo.

4.7.2. Gbogbogbo 2 Tab

Table 13. Gbogbogbo 2 Tab

Paramita

Igbewọle Data

Ṣe ọkọ akero igbewọle 'datab' ni iye igbagbogbo bi?

Bẹẹkọ Bẹẹni

Iye

Aiyipada Iye

Apejuwe

Rara

Yan Bẹẹni lati pato iye igbagbogbo ti

`datab' igbewọle akero, ti o ba eyikeyi.

tesiwaju…

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 20

Fi esi ranṣẹ

4. LPM_MULT (Multiplier) IP mojuto 683490 | 2020.10.05

Paramita

Iye

Eyikeyi iye ti o tobi ju 0

Orisi isodipupo

Iru iru

Ti ko fowo si

isodipupo ṣe o fẹ? Ti fowo si

Aṣa imuse

Eyi ti imuse multiplier yẹ ki o ṣee lo?

Lo imuse aiyipada
Lo awọn ifiṣootọ multiplier circuitry
Lo awọn eroja ọgbọn

Aiyipada Iye

Apejuwe

Pato iye igbagbogbo ti datab[] ibudo.

Ti ko fowo si

Pato ọna kika aṣoju fun dataa[] ati datab[] mejeeji.

Lo ion aiyipada imuse

Yan ọna ti o fẹ lati pinnu iwọn abajade [] ibudo.

4.7.3. Pipelining

Table 14. Pipelining Tab

Paramita

Iye

Ṣe o fẹ lati paipu iṣẹ naa?

Pipeline

Bẹẹkọ Bẹẹni

Lairi Ko Iru ifihan agbara

Eyikeyi iye ti o tobi ju 0.
Kò ACLR SCLR

Ṣẹda aago 'clken' kan

—

sise aago

Iru iṣapeye wo ni o fẹ?

Iru

Agbegbe Iyara Aiyipada

Aiyipada Iye

Apejuwe

Ko si 1 KO
—

Yan Bẹẹni lati jeki iforukọsilẹ opo gigun ti epo si iṣẹjade pupọ. Ṣiṣe iforukọsilẹ opo gigun ti epo n ṣe afikun idaduro afikun si iṣẹjade.
Pato iṣẹjade ti o fẹ ni iwọn aago.
Pato iru atunto fun iforukọsilẹ opo gigun ti epo. Yan KO SI ti o ko ba lo iforukọsilẹ opo gigun ti epo. Yan ACLR lati lo asynchronous ko o fun iforukọsilẹ opo gigun ti epo. Eleyi yoo se ina ACLR ibudo. Yan SCLR lati lo amuṣiṣẹpọ ko o fun iforukọsilẹ opo gigun ti epo. Eleyi yoo se ina SCLR ibudo.
Ni pato ṣiṣẹ aago giga ti nṣiṣe lọwọ fun ibudo aago ti iforukọsilẹ opo gigun ti epo

Aiyipada

Pato iṣapeye ti o fẹ fun ipilẹ IP.
Yan Aiyipada lati jẹ ki sọfitiwia Intel Quartus Prime lati pinnu iṣapeye ti o dara julọ fun ipilẹ IP.

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 21

683490 | 2020.10.05 Firanṣẹ esi

5. LPM_ADD_SUB (Adder/Subtractor)

Olusin 4.

LPM_ADD_SUB IP mojuto n jẹ ki o ṣe amulo paramọlẹ tabi iyokuro kan lati ṣafikun tabi yọkuro awọn akojọpọ data lati ṣe iṣelọpọ ohun ti o ni aropọ tabi iyatọ ti awọn iye titẹ sii.

Nọmba atẹle yii fihan awọn ebute oko oju omi fun LPM_ADD_SUB IP mojuto.

Awọn ibudo LPM_ADD_SUB

LPM_ADD_SUB add_sub cin

data[]

aago claken datab[] aclr

esi[] àkúnwọsílẹ cout

inst

5.1. Awọn ẹya ara ẹrọ
LPM_ADD_SUB IP mojuto n funni ni awọn ẹya wọnyi: · Ṣe ipilẹṣẹ paramọlẹ, iyokuro, ati paramọlẹ/iyọkuro ni atunto ni agbara.
awọn iṣẹ. · Atilẹyin data iwọn ti 1 die-die. · Ṣe atilẹyin ọna kika aṣoju data gẹgẹbi ibuwọlu ati aifọwọsi. · Atilẹyin iyan gbe-in (yiya-jade), asynchronous ko o, ati aago sise
awọn ibudo igbewọle. · Atilẹyin iyan gbe-jade (yiya-ni) ati aponsedanu o wu ebute oko. · Fi boya ọkan ninu awọn akero data igbewọle si kan ibakan. · Ṣe atilẹyin pipelining pẹlu lairi o wu atunto.

ISO 9001: 2015 forukọsilẹ

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05
5.2. Verilog HDL Afọwọkọ
Afọwọkọ Verilog HDL atẹle wa ni Apẹrẹ Verilog File (.v) lpm.v ninu awọn edasynthesis liana.
module lpm_add_sub (abajade, cout, àkúnwọsílẹ, add_sub, cin, dataa, datab, aago, klken, aclr); paramita lpm_type = "lpm_add_sub"; paramita lpm_width = 1; paramita lpm_direction = “UNUSED”; paramita lpm_representation = "SIGNED"; paramita lpm_pipeline = 0; paramita lpm_hint = “A ko lo”; igbewọle [lpm_width-1: 0] data, datab; input add_sub, cin; aago titẹ sii; klken igbewọle; igbewọle aclr; àbájáde [lpm_width-1: 0]; o wu cout, aponsedanu; endmodule
5.3. Ikede paati VHDL
Ìkéde paati VHDL wa ninu Apẹrẹ VHDL File (.vhd) LPM_PACK.vhd ninu awọn librariesvhdllpm liana.
paati LPM_ADD_SUB jeneriki (LPM_WIDTH: adayeba;
LPM_DIRECTION: okun: = "A ko lo"; LPM_Aṣoju: okun: = "ṢẸṢẸ"; LPM_PIPELINE: adayeba:= 0; LPM_TYPE: okun: = L_ADD_SUB; LPM_HINT: okun: = "A ko lo"); ibudo (DATAA: ni std_logic_vector (LPM_WIDTH-1 si isalẹ 0); DATAB: ni std_logic_vector (LPM_WIDTH-1 si isalẹ 0); ACLR: ni std_logic: = '0'; Aago: ni std_logic ni: CL '0'; : = '1'; CIN: ni std_logic: = 'Z'; paati ipari;
5.4. Ìkéde VHDL LIBRARY_USE
Ìkéde VHDL LIBRARY-LILO ko nilo ti o ba lo Ikede paati VHDL.
IKÚN Lpm; LO lpm.lpm_components.all;
5.5. Awọn ibudo
Awọn tabili atẹle ṣe atokọ igbewọle ati awọn ebute agbejade fun LPM_ADD_SUB IP mojuto.

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 23

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05

Table 15. LPM_ADD_SUB IP mojuto Input Ports

Orukọ Port

Ti beere fun

Apejuwe

cin

Rara

Gbe-ni si kekere-ibere bit. Fun awọn iṣẹ afikun, iye aiyipada jẹ 0. Fun

awọn iṣẹ iyokuro, iye aiyipada jẹ 1.

data[]

Bẹẹni

Iṣagbewọle data. Iwọn ibudo titẹ sii da lori iye paramita LPM_WIDTH.

data[]

Bẹẹni

Iṣagbewọle data. Iwọn ibudo titẹ sii da lori iye paramita LPM_WIDTH.

add_sub

Rara

Iyan ibudo igbewọle lati jeki ìmúdàgba yi pada laarin paramọlẹ ati iyokuro

awọn iṣẹ. Ti a ba lo paramita LPM_DIRECTION, add_sub ko le ṣee lo. Ti o ba jẹ

ti own, awọn aiyipada iye ni ADD. Intel ṣe iṣeduro pe ki o lo

paramita LPM_DIRECTION lati pato isẹ ti iṣẹ LPM_ADD_SUB,

kuku ju sọtọ ibakan si ibudo add_sub.

aago

Rara

Iṣagbewọle fun lilo pipeline. Ibudo aago n pese titẹ sii aago fun pipelin kan

isẹ. Fun awọn iye LPM_PIPELINE yatọ si 0 (aiyipada), ibudo aago gbọdọ jẹ

ṣiṣẹ.

klken

Rara

Ṣiṣẹ aago fun lilo pipeline. Nigbati ibudo klken ti sọ pe o ga, paramọlẹ /

iyokuro isẹ ti gba ibi. Nigbati ifihan ba lọ silẹ, ko si iṣẹ kan. Ti o ba jẹ

ti yọkuro, iye aiyipada jẹ 1.

aclr

Rara

Asynchronous ko o fun pipeline lilo. Opo opo gigun ti epo naa bẹrẹ si aisọye (X)

ipele kannaa. Ibudo aclr le ṣee lo nigbakugba lati tun opo gigun ti epo si gbogbo awọn 0s,

asynchronously to aago ifihan agbara.

Table 16. LPM_ADD_SUB IP mojuto o wu Ports

Orukọ Port

Ti beere fun

Apejuwe

abajade[]

Bẹẹni

Ijade data. Iwọn ibudo ti njade da lori paramita LPM_WIDTH

iye.

kootu

Rara

Gbe-jade (yawo-ni) ti bit ti o ṣe pataki julọ (MSB). Awọn ibudo cout ni o ni a ti ara

itumọ bi gbigbe-jade (yawo-ni) ti MSB. Ibudo cout iwari

àkúnwọsílẹ ni UNSIGNED awọn iṣẹ. Awọn ibudo cout ṣiṣẹ ni ọna kanna fun

Awọn iṣẹ ti a forukọsilẹ ati ti a ko forukọsilẹ.

àkúnwọ́sílẹ̀

Rara

Iyan aponsedanu isejade. Awọn aponsedanu ibudo ni o ni a ti ara itumọ bi

XOR ti gbigbe si MSB pẹlu gbigbe-jade ti MSB. The aponsedanu ibudo

asserts nigbati awọn esi koja awọn konge ti o wa, ati awọn ti a lo nikan nigbati awọn

Iye paramita LPM_REPRESENTATION jẹ SIGNED.

5.6. Awọn ipin

Tabili ti o tẹle ṣe atokọ LPM_ADD_SUB IP awọn paramita ipilẹ.

Table 17. LPM_ADD_SUB IP mojuto paramita

Orukọ paramita LPM_WIDTH

Iru odidi

Ti beere Bẹẹni

Apejuwe
Ntọkasi awọn iwọn ti data[], datab[], ati abajade[] awọn ibudo.

LPM_DIRECTION

Okun

Rara

Awọn iye jẹ ADD, SUB, ati LAILOlo. Ti o ba yọkuro, iye aiyipada jẹ DEFAULT, eyiti o ṣe itọsọna paramita lati mu iye rẹ lati ibudo add_sub. Ibudo add_sub ko le ṣee lo ti LPM_DIRECTION ba lo. Intel ṣeduro pe ki o lo paramita LPM_DIRECTION lati ṣọkasi iṣẹ ti iṣẹ LPM_ADD_SUB, ju ki o fi ipin kan nigbagbogbo si ibudo add_sub.
tesiwaju…

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 24

Fi esi ranṣẹ

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05

Orukọ paramita LPM_REPRESENTATION LPM_PIPELINE LPM_HINT LPM_TYPE ONE_INPUT_IS_CONSTANT MAXIMIZE_SPEED
INTENDED_DEVICE_FAMILY

Iru Okun Integer Okun Okun Okun Okun Integer
Okun

Ti beere Ko Bẹẹkọ Bẹẹkọ Bẹẹkọ Bẹẹkọ
Rara

Apejuwe
Ni pato iru afikun ti a ṣe. Awọn iye ti wa ni wole ati ki o ko wọle. Ti o ba ti yọkuro, iye aiyipada jẹ fọwọsi. Nigba ti a ba ṣeto paramita yii si SIGNED, paramita / iyokuro n ṣe itumọ igbewọle data bi afikun meji ti fowo si.
Ntọkasi nọmba awọn iyika aago lairi ti o ni nkan ṣe pẹlu abajade[]jade. Iye kan ti odo (0) tọkasi pe ko si idaduro to wa, ati pe iṣẹ apapọ kan yoo jẹ lẹsẹkẹsẹ. Ti o ba ti yọkuro, iye aiyipada jẹ 0 (ti kii-pipelin).
Gba ọ laaye lati tokasi awọn paramita-kan pato Intel ni apẹrẹ VHDL files (.vhd). Awọn aiyipada iye ti wa ni Ailolo.
Ṣe idanimọ ile-ikawe ti awọn modulu parameterized (LPM) orukọ nkan ni apẹrẹ VHDL files.
paramita kan pato Intel. O gbọdọ lo paramita LPM_HINT lati ṣe pato paramita ONE_INPUT_IS_CONSTANT ni apẹrẹ VHDL files. Awọn iye jẹ BẸẸNI, Bẹẹkọ, ati Ailolo. Pese iṣapeye nla ti titẹ sii kan ba jẹ igbagbogbo. Ti o ba yọkuro, iye aiyipada jẹ KO.
paramita kan pato Intel. O gbọdọ lo paramita LPM_HINT lati sọ pato MAXIMIZE_SPEED paramita ni apẹrẹ VHDL files. O le pato kan iye laarin 0 ati 10. Ti o ba ti lo, Intel Quartus Prime software igbiyanju a je ki kan pato apeere ti LPM_ADD_SUB iṣẹ fun iyara kuku ju afisona, ati ki o idojuk awọn eto ti o dara ju Technique kannaa. Ti MAXIMIZE_SPEED ko ba lo, iye aṣayan Imọ-ẹrọ Imudara ni a lo dipo. Ti eto MAXIMIZE_SPEED ba jẹ 6 tabi ju bẹẹ lọ, Olupilẹṣẹ ṣe iṣapeye LPM_ADD_SUB IP mojuto fun iyara giga nipa lilo awọn ẹwọn gbigbe; ti eto naa ba jẹ 5 tabi kere si, Akopọ ṣe apẹrẹ laisi awọn ẹwọn gbigbe. paramita yii gbọdọ jẹ pato fun Cyclone, Stratix, ati awọn ẹrọ Stratix GX nikan nigbati ibudo add_sub ko ba lo.
A lo paramita yii fun apẹrẹ ati awọn idi kikopa ihuwasi. Olootu paramita ṣe iṣiro iye fun paramita yii.

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 25

683490 | 2020.10.05 Firanṣẹ esi

6. LPM_COMPARE (Comparator)

Olusin 5.

LPM_COMPARE IP mojuto ṣe afiwe iye ti awọn eto data meji lati pinnu ibatan laarin wọn. Ni ọna ti o rọrun julọ, o le lo ẹnu-ọna iyasoto-OR lati pinnu boya awọn die-die meji ti data jẹ dogba.

Nọmba atẹle yii fihan awọn ebute oko oju omi fun LPM_COMPARE IP mojuto.

Awọn ibudo LPM_COMPARE

LPM_COMPARE

klken

alb

aeb

data[]

agba

data[]

agba

aago

ohun

aclr

aleebu

inst

6.1. Awọn ẹya ara ẹrọ
LPM_COMPARE IP mojuto nfunni ni awọn ẹya wọnyi: · Ṣe ipilẹṣẹ iṣẹ afiwe lati ṣe afiwe awọn eto data meji · Atilẹyin iwọn data ti awọn bits 1 · Atilẹyin ọna kika aṣoju data gẹgẹbi fowo si ati aifọwọsi · Ṣe agbejade awọn iru iṣẹjade wọnyi:
— alb (input A kere ju igbewọle B) — aeb (input A jẹ dogba si igbewọle B) — agb (input A tobi ju igbewọle B) — ageb (igbewọle A tobi ju tabi dọgba si igbewọle B) — aneb ( input A ko dogba si igbewọle B) — aleb (input A kere ju tabi dogba si igbewọle B) · Atilẹyin iyan asynchronous ko o ati aago jeki awọn ibudo igbewọle · Fi datab[] igbewọle si kan ibakan · Atilẹyin pipelining pẹlu atunto o wu jade lairi

ISO 9001: 2015 forukọsilẹ

6. LPM_COMPARE (Comparator) 683490 | 2020.10.05
6.2. Verilog HDL Afọwọkọ
Afọwọkọ Verilog HDL atẹle wa ni Apẹrẹ Verilog File (.v) lpm.v ninu awọn edasynthesis liana.
module lpm_compare (alb, aeb, agb, aleb, aneb, ageb, dataa, datab, aago, clken, aclr); paramita lpm_type = "lpm_compare"; paramita lpm_width = 1; paramita lpm_representation = "UNSIGNED"; paramita lpm_pipeline = 0; paramita lpm_hint = “A ko lo”; igbewọle [lpm_width-1: 0] data, datab; aago titẹ sii; klken igbewọle; igbewọle aclr; àbájáde alb, aeb, agb, aleb, aneb, ageb; endmodule
6.3. Ikede paati VHDL
Ìkéde paati VHDL wa ninu Apẹrẹ VHDL File (.vhd) LPM_PACK.vhd ninu awọn librariesvhdllpm liana.
paati LPM_COMPARE jeneriki (LPM_WIDTH: adayeba;
LPM_Aṣoju : okun: = "A ko forukọsilẹ"; LPM_PIPELINE: adayeba:= 0; LPM_TYPE: okun: = L_COMPARE; LPM_HINT: okun: = "A ko lo"); ibudo (DATAA: ni std_logic_vector (LPM_WIDTH-1 si isalẹ 0); DATAB: ni std_logic_vector (LPM_WIDTH-1 si isalẹ 0); ACLR: ni std_logic: = '0'; Aago: ni std_logic ni: CL '0'; : = '1'; AGB : jade std_logic; paati ipari;
6.4. Ìkéde VHDL LIBRARY_USE
Ìkéde VHDL LIBRARY-LILO ko nilo ti o ba lo Ikede paati VHDL.
IKÚN Lpm; LO lpm.lpm_components.all;
6.5. Awọn ibudo
Awọn tabili atẹle ṣe atokọ awọn titẹ sii ati awọn ebute oko oju omi ti o wu fun LMP_COMPARE IP mojuto.

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 27

6. LPM_COMPARE (Comparator) 683490 | 2020.10.05

Table 18. LPM_COMPARE IP mojuto Input Ports

Orukọ Port

Ti beere fun

Apejuwe

data[]

Bẹẹni

Iṣagbewọle data. Iwọn ibudo titẹ sii da lori iye paramita LPM_WIDTH.

data[]

Bẹẹni

Iṣagbewọle data. Iwọn ibudo titẹ sii da lori iye paramita LPM_WIDTH.

aago

Rara

Iṣagbewọle aago fun lilo pipeline. Ibudo aago n pese titẹ sii aago fun pipelin kan

isẹ. Fun awọn iye LPM_PIPELINE yatọ si 0 (aiyipada), ibudo aago gbọdọ jẹ

ṣiṣẹ.

klken

Rara

Ṣiṣẹ aago fun lilo pipeline. Nigba ti klken ibudo ti wa ni asserted ga, awọn

lafiwe isẹ ti gba ibi. Nigbati ifihan ba lọ silẹ, ko si iṣẹ kan. Ti o ba jẹ

ti yọkuro, iye aiyipada jẹ 1.

aclr

Rara

Asynchronous ko o fun pipeline lilo. Opo gigun ti epo naa bẹrẹ si imọran aisọye (X).

ipele. Ibudo aclr le ṣee lo nigbakugba lati tun opo gigun ti epo si gbogbo awọn 0s,

asynchronously to aago ifihan agbara.

Table 19. LPM_COMPARE IP mojuto o wu Ports

Orukọ Port

Ti beere fun

Apejuwe

alb

Rara

O wu ibudo fun comparator. Ti fi idi rẹ mulẹ ti titẹ A ba kere ju igbewọle B.

aeb

Rara

O wu ibudo fun comparator. Ti fi idi rẹ mulẹ ti titẹ A ba dọgba si igbewọle B.

agba

Rara

O wu ibudo fun comparator. Ti fi idi rẹ mulẹ ti titẹ A ba tobi ju igbewọle B.

agba

Rara

O wu ibudo fun comparator. Ti fi idi rẹ mulẹ ti titẹ A ba tobi ju tabi dogba si igbewọle

ohun

Rara

O wu ibudo fun comparator. Ti fi idi rẹ mulẹ ti titẹ A ko ba dọgba si igbewọle B.

aleebu

Rara

O wu ibudo fun comparator. Ti fi idi rẹ mulẹ ti titẹ A ba kere ju tabi dogba si igbewọle B.

6.6. Awọn ipin

Tabili ti o tẹle ṣe atokọ awọn aye fun LPM_COMPARE IP mojuto.

Table 20. LPM_COMPARE IP mojuto paramita

Orukọ paramita

Iru

Ti beere fun

LPM_WIDTH

Odidi Bẹẹni

LPM_REPRESENTATION

Okun

Rara

LPM_PIPELINE

Odidi No

LPM_HINT

Okun

Rara

Apejuwe
Ni pato awọn iwọn ti data[] ati datab[] ebute oko.
So iru ti lafiwe ṣe. Awọn iye ti wa ni wole ati ki o ko wọle. Ti o ba ti yọkuro, iye aifọwọyi jẹ UNSIGNED. Nigba ti a ba ṣeto iye paramita yii si SIGNED, olufiwera tumọ igbewọle data bi afọwọṣe meji ti fowo si.
Ntọka nọmba awọn iyika aago ti lairi ni nkan ṣe pẹlu alb, aeb, agb, ageb, aleb, tabi iṣẹjade aneb. Iye kan ti odo (0) tọkasi pe ko si idaduro to wa, ati pe iṣẹ apapọ kan yoo jẹ lẹsẹkẹsẹ. Ti o ba ti yọkuro, iye aiyipada jẹ 0 (ti kii ṣe pipelin).
Gba ọ laaye lati tokasi awọn paramita-kan pato Intel ni apẹrẹ VHDL files (.vhd). Awọn aiyipada iye ti wa ni Ailolo.
tesiwaju…

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 28

Fi esi ranṣẹ

6. LPM_COMPARE (Comparator) 683490 | 2020.10.05
Orukọ paramita LPM_TYPE INTENDED_DEVICE_FAMILY
ONE_INPUT_IS_CONSTANT

Tẹ Okun Okun
Okun

Ti beere fun Bẹẹkọ
Rara

Apejuwe
Ṣe idanimọ ile-ikawe ti awọn modulu parameterized (LPM) orukọ nkan ni apẹrẹ VHDL files.
A lo paramita yii fun apẹrẹ ati awọn idi kikopa ihuwasi. Olootu paramita ṣe iṣiro iye fun paramita yii.
paramita kan pato Intel. O gbọdọ lo paramita LPM_HINT lati ṣe pato paramita ONE_INPUT_IS_CONSTANT ni apẹrẹ VHDL files. Awọn iye jẹ BẸẸNI, Bẹẹkọ, tabi Ailolo. Pese iṣapeye nla ti titẹ sii ba jẹ igbagbogbo. Ti o ba yọkuro, iye aiyipada jẹ KO.

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 29

683490 | 2020.10.05 Firanṣẹ esi

7. ALTECC (Aṣiṣe Atunse koodu: Encoder/Decoder) IP mojuto

Olusin 6.

Intel pese ALTECC IP mojuto lati ṣe iṣẹ ṣiṣe ECC. ECC ṣe awari data ibajẹ ti o waye ni ẹgbẹ olugba lakoko gbigbe data. Ọna atunṣe aṣiṣe yii dara julọ fun awọn ipo nibiti awọn aṣiṣe waye ni laileto kuku ju ninu awọn ti nwaye.

ECC n ṣawari awọn aṣiṣe nipasẹ ilana fifi koodu ati iyipada data. Fun example, nigbati awọn ECC ti wa ni loo ni a gbigbe ohun elo, data ka lati awọn orisun ti wa ni koodu ṣaaju ki o to ni rán si awọn olugba. Ijade (ọrọ koodu) lati koodu koodu ni awọn data aise ti a fikun pẹlu nọmba awọn iwọn ilawọn. Nọmba deede ti awọn iwọn ilawọn ti a fikun da lori nọmba awọn die-die ninu data igbewọle. Ọrọ koodu ti ipilẹṣẹ lẹhinna ni gbigbe si ibi ti o nlo.

Olugba gba ọrọ koodu ati pinnu rẹ. Alaye ti o gba nipasẹ oluyipada pinnu boya a ti rii aṣiṣe. Oluyipada ṣe iwari ẹyọkan-bit ati awọn aṣiṣe-meji-bit, ṣugbọn o le ṣatunṣe awọn aṣiṣe ẹyọ-bit nikan ni data ti bajẹ. Iru ECC yii jẹ ṣiṣawari aṣiṣe ilọpo meji (SECDED).

O le tunto kooduopo ati awọn iṣẹ decoder ti ALTECC IP mojuto. Iṣagbewọle data si kooduopo ti wa ni koodu lati ṣe ipilẹṣẹ ọrọ koodu kan ti o jẹ apapọ ti igbewọle data ati awọn iwọn ilawọn ti ipilẹṣẹ. Ọrọ koodu ti ipilẹṣẹ ti wa ni gbigbe si module decoder fun iyipada ni kete ki o to de idina opin irin ajo rẹ. Oluyipada ṣe ipilẹṣẹ fekito aisan lati pinnu boya aṣiṣe eyikeyi wa ninu ọrọ koodu ti o gba. Oluyipada ṣe atunṣe data nikan ti aṣiṣe-bit kan ba wa lati awọn die-die data. Ko si ifihan agbara ti o ba jẹ pe aṣiṣe-ẹyọkan ba wa lati awọn iwọn ilawọn. Oluyipada tun ni awọn ifihan agbara asia lati ṣafihan ipo ti data ti o gba ati igbese ti oluyipada ṣe, ti o ba jẹ eyikeyi.

Awọn isiro wọnyi fihan awọn ebute oko oju omi fun ipilẹ IP ALTECC.

ALTECC kooduopo Ports

ALTECC_ENCODER

data[]

q[]

aago

aclr

inst

ISO 9001: 2015 forukọsilẹ

7. ALTECC (Aṣiṣe Atunse koodu: Encoder/Decoder) IP Core 683490 | 2020.10.05

olusin 7. ALTECC Decoder Ports

ALTECC_DECODER

data [] aago aago

q[] err_detected err_atunse
aṣiṣe_fatal

aclr

inst

7.1. ALTECC Encoder Awọn ẹya ara ẹrọ

AlTECC encoder IP core nfunni ni awọn ẹya wọnyi: · Ṣiṣe koodu data nipa lilo ero koodu Hamming · Atilẹyin iwọn data ti awọn bits 2 · Ṣe atilẹyin ọna kika aṣoju data ti a fowo si ati ti a ko fowo si · Atilẹyin pipelining pẹlu lairi iṣẹjade ti boya ọkan tabi awọn akoko aago meji · Atilẹyin iyan asynchronous ko o ati aago jeki awọn ibudo

AlTECC koodu IP mojuto gba wọle ati ṣe koodu data nipa lilo ero ifaminsi Hamming. Eto ifaminsi Hamming n gba awọn iwọn ilawọn ati fi wọn kun data atilẹba lati ṣe agbejade ọrọ koodu iṣelọpọ. Nọmba awọn iwọn ilawọn ti a fikun da lori iwọn data naa.

Tabili ti o tẹle yii ṣe atokọ nọmba awọn iwọn ilawọn ti a fikun fun awọn sakani oriṣiriṣi ti awọn iwọn data. Àpapọ̀ Àpapọ̀ Ìwọ̀n Ìwọ̀n dúró fún àpapọ̀ iye àwọn ìkọ̀wọlé dátà àti àfikún ọ̀tọ̀ọ̀tọ̀ díẹ̀.

Tabili 21.

Nọmba ti Parity Bits ati Ọrọ koodu Ni ibamu si Iwọn Data

Iwọn Data

Nọmba ti Parity Bits

Lapapọ Awọn ipin (Ọrọ koodu)

2-4

3+1

6-8

5-11

4+1

10-16

12-26

5+1

18-32

27-57

6+1

34-64

58-64

7+1

66-72

Itọsẹ-itọpa-bit ni ibamu nlo iṣayẹwo ani-parati. Awọn afikun 1 bit (ti o han ninu tabili bi +1) ti wa ni ifikun si awọn iwọn ilawọn bi MSB ti ọrọ koodu. Eyi ṣe idaniloju pe ọrọ koodu ni nọmba ani ti 1's. Fun example, ti o ba ti data iwọn jẹ 4 die-die, 4 parity die-die appended si awọn data lati di a koodu ọrọ pẹlu kan lapapọ ti 8 die-die. Ti awọn ege 7 lati LSB ti ọrọ koodu 8-bit ni nọmba aibikita ti 1, bit 8th (MSB) ti ọrọ koodu jẹ 1 ti o jẹ ki nọmba lapapọ ti 1s ninu ọrọ koodu paapaa.
Nọmba ti o tẹle n ṣe afihan ọrọ koodu ti ipilẹṣẹ ati iṣeto ti awọn iwọn ilawọn ati awọn die-die data ninu titẹ sii data 8-bit kan.

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 31

7. ALTECC (Aṣiṣe Atunse koodu: Encoder/Decoder) IP Core 683490 | 2020.10.05

Olusin 8.

Parity Bits ati Data Bits Eto ni 8-Bit ti ipilẹṣẹ Ọrọ koodu

MSB

LSB

4 parity die-die

4 data die-die

ALTECC koodu IP mojuto gba awọn iwọn titẹ sii nikan ti 2 si 64 die-die ni akoko kan. Awọn iwọn titẹ sii ti awọn die-die 12, awọn bit 29, ati awọn bit 64, eyiti o baamu ni pipe si awọn ẹrọ Intel, ṣe agbejade awọn abajade ti awọn bit 18, awọn bit 36, ati awọn bit 72 ni atele. O le ṣakoso aropin bitselection ni olootu paramita.

7.2. Verilog HDL Afọwọkọ (ALTECC_ENCODER)
Afọwọkọ Verilog HDL atẹle wa ni Apẹrẹ Verilog File (.v) lpm.v ninu awọn edasynthesis liana.
module altecc_encoder #(parameter called_device_family = “ailolò”, paramita lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = “altecc_encoder”, parameter lpm_hint = “ailosed”) (aago waya titẹ sii, aclr wire waya clocken, input waya [width_dataword-1: 0] data, o wu waya [width_codeword-1: 0] q; endmodule

7.3. Verilog HDL Afọwọkọ (ALTECC_DECODER)
Afọwọkọ Verilog HDL atẹle wa ni Apẹrẹ Verilog File (.v) lpm.v ninu awọn edasynthesis liana.
module altecc_decoder #(parametertention_device_family = “ailolò”, paramita lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = “altecc_decoder”, parameter lpm_hint = “ailosed”) (aago waya titẹ sii, aclr wire waya clocken, input waya [width_codeword-1: 0] data, o wu waya err_corrected, o wu waya err_detected, outut waya err_fatal, o wu waya [width_dataword-1: 0] q); endmodule

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 32

Fi esi ranṣẹ

7. ALTECC (Aṣiṣe Atunse koodu: Encoder/Decoder) IP Core 683490 | 2020.10.05
7.4. Ìkéde paati VHDL (ALTECC_ENCODER)
Ìkéde paati VHDL wa ninu Apẹrẹ VHDL File (.vhd) altera_mf_components.vhd ninu awọn librariesvhdlaltera_mf liana.
paati altecc_encoder jeneriki (ti a pinnu_device_family: okun: = “a ko lo”; lpm_pipeline: adayeba: = 0; width_codeword: adayeba: = 8; width_dataword: adayeba: = 8; lpm_hint: okun: = “UNUSED”; lpm_encod: string: cc ”); ibudo (aclr: ni std_logic: = '0'; aago: ni std_logic: = '0'; clocken: ni std_logic: = '1'; data: ni std_logic_vector (width_dataword-1 si isalẹ 0); q: jade std_logic_vector (width_logic_vector) -1 si isalẹ 0)); paati ipari;
7.5. Ìkéde paati VHDL (ALTECC_DECODER)
Ìkéde paati VHDL wa ninu Apẹrẹ VHDL File (.vhd) altera_mf_components.vhd ninu awọn librariesvhdlaltera_mf liana.
paati altecc_decoder jeneriki (ti a pinnu_device_family: okun: = “a ko lo”; lpm_pipeline: adayeba: = 0; width_codeword: adayeba: = 8; width_dataword: adayeba: = 8; lpm_hint: okun: = “UNUSED”; lpm_dealtealte: string ”); ibudo (aclr: in std_logic: = '0'; aago: ni std_logic: = '0'; clocken: in std_logic: = '1'; data: ni std_logic_vector (width_codeword-1 si isalẹ 0); err_corrected : out std_logic : jade std_logic; q: jade std_logic_vector (width_dataword-1 downto 0); paati ipari;
7.6. Ìkéde VHDL LIBRARY_USE
Ìkéde VHDL LIBRARY-LILO ko nilo ti o ba lo Ikede paati VHDL.
LIBRARY altera_mf; LO altera_mf.altera_mf_components.all;
7.7. Awọn ibudo kooduopo
Awọn tabili atẹle ṣe atokọ igbewọle ati awọn ebute agbejade fun ipilẹ koodu ALTECC IP mojuto.

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 33

7. ALTECC (Aṣiṣe Atunse koodu: Encoder/Decoder) IP Core 683490 | 2020.10.05

Table 22. ALTECC Encoder Input Ports

Orukọ Port

Ti beere fun

Apejuwe

data[]

Bẹẹni

Data input ibudo. Iwọn ibudo titẹ sii da lori WIDTH_DATAWORD

paramita iye. Awọn data[] ibudo ni awọn aise data lati wa ni kooduopo.

aago

Bẹẹni

Ibudo titẹ sii aago ti o pese ifihan agbara aago lati muuṣiṣẹpọ iṣẹ fifi koodu.

Ibudo aago ni o nilo nigbati iye LPM_PIPELINE ba tobi ju 0 lọ.

aago

Rara

Aago ṣiṣẹ. Ti o ba yọkuro, iye aiyipada jẹ 1.

aclr

Rara

Iṣagbewọle alaiṣẹpọ mọ. Awọn ti nṣiṣe lọwọ ga aclr ifihan agbara le ṣee lo ni eyikeyi akoko lati

asynchronously ko awọn iforukọsilẹ.

Table 23. ALTECC Encoder o wu Ports

Orukọ ibudo q[]

Ti beere Bẹẹni

Apejuwe
Ti koodu koodu o wu ibudo. Iwọn ibudo iṣẹjade da lori iye paramita WIDTH_CODEWORD.

7.8. Decoder Ports

Awọn tabili atẹle ṣe atokọ igbewọle ati awọn ebute agbejade fun ipilẹ IP decoder ALTECC.

Table 24. ALTECC Decoder Input Ports

Orukọ Port

Ti beere fun

Apejuwe

data[]

Bẹẹni

Data input ibudo. Iwọn ibudo titẹ sii da lori iye paramita WIDTH_CODEWORD.

aago

Bẹẹni

Ibudo titẹ sii aago ti o pese ifihan agbara aago lati muuṣiṣẹpọ iṣẹ fifi koodu. Ibudo aago ni o nilo nigbati iye LPM_PIPELINE ba tobi ju 0 lọ.

aago

Rara

Aago ṣiṣẹ. Ti o ba yọkuro, iye aiyipada jẹ 1.

aclr

Rara

Iṣagbewọle ko o Asynchronous. Ifihan agbara aclr giga ti nṣiṣe lọwọ le ṣee lo nigbakugba lati nu asynchronously kuro awọn iforukọsilẹ.

Table 25. ALTECC Decoder o wu Ports

Orukọ ibudo q[]

Ti beere Bẹẹni

Apejuwe
Decoded o wu ibudo. Iwọn ibudo iṣẹjade da lori iye paramita WIDTH_DATAWORD.

err_detected Bẹẹni

Ifihan agbara asia lati ṣe afihan ipo ti data ti o gba ati pato awọn aṣiṣe eyikeyi ti o rii.

err_atunse Bẹẹni d

Ifihan agbara asia lati ṣe afihan ipo ti data ti o gba. Ntọkasi aṣiṣe-bit kan ti a rii ati atunṣe. O le lo data naa nitori pe o ti ṣe atunṣe tẹlẹ.

aṣiṣe_fatal

Bẹẹni

Ifihan agbara asia lati ṣe afihan ipo ti data ti o gba. Ṣe afihan aṣiṣe-meji-bit ti a rii, ṣugbọn ko ṣe atunṣe. Iwọ ko gbọdọ lo data naa ti ifihan yii ba jẹ idaniloju.

syn_e

Rara

Ifihan agbara ti yoo ga nigbakugba ti a ba rii aṣiṣe-bit kan lori alakan

die-die.

7.9. Awọn paramita kooduopo
Tabili ti o tẹle n ṣe atokọ awọn ayewọn fun ipilẹ koodu IP ALTECC.

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 34

Fi esi ranṣẹ

7. ALTECC (Aṣiṣe Atunse koodu: Encoder/Decoder) IP Core 683490 | 2020.10.05

Table 26. ALTECC Encoder paramita

Orukọ paramita

Iru

Ti beere fun

Apejuwe

WIDTH_DATAWORD

Odidi Bẹẹni

So awọn iwọn ti awọn aise data. Awọn iye wa lati 2 si 64. Ti o ba yọkuro, iye aiyipada jẹ 8.

WIDTH_CODEWORD

Odidi Bẹẹni

So awọn iwọn ti awọn ti o baamu koodu ọrọ. Awọn iye to wulo jẹ lati 6 si 72, laisi 9, 17, 33, ati 65. Ti o ba yọkuro, iye aiyipada jẹ 13.

LPM_PIPELINE

Odidi No

Ni pato opo gigun ti epo fun Circuit. Awọn iye wa lati 0 si 2. Ti iye ba jẹ 0, awọn ebute oko oju omi ko forukọsilẹ. Ti iye naa ba jẹ 1, awọn ebute oko oju omi ti o wa ni aami. Ti iye naa ba jẹ 2, titẹ sii ati awọn ebute oko oju omi ti o wuyi ti forukọsilẹ. Ti o ba yọkuro, iye aiyipada jẹ 0.

7.10. Decoder Parameters

Tabili ti o tẹle ṣe atokọ ALTECC decoder IP awọn paramita ipilẹ.

Table 27. ALTECC Decoder paramita

Orukọ paramita WIDTH_DATAWORD

Iru odidi

Ti beere fun

Apejuwe

Bẹẹni

So awọn iwọn ti awọn aise data. Awọn iye jẹ 2 to 64. Awọn

iye aiyipada jẹ 8.

WIDTH_CODEWORD

Odidi

Bẹẹni

So awọn iwọn ti awọn ti o baamu koodu ọrọ. Awọn iye jẹ 6

si 72, laisi 9, 17, 33, ati 65. Ti o ba yọkuro, iye aiyipada

jẹ 13.

LPM_PIPELINE

Odidi

Rara

So awọn Forukọsilẹ ti awọn Circuit. Awọn iye ni o wa lati 0 to 2. Ti o ba ti

iye jẹ 0, ko si iforukọsilẹ ti wa ni imuse. Ti iye naa ba jẹ 1, awọn

o wu ti wa ni aami-. Ti iye naa ba jẹ 2, mejeeji titẹ sii ati awọn

o wu ti wa ni aami-. Ti iye naa ba tobi ju 2 lọ, afikun

awọn iforukọsilẹ ti wa ni imuse ni o wu fun awọn afikun

lairi. Ti o ba yọkuro, iye aiyipada jẹ 0.

Ṣẹda ibudo 'syn_e' kan

Odidi

Rara

Tan paramita yii lati ṣẹda ibudo syn_e kan.

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 35

683490 | 2020.10.05 Firanṣẹ esi

8. Intel FPGA isodipupo paramọlẹ IP mojuto

Olusin 9.

Intel FPGA Multiply Adder (Intel Stratix 10, Intel Arria 10, ati Intel Cyclone 10 GX awọn ẹrọ) tabi ALTERA_MULT_ADD (Arria V, Stratix V, ati Cyclone V awọn ẹrọ) IP mojuto gba ọ laaye lati ṣe imuse pupọ-adder.

Nọmba atẹle yii fihan awọn ebute oko oju omi fun Intel FPGA Multiply Adder tabi ALTERA_MULT_ADD IP mojuto.

Intel FPGA isodipupo Adder tabi ALTERA_MULT_ADD Ports

Intel FPGA isodipupo Adder tabi ALTERA_MULT_ADD

dataa[] ami datab[] signb datac[] coefsel0[] coefsel1[] coefsel2[] coefsel3[] addnsub1 addnsub3 aclr/sclr[] scanina[] clock0 clock1 clock2 ena0 ena1 ena2 sload_accum
accum_sload chainin[]

abajade[][]

aclr0 aclr1

inst
Adder-multiplikator gba awọn orisii awọn igbewọle, ṣe isodipupo awọn iye papọ lẹhinna ṣafikun tabi yọkuro lati awọn ọja ti gbogbo awọn orisii miiran.
Ti gbogbo awọn iwọn data titẹ sii ba jẹ 9-bits fife tabi kere si, iṣẹ naa nlo 9 x 9 bit input multiplier iṣeto ni DSP Àkọsílẹ fun awọn ẹrọ ti o ṣe atilẹyin iṣeto 9 x 9. Bi kii ba ṣe bẹ, bulọọki DSP nlo 18 × 18-bit multiplikator input lati ṣe ilana data pẹlu awọn iwọn 10 ati awọn die-die 18. Ti ọpọ Intel FPGA Multiply Adder tabi ALTERA_MULT_ADD awọn ohun kohun IP waye ni apẹrẹ kan, awọn iṣẹ naa ti pin si bi

ISO 9001: 2015 forukọsilẹ

8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05
ọpọlọpọ awọn oriṣiriṣi awọn bulọọki DSP bi o ti ṣee ṣe ki ipa-ọna si awọn bulọọki wọnyi jẹ irọrun diẹ sii. Diẹ awọn isodipupo fun bulọọki DSP gba awọn yiyan ipa-ọna diẹ sii sinu bulọki nipa idinku awọn ọna si iyoku ẹrọ naa.
Awọn iforukọsilẹ ati awọn iforukọsilẹ opo gigun ti epo fun awọn ifihan agbara wọnyi ni a tun gbe sinu bulọọki DSP: · Iṣagbewọle data · Wọle tabi ti a ko fowo si yan · Fikun tabi yọkuro yan · Awọn ọja ti awọn isodipupo
Ninu ọran abajade abajade, iforukọsilẹ akọkọ ni a gbe sinu bulọọki DSP. Sibẹsibẹ awọn iforukọsilẹ lairi afikun ni a gbe sinu awọn eroja kannaa ni ita bulọọki naa. Agbeegbe si DSP Àkọsílẹ, pẹlu awọn igbewọle data si multiplier, iṣakoso ifihan agbara awọn igbewọle, ati awọn esi ti paramọlẹ, lo deede afisona lati baraẹnisọrọ pẹlu awọn iyokù ti awọn ẹrọ. Gbogbo awọn asopọ ti o wa ninu iṣẹ naa lo ipa-ọna iyasọtọ inu bulọọki DSP. Itọnisọna iyasọtọ yii pẹlu awọn ẹwọn iforukọsilẹ iyipada nigbati o yan aṣayan lati yi data igbewọle ti o forukọsilẹ ti isodipupo kan lati ọdọ pupọ kan si isodipupo nitosi.
Fun alaye diẹ sii nipa awọn bulọọki DSP ni eyikeyi ti Stratix V, ati jara ẹrọ Arria V, tọka si apakan DSP Ohun amorindun ti awọn iwe-ifọwọyi oniwun lori Oju-iwe Iwe Iwe ati Imọ-ẹrọ.
Alaye ti o jọmọ AN 306: Ṣiṣe awọn Multipliers ni Awọn ẹrọ FPGA
Pese alaye diẹ sii nipa imuse awọn isodipupo nipa lilo DSP ati awọn bulọọki iranti ni awọn ẹrọ FPGA Intel.
8.1. Awọn ẹya ara ẹrọ
Intel FPGA Multiply Adder tabi ALTERA_MULT_ADD IP mojuto nfunni awọn ẹya wọnyi: · Ṣe ipilẹṣẹ isodipupo lati ṣe awọn iṣẹ isodipupo ti eka meji.
awọn nọmba Akiyesi: Nigba ti o ba kọ awọn isodipupo ti o tobi ju iwọn atilẹyin abinibi lọ le /
yoo jẹ ipa iṣẹ ṣiṣe ti o waye lati cascading ti awọn bulọọki DSP. Ṣe atilẹyin awọn iwọn data ti awọn iwọn 1 256 · Atilẹyin ọna kika aṣoju data ti fowo si ati aifọwọsi · Atilẹyin pipelining pẹlu airi titẹ sii atunto · Pese aṣayan lati yipada ni agbara laarin fowo si ati atilẹyin data ti a ko fowo si · Pese aṣayan lati yipada ni agbara laarin fikun ati iyokuro iṣẹ · Atilẹyin asynchronous iyan ati mimuuṣiṣẹpọ ko o ati aago mu awọn ebute titẹ sii ṣiṣẹ · Atilẹyin ipo iforukọsilẹ idaduro systolic · Ṣe atilẹyin paramọlẹ iṣaaju pẹlu awọn iye-iṣaaju iṣaju iṣaju 8 fun pupọ pupọ · Atilẹyin igbagbogbo fifuye ṣaaju lati ṣe ibamu awọn esi ikojọpọ

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 37

8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

8.1.1. Pre-adder
Pẹlu paramọlẹ-tẹlẹ, awọn afikun tabi iyokuro ni a ṣe ṣaaju ifunni pupọ.
Awọn ọna paramọlẹ marun lo wa: · Ipo ti o rọrun · Ipo olùsọdipúpọ · Ipo igbewọle · Ipo onigun mẹrin · Ipo ibakan

Akiyesi:

Nigbati o ba ti lo ami-adder (alafisọdipupo iṣaaju-adder/igbewọle/ipo square), gbogbo awọn igbewọle data si pupọ gbọdọ ni eto aago kanna.

8.1.1.1. Pre-adder Simple Ipo

Ni ipo yii, awọn operands mejeeji gba lati awọn ebute titẹ sii ati pe a ko lo-adder ṣaaju tabi ko kọja. Eyi ni ipo aiyipada.

olusin 10. Pre- paramọlẹ Simple Mode
a0 b0

Pupọ0

esi

8.1.1.2. Pre-adder olùsọdipúpọ Ipo
Ni yi mode, ọkan multiplier operand yo lati awọn aso-adder, ati awọn miiran operand yo lati awọn ti abẹnu olùsọdipúpọ ibi ipamọ. Ibi ipamọ olùsọdipúpọ ngbanilaaye to awọn iwọn tito tẹlẹ 8. Awọn ifihan agbara yiyan olùsọdipúpọ jẹ coefsel[0..3].
Ipo yii jẹ afihan ni idogba atẹle.

Atẹle yii fihan ipo olùsọdipúpọ ṣaaju-adder ti multiplier.

olusin 11. Pre-adder olùsọdipúpọ Mode

Apesile

Pupọ0

+/-

esi

coefsel0 kofa

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 38

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8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05
8.1.1.3. Ipo Input Pre-adder Ni ipo yii, operand isodipupo kan n gba lati inu paramọlẹ iṣaaju, ati operand miiran n gba lati ibudo titẹ sii datac[]. Ipo yii jẹ afihan ni idogba atẹle.

Atẹle yii ṣe afihan ipo igbewọle iṣaaju-adder ti multiplier.

olusin 12. Pre-adder Input Ipo
a0 b0

Pupọ0

+/-

esi

8.1.1.4. Pre-adder Square Ipo Eleyi mode ti wa ni kosile ni awọn wọnyi idogba.

Awọn wọnyi fihan awọn aso-parapọ square mode ti meji multipliers.

olusin 13. Pre-adder Square Mode
a0 b0

Pupọ0

+/-

esi

8.1.1.5. Pre-adder Constant Ipo
Ni yi mode, ọkan multiplier operand yo lati input ibudo, ati awọn miiran operand yo lati awọn ti abẹnu olùsọdipúpọ ibi ipamọ. Ibi ipamọ olùsọdipúpọ ngbanilaaye to awọn iwọn tito tẹlẹ 8. Awọn ifihan agbara yiyan olùsọdipúpọ jẹ coefsel[0..3].
Ipo yii jẹ afihan ni idogba atẹle.

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 39

8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

Awọn wọnyi olusin fihan awọn aso-parapọ ibakan mode ti a multiplier.

olusin 14. Pre-adder Constant Mode
a0

Pupọ0

esi

coefsel0
kofa
8.1.2. Iforukọsilẹ Idaduro Systolic
Ninu faaji systolic, data igbewọle ti jẹ ifunni sinu kasikedi ti awọn iforukọsilẹ ti n ṣiṣẹ bi ifipamọ data. Iforukọsilẹ kọọkan n pese s titẹ siiample to a multiplier ibi ti o ti wa ni isodipupo nipasẹ awọn oniwun olùsọdipúpọ. Awọn paramọlẹ pq tọjú awọn maa ni idapo esi lati awọn multiplier ati awọn tẹlẹ aami-esi lati awọn chainin [] input ibudo lati dagba awọn ik esi. Ohun elo-ilọpo-ilọpo kọọkan gbọdọ jẹ idaduro nipasẹ yiyipo kan ki awọn abajade muṣiṣẹpọ ni deede nigbati a ba ṣafikun papọ. Idaduro ti o tẹle kọọkan ni a lo lati koju mejeeji iranti iyeida ati ifipamọ data ti awọn eroja isodipupo oniwun wọn. Fun example, a nikan idaduro fun awọn keji isodipupo fi ano, meji idaduro fun awọn kẹta isodipupo-fi ano, ati be be lo.
olusin 15. Systolic registers
Awọn iforukọsilẹ Systolic

x (t) c (0)

S -1

c(1)

S -1

c(2)

S -1

c(N-1)

S -1

S -1 y (t)

x (t) duro fun awọn abajade lati ṣiṣan lilọsiwaju ti awọn s igbewọleamples ati y (t)
duro fun akopọ ti ṣeto ti igbewọle samples, ati ni akoko, pupọ nipa wọn
oniwun iyeida. Mejeeji igbewọle ati awọn abajade abajade nṣàn lati osi si otun. c(0) si c(N-1) tọkasi awọn iye-iye. Awọn iforukọsilẹ idaduro systolic jẹ itọkasi nipasẹ S-1, lakoko ti 1 duro fun idaduro aago kan. Awọn iforukọsilẹ idaduro systolic ti wa ni afikun ni
awọn igbewọle ati awọn abajade fun pipelining ni ọna ti o ṣe idaniloju awọn abajade lati inu
operand multiplier ati awọn akojo apao duro ni synch. Eleyi processing ano
ti wa ni replicated lati fẹlẹfẹlẹ kan ti Circuit ti o oniṣiro awọn sisẹ iṣẹ. Iṣẹ yii jẹ
ti a fihan ni idogba atẹle.

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 40

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8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

N duro fun nọmba awọn iyika ti data ti o ti wọ inu ikojọpọ, y (t) duro fun iṣẹjade ni akoko t, A (t) duro fun titẹ sii ni akoko t, ati B (i) jẹ awọn iye-iye. t ati i ti o wa ninu idogba ṣe deede si iṣẹju kan pato ni akoko, nitorinaa lati ṣe iṣiro awọn abajade sample y (t) ni akoko t, ẹgbẹ kan ti igbewọle samples ni N oriṣiriṣi awọn aaye ni akoko, tabi A(n), A(n-1), A(n-2), … A(n-N+1) nilo. Awọn ẹgbẹ ti N igbewọle samples ti wa ni isodipupo nipasẹ N iyeida ati akopọ papo lati dagba awọn ik esi y.
Awọn faaji iforukọsilẹ systolic wa fun apao-2 ati apao-ti-4 awọn ipo. Fun awọn ipo faaji iforukọsilẹ systolic mejeeji, ifihan chainin akọkọ nilo lati so mọ 0.
Nọmba atẹle yii fihan imuse iforukọsilẹ idaduro systolic ti 2 multipliers.
Ṣe nọmba 16. Iforukọsilẹ Idaduro Systolic Imuse ti 2 Multipliers
chainin

Pupọ0

+/-

Pupọ1

+/-

esi
Awọn apao ti meji multipliers ti wa ni kosile ni awọn wọnyi idogba.
Nọmba atẹle yii fihan imuse iforukọsilẹ idaduro systolic ti 4 multipliers.

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 41

8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

Ṣe nọmba 17. Iforukọsilẹ Idaduro Systolic Imuse ti 4 Multipliers
chainin

Pupọ0

+/-

Pupọ1

+/-

Pupọ2

+/-

Pupọ3

+/-

esi
Awọn apao mẹrin multipliers ti wa ni kosile ni awọn wọnyi idogba. olusin 18. Apapọ 4 Multipliers
Awọn atẹle ṣe atokọ advantages of systolic Forukọsilẹ imuse: · Din DSP awọn oluşewadi lilo · Mu ki aworan agbaye ṣiṣẹ daradara ni DSP Àkọsílẹ nipa lilo awọn pq paramọlẹ be

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 42

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8.1.3. Pre-fifuye Constant
Igbagbogbo iṣaju iṣaju iṣakojọpọ nṣakoso operand ikojọpọ ati pe o ni ibamu pẹlu esi ikojọpọ. LOADCONST_VALUE to wulo wa lati 0. Iye igbagbogbo jẹ dogba si 64N, nibiti N = LOADCONST_VALUE. Nigba ti LOADCONST_VALUE ti ṣeto si 2, iye igbagbogbo jẹ dogba si 64. Iṣẹ yii le ṣee lo bi iyipo aiṣedeede.
Nọmba atẹle yii ṣe afihan imuse igbagbogbo fifuye ṣaaju.
olusin 19. Pre-fifuye Constant

Accumulator esi

ibakan

Pupọ0

+/-

Pupọ1

+/b1

esi

accum_sload sload_accum

Tọkasi awọn ohun kohun IP wọnyi fun awọn imuse isodipupo miiran: · ALTMULT_ACCUM · ALTMEMMULT · LPM_MULT
8.1.4. Double Accumulator
Ẹya ikojọpọ ilọpo meji ṣafikun iforukọsilẹ afikun ni ọna esi ikojọpọ. Iforukọsilẹ ikojọpọ ilọpo meji tẹle iforukọsilẹ iṣelọpọ, eyiti o pẹlu aago, ṣiṣẹ aago, ati aclr. Iforukọsilẹ ikojọpọ afikun da abajade pada pẹlu idaduro ọmọ-ọkan kan. Ẹya yii n gba ọ laaye lati ni awọn ikanni ikojọpọ meji pẹlu kika awọn orisun kanna.
Nọmba atẹle yii fihan imuse ikojọpọ ilọpo meji.

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 43

8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

olusin 20. Double Accumulator

Dou ble Accu mulator Forukọsilẹ

Accu mulator kikọ sii ck

Pupọ0

+/-

Pupọ1

+/b1

Iforukọsilẹ abajade esi

8.2. Verilog HDL Afọwọkọ
O le wa Intel FPGA Multiply Adder tabi ALTERA_MULT_ADD Verilog HDL apẹrẹ file (altera_mult_add_rtl.v) ninu awọn librariesmegafunctions liana.
8.3. Ikede paati VHDL
Ìkéde paati VHDL wa ni altera_lnsim_components.vhd ninu librariesvhdl altera_lnsim liana.
8.4. Ìkéde VHDL LIBRARY_USE
Ìkéde VHDL LIBRARY-LILO ko nilo ti o ba lo Ikede paati VHDL.
LIBRARY altera_mf; LO altera_mf.altera_mf_components.all;

8.5. Awọn ifihan agbara

Awọn tabili atẹle wọnyi ṣe atokọ igbewọle ati awọn ifihan agbara iṣelọpọ ti Multiply Adder Intel FPGA IPor ALTERA_MULT_ADD IP mojuto.

Tabili 28. Isodipupo Adder Intel FPGA IPor ALTERA_MULT_ADD Awọn ifihan agbara Input

Ifihan agbara

Ti beere fun

Apejuwe

dataa_0[]/data_1[]/

Bẹẹni

dataa_2[]/data_3[]

Data input to multiplier. Ibudo igbewọle [NUMBER_OF_MULTIPLIERS * WIDTH_A – 1 … 0] fife
tesiwaju…

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 44

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Signal datab_0[]/datab_1[]/ datab_2[]/datab_3[] datac_0[] /datac_1[]/ datac_2[]/datac_3[] aago[1:0] aclr[1:0] sclr[1:0] ena [1:0] ami
ami
scanina[] accum_sload

Ti beere Bẹẹni Bẹẹkọ
Bẹẹkọ Bẹẹkọ Bẹẹkọ Bẹẹkọ
Rara
Rara Bẹẹkọ

Apejuwe
Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si awọn ifihan agbara wọnyi. Nigbati o ba pese iye X si awọn ifihan agbara wọnyi, iye X ti tan kaakiri lori awọn ifihan agbara iṣẹjade.
Data input to multiplier. Ifihan agbara igbewọle [NUMBER_OF_MULTIPLIERS * WIDTH_B – 1 … 0] jakejado Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si awọn ifihan agbara wọnyi. Nigbati o ba pese iye X si awọn ifihan agbara wọnyi, iye X jẹ ikede lori awọn ifihan agbara ti o jade.
Data input to multiplier. Ifihan agbara igbewọle [NUMBER_OF_MULTIPLIERS * WIDTH_C – 1, … 0] jakejado Yan INPUT fun Yan ipo apejuwe lati mu awọn ifihan agbara wọnyi ṣiṣẹ. Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si awọn ifihan agbara wọnyi. Nigbati o ba pese iye X si awọn ifihan agbara wọnyi, iye X jẹ ikede lori awọn ifihan agbara ti o jade.
Titiipa ibudo titẹ sii aago si iforukọsilẹ ti o baamu. Yi ifihan agbara le ṣee lo nipa eyikeyi Forukọsilẹ ninu awọn IP mojuto. Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si awọn ifihan agbara wọnyi. Nigbati o ba pese iye X si awọn ifihan agbara wọnyi, iye X jẹ ikede lori awọn ifihan agbara ti o jade.
Iṣagbewọle alaiṣẹpọpọ si iforukọsilẹ ti o baamu. Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si awọn ifihan agbara wọnyi. Nigbati o ba pese iye X si awọn ifihan agbara wọnyi, iye X jẹ ikede lori awọn ifihan agbara ti o jade.
Iṣagbewọle mimọ amuṣiṣẹpọ si iforukọsilẹ ti o baamu. Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu X si awọn ifihan agbara wọnyi. Nigbati o ba pese iye X si awọn ifihan agbara wọnyi, iye X jẹ ikede lori awọn ifihan agbara ti o jade
Mu titẹ sii ifihan agbara ṣiṣẹ si iforukọsilẹ ti o baamu. Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si awọn ifihan agbara wọnyi. Nigbati o ba pese iye X si awọn ifihan agbara wọnyi, iye X jẹ ikede lori awọn ifihan agbara ti o jade.
Soju awọn nomba oniduro ti awọn multiplikator input A. Ti o ba ti awọn ifihan agbara ifihan jẹ ga, awọn itọju multiplier awọn multiplier input A ifihan bi a wole nọmba. Ti o ba ti awọn ifihan agbara ti wa ni kekere, awọn itọju multiplier input A ifihan agbara bi ohun unsigned nọmba. Yan VARIABLE fun Kini ọna kika oniduro fun Multipliers A paramita igbewọle lati mu ifihan agbara ṣiṣẹ. Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si ifihan agbara yii. Nigbati o ba pese iye X si titẹ sii yii, iye X ti wa ni ikede lori awọn ifihan agbara iṣẹjade.
Soju awọn nomba oniduro ti awọn multiplier input B ifihan agbara. Ti o ba ti signb ifihan agbara jẹ ga, awọn itọju multiplier input B ifihan agbara bi a wole meji ká iranlowo nọmba. Ti o ba ti signb ifihan agbara ti wa ni kekere, awọn itọju multiplier input B ifihan agbara bi ohun unsigned nọmba. Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si ifihan agbara yii. Nigbati o ba pese iye X si titẹ sii yii, iye X ti wa ni ikede lori awọn ifihan agbara iṣẹjade.
Iṣagbewọle fun ẹwọn ọlọjẹ A. Ifihan agbara titẹ sii [WIDTH_A – 1, … 0] fife. Nigbati paramita INPUT_SOURCE_A ni iye SCANA, a nilo ifihan agbara scanina.
Yiyi to pato boya awọn accumulator iye ni ibakan. Ti o ba ti accum_sload ifihan agbara ni kekere, ki o si awọn multiplier o wu wa ni ti kojọpọ sinu accumulator. Maṣe lo accum_sload ati sload_accum nigbakanna.
tesiwaju…

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 45

8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

Ifihan agbara sload_accum
chainin[] addnsub1
addnsub3
coefsel0[] coefsel1[] coefsel2[] coefsel3[]

Ti beere No
Rara Bẹẹkọ
Rara
Bẹẹkọ Bẹẹkọ Bẹẹkọ

Apejuwe
Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si ifihan agbara yii. Nigbati o ba pese iye X si titẹ sii yii, iye X ti wa ni ikede lori awọn ifihan agbara iṣẹjade.
Yiyi to pato boya awọn accumulator iye ni ibakan. Ti ifihan agbara sload_accum ba ga, lẹhinna a ti kojọpọ iṣelọpọ pupọ sinu ikojọpọ. Maṣe lo accum_sload ati sload_accum nigbakanna. Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si ifihan agbara yii. Nigbati o ba pese iye X si titẹ sii yii, iye X ti wa ni ikede lori awọn ifihan agbara iṣẹjade.
Bosi igbewọle esi paramọlẹ lati awọn s iṣaajutage. Ifihan agbara igbewọle [WIDTH_CHAININ – 1, … 0] fife.
Ṣe afikun tabi iyokuro si awọn abajade lati bata akọkọ ti multipliers. Tẹ 1 wọle si ifihan agbara addnsub1 lati ṣafikun awọn abajade lati bata meji ti multipliers akọkọ. Tẹ 0 wọle si ifihan addnsub1 lati yọkuro awọn abajade lati bata pupọ ti awọn onisọpo akọkọ. Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si ifihan agbara yii. Nigbati o ba pese iye X si titẹ sii yii, iye X ti wa ni ikede lori awọn ifihan agbara iṣẹjade.
Ṣe afikun tabi iyokuro si awọn abajade lati bata akọkọ ti multipliers. Input 1 to addnsub3 ifihan agbara lati fi awọn abajade lati awọn keji bata ti multipliers. Tẹ 0 wọle si ifihan addnsub3 lati yọkuro awọn abajade lati bata pupọ ti awọn onisọpo akọkọ. Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si ifihan agbara yii. Nigbati o ba pese iye X si titẹ sii yii, iye X ti wa ni ikede lori awọn ifihan agbara iṣẹjade.
ifihan agbara igbewọle olùsọdipúpọ [0: 3] si isodipupo akọkọ. Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si ifihan agbara yii. Nigbati o ba pese iye X si titẹ sii yii, iye X ti wa ni ikede lori awọn ifihan agbara iṣẹjade.
ifihan agbara igbewọle olùsọdipúpọ [0:3] si awọn keji multiplier. Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si ifihan agbara yii. Nigbati o ba pese iye X si titẹ sii yii, iye X ti wa ni ikede lori awọn ifihan agbara iṣẹjade.
ifihan agbara igbewọle olùsọdipúpọ [0:3] si awọn kẹta multiplier. Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si ifihan agbara yii. Nigbati o ba pese iye X si titẹ sii yii, iye X ti wa ni ikede lori awọn ifihan agbara iṣẹjade.
Alasọdipúpọ input ifihan agbara [0:3] to kẹrin multiplier. Awoṣe kikopa fun IP yii ṣe atilẹyin iye titẹ sii ti a ko pinnu (X) si ifihan agbara yii. Nigbati o ba pese iye X si titẹ sii yii, iye X ti wa ni ikede lori awọn ifihan agbara iṣẹjade.

Table 29. Isodipupo paramọlẹ Intel FPGA IP o wu awọn ifihan agbara

Ifihan agbara

Ti beere fun

Apejuwe

esi []

Bẹẹni

Multiplier o wu ifihan agbara. Ifihan agbara jade [WIDTH_RESULT – 1 … 0] fife

Awoṣe kikopa fun IP yii ṣe atilẹyin iye iṣelọpọ ti a ko pinnu (X). Nigbati o ba pese iye X bi titẹ sii, iye X ti tan kaakiri lori ifihan agbara yii.

scanouta []

Rara

Ijade ti ẹwọn ọlọjẹ A. Ojade ifihan agbara [WIDTH_A – 1..0] fife.

Yan diẹ ẹ sii ju 2 fun awọn nọmba ti multipliserer ki o si yan wíwọlé pq input fun Kini igbewọle A ti awọn multiplier ti sopọ si paramita lati jeki yi ifihan agbara.

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 46

Fi esi ranṣẹ

8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

8.6. Awọn ipin

8.6.1. Gbogbogbo Taabu

Table 30. Gbogbogbo Tab

Paramita

IP ti ipilẹṣẹ Paramita

Iye

Kini awọn nọmba ti multipliers?

nọmba_of_m 1 - 4 ultipliers

Bawo ni o yẹ ki awọn ọkọ akero titẹ sii width_a jẹ bi?

1 – 256

Bawo ni awọn bọọsi igbewọle B width_b yẹ ki o jẹ?

1 – 256

Bawo ni o yẹ ki ọkọ ayọkẹlẹ ti o jade 'esi' jẹ iwọn?

width_esi

1 – 256

Ṣẹda aago to somọ fun aago kọọkan

gui_associate Lori d_clock_enabl Pa e

8.6.2. Awọn ọna afikun Taabu

Table 31. Afikun igbe Tab

Paramita

IP ti ipilẹṣẹ Paramita

Iye

Iṣeto ni awọn abajade

Forukọsilẹ o wu ti paramọlẹ kuro

gui_output_re Tan

gister

Paa

Kini orisun fun titẹ sii aago?

gui_output_re gister_clock

Clock0 Aago1 Aago2

Kini orisun fun titẹ asynchronous ko o?

gui_output_re gister_aclr

Kò ACLR0 ACLR1

Kini orisun fun titẹ sii mimọ amuṣiṣẹpọ?

gui_output_re gister_sclr

Kò SCLR0 SCLR1

Isẹ paramọlẹ

Isẹ wo ni o yẹ ki o ṣe lori awọn abajade ti bata akọkọ ti multipliers?

gui_multiplier 1_direction

Ṣafikun, SUB, variABLE

Iye aiyipada 1
16

Apejuwe
Nọmba ti multipliers lati wa ni afikun papo. Awọn iye jẹ 1 soke si 4. Pato iwọn ti ibudo dataa[].

Pato awọn iwọn ti datab[] ibudo.

Pato iwọn abajade [] ibudo.

Paa

Yan aṣayan yii lati ṣẹda aago ṣiṣẹ

fun kọọkan aago.

Aiyipada Iye

Apejuwe

Pa Aago0
KO SI OKAN

Yan yi aṣayan lati jeki o wu Forukọsilẹ ti paramọlẹ module.
Yan Clock0, Clock1 tabi Clock2 lati mu ṣiṣẹ ati pato orisun aago fun awọn iforukọsilẹ iṣẹjade. O gbọdọ yan Iforukọsilẹ iṣẹjade ti ẹyọ paramita lati mu paramita yii ṣiṣẹ.
Sọtọ orisun asynchronous ko o fun iforukọsilẹ iṣelọpọ paramọlẹ. O gbọdọ yan Iforukọsilẹ iṣẹjade ti ẹyọ paramita lati mu paramita yii ṣiṣẹ.
Sọto orisun mimọ amuṣiṣẹpọ fun iforukọsilẹ iṣẹjade paramọlẹ. O gbọdọ yan Iforukọsilẹ iṣẹjade ti ẹyọ paramita lati mu paramita yii ṣiṣẹ.

FIKÚN

Yan afikun tabi iṣẹ iyokuro lati ṣe fun awọn abajade laarin akọkọ ati elekeji pupọ.
· Yan ADD lati ṣe iṣẹ afikun.
· Yan SUB lati ṣe iṣẹ iyokuro.
· Yan VARIABLE lati lo addnsub1 ibudo fun iṣakoso afikun/iyokuro ti o ni agbara.
tesiwaju…

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 47

8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

Paramita

IP ti ipilẹṣẹ Paramita

Iye

Forukọsilẹ 'adnsub1' igbewọle

gui_addnsub_ Lori multiplier_reg Pa ister1

Kini orisun fun titẹ sii aago?

gui_addnsub_ multiplier_reg ister1_clock

Clock0 Aago1 Aago2

Kini orisun fun titẹ asynchronous ko o?

gui_addnsub_ multiplier_aclr 1

Kò ACLR0 ACLR1

Kini orisun fun titẹ sii mimọ amuṣiṣẹpọ?

gui_addnsub_ multiplier_sclr 1

Kò SCLR0 SCLR1

Isẹ wo ni o yẹ ki o ṣe lori awọn abajade ti bata meji ti multipliers?

gui_multiplier 3_direction

Ṣafikun, SUB, variABLE

Forukọsilẹ 'adnsub3' igbewọle

gui_addnsub_ Lori multiplier_reg Pa ister3

Kini orisun fun titẹ sii aago?

gui_addnsub_ multiplier_reg ister3_clock

Clock0 Aago1 Aago2

Aiyipada Iye
Pa Clock0 KO SI OHUN FI
Pa Aago0

Apejuwe
Nigbati o ba yan iye VARIABLE: · Wakọ addnsub1 ifihan agbara si giga fun
afikun isẹ. · Wakọ addnsub1 ifihan agbara si kekere fun
iyokuro isẹ. O gbọdọ yan diẹ ẹ sii ju meji multipliers lati jeki yi paramita.
Yan aṣayan yii lati mu iforukọsilẹ titẹ sii ṣiṣẹ fun ibudo addnsub1. O gbọdọ yan VARIABLE fun iṣẹ wo ni o yẹ ki o ṣee ṣe lori awọn abajade ti bata meji ti multipliers akọkọ lati mu paramita yii ṣiṣẹ.
Yan Clock0, Clock1 tabi Clock2 lati pato ifihan aago titẹ sii fun iforukọsilẹ addnsub1. O gbọdọ yan Forukọsilẹ 'addnsub1' igbewọle lati jeki yi paramita.
Ṣetọ orisun mimọ asynchronous fun iforukọsilẹ addnsub1. O gbọdọ yan Forukọsilẹ 'addnsub1' igbewọle lati jeki yi paramita.
Ṣeto orisun mimọ amuṣiṣẹpọ fun iforukọsilẹ addnsub1. O gbọdọ yan Forukọsilẹ 'addnsub1' igbewọle lati jeki yi paramita.
Yan afikun tabi iṣẹ iyokuro lati ṣe fun awọn abajade laarin awọn onilọpo kẹta ati ẹkẹrin. · Yan ADD lati ṣe afikun
isẹ. · Yan SUB lati ṣe iyokuro
isẹ. Yan VARIABLE lati lo addnsub1
ibudo fun ìmúdàgba afikun / iyokuro Iṣakoso. Nigbati iye VARIABLE ti yan: · Wakọ addnsub1 ifihan agbara si giga fun iṣẹ afikun. Wakọ ifihan agbara addnsub1 si kekere fun iṣẹ iyokuro. O gbọdọ yan awọn iye 4 fun Kini awọn nọmba ti multipliers? lati jeki yi paramita.
Yan aṣayan yii lati mu iforukọsilẹ titẹ sii ṣiṣẹ fun ifihan addnsub3. O gbọdọ yan VARIABLE fun iṣẹ wo ni o yẹ ki o ṣee ṣe lori awọn abajade ti bata meji ti multipliers lati mu paramita yii ṣiṣẹ.
Yan Clock0, Clock1 tabi Clock2 lati pato ifihan aago titẹ sii fun iforukọsilẹ addnsub3. O gbọdọ yan Forukọsilẹ 'addnsub3' input lati jeki yi paramita.
tesiwaju…

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 48

Fi esi ranṣẹ

8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

Paramita
Kini orisun fun titẹ asynchronous ko o?

IP ti ipilẹṣẹ Paramita

Iye

gui_addnsub_ multiplier_aclr 3

Kò ACLR0 ACLR1

Kini orisun fun titẹ sii mimọ amuṣiṣẹpọ?

gui_addnsub_ multiplier_sclr 3

Kò SCLR0 SCLR1

Jeki Polarity ṣiṣẹ `lilo_subadd'

gui_use_sub Lori

fi kun

Paa

8.6.3. Multipliers Tab

Table 32. Multipliers Tab

Paramita

IP ti ipilẹṣẹ Paramita

Iye

Kini ni

gui_aṣoju

aṣoju ọna kika ation_a

fun Multipliers A awọn igbewọle?

Afọwọsi, ti ko forukọsilẹ, IYATO

Forukọsilẹ 'signa' igbewọle

gui_register_s Tan

igna

Paa

Kini orisun fun titẹ sii aago?

gui_register_s igna_clock

Clock0 Aago1 Aago2

Kini orisun fun titẹ asynchronous ko o?

gui_register_s igna_aclr

Kò ACLR0 ACLR1

Kini orisun fun titẹ sii mimọ amuṣiṣẹpọ?

gui_register_s igna_sclr

Kò SCLR0 SCLR1

Kini ni

gui_aṣoju

aṣoju ọna kika ation_b

fun Multipliers B awọn igbewọle?

Afọwọsi, ti ko forukọsilẹ, IYATO

Forukọsilẹ 'signb' igbewọle

gui_register_s Tan

ignb

Paa

Aiyipada Iye KO
KOSI

Apejuwe
Ṣetọ orisun mimọ asynchronous fun iforukọsilẹ addnsub3. O gbọdọ yan Forukọsilẹ 'addnsub3' igbewọle lati jeki yi paramita.
Ṣeto orisun mimọ amuṣiṣẹpọ fun iforukọsilẹ addnsub3. O gbọdọ yan Forukọsilẹ 'addnsub3' input lati jeki yi paramita.

Paa

Yan aṣayan yii lati yi iṣẹ naa pada

ti addnsub input ibudo.

Wakọ addnsub si giga fun iṣẹ iyokuro.

Wakọ addnsub si kekere fun iṣẹ afikun.

Aiyipada Iye

Apejuwe

UNSIGNED Pato ọna kika oniduro fun titẹ sii pupọ A.

Paa

Yan aṣayan yii lati mu ami ṣiṣẹ

forukọsilẹ.

O gbọdọ yan iye VARIABLE fun Kini ọna kika aṣoju fun awọn igbewọle Multipliers A? paramita lati jeki yi aṣayan.

Aago0

Yan Clock0, Clock1 tabi Clock2 lati mu ṣiṣẹ ati pato ifihan aago titẹ sii fun iforukọsilẹ ami.
O gbọdọ yan iforukọsilẹ 'signa' igbewọle lati mu paramita yii ṣiṣẹ.

KOSI

Ni pato orisun mimọ asynchronous fun iforukọsilẹ awọn ami.
O gbọdọ yan iforukọsilẹ 'signa' igbewọle lati mu paramita yii ṣiṣẹ.

KOSI

Sọto orisun mimọ amuṣiṣẹpọ fun iforukọsilẹ ami.
O gbọdọ yan iforukọsilẹ 'signa' igbewọle lati mu paramita yii ṣiṣẹ.

UNSIGNED Pato ọna kika oniduro fun titẹ sii B pupọ.

Paa

Yan aṣayan yii lati mu ami ami ṣiṣẹ

forukọsilẹ.

tesiwaju…

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 49

8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

Paramita

IP ti ipilẹṣẹ Paramita

Iye

Aiyipada Iye

Kini orisun fun titẹ sii aago?

gui_register_s ignb_clock

Clock0 Aago1 Aago2

Aago0

Kini orisun fun titẹ asynchronous ko o?

gui_register_s ignb_aclr

Kò ACLR0 ACLR1

Kini orisun fun titẹ sii mimọ amuṣiṣẹpọ?

gui_register_s ignb_sclr

Kò SCLR0 SCLR1

Iṣeto ti igbewọle
Forukọsilẹ input A ti awọn multiplier
Kini orisun fun titẹ sii aago?

gui_input_reg Tan

ister_a

Paa

gui_input_reg ister_a_clock

Clock0 Aago1 Aago2

KO SI OKAN
Pa Aago0

Kini orisun fun titẹ asynchronous ko o?

gui_input_reg ister_a_aclr

Kò ACLR0 ACLR1

Kini orisun fun titẹ sii mimọ amuṣiṣẹpọ?

gui_input_reg ister_a_sclr

Kò SCLR0 SCLR1

Forukọsilẹ input B ti awọn multiplier
Kini orisun fun titẹ sii aago?

gui_input_reg Tan

ister_b

Paa

gui_input_reg ister_b_clock

Clock0 Aago1 Aago2

Kò si pa clock0

Kini orisun fun titẹ asynchronous ko o?

gui_input_reg ister_b_aclr

Kò ACLR0 ACLR1

KOSI

Kini orisun fun titẹ sii mimọ amuṣiṣẹpọ?

gui_input_reg ister_b_sclr

Kò SCLR0 SCLR1

KOSI

Kini igbewọle A ti isodipupo ti a ti sopọ si?

gui_multiplier Multiplier input Multiplier

_igbewọle

Ṣiṣayẹwo titẹ sii pq

Apejuwe
O gbọdọ yan iye VARIABLE fun Kini ọna kika oniduro fun awọn igbewọle Multipliers B? paramita lati jeki yi aṣayan.
Yan Clock0, Clock1 tabi Clock2 lati mu ṣiṣẹ ati pato ifihan aago titẹ sii fun iforukọsilẹ ami. O gbọdọ yan Forukọsilẹ 'signb' igbewọle lati jeki yi paramita.
Ni pato orisun asynchronous ko o fun iforukọsilẹ ami. O gbọdọ yan Forukọsilẹ 'signb' igbewọle lati jeki yi paramita.
Ṣeto orisun mimọ amuṣiṣẹpọ fun iforukọsilẹ ami. O gbọdọ yan Forukọsilẹ 'signb' igbewọle lati jeki yi paramita.
Yan aṣayan yii lati mu iforukọsilẹ titẹ sii ṣiṣẹ fun ọkọ akero igbewọle data.
Yan Clock0, Clock1 tabi Clock2 lati mu ṣiṣẹ ati pato ifihan aago titẹ iforukọsilẹ fun ọkọ akero titẹ sii data. O gbọdọ yan Forukọsilẹ input A ti awọn multiplier lati jeki yi paramita.
Ni pato awọn iforukọsilẹ asynchronous ko o orisun fun awọn data input akero. O gbọdọ yan Forukọsilẹ input A ti awọn multiplier lati jeki yi paramita.
Sọtọ orisun mimọ amuṣiṣẹpọ iforukọsilẹ fun ọkọ akero titẹ sii data. O gbọdọ yan Forukọsilẹ input A ti awọn multiplier lati jeki yi paramita.
Yan aṣayan yii lati mu iforukọsilẹ titẹ sii ṣiṣẹ fun ọkọ akero igbewọle data.
Yan Clock0, Clock1 tabi Clock2 lati mu ṣiṣẹ ati pato ifihan aago titẹ iforukọsilẹ fun ọkọ akero titẹ sii data. O gbọdọ yan Forukọsilẹ input B ti awọn multiplier lati jeki yi paramita.
Ni pato awọn iforukọsilẹ asynchronous ko o orisun fun awọn data input akero. O gbọdọ yan Forukọsilẹ input B ti awọn multiplier lati jeki yi paramita.
Sọtọ orisun mimọ amuṣiṣẹpọ forukọsilẹ fun bosi igbewọle datab. O gbọdọ yan Forukọsilẹ input B ti awọn multiplier lati jeki yi paramita.
Yan orisun titẹ sii fun titẹ sii A ti multiplier.
tesiwaju…

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 50

Fi esi ranṣẹ

8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

Paramita

IP ti ipilẹṣẹ Paramita

Iye

Scanout A Iforukọsilẹ iṣeto ni

Forukọsilẹ o wu ti awọn ọlọjẹ pq

gui_scanouta Lori

_forukọsilẹ

Paa

Kini orisun fun titẹ sii aago?

gui_scanouta _register_clock k

Clock0 Aago1 Aago2

Kini orisun fun titẹ asynchronous ko o?

gui_scanouta _register_aclr

Kò ACLR0 ACLR1

Kini orisun fun titẹ sii mimọ amuṣiṣẹpọ?

gui_scanouta _register_sclr

Kò SCLR0 SCLR1

8.6.4. Taabu Preadder

Table 33. Preadder Tab

Paramita

IP ti ipilẹṣẹ Paramita

Iye

Yan ipo apesile

preadder_mo de

RỌRÙN, COEF, INPUT, Square, Ibakan

Aiyipada Iye

Apejuwe
Yan titẹ sii Multiplier lati lo ọkọ akero igbewọle data bi orisun si isodipupo. Yan Ayẹwo pq igbewọle lati lo scanin input akero bi awọn orisun si awọn multiplier ati ki o jeki awọn scanout o wu akero. Yi paramita ti o wa nigbati o ba yan 2, 3 tabi 4 fun Kini awọn nọmba ti multipliers? paramita.

Pa Clock0 KO SI

Yan yi aṣayan lati jeki o wu Forukọsilẹ fun scanouta o wu akero.
O gbọdọ yan wíwo pq input fun Kí ni input A ti awọn multiplier ti a ti sopọ si? paramita lati jeki yi aṣayan.
Yan Clock0 , Clock1 tabi Clock2 lati mu ṣiṣẹ ati pato ifihan aago titẹ iforukọsilẹ fun ọkọ ayọkẹlẹ ti njade scanouta.
O gbọdọ tan iṣẹjade Forukọsilẹ ti paramita pq ọlọjẹ lati mu aṣayan yii ṣiṣẹ.
Ni pato awọn iforukọsilẹ asynchronous ko o orisun fun awọn scanouta o wu akero.
O gbọdọ tan iṣẹjade Forukọsilẹ ti paramita pq ọlọjẹ lati mu aṣayan yii ṣiṣẹ.
Ni pato awọn iforukọsilẹ amuṣiṣẹpọ ko o orisun fun awọn scanouta o wu akero.
O gbọdọ yan Iforukọsilẹ iṣelọpọ ti paramita pq ọlọjẹ lati mu aṣayan yii ṣiṣẹ.

Aiyipada Iye
RỌRỌRUN

Apejuwe
So awọn isẹ mode fun preadder module. RỌRỌ: Ipo yii fori atẹlẹsẹ naa. Eyi ni ipo aiyipada. COEF: Eleyi mode nlo awọn o wu ti awọn preadder ati coefsel input akero bi awọn igbewọle si awọn multiplier. INPUT: Eleyi mode nlo awọn o wu ti awọn preadder ati datac input akero bi awọn igbewọle si awọn multiplier. SQUARE: Ipo yii nlo iṣẹjade ti preadder bi mejeeji awọn igbewọle si isodipupo.
tesiwaju…

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 51

8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

Paramita

IP ti ipilẹṣẹ Paramita

Iye

Yan itọsọna apilẹṣẹ

gui_reader ADD,

_itọnisọna

SUB

Bawo ni awọn ọkọ akero igbewọle C width_c yẹ ki o jẹ?

1 – 256

Data C Input Forukọsilẹ iṣeto ni

Forukọsilẹ datac input

gui_datac_inp Lori

ut_forukọsilẹ

Paa

Kini orisun fun titẹ sii aago?

gui_datac_inp ut_register_cl oki

Clock0 Aago1 Aago2

Kini orisun fun titẹ asynchronous ko o?

gui_datac_inp ut_register_a clr

Kò ACLR0 ACLR1

Kini orisun fun titẹ sii mimọ amuṣiṣẹpọ?

gui_datac_inp ut_register_sc lr

Kò SCLR0 SCLR1

Awọn iye-iye
Báwo ló ṣe yẹ kí ìbú màlúù náà fẹ̀ tó?

width_coef

1 – 27

Coef Forukọsilẹ iṣeto ni

Forukọsilẹ titẹ sii coefsel

gui_coef_regi Lori

ster

Paa

Kini orisun fun titẹ sii aago?

gui_coef_regi ster_clock

Clock0 Aago1 Aago2

Aiyipada Iye
FIKÚN
16

Apejuwe
Ibapakan: Ipo yii nlo ọkọ akero igbewọle dataa pẹlu iṣaju iṣaju ati ọkọ akero igbewọle coefsel bi awọn igbewọle si isodipupo.
So isẹ ti awọn preadder. Lati mu paramita yii ṣiṣẹ, yan atẹle naa fun Yan ipo atẹlẹsẹ: · COEF · INPUT · SQUARE tabi · COSTANT
Pato awọn nọmba ti die-die fun C input akero. O gbọdọ yan INPUT fun Yan ipo atẹlẹsẹ lati mu paramita yii ṣiṣẹ.

Lori Clock0 KO SI OKAN

Yan aṣayan yii lati mu iforukọsilẹ titẹ sii ṣiṣẹ fun ọkọ akero igbewọle datac. O gbọdọ ṣeto INPUT lati Yan ipo paramita lati mu aṣayan yii ṣiṣẹ.
Yan Clock0, Clock1 tabi Clock2 lati pato ifihan aago titẹ sii fun iforukọsilẹ datac input. O gbọdọ yan Forukọsilẹ datac input lati jeki yi paramita.
Ṣetọ orisun mimọ asynchronous fun iforukọsilẹ titẹ sii datac. O gbọdọ yan Forukọsilẹ datac input lati jeki yi paramita.
Sọto orisun mimọ amuṣiṣẹpọ fun iforukọsilẹ titẹ sii datac. O gbọdọ yan Forukọsilẹ datac input lati jeki yi paramita.

So awọn nọmba ti die-die fun

coefsel input akero.

O gbọdọ yan COEF tabi CONSTANT fun ipo iṣaju lati mu paramita yii ṣiṣẹ.

Lori aago0

Yan aṣayan yii lati mu iforukọsilẹ titẹ sii fun ọkọ akero titẹ sii coefsel. O gbọdọ yan COEF tabi CONSTANT fun ipo iṣaju lati mu paramita yii ṣiṣẹ.
Yan Clock0, Clock1 tabi Clock2 lati pato ifihan aago titẹ sii fun iforukọsilẹ titẹ sii coefsel. O gbọdọ yan Forukọsilẹ titẹ sii coefsel lati mu paramita yii ṣiṣẹ.
tesiwaju…

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 52

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8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

Paramita
Kini orisun fun titẹ asynchronous ko o?

IP ti ipilẹṣẹ Paramita

Iye

gui_coef_regi ster_aclr

Kò ACLR0 ACLR1

Kini orisun fun titẹ sii mimọ amuṣiṣẹpọ

gui_coef_regi ster_sclr

Kò SCLR0 SCLR1

Coefficient_0 Iṣeto ni

coef0_0 si coef0_7

0x00000 0xFFFFFF

Coefficient_1 Iṣeto ni

coef1_0 si coef1_7

0x00000 0xFFFFFF

Coefficient_2 Iṣeto ni

coef2_0 si coef2_7

0x00000 0xFFFFFF

Coefficient_3 Iṣeto ni

coef3_0 si coef3_7

0x00000 0xFFFFFF

8.6.5. Accumulator Tab

Table 34. Accumulator Tab

Paramita

IP ti ipilẹṣẹ Paramita

Iye

Mu alakojo ṣiṣẹ bi?

akojo

BEENI BEEKO

Kini iru iṣẹ accumulator?

accum_directi ADD,

SUB

Aiyipada Iye KO
KOSI
0x0000000
0x0000000
0x0000000
0x0000000

Apejuwe
Sọto orisun mimọ asynchronous fun iforukọsilẹ titẹ sii coefsel. O gbọdọ yan Forukọsilẹ titẹ sii coefsel lati mu paramita yii ṣiṣẹ.
Ṣeto orisun mimọ amuṣiṣẹpọ fun iforukọsilẹ titẹ sii coefsel. O gbọdọ yan Forukọsilẹ titẹ sii coefsel lati mu paramita yii ṣiṣẹ.
Ni pato awọn iye-iye fun onisọdipúpọ akọkọ yii. Nọmba awọn die-die gbọdọ jẹ kanna gẹgẹbi a ti pato ninu Bawo ni o yẹ ki ibú coef jẹ bi? paramita. O gbọdọ yan COEF tabi CONSTANT fun ipo iṣaju lati mu paramita yii ṣiṣẹ.
So awọn iye alasọdipúpọ fun elekeji yi. Nọmba awọn die-die gbọdọ jẹ kanna gẹgẹbi a ti pato ninu Bawo ni o yẹ ki ibú coef jẹ bi? paramita. O gbọdọ yan COEF tabi CONSTANT fun ipo iṣaju lati mu paramita yii ṣiṣẹ.
So awọn iye alasọdipúpọ fun yi kẹta multiplier. Nọmba awọn die-die gbọdọ jẹ kanna gẹgẹbi a ti pato ninu Bawo ni o yẹ ki ibú coef jẹ bi? paramita. O gbọdọ yan COEF tabi CONSTANT fun ipo iṣaju lati mu paramita yii ṣiṣẹ.
Ni pato awọn iye alasọdipúpọ fun yi kẹrin multiplier. Nọmba awọn die-die gbọdọ jẹ kanna gẹgẹbi a ti pato ninu Bawo ni o yẹ ki ibú coef jẹ bi? paramita. O gbọdọ yan COEF tabi CONSTANT fun ipo iṣaju lati mu paramita yii ṣiṣẹ.

Aiyipada Iye NỌ
FIKÚN

Apejuwe
Yan BẸẸNI lati jeki akojo. O gbọdọ yan Forukọsilẹ ti o wu ti paramọlẹ kuro nigba lilo accumulator ẹya ara ẹrọ.
Sọ iṣẹ ṣiṣe ti ikojọpọ: · ADD fun iṣẹ afikun · SUB fun iṣẹ iyokuro. O gbọdọ yan BẸẸNI fun Muu accumulator ṣiṣẹ? paramita lati jeki yi aṣayan.
tesiwaju…

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 53

8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

Paramita
Iṣagbekalẹ Constant Muu iṣaju iṣaju igbagbogbo ṣiṣẹ

IP ti ipilẹṣẹ Paramita

Iye

gui_ena_prelo Lori

ad_const

Paa

Kini igbewọle ti akojo ibudo ti a ti sopọ si?

gui_accumula ACCUM_SLOAD, te_port_select SLOAD_ACCUM

Yan iye fun iṣaju iṣaju loadconst_val 0 – 64

ibakan

Kini orisun fun titẹ sii aago?

aago gui_accum_sl oad_register_

Clock0 Aago1 Aago2

Kini orisun fun titẹ asynchronous ko o?

gui_accum_sl oad_register_ aclr

Kò ACLR0 ACLR1

Kini orisun fun titẹ sii mimọ amuṣiṣẹpọ?

gui_accum_sl oad_register_ sclr

Kò SCLR0 SCLR1

Mu olukojo meji ṣiṣẹ

gui_double_a Lori

kumu

Paa

Aiyipada Iye

Apejuwe

Paa

Mu accum_sload ṣiṣẹ tabi

sload_accum awọn ifihan agbara ati forukọsilẹ input

lati dynamically yan awọn input si awọn

akojo.

Nigba ti accum_sload ni kekere tabi sload_accum, awọn multiplier o wu kikọ sii sinu accumulator.

Nigbati accum_sload ba ga tabi sload_accum, olumulo kan pato iṣaju iṣaju ibakan jẹ ifunni sinu ikojọpọ.

O gbọdọ yan BẸẸNI fun Muu accumulator ṣiṣẹ? paramita lati jeki yi aṣayan.

ACCUM_SL OAD

Ni pato ihuwasi accum_sload/ sload_accum ifihan agbara.
ACCUM_SLOAD: Wakọ accum_sload kekere lati gbejade iṣelọpọ pupọ si ikojọpọ.
SLOAD_ACCUM: Wakọ sload_accum ga lati ṣagbejade iṣelọpọ pupọ si ikojọpọ.
O gbọdọ yan Muu aṣayan iṣaju iṣaju igbagbogbo ṣiṣẹ lati mu paramita yii ṣiṣẹ.

Pato iye igbagbogbo tito tẹlẹ.

Iye yii le jẹ 2N nibiti N jẹ iye igbagbogbo tito tẹlẹ.

Nigbati N=64, o duro fun odo igbagbogbo.

O gbọdọ yan Muu aṣayan iṣaju iṣaju igbagbogbo ṣiṣẹ lati mu paramita yii ṣiṣẹ.

Aago0

Yan Clock0, Clock1 tabi Clock2 lati pato ifihan aago titẹ sii fun iforukọsilẹ accum_sload/sload_accum.
O gbọdọ yan Muu aṣayan iṣaju iṣaju igbagbogbo ṣiṣẹ lati mu paramita yii ṣiṣẹ.

KOSI

Ni pato orisun mimọ asynchronous fun iforukọsilẹ accum_sload/sload_accum.
O gbọdọ yan Muu aṣayan iṣaju iṣaju igbagbogbo ṣiṣẹ lati mu paramita yii ṣiṣẹ.

KOSI

Ṣeto orisun mimọ amuṣiṣẹpọ fun iforukọsilẹ accum_sload/sload_accum.
O gbọdọ yan Muu aṣayan iṣaju iṣaju igbagbogbo ṣiṣẹ lati mu paramita yii ṣiṣẹ.

Paa

Mu ki awọn ė akojo Forukọsilẹ.

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 54

Fi esi ranṣẹ

8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

8.6.6. Systolic/Chainout Taabu

Table 35. Systolic / Chainout paramọlẹ Tab

Paramita Jeki chainout paramọlẹ

IP ti ipilẹṣẹ Paramita

Iye

chainout_fikun BẸẸNI,

RARA

Kini iru iṣẹ ṣiṣe ti paramọlẹ chainout?

chainout_afikun ADD,

er_direction

SUB

Mu igbewọle `negate' ṣiṣẹ fun paramọlẹ chainout bi?

Port_negate

PORT_USED, PORT_UNUSED

Ṣe iforukọsilẹ 'ailopin' igbewọle? negate_regist Eri

TI KO forukọsilẹ, CLOCK0, CLOCK1, CLOCK2, CLOCK3

Kini orisun fun titẹ asynchronous ko o?

negate_aclr

Kò ACLR0 ACLR1

Kini orisun fun titẹ sii mimọ amuṣiṣẹpọ?

negate_sclr

Kò SCLR0 SCLR1

Idaduro Systolic
Mu awọn iforukọsilẹ idaduro systolic ṣiṣẹ

gui_systolic_d Tan

elay

Paa

Kini orisun fun titẹ sii aago?

gui_systolic_d CLOCK0,

aago_elay

Aago 1,

Aiyipada Iye
RARA

Apejuwe
Yan BẸẸNI lati jeki chainout paramọlẹ module.

FIKÚN

Ni pato iṣẹ paramọlẹ chainout.
Fun iṣẹ iyokuro, SIGNED gbọdọ yan fun Kini ọna kika aṣoju fun awọn igbewọle Multipliers A? ati Kini ọna kika oniduro fun awọn igbewọle Multipliers B? ni Multipliers Tab.

PORT_UN LO

Yan PORT_USED lati mu ifihan agbara titẹ negate ṣiṣẹ.
Paramita yii ko wulo nigbati paramita chainout jẹ alaabo.

RED REGIST

Lati jeki iforukọsilẹ titẹ sii fun ifihan agbara titẹ sii negate ati pato ifihan aago titẹ sii fun iforukọsilẹ negate.
Yan UNFISTERI ti iforukọsilẹ titẹ sii negate si ko nilo
Paramita yii ko wulo nigbati o yan:
· KO fun Jeki chainout paramọlẹ tabi
· PORT_UNUSED fun Jeki igbewọle 'negate' fun paramọlẹ chainout bi? paramita tabi

KOSI

Ni pato orisun mimọ asynchronous fun iforukọsilẹ negate.
Paramita yii ko wulo nigbati o yan:
· KO fun Jeki chainout paramọlẹ tabi
· PORT_UNUSED fun Jeki igbewọle 'negate' fun paramọlẹ chainout bi? paramita tabi

KOSI

Ṣeto orisun mimọ amuṣiṣẹpọ fun iforukọsilẹ negate.
Paramita yii ko wulo nigbati o yan:
· KO fun Jeki chainout paramọlẹ tabi
· PORT_UNUSED fun Jeki igbewọle 'negate' fun paramọlẹ chainout bi? paramita tabi

Pa CLOCK0

Yan aṣayan yii lati mu ipo systolic ṣiṣẹ. Yi paramita ti o wa nigbati o ba yan 2, tabi 4 fun Kini awọn nọmba ti multipliers? paramita. O gbọdọ mu iṣẹjade Iforukọsilẹ ti ẹyọkan paramọlẹ ṣiṣẹ lati lo awọn iforukọsilẹ idaduro systolic.
Ṣe apejuwe ifihan aago titẹ sii fun iforukọsilẹ idaduro systolic.
tesiwaju…

Fi esi ranṣẹ

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 55

8. Intel FPGA isodipupo paramọlẹ IP mojuto 683490 | 2020.10.05

Paramita

IP ti ipilẹṣẹ Paramita

Iye

Aago 2,

Kini orisun fun titẹ asynchronous ko o?

gui_systolic_d elay_aclr

Kò ACLR0 ACLR1

Kini orisun fun titẹ sii mimọ amuṣiṣẹpọ?

gui_systolic_d elay_sclr

Kò SCLR0 SCLR1

Aiyipada Iye
KOSI
KOSI

Apejuwe
O gbọdọ yan mu awọn iforukọsilẹ idaduro systolic ṣiṣẹ lati mu aṣayan yii ṣiṣẹ.
Ni pato orisun mimọ asynchronous fun iforukọsilẹ idaduro systolic. O gbọdọ yan mu awọn iforukọsilẹ idaduro systolic ṣiṣẹ lati mu aṣayan yii ṣiṣẹ.
Sọto orisun mimọ amuṣiṣẹpọ fun iforukọsilẹ idaduro systolic. O gbọdọ yan mu awọn iforukọsilẹ idaduro systolic ṣiṣẹ lati mu aṣayan yii ṣiṣẹ.

8.6.7. Pipelining Tab

Table 36. Pipelining Tab

Parameter Pipelining iṣeto ni

IP ti ipilẹṣẹ Paramita

Iye

Ṣe o fẹ lati ṣafikun iforukọsilẹ opo gigun ti epo si titẹ sii?

gui_pipelining Rara, Bẹẹni

Aiyipada Iye
Rara

Jọwọ pato awọn

lairi

nọmba ti lairi aago

awọn iyipo

Eyikeyi iye ti o tobi ju 0 lọ

Kini orisun fun titẹ sii aago?

gui_input_late ncy_clock

CLOCK0, CLOCK1, CLOCK2

Kini orisun fun titẹ asynchronous ko o?

gui_input_late ncy_aclr

Kò ACLR0 ACLR1

Kini orisun fun titẹ sii mimọ amuṣiṣẹpọ?

gui_input_late ncy_sclr

Kò SCLR0 SCLR1

CLOCK0 KO SI

Apejuwe
Yan Bẹẹni lati jeki ipele afikun ti iforukọsilẹ opo gigun ti epo si awọn ifihan agbara titẹ sii. O gbọdọ pato kan iye ti o tobi ju 0 fun Jọwọ pato awọn nọmba ti lairi aago paramita.
Sọtọ airi ti o fẹ ni awọn akoko aago. Ipele kan ti iforukọsilẹ opo gigun ti epo = 1 lairi ni iyipo aago. O gbọdọ yan BẸẸNI fun Ṣe o fẹ lati fi iforukọsilẹ opo gigun ti epo si titẹ sii? lati jeki yi aṣayan.
Yan Clock0, Clock1 tabi Clock2 lati mu ṣiṣẹ ati pato ifihan aago titẹ sii iforukọsilẹ opo gigun ti epo. O gbọdọ yan BẸẸNI fun Ṣe o fẹ lati fi iforukọsilẹ opo gigun ti epo si titẹ sii? lati jeki yi aṣayan.
Ṣeto iforukọsilẹ orisun mimọ asynchronous fun afikun iforukọsilẹ opo gigun ti epo. O gbọdọ yan BẸẸNI fun Ṣe o fẹ lati fi iforukọsilẹ opo gigun ti epo si titẹ sii? lati jeki yi aṣayan.
Sọtọ orisun mimọ amuṣiṣẹpọ iforukọsilẹ fun iforukọsilẹ opo gigun ti epo. O gbọdọ yan BẸẸNI fun Ṣe o fẹ lati fi iforukọsilẹ opo gigun ti epo si titẹ sii? lati jeki yi aṣayan.

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 56

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683490 | 2020.10.05 Firanṣẹ esi

9. ALTMEMMULT (Memory-orisun Constant olùsọdipúpọ Multiplier) IP mojuto

Ifarabalẹ:

Intel ti yọ atilẹyin IP yii kuro ni ẹya Intel Quartus Prime Pro Edition 20.3. Ti ipilẹ IP inu apẹrẹ rẹ ba fojusi awọn ẹrọ ni Intel Quartus Prime Pro Edition, o le rọpo IP pẹlu LPM_MULT Intel FPGA IP tabi tun-ipilẹṣẹ IP ki o ṣajọ apẹrẹ rẹ nipa lilo sọfitiwia Intel Quartus Prime Standard Edition.

AlTMEMMULT IP mojuto ni a lo lati ṣẹda awọn isodipupo ti o da lori iranti ni lilo awọn bulọọki iranti onchip ti a rii ni Intel FPGA (pẹlu M512, M4K, M9K, ati awọn bulọọki iranti MLAB). Ipilẹ IP yii wulo ti o ko ba ni awọn orisun to lati ṣe imuse awọn isodipupo ni awọn eroja kannaa (LEs) tabi awọn orisun isodipupo igbẹhin.
AlTMEMMULT IP mojuto jẹ iṣẹ amuṣiṣẹpọ ti o nilo aago kan. AlTMEMMULT IP mojuto n ṣe imuse pupọ pẹlu ilosi ti o kere julọ ati lairi ti o ṣee ṣe fun eto ti a fun ti awọn paramita ati awọn pato.
Nọmba atẹle yii fihan awọn ebute oko oju omi fun ALTMEMMULT IP mojuto.

olusin 21. ALTMEMMULT Ports

ALTMEMMULT

data_in[] sload_data coeff_in[]

esi[] abajade_valid load_done

sload_coeff

sclr aago
inst

Alaye ti o jọmọ Awọn ẹya ara ẹrọ loju iwe 71

9.1. Awọn ẹya ara ẹrọ
AlTMEMMULT IP mojuto nfunni awọn ẹya wọnyi: · Ṣẹda awọn isodipupo ti o da lori iranti nikan nipa lilo awọn bulọọki iranti lori-chip ti a rii ni
Intel FPGAs · Atilẹyin data iwọn ti 1 bits · Atilẹyin ti fowo si ati ọna kika aṣoju data ti a ko fowo si · Atilẹyin pipelining pẹlu airi iṣelọpọ ti o wa titi

ISO 9001: 2015 forukọsilẹ

9. ALTMEMMULT (Memory-orisun Constant olùsọdipúpọ Multiplier) IP Core 683490 | 2020.10.05
+ Ṣafipamọ awọn iye-idaduro ni iranti wiwọle laileto (Ramu)
· Pese aṣayan lati yan awọn Ramu Àkọsílẹ iru
· Atilẹyin iyan amuṣiṣẹpọ ko o ati fifuye-Iṣakoso awọn ebute oko input
9.2. Verilog HDL Afọwọkọ
Afọwọkọ Verilog HDL atẹle wa ni Apẹrẹ Verilog File (.v) altera_mf.v ninu awọn eda synthesis liana.
module altmemmult #( paramita coeff_representation = "SIGNED", parameter coefficient0 = "UNUSED", parameter data_representation = "SIGNED", parameter ti a pinnu_device_family = "ailolo", parameter max_clock_cycles_per_result = 1, parameter number_of_coefficient AU total_latency = 1, paramita width_c = 1, paramita width_d = 1, paramita width_r = 1, paramita width_s = 1, paramita lpm_type = “altmemmult”, paramita lpm_hint = “ailolo”) (aago waya titẹ sii, okun waya titẹ sii [iwọn_c-1: 1]coeff_in, okun waya titẹ sii [width_d-0:1] data_in, waya agbejade load_done, waya ti njade [width_r-0:1] abajade, abajade waya ti njade_valid, waya titẹ sii sclr, okun titẹ sii [width_s-0:1] sel, titẹ sii waya sload_coeff, input waya sload_data)/* kolaginni syn_black_box=0 */; endmodule
9.3. Ikede paati VHDL
Ìkéde paati VHDL wa ninu Apẹrẹ VHDL File (.vhd) altera_mf_components.vhd ninu awọn librariesvhdlaltera_mf liana.
paati altmemmult jeneriki (coeff_representation: okun: = "SIGNED"; olùsọdipúpọ0: okun : = "UNUSED"; data_representation: okun : = "SIGNED"; ti a pinnu_device_family: okun : = "ailolo"; max_clock_cycles_per_result = adayeba nọmba:_natural:s_natural number:_natural number:_natural number:_natural number: : = 1; ram_block_type: string: = "AUTO"; "altmemmult"); ibudo ( aago: ni std_logic; coeff_in: ni std_logic_vector (width_c-1 si isalẹ 1): = (awọn omiiran => '1'); data_in: ni std_logic_vector (width_d-0 si isalẹ 0);

Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 58

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9. ALTMEMMULT (Memory-orisun Constant olùsọdipúpọ Multiplier) IP Core 683490 | 2020.10.05

fifuye_ṣe: jade std_logic; esi: jade std_logic_vector (width_r-1 si isalẹ 0); result_valid: jade std_logic; sclr: ni std_logic: = '0'; sel:in std_logic_vector(width_s-1 si isalẹ 0): = (awọn omiiran => '0'); sload_coeff: ni std_logic: = '0'; sload_data: ni std_logic: = '0'); paati ipari;

9.4. Awọn ibudo

Awọn tabili atẹle ṣe atokọ igbewọle ati awọn ebute agbejade fun ALTMEMMULT IP mojuto.

Table 37. ALTMEMMULT Input Ports

Orukọ Port

Ti beere fun

Apejuwe

aago

Bẹẹni

Aago igbewọle si awọn multiplier.

coeff_in[]

Rara

Olusọdipúpọ input ibudo fun multiplier. Iwọn ibudo titẹ sii da lori iye paramita WIDTH_C.

data_in[]

Bẹẹni

Data input ibudo to multiplier. Iwọn ibudo titẹ sii da lori iye paramita WIDTH_D.

sclr

Rara

Iṣagbewọle mimọ amuṣiṣẹpọ. Ti ko ba lo, iye aiyipada nṣiṣẹ ga.

ara[]

Rara

Aṣayan olùsọdipúpọ ti o wa titi. Iwọn ibudo titẹ sii da lori WIDTH_S

paramita iye.

sload_coeff

Rara

Amuṣiṣẹpọ fifuye olùsọdipúpọ input ibudo. Rọpo iye olùsọdipúpọ ti o yan lọwọlọwọ pẹlu iye ti a pato ninu titẹ sii coeff_in.

sload_data

Rara

Amuṣiṣẹpọ fifuye data input ibudo. Ifihan agbara ti o ṣalaye iṣẹ isodipupo tuntun ati fagile eyikeyi iṣẹ isodipupo ti o wa tẹlẹ. Ti paramita MAX_CLOCK_CYCLES_PER_RESULT ni iye kan ti 1, ibudo igbewọle sload_data ko bikita.

Table 38. ALTMEMMULT o wu Ports

Orukọ Port

Ti beere fun

Apejuwe

abajade[]

Bẹẹni

Multiplier o wu ibudo. Iwọn ibudo titẹ sii da lori iye paramita WIDTH_R.

abajade_wulo

Bẹẹni

Tọkasi nigbati abajade jẹ abajade to wulo ti isodipupo pipe. Ti paramita MAX_CLOCK_CYCLES_PER_RESULT ni iye kan ti 1, ibudo abajade abajade_valid ko lo.

fifuye_ti ṣe

Rara

Tọkasi nigbati olùsọdipúpọ tuntun ti pari ikojọpọ. Awọn ifihan agbara load_done sọ nigbati olùsọdipúpọ tuntun ti pari ikojọpọ. Ayafi ti ifihan load_done ba ga, ko si iye alasọdipupo miiran ti a le kojọpọ sinu iranti.

9.5. Awọn ipin

Tabili ti o tẹle ṣe atokọ awọn aye fun ipilẹ IP ALTMEMMULT.

Tabili 39.
WIDTH_D WIDTH_C

ALTMEMMULT paramita
Orukọ paramita

Iru Ti beere fun

Apejuwe

Odidi Bẹẹni

Sọ awọn iwọn ti data_in[] ibudo.

Odidi Bẹẹni

Ntọka iwọn ti ibudo coeff_in[]. tesiwaju…

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Intel FPGA Integer Itọnisọna Olumulo Awọn Cores IP Arithmetic 59

9. ALTMEMMULT (Memory-orisun Constant olùsọdipúpọ Multiplier) IP Core 683490 | 2020.10.05

Orukọ paramita WIDTH_R WIDTH

Awọn iwe aṣẹ / Awọn orisun

intel FPGA Integer Arithmetic IP ohun kohun [pdf] Itọsọna olumulo
FPGA Integer Awọn Cores IP Arithmetic, Integer IP Cores, Awọn Cores IP Arithmetic, Awọn Kokoro IP

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Itọsọna olumulo

FPGA Integer Arithmetic IP ohun kohun

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