Ifiranṣẹ aṣiṣe intel Forukọsilẹ Unloader FPGA IP

Ifiranṣẹ aṣiṣe Iforukọsilẹ Unloader Intel® FPGA IP Itọsọna olumulo Core

Ifiranṣẹ Aṣiṣe Iforukọsilẹ Unloader Intel® FPGA IP mojuto (altera_emr_unloader) n ka ati tọju data lati inu ẹrọ wiwa aṣiṣe lile ni awọn ẹrọ Intel FPGA ti o ni atilẹyin. O le lo Ifiranṣẹ Aṣiṣe Iforukọsilẹ Unloader IP core's Avalon® Streaming (Avalon-ST) ni wiwo kannaa lati ka ẹrọ EMR naa.

olusin 1. Aṣiṣe Ifiranṣẹ Forukọsilẹ Unloader Block aworan atọka

Nigbati ohun elo ba ṣe imudojuiwọn akoonu EMR, mojuto IP naa ka (tabi gbejade) ati sọ akoonu EMR sọ di mimọ, ati gba oye miiran (bii Intel FPGA Advanced SEU Detection IP mojuto, Intel FPGA Fault Injection IP mojuto, tabi kannaa olumulo) lati wọle si akoonu EMR nigbakanna.

Awọn ẹya ara ẹrọ

• Ngba pada ati fipamọ awọn akoonu ifiranṣẹ iforukọsilẹ aṣiṣe fun awọn ẹrọ FPGA Intel
• Awọn iyọọda abẹrẹ ti iye akoonu iforukọsilẹ EMR laisi iyipada awọn die-die CRAM
• Avalon (-ST) ni wiwo
• Ifarabalẹ irọrun pẹlu olootu paramita GUI
• Ṣe ipilẹṣẹ VHDL tabi Verilog HDL kolaginni files

IP mojuto Device Support

Awọn ẹrọ atẹle ṣe atilẹyin Ifiranṣẹ Aṣiṣe Iforukọsilẹ Unloader IP mojuto:

Table 1. IP mojuto Device Support

Software oniru	IP mojuto Device Support
Intel Quartus® NOMBA Pro Edition	Intel Arria® 10 ati Intel Cyclone® 10 GX awọn ẹrọ
Intel kuotisi NOMBA Standard Edition	Arria V, Arria II GX/GZ, Intel Arria 10, Cyclone V, Stratix® IV, ati awọn ẹrọ Stratix V

Awọn oluşewadi iṣamulo ati Performance

Sọfitiwia Intel Quartus Prime ṣe ipilẹṣẹ iṣiro orisun atẹle fun ẹrọ Cyclone V (5CGXFC7C7F23C8) FPGA. Awọn abajade fun awọn ẹrọ atilẹyin miiran jẹ iru.

Table 2. Aṣiṣe Ifiranṣẹ Forukọsilẹ Unloader IP Core Device Resource iṣamulo

Ẹrọ	Awọn ALMs	kannaa registers		M20K
		Alakoko	Atẹle
5CGXFC7C7F23C8	37	128	33	0

Apejuwe iṣẹ-ṣiṣe

Awọn ẹrọ Intel FPGA ti o ni atilẹyin ni iforukọsilẹ ifiranṣẹ aṣiṣe ti o tọka iṣẹlẹ ti aṣiṣe CRC kan ninu Ramu iṣeto ni (CRAM). Awọn aṣiṣe CRAM le waye nitori ibinu iṣẹlẹ kan (SEU). O le lo Ifiranṣẹ Aṣiṣe Iforukọsilẹ Unloader IP core's Avalon-ST logic interface lati wọle si ẹrọ FPGA EMR. Fun example, o le lo Ifiranṣẹ Ifiranṣẹ Aṣiṣe Iforukọsilẹ Unloader IP mojuto pẹlu Injection Fault Intel FPGA ati Intel FPGA Advanced SEU Detection IP awọn ohun kohun lati wọle si alaye EMR ẹrọ. Ifiranṣẹ Aṣiṣe Iforukọsilẹ Unloader IP mojuto ṣe abojuto ẹrọ EMR naa. Nigbatihardware ṣe imudojuiwọn akoonu EMR, mojuto IP naa ka (tabi gbejade) ati de-serializes akoonu EMR naa. Kokoro IP ngbanilaaye imọran miiran (bii Intel FPGA Advanced SEU Detection IP core, Intel FPGA Fault Injection IP core, tabi ọgbọn olumulo) lati wọle si akoonu EMR nigbakanna. Gẹgẹbi a ṣe han ni #unique_1/unique_1_Connect_42_image_fbb_3mm_gs ni oju-iwe 3, Ifiranṣẹ Aṣiṣe Iforukọsilẹ Unloader IP mojuto ṣe imudara aṣiṣe CRC Ṣe idaniloju ipilẹ IP fun diẹ ninu awọn ẹrọ.
Akiyesi: Fun alaye diẹ sii lori atilẹyin SEU fun ẹrọ FPGA rẹ, tọka si ipin idinku SEU ti ẹrọ amudani.

Ifiranṣẹ aṣiṣe Iforukọsilẹ
Diẹ ninu awọn ohun elo FPGA iṣẹlẹ kan ti o binu (SEU) ni idawọle wiwa aṣiṣe ti a ṣe sinu lati ṣe iwari isipade ni eyikeyi awọn iwọn CRAM ẹrọ nitori aṣiṣe rirọ. Awọn iṣẹ iyansilẹ bit fun ẹrọ EMR yatọ nipasẹ ẹbi ẹrọ. Fun awọn alaye lori awọn iwọn EMR fun ẹbi ohun elo FPGA rẹ, tọka si ipin idinku SEU ti ẹrọ amudani.

Awọn ifihan agbara

Table 3. Aṣiṣe Ifiranṣẹ Forukọsilẹ Unloader Awọn ifihan agbara

Ifihan agbara	Ìbú	Itọsọna	Apejuwe
aago	1	Iṣawọle	Ifihan aago titẹ sii.
tunto	1	Iṣawọle	Ti nṣiṣe lọwọ-ga kannaa ipilẹ ifihan agbara.
emr_ka	1	Iṣawọle	iyan. Ifihan agbara-giga yii bẹrẹ atunka akoonu EMR lọwọlọwọ. Awọn imudojuiwọn akoonu EMR nigbati ẹrọ ba ṣawari aṣiṣe tuntun kan. EMR naa ni aṣiṣe ninu titi ti aṣiṣe tuntun yoo fi rii, paapaa ti fifọ inu tabi ita ba ṣe atunṣe aṣiṣe naa.
crcerror	1	Abajade	Tọkasi wiwa ti aṣiṣe CRC kan. Ifihan agbara yii muṣiṣẹpọ si ibudo aago ti Ifiranṣẹ Aṣiṣe Iforukọsilẹ Unloader IP mojuto.
crcerror_pin	1	Abajade	So ifihan agbara yii pọ mọ PIN CRC_Error. Ifihan agbara yii jẹ amuṣiṣẹpọ si oscillator inu ẹrọ naa.
crcerror_clk	1	Iṣawọle	Aṣiṣe CRC Ṣe idaniloju ifihan aago titẹ sii mojuto IP.
crcerror_reset	1	Iṣawọle	Aṣiṣe CRC Daju IP mojuto ifihan agbara atunto kannaa giga.
Emir[N-1:0]	46, 67, tabi 78	Abajade	Ibudo data yii ni awọn akoonu iforukọsilẹ aṣiṣe ti ẹrọ naa ni, gẹgẹbi a ti ṣalaye ninu iwe amudani ẹrọ ti ipin idinku SEU: • Intel Arria 10 ati Intel Cyclone 10 GX awọn ẹrọ ni 78-bit EMRs • Stratix V, Arria V, ati awọn ẹrọ Cyclone V ni awọn EMRs 67-bit • Awọn ẹrọ agbalagba ni awọn EMRs 46-bit Awọn ifihan agbara iṣẹjade EMR ni ibamu pẹlu itumọ wiwo Avalon-ST. N jẹ 46, 67, tabi 78.
emr_wulo	1	Abajade	Giga ti n ṣiṣẹ nigbati awọn akoonu ifihan emr wulo. Yi ifihan agbara complies pẹlu Avalon ni wiwo definition.
emr_aṣiṣe	1	Abajade	Ifihan agbara yii n ṣiṣẹ ga nigbati gbigbejade EMR lọwọlọwọ ni aṣiṣe ati pe o yẹ ki o gbagbe. Ni deede, ifihan agbara yii tọka si pe aago titẹ sii EMR ti lọra pupọ. Yi ifihan agbara complies pẹlu Avalon ni wiwo definition.
endoffulchip	1	Abajade	Ifihan agbara iyan ti o tọkasi opin ti kọọkan-pip aṣiṣe wiwa ọmọ fun gbogbo ẹrọ. Intel Arria 10, Intel Cyclone 10 GX, Stratix V, Arria V, ati Cyclone V awọn ẹrọ nikan.

Àkókò

Ifiranṣẹ Aṣiṣe Ifiranṣẹ Iforukọsilẹ Unloader IP mojuto nilo awọn akoko aago meji fun ẹrọ ašiše ifiranšẹ ašiše, pẹlu afikun atẹle Aṣiṣe Ifiranṣẹ Ifiranṣẹ Iforukọsilẹ Unloader awọn akoko titẹ sii lati gbe akoonu EMR silẹ: N + 3 nibiti N jẹ iwọn ifihan emr.

• Awọn iyipo aago 122 fun Intel Arria 10 ati Intel Cyclone 10 GX awọn ẹrọ
• Awọn iyipo aago 70 fun Stratix V, Arria V, ati awọn ẹrọ Cyclone V
• Awọn akoko aago 49 fun Stratix IV ati Arria II GZ/GX awọn ẹrọ

Ihuwasi akoko IP (Intel Arria 10 ati Intel Cyclone 10 GX Awọn ẹrọ)
Awọn fọọmu igbi atẹle yii ṣafihan Ifiranṣẹ Aṣiṣe Iforukọsilẹ Unloader IP mojuto akoko ihuwasi fun Intel Arria 10 ati Intel Cyclone 10 GX awọn ẹrọ.

Nọmba 2. Ifihan agbara emr_valid fun Awọn aṣiṣe Atunse (0 <Iru orisun-iwe <3'b111) Aworan akoko

Nọmba 3. Ifihan agbara emr_valid fun Awọn aṣiṣe Atunse lẹhin Agbara Soke Nikan (Iru orisun-iwe == 3'b0)
Akiyesi: Nigbati akọkọ ti kojọpọ pẹlu bitstream, FPGA ṣiṣẹ EDCRC ti o da lori Fireemu lẹẹkan, ṣe iṣiro iwọn ayẹwo ti o da lori ọwọn o si yipada si EDCRC ti o da ọwọn. Aworan akoko yii n tọka si aṣiṣe ti a rii lakoko EDCRC ti o da lori fireemu.

Nọmba 4. Ifihan agbara emr_valid fun Awọn aṣiṣe ti ko ṣe atunṣe

olusin 5. emr_error Time Diagram

Gbogbo Miiran Device Time
Awọn fọọmu igbi wọnyi fihan Ifiranṣẹ Aṣiṣe Iforukọsilẹ Unloader IP mojuto akoko ihuwasi fun Stratix V, Stratix IV, Arria V, Arria II GZ/GX, ati awọn ẹrọ Cyclone V.

olusin 6. emr_read Time Diagram

olusin 7. emr_valid Time Diagram

Aworan 8. Eksample EMR Asise ìlà aworan atọka

• Ninu ọran ti awọn aṣiṣe SEU itẹlera 2, ipilẹ IP n sọ emr_error fun akoonu EMR ti o sọnu.
• IP mojuto n sọ emr_error ti o ba ṣe awari eti isubu ti pulse crcerror fun aṣiṣe atẹle, ṣaaju ki IP mojuto gbe akoonu iṣaaju ti iforukọsilẹ imudojuiwọn olumulo EMR sinu iforukọsilẹ iyipada olumulo.
• Awọn jinde eti crcerror deasserts emr_error.
• emr_error jẹ ipo eto to ṣe pataki ati pe o le tọka si pe aago titẹ Unloader Ifiranṣẹ Aṣiṣe ti lọra pupọ.

Paramita Eto

Table 4. Aṣiṣe Ifiranṣẹ Forukọsilẹ Unloader paramita

Paramita	Iye	Aiyipada	Apejuwe
CRC aṣiṣe ayẹwo aago pin	1, 2, 4, 8, 16, 32, 64, 128, 256	2	Tọkasi aṣiṣe wiwa aago onipin iye lati kan si oscillator inu. Aago ti o pin n ṣakoso iṣẹ CRC inu. Eto yi gbọdọ baramu ERROR_CHECK_FREQUENCY_DIVISOR Intel Quartus NOMBA Eto File (.qsf) eto, bibẹkọ ti awọn software oran kan Ikilọ. Awọn ẹrọ Stratix IV ati Arria II ko ṣe atilẹyin iye kan ti 1.
Muu Foju JTAG CRC aṣiṣe abẹrẹ	Tan, pipa	Paa	Mu awọn orisun inu eto ṣiṣẹ ati iṣẹ ṣiṣe awọn iwadii (ISSP) lati fun akoonu iforukọsilẹ EMR nipasẹ JTAG ni wiwo lai yiyipada CRAM iye. Lo yi ni wiwo to a troubleshoot olumulo kannaa ti o ti wa ni ti sopọ si mojuto.
Input aago igbohunsafẹfẹ	Eyikeyi	50 MHz	Ni pato awọn igbohunsafẹfẹ ti Ifiranṣẹ Aṣiṣe Iforukọsilẹ Unloader IP mojuto input aago. Yi aṣayan jẹ wulo nigbati awọn Aago igbewọle wa ni idari lati inu Oscillator paramita wa ni pipa.
Aago igbewọle wa ni idari lati inu Oscillator	Tan, pipa	Paa	Tọkasi wipe awọn ti abẹnu oscillator pese awọn mojuto input aago. Mu paramita yii ṣiṣẹ ti oscillator inu ba wakọ aago igbewọle mojuto apẹrẹ olumulo. Akiyesi: Igbohunsafẹfẹ ti oscillator inu ko ni kan nipasẹ aṣiṣe ayẹwo aago CRC.
Aṣiṣe CRC Ṣe idaniloju igbohunsafẹfẹ titẹ sii aago	10 - 50 MHz	50 MHz	Ni pato aṣiṣe CRC Ṣe idaniloju ipilẹ IP (ALTERA_CRCERROR_VERIFY) igbohunsafẹfẹ aago titẹ sii. Stratix IV ati Arria II awọn ẹrọ nikan.
Ipari ti ni kikun ërún aṣiṣe erin ọmọ	Tan, pipa	Paa	iyan. Tan-an lati sọ ifihan agbara yii ni opin ipari wiwa aṣiṣe ni ërún kọọkan. Stratix V, Intel Arria 10, Arria V, Cyclone V, ati Intel Cyclone 10 GX awọn ẹrọ nikan.

Fifi ati asẹ ni Intel FPGA IP ohun kohun

Fifi sori sọfitiwia Intel Quartus Prime pẹlu ile-ikawe Intel FPGA IP. Ile-ikawe yii n pese ọpọlọpọ awọn ohun kohun IP ti o wulo fun lilo iṣelọpọ rẹ laisi iwulo fun iwe-aṣẹ afikun. Diẹ ninu awọn ohun kohun Intel FPGA IP nilo rira iwe-aṣẹ lọtọ fun lilo iṣelọpọ. Ipo Igbelewọn IP FPGA Intel gba ọ laaye lati ṣe iṣiro awọn ohun kohun Intel FPGA IP ti o ni iwe-aṣẹ ni kikopa ati ohun elo, ṣaaju ṣiṣe ipinnu lati ra iwe-aṣẹ ipilẹ IP iṣelọpọ ni kikun. Iwọ nikan nilo lati ra iwe-aṣẹ iṣelọpọ ni kikun fun awọn ohun kohun Intel IP ti o ni iwe-aṣẹ lẹhin ti o pari idanwo ohun elo ati pe o ti ṣetan lati lo IP ni iṣelọpọ. Sọfitiwia Intel Quartus Prime n fi awọn ohun kohun IP sori awọn ipo atẹle nipasẹ aiyipada:

olusin 9. IP Core fifi sori Ona

Table 5. IP mojuto fifi sori awọn ipo

Ipo	Software	Platform
: \ intelFPGA_pro \ kuotisi \ ip \ altera	Intel kuotisi NOMBA Pro Edition	Windows *
: \ intelFPGA \ kuotisi \ ip \ altera	Intel kuotisi NOMBA Standard Edition	Windows
:/intelFPGA_pro/quartus/ip/altera	Intel kuotisi NOMBA Pro Edition	Linux *
:/intelFPGA/quartus/ip/altera	Intel kuotisi NOMBA Standard Edition	Lainos

Isọdi ati ti ipilẹṣẹ IP ohun kohun
O le ṣe awọn ohun kohun IP lati ṣe atilẹyin ọpọlọpọ awọn ohun elo lọpọlọpọ. Intel Quartus Prime IP Catalog ati olootu paramita gba ọ laaye lati yara yan ati tunto awọn ebute oko oju omi IP, awọn ẹya, ati iṣelọpọ files.

IP Catalog ati Parameter Olootu
Katalogi IP ṣe afihan awọn ohun kohun IP ti o wa fun iṣẹ akanṣe rẹ, pẹlu Intel FPGA IP ati IP miiran ti o ṣafikun si ọna wiwa Catalog IP.. Lo awọn ẹya wọnyi ti Katalogi IP lati wa ati ṣe akanṣe ipilẹ IP kan:

• Àlẹmọ IP Catalog lati Fi IP han fun ẹbi ẹrọ ti nṣiṣe lọwọ tabi Fihan IP fun gbogbo awọn idile ẹrọ. Ti o ko ba ni iṣẹ akanṣe ṣiṣi, yan Ẹbi Ẹrọ ni Katalogi IP.
• Tẹ ninu aaye wiwa lati wa eyikeyi kikun tabi apa kan orukọ ipilẹ IP ni Katalogi IP.
• Tẹ-ọtun orukọ ipilẹ IP kan ninu Katalogi IP lati ṣafihan awọn alaye nipa awọn ẹrọ atilẹyin, lati ṣii folda fifi sori mojuto IP, ati fun awọn ọna asopọ si iwe IP.
• Tẹ Wa fun Alabaṣepọ IP lati wọle si alaye IP alabaṣepọ lori web.

Olootu paramita naa ta ọ lati pato orukọ iyatọ IP kan, awọn ebute oko oju omi iyan, ati iṣelọpọ file iran awọn aṣayan. Olootu paramita ṣe ipilẹṣẹ Intel Quartus Prime IP ipele-oke file (.ip) fun iyatọ IP ni awọn iṣẹ akanṣe Intel Quartus Prime Pro Edition. Olootu paramita ṣe ipilẹṣẹ Quartus IP ipele-oke kan file (.qip) fun ẹya IP iyatọ ninu Intel Quartus Prime Standard Edition ise agbese. Awọn wọnyi files duro IP iyatọ ninu ise agbese, ati itaja parameterization alaye.

Nọmba 10. Olootu IP Parameter (Intel Quartus Prime Pro Edition)

Nọmba 11. Olootu IP Parameter (Intel Quartus Prime Standard Edition)

Olootu paramita
Olootu paramita ṣe iranlọwọ fun ọ lati tunto awọn ebute oko oju omi IP, awọn paramita, ati iṣelọpọ file iran awọn aṣayan. Awọn iṣakoso olootu paramita ipilẹ pẹlu atẹle naa:

• Lo ferese tito tẹlẹ lati lo awọn iye paramita tito tẹlẹ fun awọn ohun elo kan pato (fun yan awọn ohun kohun).
• Lo window Awọn alaye si view ibudo ati awọn apejuwe paramita, ki o si tẹ awọn ọna asopọ si iwe.
• Tẹ Ina ➤ Ina Testbench System lati se ina kan testbench eto (fun yan ohun kohun).
• Tẹ ina ➤ ina Example Design lati se ina ohun Mofiample design (fun yan ohun kohun).
• Tẹ Imudaniloju Eto Iduroṣinṣin lati jẹrisi awọn paati jeneriki ti eto kan lodi si ẹlẹgbẹ files. (Awọn eto Onise Platform nikan)
• Tẹ Gbogbo Alaye Eto Amuṣiṣẹpọ lati jẹrisi awọn paati jeneriki ti eto kan lodi si ẹlẹgbẹ files. (Awọn eto Onise Platform nikan)

Katalogi IP naa tun wa ni Apẹrẹ Platform (View ➤ IP Catalog). Apẹrẹ Platform IP Catalog pẹlu isọpọ eto iyasoto, fidio ati sisẹ aworan, ati IP ipele eto miiran ti ko si ninu Intel Quartus Prime IP Catalog. Tọkasi si Ṣiṣẹda Eto pẹlu Oluṣeto Platform tabi Ṣiṣẹda Eto kan pẹlu Oluṣeto Platform (Standard) fun alaye lori lilo IP ni Apẹrẹ Platform (Standard) ati Onise Platform, lẹsẹsẹ.

Alaye ti o jọmọ

• Ṣiṣẹda Eto pẹlu Onise Platform
• Ṣiṣẹda Eto kan pẹlu Onise Platform (Iwọn boṣewa) (Iwọn)

Pato IP Core paramita ati awọn aṣayan
Tẹle awọn igbesẹ wọnyi lati tokasi awọn aye ipilẹ IP ati awọn aṣayan.

1. Ni Platform Designer IP Catalog (Awọn irinṣẹ ➤ IP Catalog), wa ki o tẹ lẹẹmeji orukọ IP mojuto lati ṣe akanṣe. Olootu paramita yoo han.
2. Pato orukọ ipele-oke fun iyatọ IP aṣa rẹ. Orukọ yii n ṣe idanimọ iyatọ ipilẹ IP files ninu rẹ ise agbese. Ti o ba ṣetan, tun pato ibi-afẹde FPGA ẹrọ ẹbi ati abajade file HDL ààyò. Tẹ O DARA.
3. Pato awọn paramita ati awọn aṣayan fun iyatọ IP rẹ:
   • Ni yiyan yan awọn iye paramita tito tẹlẹ. Awọn tito tẹlẹ pato gbogbo awọn iye paramita akọkọ fun awọn ohun elo kan pato (nibiti a ti pese).
   • Pato awọn paramita ti n ṣalaye iṣẹ ṣiṣe ipilẹ IP, awọn atunto ibudo, ati awọn ẹya ẹrọ kan pato.
   • Pato awọn aṣayan fun iran ti awọn nẹtiwọọki akoko, awoṣe kikopa, testbench, tabi example design (ibi ti o wulo).
   • Pato awọn aṣayan fun sisẹ mojuto IP files ni awọn irinṣẹ EDA miiran.
4. Tẹ Pari lati ṣe ipilẹṣẹ iṣelọpọ ati iyan miiran files ibaamu awọn pato iyatọ IP rẹ. Olootu paramita n ṣe ipilẹṣẹ .qsys IP iyatọ oke-ipele file ati HDL files fun kolaginni ati kikopa. Diẹ ninu awọn ohun kohun IP tun ni igbakanna ṣe ipilẹṣẹ testbench tabi example apẹrẹ fun hardware igbeyewo.
5. Lati se ina kan kikopa testbench, tẹ ina ➤ Ina Testbench System. Ṣe ina Testbench System ko si fun diẹ ninu awọn ohun kohun IP ti ko pese aaye idanwo kikopa.
6. Lati se ina kan oke-ipele HDL exampfun ijẹrisi ohun elo, tẹ Ina ➤ HDL Example. Ṣe ina ➤ HDL Example ko wa fun diẹ ninu awọn ohun kohun IP.

Iyatọ IP ti o ga julọ ni a ṣafikun si iṣẹ akanṣe Intel Quartus Prime lọwọlọwọ. Tẹ Project ➤ Fikun-un/Yọ kuro Files ni Ise agbese lati ṣafikun pẹlu ọwọ .qsys (Intel Quartus Prime Standard Edition) tabi .ip (Intel Quartus Prime Pro Edition) file si ise agbese kan. Ṣe awọn iṣẹ iyansilẹ pin ti o yẹ lati so awọn ibudo pọ.

Ijade Ipilẹ Core (Intel Quartus Prime Pro Edition)
Sọfitiwia Intel Quartus Prime ṣe ipilẹṣẹ iṣelọpọ atẹle file eto fun awọn ohun kohun IP kọọkan ti kii ṣe apakan ti eto Onise Platform.

Nọmba 12. Olukuluku IP Core Ijade Ijade (Intel Quartus Prime Pro Edition)

Table 6. o wu Files ti Intel FPGA IP generation

File Oruko	Apejuwe
<rẹ_ip> .ip	Oke-ipele IP iyatọ file ti o ni awọn parameterization ti ohun IP mojuto ninu rẹ ise agbese. Ti iyatọ IP ba jẹ apakan ti eto Onise Platform, olootu paramita tun ṣe ipilẹṣẹ .qsys kan file.
<rẹ_ip> .cmp	Ìkéde paati VHDL (.cmp) file jẹ ọrọ kan file ti o ni jeneriki agbegbe ati awọn asọye ibudo ti o lo ninu apẹrẹ VHDL files.
<rẹ_ip>_generation.rpt	IP tabi Platform Apẹrẹ iran log file. Ṣe afihan akopọ ti awọn ifiranṣẹ lakoko iran IP.
tesiwaju…

File Oruko	Apejuwe
<rẹ_ip>.qgsimc (Awọn ọna ṣiṣe Onise Platform nikan)	Iṣakojọpọ kikopa file ti o afiwe .qsys ati .ip files pẹlu awọn ti isiyi parameterization ti Platform onise eto ati IP mojuto. Ifiwewe yii pinnu boya Onise Platform le foju isọdọtun ti HDL.
<rẹ_ip>.qgsynth (Awọn ọna ṣiṣe Onise Platform nikan)	Iṣakojọpọ akopọ file ti o afiwe .qsys ati .ip files pẹlu awọn ti isiyi parameterization ti Platform onise eto ati IP mojuto. Ifiwewe yii pinnu boya Onise Platform le foju isọdọtun ti HDL.
<rẹ_ip> .qip	Ni gbogbo alaye ni lati ṣepọ ati ṣajọ paati IP naa.
<rẹ_ip> .csv	Ni alaye ninu nipa ipo igbesoke ti paati IP.
.bsf	Aṣoju aami ti iyatọ IP fun lilo ninu aworan atọka Dina Files (.bdf).
<rẹ_ip>.spd	Iṣawọle file pe ip-make-simscript nilo lati ṣe awọn iwe afọwọkọ kikopa. Awọn .spd file ni akojọ kan ti files o ṣe ipilẹṣẹ fun kikopa, pẹlu alaye nipa awọn iranti ti o bẹrẹ.
<rẹ_ip>.ppf	The Pin aseto File (.ppf) tọju ibudo ati awọn iṣẹ iyansilẹ ipade fun awọn paati IP ti o ṣẹda fun lilo pẹlu Alakoso Pin.
<rẹ_ip> _bb.v	Lo Verilog blackbox (_bb.v) file bi ohun ṣofo module ìkéde fun lilo bi a blackbox.
<rẹ_ip> _inst.v tabi _inst.vhd	HDL fun apẹẹrẹample instantiation awoṣe. Daakọ ati lẹẹmọ awọn akoonu inu eyi file sinu HDL rẹ file lati instantiate awọn IP iyatọ.
<rẹ_ip>. regmap	Ti IP ba ni alaye iforukọsilẹ ninu, sọfitiwia Intel Quartus Prime ṣe ipilẹṣẹ .regmap naa file. The .regmap file ṣe apejuwe alaye maapu iforukọsilẹ ti oluwa ati awọn atọkun ẹrú. Eyi file awọn afikun awọn .sopcinfo file nipa fifun alaye iforukọsilẹ alaye diẹ sii nipa eto naa. Eyi file kí àpapọ àpapọ views ati awọn iṣiro isọdi olumulo ni System Console.
<rẹ_ip> .svd	Gba awọn irinṣẹ yokokoro Eto HPS laaye lati view awọn maapu iforukọsilẹ ti awọn agbeegbe ti o sopọ si HPS laarin eto Onise Platform. Lakoko iṣelọpọ, sọfitiwia Intel Quartus Prime tọjú .svd files fun ẹrú ni wiwo han si awọn System Console oluwa ni .sof file ni igba yokokoro. Console System ka abala yii, eyiti Apẹrẹ Platform n beere fun alaye maapu iforukọsilẹ. Fun awọn ẹrú eto, Apẹrẹ Platform wọle si awọn iforukọsilẹ nipasẹ orukọ.
<rẹ_ip>.vrẹ_ip> .vhd	HDL files ti o instantiate kọọkan submodule tabi ọmọ IP mojuto fun kolaginni tabi kikopa.
olutojueni/	Ni iwe afọwọkọ msim_setup.tcl kan lati ṣeto ati ṣiṣe kikopa kan.
aldec/	Ni iwe afọwọkọ kan rivierapro_setup.tcl lati ṣeto ati ṣiṣe kikopa kan.
/ synopsys/vcs / synopsys/vcsmx	Ni iwe afọwọkọ ikarahun kan ninu vcs_setup.sh lati ṣeto ati ṣiṣẹ kikopa kan. Ni ninu iwe afọwọkọ ikarahun vcsmx_setup.sh ati synopsys_sim.setup file lati ṣeto ati ṣiṣe a kikopa.
/ cadence	Ni iwe afọwọkọ ikarahun kan ncsim_setup.sh ati iṣeto miiran files lati ṣeto ati ṣiṣe iṣeṣiro kan.
/ xcelium	Ni iwe afọwọkọ ikarahun Simulator Parallel kan xcelium_setup.sh ati iṣeto miiran files lati ṣeto ati ṣiṣe a kikopa.
/ submodules	HDL ni ninu files fun IP mojuto submodule.
<IP submodule>/	Apẹrẹ Platform n ṣe ipilẹṣẹ / synth ati / awọn iwe-ilana-apakan SIM fun itọsọna submodule IP kọọkan ti Onise Platform ṣe ipilẹṣẹ.

Ni pato IP Core Parameters ati Awọn aṣayan (Awọn oluṣatunkọ Parameter Legacy)

Diẹ ninu awọn ohun kohun IP lo ẹya julọ ti olootu paramita fun iṣeto ati iran. Lo awọn igbesẹ wọnyi lati tunto ati ṣe agbekalẹ iyatọ IP kan nipa lilo olootu paramita pataki kan.
Akiyesi: Olootu paramita ti ogún n ṣe agbekalẹ iṣelọpọ ti o yatọ file be ju titun paramita olootu. Tọkasi pato Awọn paramita Core IP ati Awọn aṣayan fun iṣeto ti awọn ohun kohun IP ti o lo olootu paramita tuntun

olusin 13. Legacy Parameter Editors

1. Ninu Katalogi IP (Awọn irinṣẹ ➤ IP Catalog), wa ki o tẹ lẹẹmeji orukọ IP mojuto lati ṣe akanṣe. Olootu paramita yoo han.
2. Pato orukọ ipele oke ati HDL ti o jade file tẹ fun iyatọ IP rẹ. Orukọ yii n ṣe idanimọ iyatọ ipilẹ IP files ninu rẹ ise agbese. Tẹ O DARA.
3. Pato awọn paramita ati awọn aṣayan fun iyatọ IP rẹ ninu olootu paramita. Tọkasi itọsọna olumulo mojuto IP rẹ fun alaye nipa awọn paramita mojuto IP kan pato.
4. Tẹ Pari tabi Ina (da lori ẹya paramita olootu). Awọn paramita olootu gbogbo awọn files fun iyatọ IP rẹ gẹgẹbi awọn pato rẹ. Tẹ Jade ti o ba ti ṣetan nigbati iran ba ti pari. Olootu paramita ṣafikun ipele-oke .qip file si awọn ti isiyi ise agbese laifọwọyi.

Akiyesi: Lati fi ọwọ kun iyatọ IP ti ipilẹṣẹ pẹlu olootu paramita julọ si iṣẹ akanṣe kan, tẹ Ise agbese ➤ Fikun-un/Yọ kuro Files ni Project ki o si fi awọn IP iyatọ .qip file.

Ijade Ipilẹ Core IP (Intel Quartus Prime Standard Edition)
Sọfitiwia Ipele Ipele Intel Quartus Prime ṣe ipilẹṣẹ ọkan ninu iṣelọpọ atẹle file awọn ẹya fun awọn ohun kohun IP kọọkan ti o lo ọkan ninu awọn olootu paramita julọ.

olusin 14. IP Core ti ipilẹṣẹ Files (Àwọn alátúnṣe Ìpínlẹ̀ Ògún)

Ti ipilẹṣẹ IP File Ijade A

Ti ipilẹṣẹ IP File Ijade B

Ti ipilẹṣẹ IP File Ijade C

Ti ipilẹṣẹ IP File Ijade D

Awọn akọsilẹ:

1. Ti o ba ni atilẹyin ati ṣiṣẹ fun iyatọ IP rẹ
2. Ti awọn awoṣe kikopa iṣẹ ṣiṣe ti wa ni ipilẹṣẹ
3. Foju iwe ilana yii

Itan Atunyẹwo Iwe fun Aṣiṣe Ifiranṣẹ Iforukọsilẹ Unloader Intel FPGA IP Itọsọna Olumulo Core

Ẹya Iwe aṣẹ	Intel Quartus NOMBA Version	Awọn iyipada
2018.05.23	18.0	IP lorukọmii lati Ifiranṣẹ aṣiṣe Intel FPGA Forukọsilẹ Unloader IP mojuto si Ifiranṣẹ aṣiṣe Iforukọsilẹ Unloader Intel FPGA IP mojuto. • Awọn nọmba imudojuiwọn Ifihan agbara emr_valid fun Awọn aṣiṣe Atunse lẹhin Agbara Soke Nikan (Iru orisun-iwe == 3'b0) ati Ifihan agbara emr_valid fun Awọn aṣiṣe ti ko ṣe atunṣe.

Ọjọ	Ẹya	Awọn iyipada
Oṣu kejila ọjọ 2017	2017.12.18	Tunrukọ iwe naa bi Ifiranṣẹ Aṣiṣe Intel FPGA Ifiranṣẹ Iforukọsilẹ Unloader IP Itọsọna olumulo Core. • Ṣe imudojuiwọn tabili tabili “Atilẹyin Ẹrọ mojuto IP”. • Imudojuiwọn fun titun so loruko awọn ajohunše. Ṣe awọn imudojuiwọn olootu jakejado iwe-ipamọ naa.
Oṣu Keje ọdun 2017	2017.07.15	• Afikun Intel Cyclone 10 GX ẹrọ support. • Iyipada V-Iru si Iru-orisun Ọwọ ni awọn aworan aago IP. • Ti pese awọn ilana parameterization lọtọ fun Intel Quartus Prime Pro Edition ati Intel Quartus Prime Standard Edition. • Imudojuiwọn fun titun so loruko awọn ajohunše.
Oṣu Karun ọdun 2016	2016.05.02	• Awọn ọta ibọn ẹya kuro nipa atilẹyin Verilog HDL RTL. • Iyipada Quartus II awọn itọkasi si Quartus Prime.
Oṣu Kẹfa ọdun 2015	2015.06.12	Imudojuiwọn Arria 10 awọn alaye atilẹyin.
Oṣu kejila ọjọ 2014	2014.12.15	Itusilẹ akọkọ.

Intel Corporation. Gbogbo awọn ẹtọ wa ni ipamọ. Intel, aami Intel, ati awọn ami Intel miiran jẹ aami-išowo ti Intel Corporation tabi awọn oniranlọwọ rẹ. Intel ṣe atilẹyin iṣẹ ti FPGA rẹ ati awọn ọja semikondokito si awọn pato lọwọlọwọ ni ibamu pẹlu atilẹyin ọja boṣewa Intel, ṣugbọn ni ẹtọ lati ṣe awọn ayipada si eyikeyi awọn ọja ati iṣẹ nigbakugba laisi akiyesi. Intel ko gba ojuse tabi layabiliti ti o dide lati inu ohun elo tabi lilo eyikeyi alaye, ọja, tabi iṣẹ ti a ṣalaye ninu rẹ ayafi bi a ti gba ni kikun si kikọ nipasẹ Intel. A gba awọn alabara Intel nimọran lati gba ẹya tuntun ti awọn pato ẹrọ ṣaaju gbigbekele eyikeyi alaye ti a tẹjade ati ṣaaju gbigbe awọn aṣẹ fun awọn ọja tabi awọn iṣẹ. * Awọn orukọ miiran ati awọn ami iyasọtọ le jẹ ẹtọ bi ohun-ini ti awọn miiran.

Awọn iwe aṣẹ / Awọn orisun

Ifiranṣẹ aṣiṣe intel Forukọsilẹ Unloader FPGA IP Core [pdf] Itọsọna olumulo Ifiranṣẹ Aṣiṣe Iforukọsilẹ Unloader FPGA IP Core, Aṣiṣe, Iforukọsilẹ Ifiranṣẹ Unloader FPGA IP Core, Iforukọsilẹ Unloader FPGA IP Core, Unloader FPGA IP Core

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