Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi

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1 FPGA Integer Arithmetic IP Cores

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FPGA Integer Arithmetic IP Cores

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Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi
Ihlaziywe kwi-Intel® Quartus® Prime Design Suite: 20.3

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UG-01063

ID: 683490 Inguqulelo: 2020.10.05

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1. Intel FPGA Integer Arithmetic IP Cores……………………………………………………………….. 5
2. LPM_COUNTER (Counter) IP Core……………………………………………………………………….. 7 2.1. Iimpawu……………………………………………………………………………………………………… I-Verilog HDL Prototype……………………………………………………………………………….. 7 2.2. i-VHDL Component Declaration……………………………………………………………………….8 2.3. I-VHDL LIBRARY_SE Declaration………………………………………………………………………………………………………………………………………………………………………… Amazibuko……………………………………………………………………………………………………..8 2.4. Iiparamitha……………………………………………………………………………………………………
3. LPM_DIVIDE (I-Divider) Intel FPGA IP Core………………………………………………………….. 12 3.1. Iimbonakalo………………………………………………………………………………………………. 12 3.2. I-Verilog HDL Prototype……………………………………………………………………………………… 12 3.3. i-VHDL Component Declaration……………………………………………………………………….. 13 3.4. I-VHDL LIBRARY_SE Declaration………………………………………………………………………. 13 3.5. Amazibuko…………………………………………………………………………………………………………………………………………………………………………………………… 13 3.6. Iiparamitha……………………………………………………………………………………………………
4. LPM_MULT (Multiplier) IP Core………………………………………………………………………………. 16 4.1. Iimbonakalo………………………………………………………………………………………………. 16 4.2. I-Verilog HDL Prototype………………………………………………………………………………………………………………………………………………………………………… 17 4.3. i-VHDL Component Declaration…………………………………………………………………….. 17 4.4. I-VHDL LIBRARY_SE Declaration………………………………………………………………………. 17 4.5. Iimpawu…………………………………………………………………………………………………………………………………………………………………………………………………… Iiparamitha ze-Stratix V, i-Arria V, i-Cyclone V, kunye ne-Intel Cyclone 18 LP Devices……………… 4.6 10. IThebhu ngokubanzi……………………………………………………………………………………… Ngokubanzi 18 Ithebhu…………………………………………………………………………………………………………………………… IThebhu yokuBopha………………………………………………………………………………………………………………………………………………………………………………… Iiparamitha ze-Intel Stratix 4.6.1, i-Intel Arria 18, kunye ne-Intel Cyclone 4.6.2 GX Devices ……….. 2 19. IThebhu ngokubanzi…………………………………………………………………………………… Ngokubanzi 4.6.3 Ithebhu………………………………………………………………………………………………………………………………… Ukufakwa kwemibhobho……………………………………………………………………………………
5. LPM_ADD_SUB (I-Adder/Subtractor)……………………………………………………………………… 22 5.1. Iimbonakalo………………………………………………………………………………………………. 22 5.2. I-Verilog HDL Prototype……………………………………………………………………………………… 23 5.3. i-VHDL Component Declaration…………………………………………………………………….. 23 5.4. I-VHDL LIBRARY_SE Declaration………………………………………………………………………. 23 5.5. Amazibuko …………………………………………………………………………………………………………………………………………………………………………………………… 23 5.6. Iiparamitha…………………………………………………………………………………………………
6. LPM_COMPARRE (Isithelekisi)………………………………………………………………………………………………………………………………………………………………………………… Iimbonakalo………………………………………………………………………………………………. 26 6.1. I-Verilog HDL Prototype……………………………………………………………………………………………………………………………………………………………………… 26 6.2. i-VHDL Component Declaration…………………………………………………………………….. 27 6.3. I-VHDL LIBRARY_SE Declaration………………………………………………………………………. 27 6.4. Amazibuko……………………………………………………………………………………………………………………………………………………………………………………………… 27 6.5. Iiparamitha…………………………………………………………………………………………………

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7. I-ALTECC (IKhowudi yoLungiso lwempazamo: I-Encoder/Decoder) IP Core……………………………………………
7.1. Iimpawu ze-ALTECC Encoder…………………………………………………………………………..31 7.2. I-Verilog HDL Prototype (ALTECC_ENCODER)…………………………………………………………. 32 7.3. I-Verilog HDL Prototype (ALTECC_DECODER)…………………………………………………………. 32 7.4. I-VHDL Component Declaration (ALTECC_ENCODER)………………………………………………33 7.5. IsiBhengezo seCandelo le-VHDL (ALTECC_DECODER)…………………………………………………33 7.6. I-VHDL LIBRARY_SE Declaration………………………………………………………………………. 33 7.7. Ii-Encoder Ports…………………………………………………………………………………………………… Iizibuko zedikhowuda……………………………………………………………………………………………… Ii-Encoder Parameters……………………………………………………………………………………………………………………………………………………………………………… 33 7.8. Iiparamitha zedikhowuda …………………………………………………………………………………………
8. Intel FPGA Multiply Adder IP Core…………………………………………………………………………. 36
8.1. Iimbonakalo………………………………………………………………………………………………. 37 8.1.1. I-pre-adder……………………………………………………………………………….. 38 8.1.2. Irejista yokulibazisa iSystolic…………………………………………………………………….. 40 8.1.3. I-Pre-load Constant…………………………………………………………………………… 43 8.1.4. I-Double Accumulator………………………………………………………………………… 43
8.2. I-Verilog HDL Prototype…………………………………………………………………………………… 44 8.3. i-VHDL Component Declaration……………………………………………………………………….. 44 8.4. I-VHDL LIBRARY_SE Declaration………………………………………………………………………. 44 8.5. Iimpawu ………………………………………………………………………………………………………………………………………………………………………………………………… Iiparamitha………………………………………………………………………………………………
8.6.1. IThebhu ngokubanzi………………………………………………………………………………………47 8.6.2. IThebhu yeeModi ezongezelelweyo………………………………………………………………………….. 47 8.6.3. Ii-Multipliers Tab…………………………………………………………………………….. 49 8.6.4. Preadder Tab…………………………………………………………………………………. 51 8.6.5. I-Accumulator Tab………………………………………………………………………….. 53 8.6.6. I-Systolic/Chainout Tab…………………………………………………………………………. 55 8.6.7. Itheyibhile yePipelining………………………………………………………………………………………
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core ……………………… 57
9.1. Iimbonakalo………………………………………………………………………………………………. 57 9.2. I-Verilog HDL Prototype………………………………………………………………………………… 58 9.3. i-VHDL Component Declaration……………………………………………………………………….. 58 9.4. Amazibuko ………………………………………………………………………………………………………………………………………………………………………………………………… 59 9.5. Iiparamitha…………………………………………………………………………………………………
10. ALTMULT_ACCUM (Ziphindaphinde-Ziqokelele) IP Core………………………………………………………
10.1. Iimpawu…………………………………………………………………………………………….. 62 10.2. I-Verilog HDL Prototype……………………………………………………………………………..62 10.3. i-VHDL Component Declaration…………………………………………………………………………………………… I-VHDL LIBRARY_SE Declaration………………………………………………………………………… Amazibuko……………………………………………………………………………………………………………………………………………………. 63 10.4. Iiparamitha……………………………………………………………………………………………. 63
11. ALTMULT_ADD (I-Multiply-Adder) IP Core……………………………………………………………..69
11.1. Iimpawu……………………………………………………………………………………………….. 71 11.2. I-Verilog HDL Prototype…………………………………………………………………………..72 11.3. i-VHDL Component Declaration…………………………………………………………………………… I-VHDL LIBRARY_SE Declaration…………………………………………………………………….72

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11.5. Amazibuko……………………………………………………………………………………………………………………………………………………. 72 11.6. Iiparamitha……………………………………………………………………………………………. 73
12. ALTMULT_COMPLEX (I-Complex Multiplier) IP Core…………………………………………………… 86 12.1. Uphinda-phindo oluntsonkothileyo………………………………………………………………………………. 86 12.2. ICanonical Representation …………………………………………………………………………… 87 12.3. Umelo oluQhelekileyo………………………………………………………………………. 87 12.4. Iimpawu……………………………………………………………………………………………….. 88 12.5. I-Verilog HDL Prototype…………………………………………………………………………..88 12.6. i-VHDL Component Declaration………………………………………………………………………………… I-VHDL LIBRARY_SE Declaration………………………………………………………………………89 12.7. Iimpawu ……………………………………………………………………………………………………. 89 12.8. Iiparamitha……………………………………………………………………………………………. 89
13. ALTSQRT (Integer Square Root) IP Core………………………………………………………………… Iimpawu……………………………………………………………………………………………….. 92 13.1. I-Verilog HDL Prototype…………………………………………………………………………..92 13.2. i-VHDL Component Declaration…………………………………………………………………………………………… I-VHDL LIBRARY_SE Declaration………………………………………………………………………92 13.3. Amazibuko……………………………………………………………………………………………………………………………………………………. 93 13.4. Iiparamitha……………………………………………………………………………………………. 93
14. PARALLEL_ADD (Parallel Adder) IP Core………………………………………………………….. 95 14.1. Inqaku……………………………………………………………………………………………….95 14.2. I-Verilog HDL Prototype……………………………………………………………………………..95 14.3. i-VHDL Component Declaration………………………………………………………………………………………… I-VHDL LIBRARY_SE Declaration…………………………………………………………………………96 14.4. Amazibuko……………………………………………………………………………………………………………………………………………………. 96 14.5. Iiparamitha……………………………………………………………………………………………. 96
15. I-Integer Arithmetic IP Cores UVimba woMsebenzisi weSikhokelo soXwebhu …………………………………… 98
16. Uhlaziyo lweMbali yoXwebhu lwe-Intel FPGA Integer Arithmetic IP Cores IsiKhokelo somsebenzisi…. 99

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1. Intel FPGA Integer Arithmetic IP Cores

Ungasebenzisa i-Intel® FPGA integer IP cores ukwenza imisebenzi yemathematika kuyilo lwakho.

Le misebenzi ibonelela ngolungelelwaniso olululo kunye nokuphunyezwa kwesixhobo kunokubhala eyakho imisebenzi. Unokwenza ngokwezifiso ii-IP cores ukulungiselela iimfuno zakho zoyilo.

I-Intel integer arithmetic IP cores zahlulwe ngokwala mahlelo mabini alandelayo: · Ithala leencwadi lemodyuli ezicwangcisiweyo (LPM) ii-IP cores · Intel-specific (ALT) IP cores

Le theyibhile ilandelayo idwelisa i-IP cores ye-arithmetic epheleleyo.

Uluhlu loku-1.

Uluhlu lwee-IP Cores

IP Cores

LPM IP cores

LPM_COUNTER

LPM_HLANGANISA

LPM_MULT

LPM_ADD_SUB
LPM_COMPARE
Intel-specific (ALT) IP cores ALTECC

Umsebenzi ngaphezuluview I-Counter Divider Multiplier
I-Adder okanye i-subtractor Comparator
I-ECC Encoder/Decoder

Isixhobo esixhaswayo
Arria® II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone® IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP,
Intel Cyclone 10 GX, MAX® II, MAX V, MAX 10, Stratix® IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
I-Cyclone V,Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V yaqhubeka...

Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo. *Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.

ISO 9001:2015 ibhalisiwe

1. Intel FPGA Integer Arithmetic IP Cores 683490 | 2020.10.05

IP Cores Intel FPGA Phindaphinda iAdder okanye ALTERA_MULT_ADD ALTMEMMULT
ALTMULT_ACCUM ALTMULT_ADD ALTMULT_COMPLEX
ALTSQRT
PARALLEL_ADD

Umsebenzi ngaphezuluview I-Multiplier-Adder
I-Memory-based Constant Coefficient Multiplier
I-Multiplier-Accumulator Multiplier-Adder
Complex Multiplier
I-Integer Square-Root
I-Parallel Adder

Isixhobo esixhaswayo
Arria V, Stratix V, Cyclone V, Intel Stratix 10, Intel Arria 10, Intel Cyclone
10 GX
Arria II GX, Arria II GZ, Arria V, Intel Arria 10 (Intel Quartus® Prime Standard Edition), Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
I-Cyclone 10 LP, MAX II, MAX V, MAX 10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX,Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Intel Arria 10, Arria V, Arria V GZ, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
I-Cyclone 10 GX, Intel Cyclone 10 LP, MAX 10, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
I-Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP,Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V

Ulwazi olunxulumeneyo
· I-Intel FPGAs kunye ne-Programmable Devices Release Notes
· Intshayelelo kwi-Intel FPGA IP Cores Ibonelela ngolwazi olungakumbi malunga ne-Intel FPGA IP Cores.
· Isikhokelo soMsebenzisi we-IP ye-Floating-Point Sibonelela ngolwazi oluthe kratya malunga ne-Intel FPGA eFloating-Point IP cores.
· Intshayelelo kwi-Intel FPGA IP Cores Ibonelela ngolwazi oluphangaleleyo malunga nazo zonke ii-Intel FPGA IP cores, kuquka iparameterizing, ukuvelisa, ukuphuculwa, kunye nokulinganisa ii-IP cores.
· Ukudala i-IP eZimeleyo ze-IP kunye ne-Qsys Ukulinganisa okushicilelweyo Yenza izikripthi zokulinganisa ezingadingi kuhlaziywa ngesandla kwisoftware okanye kuhlaziyo lwenguqulelo ye-IP.
· ULawulo lweProjekthi IziKhokelo zeZenzo eziLungileyo zolawulo olusebenzayo kunye nokuphatheka kweprojekthi yakho kunye ne-IP files.
· I-Integer Arithmetic IP Cores UVimba woMsebenzisi weSikhokelo soMsebenzisi kwiphepha lama-98 Ibonelela ngoluhlu lwezikhokelo zabasebenzisi kwiinguqulelo zangaphambili ze-Integer Arithmetic IP cores.

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 6

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2. LPM_COUNTER (I-Counter) IP Core

Umzobo 1.

I-LPM_COUNTER IP core yikhawuntara yokubini eyenza izinto zokubala eziphezulu, izixhobo zokubala ezisezantsi kunye nezixhobo zokubala eziphezulu okanye ezisezantsi ezinemveliso ukuya kwi-256 bits ububanzi.

Lo mzobo ulandelayo ubonisa izibuko ze LPM_COUNTER IP engundoqo.

LPM_COUNTER Amazibuko

LPM_COUNTER

ssclr sload idatha yesethi[]

q[]

Ngubani othi

Cout

aclr aload aset

clk_en cnt_en cin
inst

2.1. Iimpawu
I-LPM_COUNTER IP core inikezela ngezi mpawu zilandelayo: · Ivelisa phezulu, ezantsi, kunye nephezulu/ezantsi izixhobo zokubala · Yenza ezi ntlobo zokubala zilandelayo:
— Ibhinari engenanto- ukunyuswa kwekhawunta kuqala ukusuka kwiqanda okanye ukucutha ukusuka kuma-255
-Imodulus-ikhawuntari yonyuso ukuya okanye icuthe ukusuka kwixabiso lemodyuli elichazwe ngumsebenzisi kwaye iphinda
· Ixhasa ungqamaniso olukhethwayo olucacileyo, umthwalo, kunye nokuseta amazibuko ongeniso · Ixhasa izibuko ezikhethiweyo ezizihambelayo ezicacileyo, umthwalo, kunye nokuseta izibuko zongeniso · Ixhasa ukubala okukhethiweyo kwenza kwaye iwotshi yenza amazibuko ongeniso · Ixhasa izibuko lokungena kunye nokuthwala

ISO 9001:2015 ibhalisiwe

2. LPM_COUNTER (I-Counter) IP Core
683490 | 2020.10.05
2.2. Verilog HDL Prototype
Le prototype ilandelayo yeVerilog HDL ibekwe kuyilo lweVerilog File (.v) lpm.v kwi ulawulo lwe-edasynthesis.
imodyuli lpm_counter ( q, idatha, iwotshi, cin, cout, clk_en, cnt_en, updown, aset, aclr, aload, sset, sclr, sload, eq ); ipharamitha lpm_type = “lpm_counter”; ipharamitha lpm_width = 1; ipharamitha lpm_modulus = 0; iparameter lpm_direction = “EZINGASETYENZISWA”; iparameter lpm_avalue = “EZINGASETYENZISWA”; ipharamitha lpm_svalue = “EZINGASETYENZISWA”; iparameter lpm_pvalue = “EZINGASETYENZISWA”; iparameter lpm_port_updown = “PORT_CONNECTIVITY”; iparameter lpm_hint = “EZINGASETYENZISWA”; imveliso [lpm_width-1:0] q; ukukhutshwa kwemveliso; imveliso [15:0] eq; i-cin input; igalelo [lpm_width-1:0] data; iwotshi yokufaka, clk_en, cnt_en, phezulu; igalelo aset, aclr, aload; isethi yegalelo, sclr, sload; endmodule
2.3. Isibhengezo seCandelo leVHDL
Isibhengezo secandelo leVHDL sikwi-VHDL Design File (.vhd) LPM_PACK.vhd kwi iilayibrarivhdllpm ulawulo.
icandelo LPM_COUNTER generic ( LPM_WIDTH : yendalo; LPM_MODULUS : yendalo := 0; LPM_DIRECTION : umtya := "ENGASETYENZISWAYO"; LPM_AVALUE : umtya := "OKUNGASETYENZISWEYO"; LPM_SVALUE : umtya := "UNGASETYENZISIWEYO"; LPM_PORTIVD ; LPM_PVALUE : umtya := “LPM_TYPE : umtya := LPM_HINT : umtya := “ENGASETYENZISWA”; izibuko (IDATHA : kwi std_logic_vector(LPM_WIDTH-1 downto 0):= (OTHERS =>
'0'); IWASHI : kwi std_logic ; CLK_EN : kwi std_logic := '1'; CNT_EN : kwi-std_logic := '1'; UHLAZIYO : kwi std_logic := '1'; SLADE : kwi std_logic := '0'; SSET : kwi std_logic := '0'; SCLR : kwi std_logic := '0'; I-ALOAD : kwi-std_logic := '0'; I-ASET : kwi-std_logic := '0'; ACLR : kwi std_logic := '0'; CIN : kwi std_logic := '1'; COUT : out std_logic := '0'; Q : ngaphandle std_logic_vector(LPM_WIDTH-1 downto 0); EQ : ngaphandle std_logic_vector (15 downto 0));
isiphelo secandelo;

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2.4. VHDL LIBRARY_USE isiBhengezo
Isibhengezo se-VHDL LIBRARY-USE asiyomfuneko ukuba usebenzisa i-VHDL Component Declaration.
Ithala leencwadi lpm; SEBENZISA lpm.lpm_components.all;

2.5. Amazibuko

Ezi theyibhile zilandelayo dwelisa igalelo kunye nemveliso yezibuko LPM_COUNTER IP core.

Uluhlu loku-2.

LPM_COUNTER iZibuko zoNgeniso

Igama lePort

Kufuneka

Inkcazo

idatha[]

Hayi

Ukufakwa kwedatha enxuseneyo kwikhawuntara. Ubungakanani bezibuko longeniso luxhomekeke kwixabiso leparameter ye LPM_WIDTH.

iwotshi

Ewe

Igalelo lewotshi ephuculweyo.

clk_en

Hayi

Iwotshi yenza igalelo ukwenza yonke imisebenzi ehambelanayo. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-1.

cnt_en

Hayi

Ukubala vumela igalelo ukuvala ubalo xa kubangwa uphantsi ngaphandle kokuchaphazela islayidi, isethi, okanye sclr. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-1.

Ngubani othi

Hayi

Ilawula indlela yokubala. Xa kuthiwa uphezulu (1), isalathiso sokubala siphezulu, kwaye xa kuthiwa sisezantsi (0), isalathiso sokubala siyehla. Ukuba iparameter ye LPM_DIRECTION isetyenzisiwe, izibuko ezantsi ayinakuqhagamshelwa. Ukuba i-LPM_DIRECTION ayisetyenziswanga, izibuko elisuka phezulu liyakhethwa. Ukuba ishiyiwe, ixabiso elimiselweyo liphezulu (1).

cin

Hayi

Ngena kwi-bit ephantsi. Kwizixhobo zokubala eziphezulu, ukuziphatha kwegalelo lecin yi

iyafana nokuziphatha kwegalelo le-cnt_en. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-1

(VCC).

aclr

Hayi

Igalelo elicacileyo elingena-synchronous. Ukuba zombini i-aset kunye ne-aclr zisetyenzisiwe kwaye zibasiwe, i-aclr ibhala ngaphezulu i-asethi. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-0 (ivaliwe).

asethi

Hayi

Ungeniso lweseti engahambelaniyo. Ixela i-q[] iziphumo njengazo zonke ii-1, okanye kwixabiso elixelwe yi-LPM_AVALUE iparameter. Ukuba zombini i-aset kunye nezibuko ze-aclr zisetyenziswa kwaye zibangelwe, ixabiso lezibuko le-aclr lingaphezulu kwexabiso le-aset port. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-0, livaliwe.

umthwalo

Hayi

Igalelo lomthwalo we-asynchronous elilayisha ngokulinganayo ikhawuntara ngexabiso kwigalelo ledatha. Xa izibuko lokulayisha lisetyenziswa, idata[] izibuko kufuneka iqhagamshelwe. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-0, livaliwe.

sclr

Hayi

Igalelo elicacileyo le-synchronous elicima ikhawunta kumphetho wewotshi elandelayo esebenzayo. Ukuba zombini isethi kunye nezibuko ze-sclr zisetyenzisiwe kwaye zibangelwe, ixabiso lezibuko le-sclr lingaphezulu kwexabiso lezibuko le-sset. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-0, livaliwe.

isethi

Hayi

Ungeniso lweseti engqamanisayo emisela isibali kumphetho wewotshi elandelayo esebenzayo. Ixela ixabiso leziphumo q njengazo zonke 1s, okanye kwixabiso elixelwe yi LPM_SVALUE iparameter. Ukuba zombini isethi kunye ne-sclr port zisetyenzisiwe kwaye ziqinisekisiwe,
ixabiso lezibuko le sclr libhala ngaphezulu ixabiso le sset port. Ukuba ishiyiwe, ixabiso elimiselweyo ngu-0 (ivaliwe).

umthwalo

Hayi

Ungeniso lomthwalo olungqamaniso olulayisha ikhawuntara ngedatha[] kumphetho wewotshi elandelayo esebenzayo. Xa isilayishi sesilayishi sisetyenziswa, idatha[] izibuko kufuneka iqhagamshelwe. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-0 (ivaliwe).

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 9

2. LPM_COUNTER (Counter) IP Core 683490 | 2020.10.05

Uluhlu loku-3.

LPM_COUNTER IZibuko Zemveliso

Igama lePort

Kufuneka

Inkcazo

q[]

Hayi

Imveliso yedatha evela kwikhawuntara. Ubungakanani bezibuko lemveliso buxhomekeke kwi

LPM_WIDTH ixabiso lepharamitha. Nokuba i-q[] okanye izibuko enye ye-eq[15..0]

kufuneka idityaniswe.

eq[15..0]

Hayi

Imveliso ye-counter decode. I-eq[15..0] izibuko ayifikeleleki kumhleli weparameter kuba iparameter ixhasa kuphela i-AHDL.
Nokuba i-q[] izibuko okanye i-eq[] izibuko kufuneka iqhagamshelwe. Ukuya kuthi ga kwizibuko ze-c eq zingasetyenziswa (0 <= c <= 15). Kuphela li-16 awona maxabiso asezantsi achaziweyo. Xa ixabiso lokubala lingu-c, imveliso ye-eqc ibangwa phezulu (1). Umzekeloampi-le, xa i-0, i-eq0 = 1, xa i-1, i-eq1 = 1, kwaye xa i-15, i-eq 15 = 1. Isiphumo esicacisiweyo samanani okubalwa kwe-16 okanye ngaphezulu ifuna i-decoding yangaphandle. I-eq[15..0] iziphumo zi-asynchronous kwi-q[] imveliso.

Cout

Hayi

Qhuba izibuko le-MSB bit yekhawuntara. Ingasetyenziselwa ukudibanisa kwenye i-counter ukwenza i-counter enkulu.

2.6. Iiparameter

Le theyibhile ilandelayo idwelisa iiparamitha ze LPM_COUNTER IP core.

Uluhlu loku-4.

LPM_COUNTER Iiparamitha

Igama leParameter

Uhlobo

LPM_WIDTH

Inani elipheleleyo

LPM_DIRECTION

Umtya

LPM_MODULUS LPM_AVALUE

Inani elipheleleyo
Inani elipheleleyo/ Umtya

LPM_SVALUE LPM_HINT

Inani elipheleleyo/ Umtya
Umtya

LPM_TYPE

Umtya

Kuyafuneka Ewe Hayi Hayi Hayi
Hayi hayi
Hayi

Inkcazo
Ixela ububanzi bedatha[] kunye neq[] namazibuko, ukuba ayasetyenziswa.
Amaxabiso PHEZULU, PHANTSI, kwaye AKASETYENZISWA. Ukuba iparameter ye LPM_DIRECTION isetyenzisiwe, izibuko ezantsi ayinakuqhagamshelwa. Xa izibuko eliphezulu lingaqhagamshelwanga, i-LPM_DIRECTION ixabiso elimiselweyo lepharamitha PHEZULU.
Ubuninzi babalo, dibanisa enye. Inani leemeko ezizodwa kumjikelo wekhawuntara. Ukuba ixabiso lomthwalo likhulu kune LPM_MODULUS iparamitha, ukuziphatha kwekhawunta akuchazwanga.
Ixabiso elithe rhoqo elilayishwayo xa i-asethi ibangwa phezulu. Ukuba ixabiso elichaziweyo likhulu kuno okanye liyalingana , ukuziphatha kwe-counter yinqanaba lengqiqo (X) engachazwanga, apho yi LPM_MODULUS, ukuba ikhona, okanye 2 ^ LPM_WIDTH. I-Intel icebisa ukuba ukhankanye eli xabiso njengenani lokugqibela loyilo lwe-AHDL.
Ixabiso elithe rhoqo elilayishwe kumda onyukayo wezibuko lewotshi xa izibuko le-sset libangwa phezulu. I-Intel icebisa ukuba ukhankanye eli xabiso njengenani lokugqibela loyilo lwe-AHDL.
Xa uqinisekisa ilayibrari yeemodyuli ezineparameterized (LPM) umsebenzi kuYilo lweVHDL File (.vhd), kufuneka usebenzise i LPM_HINT iparamitha ukucacisa iparameter ethe ngqo yeIntel. Umzekeloample: LPM_HINT = “CHAIN_SIZE = 8, ONE_INPUT_IS_CONSTANT = EWE”
Ixabiso elimiselweyo AYISETYENZISWA.
Ichonga igama lequmrhu lethala leencwadi leemodyuli ezineparameterized (LPM) kuyilo lweVHDL files.
iqhubekile...

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 10

Ukuzisa impendulo

2. LPM_COUNTER (Counter) IP Core 683490 | 2020.10.05

Igama leParameter INTENDED_DEVICE_FAMILY CARRY_CNT_EN
LABWIDE_SCLR
LPM_PORT_UPOWN

Uhlobo lwentambo yomtya
Umtya
Umtya

Inombolo efunekayo
Hayi
Hayi

Inkcazo
Le parameter isetyenziselwa imodeli kunye neenjongo zokulinganisa ukuziphatha. Le parameter isetyenziselwa imodeli kunye neenjongo zokulinganisa ukuziphatha. Umhleli weparameter ubala ixabiso lale parameter.
Intel-specific parameter. Kufuneka usebenzise LPM_HINT iparamitha ukucacisa iCARRY_CNT_EN iparamitha kuyilo lweVHDL files. Amaxabiso a-SMART, ON, VALIWE, kwaye AKUSETYENZISWA. Yenza i LPM_COUNTER umsebenzi usasaze uphawu lwe cnt_en ngekhonkco lokuthwala. Kwezinye iimeko, iCARRY_CNT_EN useto lweparamitha lunokuba nefuthe elincinci kwisantya, ngoko unokufuna ukuyicima. Ixabiso elingagqibekanga yi-SMART, ebonelela ngeyona ndlela yorhwebo phakathi kobukhulu kunye nesantya.
Intel-specific parameter. Kufuneka usebenzise i LPM_HINT iparamitha ukucacisa LABWIDE_SCLR iparamitha kuyilo lwe VHDL files. Amaxabiso avuliwe, acinyiwe, okanye AYISETYENZISWA. Ixabiso elimiselweyo lithi ON. Ikuvumela ukuba uvale usetyenziso lwe-LABwide sclr inqaku elifumaneka kwiintsapho zesixhobo esiphelelweyo. Ukucima olu khetho kwandisa amathuba okusebenzisa ngokupheleleyo ii-LABs ezizaliswe ngokungaphelelanga, kwaye ngaloo ndlela kunokuvumela uxinano oluphezulu xa i-SCLR ingasebenzisi kwi-LAB epheleleyo. Le parameter ikhona ngokuhambelana nomva, kwaye i-Intel icebisa ukuba ungasebenzisi le parameter.
Ixela usebenziso lwezibuko longeniso olusezantsi. Ukuba ixabiso elimiselweyo lishiyiwe yi PORT_CONNECTIVITY. Xa ixabiso lezibuko limiselwe kwi- PORT_USED, izibuko liphathwa njengelisetyenzisiweyo. Xa ixabiso lezibuko limiselwe kwi- PORT_UNUSED, izibuko liphathwa njengengasetyenziswanga. Xa ixabiso lezibuko limiselwe PORT_CONNECTIVITY, ukusetyenziswa kwezibuko kumiselwa ngokujonga uqhagamshelwano lwezibuko.

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 11

683490 | 2020.10.05 Thumela iNgxelo

3. LPM_DIVIDE (Isahluli) Intel FPGA IP Core

Umzobo 2.

I-LPM_DIVIDE Intel FPGA IP core isebenzisa isahluli ukwahlula ixabiso legalelo lenumerator ngexabiso legalelo ledinomineyitha ukuvelisa iquotient kunye nentsalela.

Lo mzobo ulandelayo ubonisa amazibuko e-LPM_DIVIDE engundoqo we IP.

LPM_DIVIDE Iizibuko

LPM_HLANGANISA

inombolo[] denom[] iwotshi

quotient[] hlala[]

clken aclr

inst

3.1. Iimpawu
I-LPM_DIVIDE IP core inikeza ezi mpawu zilandelayo: · Ivelisa isahluli esahlula ixabiso legalelo lenumerator ngegalelo ledinomineyitha.
ixabiso lokuvelisa iquotient kunye nentsalela. · Ixhasa ububanzi bedatha ye-1 bits. · Ixhasa ifomathi esayiniweyo nengatyikitywanga yokumelwa kwedatha yazo zombini inombolo
kunye namaxabiso edinomineyitha. · Ixhasa indawo okanye usetyenziso lwesantya. · Inika inketho yokuchaza imveliso eshiyekileyo. · Ixhasa ukulibaziseka kwemibhobho elungiselelwayo. · Ixhasa i-asynchronous ekhethiweyo ecacileyo kunye newotshi ivumela amazibuko.

3.2. Verilog HDL Prototype
Le prototype ilandelayo yeVerilog HDL ibekwe kuyilo lweVerilog File (.v) lpm.v kwi ulawulo lwe-edasynthesis.
imodyuli lpm_yahlula (i-quotient, hlala, inani, idenom, iwotshi, clken, aclr); iparameter lpm_type = “lpm_divide”; ipharamitha lpm_widthn = 1; ipharamitha lpm_widthd = 1; ipharamitha lpm_nrepresentation = “AKUSAYINWA”; iparameter lpm_drepresentation = “AKUSAYINWA”; iparameter lpm_remainderpositive = “TRUE”; iparameter lpm_pipeline = 0;

ISO 9001:2015 ibhalisiwe

3. LPM_DIVIDE (Isahluli) Intel FPGA IP Core 683490 | 2020.10.05

iparameter lpm_hint = “EZINGASETYENZISWA”; iwotshi yokufaka igalelo cliken; igalelo aclr; igalelo [lpm_widthn-1:0] inani; igalelo [lpm_widthd-1:0] idenom; imveliso [lpm_widthn-1:0] quotient; imveliso [lpm_widthd-1:0] ihlala; endmodule

3.3. Isibhengezo seCandelo leVHDL
Isibhengezo secandelo leVHDL sikwi-VHDL Design File (.vhd) LPM_PACK.vhd kwi iilayibrarivhdllpm ulawulo.
ilungu LPM_DIVIDE elenziwe lafana nelo (LPM_WIDTHN : yendalo; LPM_WIDTHD : eyendalo;
LPM_NREPRESENTATION : umtya := "OKUNGASAYINWA"; LPM_DREPRESENTATION : umtya := "OKUNGASAYINWA"; LPM_PIPELINE : kwendalo := 0; LPM_TYPE : umtya := L_DIVIDE; LPM_HINT : umtya := "ENGASETYENZISWAYO"); izibuko ( NUMER : in std_logic_vector(LPM_WIDTHN-1 downto 0); DENOM : kwi std_logic_vector(LPM_WIDTHD-1 downto 0); ACLR : in std_logic := '0'; CLOCK : in std_logic := '0 logic: CdEN logic'; := '1'; QUOTIENT : out std_logic_vector(LPM_WIDTHN-1 downto 0) ; isiphelo secandelo;

3.4. VHDL LIBRARY_USE isiBhengezo
Isibhengezo se-VHDL LIBRARY-USE asiyomfuneko ukuba usebenzisa i-VHDL Component Declaration.
Ithala leencwadi lpm; SEBENZISA lpm.lpm_components.all;

3.5. Amazibuko

Ezi theyibhile zilandelayo dwelisa igalelo kunye nemveliso yezibuko LPM_DIVIDE IP core.

Uluhlu loku-5.

LPM_DIVIDE iZibuko zokuNgena

Igama lePort

Kufuneka

inombolo[]

Ewe

idenom[]

Ewe

Inkcazo
Ukufakwa kwedatha yeNyumera. Ubungakanani bezibuko longeniso luxhomekeke kwixabiso leparameter ye LPM_WIDTHN.
Ukufakwa kwedatha ye-Denominator. Ubungakanani bezibuko longeniso luxhomekeke kwixabiso leparameter ye LPM_WIDTHD.
iqhubekile...

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 13

3. LPM_DIVIDE (Isahluli) Intel FPGA IP Core 683490 | 2020.10.05

Port Igama iwotshi clken
aclr

Inombolo efunekayo
Hayi

Inkcazo
Ukufakwa kwewotshi kusetyenziso lwemibhobho. Kumaxabiso e-LPM_PIPELINE ngaphandle kwe-0 (ehlala ikho), izibuko lewotshi kufuneka livulwe.
Iwotshi ivumela ukusetyenziswa kombhobho. Xa izibuko le-clken kuthiwa liphezulu, umsebenzi wokwahlula kwenzeka. Xa isignali iphantsi, akukho msebenzi wenziwayo. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-1.
Izibuko elicacileyo elingahambelaniyo elisetyenziswa nangaliphi na ixesha ukuseta ngokutsha umbhobho kuzo zonke ii-'0 ngokulinganayo kwigalelo lewotshi.

Uluhlu loku-6.

LPM_DIVIDE Izibuko Zemveliso

Igama lePort

Kufuneka

Inkcazo

iquotient[]

Ewe

Imveliso yedatha. Ubungakanani bezibuko lemveliso lixhomekeke kwi LPM_WIDTHN

ixabiso lepharamitha.

hlala[]

Ewe

Imveliso yedatha. Ubungakanani bezibuko lemveliso lixhomekeke kwi LPM_WIDTHD

ixabiso lepharamitha.

3.6. Iiparameter

Le theyibhile ilandelayo idwelisa iiparamitha ze LPM_DIVIDE Intel FPGA IP core.

Igama leParameter

Uhlobo

Kufuneka

Inkcazo

LPM_WIDTHN

Inani elipheleleyo

Ewe

Ixela ububanzi benani[] kunye

quotient[] izibuko. Amaxabiso ngu-1 ukuya ku-64.

LPM_WIDTHD

Inani elipheleleyo

Ewe

Ixela ububanzi bedenom[] kunye

kuhlala[] kumazibuko. Amaxabiso ngu-1 ukuya ku-64.

LPM_NREPRESENTATION LPM_DREPRESENTATION

Umtya womtya

Hayi

Umboniso wophawu lwegalelo lenani.

Iinqobo ezisemgangathweni zisayiniwe kwaye AYISAYINWA. Xa oku

iparameter isetilwe KUSAYINWA, umahluli

itolika inani[] igalelo njengezibini ezityikityiweyo

umphelelisi.

Hayi

Umboniso wophawu lwegalelo ledinomineyitha.

Iinqobo ezisemgangathweni zisayiniwe kwaye AYISAYINWA. Xa oku

iparameter isetilwe KUSAYINWA, umahluli

itolika ingeniso yedenom[] njengezibini ezityikityiweyo

umphelelisi.

LPM_TYPE

Umtya

Hayi

Ichonga ilayibrari ye parameterized

iimodyuli (LPM) igama lequmrhu kuyilo lweVHDL

files (.vhd).

LPM_HINT

Umtya

Hayi

Xa umisela ithala leencwadi le

iimodyuli zeparameterized (LPM) umsebenzi kwi

Uyilo lweVHDL File (.vhd), kufuneka usebenzise i

LPM_HINT iparameter ukucacisa i Intel-

iparameter ethile. Umzekeloample: LPM_HINT

= “CHAIN_SIZE = 8,

ONE_INPUT_IS_CONSTANT = EWE” I

ixabiso elimiselweyo AYISETYENZISWA.

LPM_REMAINDERPOSITIVE

Umtya

Hayi

Intel-specific parameter. Kufuneka usebenzise i

LPM_HINT iparameter ukucacisa i

LPM_REMAINDERPOSITIVE ipharamitha kwi

Uyilo lweVHDL files. Amanani YINYANI okanye BUBUXOKI.

Ukuba le parameter imiselwe kwi TRUE, ngoko i

ixabiso lentsalela[] izibuko kufuneka libe likhulu

iqhubekile...

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 14

Ukuzisa impendulo

3. LPM_DIVIDE (Isahluli) Intel FPGA IP Core 683490 | 2020.10.05

Igama leParameter

Uhlobo

MAXIMIZE_SPEED

Inani elipheleleyo

LPM_PIPELINE

Inani elipheleleyo

INTENDED_DEVICE_FAMILY SKIP_BITS

Inani elipheleleyo lomtya

iNombolo efunekayo
Hayi Hayi Hayi

Inkcazo
kuno okanye ukulingana no-zero. Ukuba le parameter imiselwe TRUE, ngoko ixabiso lentsalela[] izibuko ngunothi, okanye ixabiso luluphawu olufanayo, nokuba lilungile okanye alibi, njengexabiso lenombolo yezibuko. Ukuze unciphise indawo kunye nokuphucula isantya, i-Intel incoma ukuseta le parameter kwi-TRUE kwimisebenzi apho intsalela kufuneka ibe yinto enhle okanye apho intsalela ingabalulekanga.
Intel-specific parameter. Kufuneka usebenzise i LPM_HINT iparamitha ukucacisa MAXIMIZE_SPEED iparamitha kuyilo lwe VHDL files. Amaxabiso [0..9]. Ukuba isetyenzisiwe, i-Intel Quartus Prime isoftwe izama ukukhulisa umzekelo othile we-LPM_DIVIDE umsebenzi wesantya kunokuphindaphindeka, kwaye ibeka ngaphezulu useto lwengqiqo yoBuchule bokuLungisa. Ukuba MAXIMIZE_SPEED ayisetyenziswanga, ixabiso loKhetho loBuchule olusetyenziswa endaweni yalo. Ukuba ixabiso le-MAXIMIZE_SPEED yi-6 okanye ngaphezulu, uMhlanganisi ulungiselela undoqo we-LPM_DIVIDE we-IP ngesantya esiphezulu ngokusebenzisa imixokelelwane yokuthwala; ukuba ixabiso li-5 okanye ngaphantsi, umqambi uphumeza uyilo ngaphandle kwamatyathanga okuthwala.
Ixela inani leewotshi zeewotshi ezinxulunyaniswa ne-quotient[] kwaye zishiye[] iziphumo. Ixabiso lika-zero (0) libonisa ukuba akukho latency ikhona, kunye nokuba umsebenzi odityanisiweyo kuphela uyaqiniswa. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-0 (ayinambhobho). Awukwazi ukukhankanya ixabiso le-LPM_PIPELINE iparamitha engaphezulu kune-LPM_WIDTHN.
Le parameter isetyenziselwa imodeli kunye neenjongo zokulinganisa ukuziphatha. Umhleli weparameter ubala ixabiso lale parameter.
Ivumela ulwahlulwa-hlulo lwe-fractional bit olusebenzayo ukunyusa ingqiqo kumasuntswana akhokelayo ngokubonelela ngenani lokukhokela i-GND ukuya kwi-LPM_DIVIDE IP core. Cacisa inani le-GND ekhokelayo kwimveliso ye-quotient kule parameter.

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 15

683490 | 2020.10.05 Thumela iNgxelo

4. LPM_MULT (Multiplier) IP Core

Umzobo 3.

I-LPM_MULT IP engundoqo iphumeza isiphindaphinda ukuphindaphinda amanani amabini edatha yokufaka ukuvelisa imveliso njengemveliso.

Lo mzobo ulandelayo ubonisa izibuko ze LPM_MULT IP engundoqo.

LPM_Izibuko ezininzi

LPM_MULT idatha yewotshi[] isiphumo[] idathab[] aclr/sclr clken
inst

Iinkcukacha Eziyeleleneyo kwiphepha lama-71

4.1. Iimpawu
Undoqo we-LPM_MULT IP unikezela ngezi mpawu zilandelayo: · Ivelisa isiphindaphindi esiphindaphinda amaxabiso edatha amabini · Ixhasa ububanzi bedatha yeebhithi ze-1 · Ixhasa ifomathi yokumelwa kwedatha esayiniweyo nengatyikitywanga · Ixhasa ummandla okanye ukulungelelaniswa kwesantya · Ixhasa ukubhobhoza ngemibhobho enokucwangciswa ukubaleka kwemveliso · Ibonelela ukhetho lokuphunyezwa kwenkqubo ezinikeleyo yophawu lwedijithali (DSP)
Ibhloko yesekethe okanye izinto ezinengqondo (LEs) Qaphela: Xa usakha iziphindaphindi ezikhulu kunobungakanani obuxhasiweyo ngokwemveli kukho/
iya kuba yimpembelelo yokusebenza ephuma kwi-cascading yeebhloko ze-DSP. · Ixhasa i-asynchronous ekhethiweyo ecacileyo kunye newotshi ivumela amazibuko okufakwayo · Ixhasa ulungelelwaniso olukhethiweyo olucacileyo lwe-Intel Stratix 10, i-Intel Arria 10 kunye ne-Intel Cyclone 10 GX izixhobo

ISO 9001:2015 ibhalisiwe

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05
4.2. Verilog HDL Prototype
Le prototype ilandelayo yeVerilog HDL ibekwe kuyilo lweVerilog File (.v) lpm.v kwi ulawulo lwe-edasynthesis.
imodyuli lpm_mult ( isiphumo, idatha, idathab, isixa, iwotshi, clken, aclr ) ipharamitha lpm_type = “lpm_mult”; ipharamitha lpm_widtha = 1; ipharamitha lpm_widthb = 1; ipharamitha lpm_widths = 1; ipharamitha lpm_widthp = 1; ipharamitha lpm_representation = “AKUSAYINWA”; iparameter lpm_pipeline = 0; iparameter lpm_hint = “EZINGASETYENZISWA”; iwotshi yokufaka igalelo cliken; igalelo aclr; igalelo [lpm_widtha-1:0] dataa; igalelo [lpm_widthb-1:0] datab; igalelo [lpm_widths-1:0] sum; isiphumo [lpm_widthp-1:0]; endmodule
4.3. Isibhengezo seCandelo leVHDL
Isibhengezo secandelo leVHDL sikwi-VHDL Design File (.vhd) LPM_PACK.vhd kwi iilayibrarivhdllpm ulawulo.
icandelo LPM_MULT elenziwe afana nalawo aveliswe ngumenzi ( LPM_WIDTHA : kwendalo; LPM_WIDTHB : kwendalo; LPM_WIDTHS : kwendalo := 1; LPM_WIDTHP : kwendalo;
LPM_REPRESENTATION : umtya := "OKUNGASAYINWA"; LPM_PIPELINE : kwendalo := 0; LPM_TYPE: umtya:= L_MULT; LPM_HINT : umtya := "ENGASETYENZISWAYO"); izibuko ( DATAA : in std_logic_vector (LPM_WIDTHA-1 downto 0); DATAB : kwi std_logic_vector (LPM_WIDTHB-1 downto 0); ACLR : in std_logic := '0'; CLOCK : in std_logic := '0 logic: CdEN logic'; := '1'; SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0' ISIPHUMO : ngaphandle std_logic_vector(LPM_WIDTHP-1 downto 0)); isiphelo secandelo;
4.4. VHDL LIBRARY_USE isiBhengezo
Isibhengezo se-VHDL LIBRARY-USE asiyomfuneko ukuba usebenzisa i-VHDL Component Declaration.
Ithala leencwadi lpm; SEBENZISA lpm.lpm_components.all;

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 17

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

4.5. Iimpawu

Uluhlu loku-7.

LPM_MULT Iimpawu zoNgeniso

Igama loMqondiso

Kufuneka

Inkcazo

idatha[]

Ewe

Ukufakwa kwedatha.

Kwi-Intel Stratix 10, i-Intel Arria 10, kunye ne-Intel Cyclone 10 GX izixhobo, ubungakanani besignali yegalelo buxhomekeke kwixabiso lepharamitha yobubanzi beDatha.

Kwizixhobo ezindala kunye ne-Intel Cyclone 10 LP, ubungakanani bomqondiso wegalelo buxhomekeke kwixabiso lepharamitha ye-LPM_WIDTHA.

idathab[]

Ewe

Ukufakwa kwedatha.

Kwi-Intel Stratix 10, i-Intel Arria 10, kunye ne-Intel Cyclone 10 GX izixhobo, ubungakanani besignali yegalelo buxhomekeke kwixabiso lepharamitha yobubanzi beDatab.

Kwizixhobo ezindala kunye ne-Intel Cyclone 10 LP, ubungakanani bomqondiso wegalelo buxhomekeke

kwixabiso leparameter ye LPM_WIDTHB.

iwotshi

Hayi

Ukufakwa kwewotshi kusetyenziso lwemibhobho.

Kwizixhobo ezindala kunye ne-Intel Cyclone 10 LP, isignali yewotshi mayivulwe kumaxabiso e-LPM_PIPELINE ngaphandle kwe-0 (ehlala ikho).

Kwi-Intel Stratix 10, i-Intel Arria 10, kunye ne-Intel Cyclone 10 GX izixhobo, isignali yewotshi kufuneka yenziwe ukuba ixabiso leLatency lingaphandle kwe-1 (engagqibekanga).

iqhosha

Hayi

Iwotshi ivuleleke ukuze isetyenziswe ngemibhobho. Xa umqondiso we-clken ubizwa ngokuba phezulu, i

ukusebenza kwe-adder/subtractor kwenzeka. Xa umqondiso uphantsi, akukho msebenzi

kwenzeka. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-1.

i-aclr sclr

Hayi

Isignali ecacileyo e-asynchronous esetyenziswa nangaliphi na ixesha ukuseta kwakhona umbhobho kuzo zonke ii-0s,

ngokungqameneyo kwisignali yewotshi. Umbhobho uqalisa ukuya kokungachazwanga (X)

inqanaba lengqiqo. Iziphumo ziyafana, kodwa ixabiso elingengo-zero.

Hayi

Ungqamaniso lwesignali ecacileyo esetyenziswa nangaliphi na ixesha ukuseta ngokutsha umbhobho kubo bonke oo-0,

ngongqamaniso kwisignali yewotshi. Umbhobho uqalisa ukuya kokungachazwanga (X)

inqanaba lengqiqo. Iziphumo ziyafana, kodwa ixabiso elingengo-zero.

Uluhlu loku-8.

LPM_MULT Iimpawu zemveliso

uphawu Igama

Kufuneka

Inkcazo

iziphumo[]

Ewe

Imveliso yedatha.

Kwizixhobo ezindala kunye ne-Intel Cyclone 10 LP, ubungakanani bomqondiso wokuphuma buxhomekeke kwixabiso lepharamitha ye-LPM_WITDHP. Ukuba LPM_WIDTHP < ubuninzi (LPM_WIDTHA + LPM_WIDTHB, LPM_WIDTHS) okanye (LPM_WIDTHA + LPM_WIDTHS), zii-LPM_WIDTHP MSB kuphela ezikhoyo.

I-Intel Stratix 10, i-Intel Arria 10 kunye ne-Intel Cyclone 10 GX, ubungakanani beempawu zemveliso buxhomekeke kwiparamitha yobubanzi beSiphumo.

4.6. Iiparamitha ze-Stratix V, i-Arria V, i-Cyclone V, kunye ne-Intel Cyclone 10 LP Devices

4.6.1. Ithebhu ngokubanzi

Uluhlu loku-9.

Ithebhu ngokubanzi

Ipharamitha

Ixabiso

Uqwalaselo lwaBaninzi

Phindaphinda-phinda igalelo elithi 'dataa' ngegalelo elithi 'datab'

Ixabiso eliMiselweyo

Inkcazo

Phindaphinda-phinda igalelo elithi 'dataa' ngegalelo elithi 'datab'

Khetha uqwalaselo olufunwayo lwesiphindaphindi.
iqhubekile...

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 18

Ukuzisa impendulo

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

Ipharamitha
Kufuneka ibe banzi kangakanani igalelo 'idatha'? Kufuneka ibe banzi kangakanani igalelo elithi 'datab'? Ububanzi 'besiphumo' kufuneka bugqitywe njani? Nciphisa ububanzi

Ixabiso
Phindaphinda-phinda igalelo 'idatha' ngokwayo (umsebenzi wokuphinda-phinda)
1 - 256 bits

Ixabiso eliMiselweyo

Inkcazo

8 amasuntswana

Chaza ububanzi bedathaa[] izibuko.

1 - 256 bits

8 amasuntswana

Chaza ububanzi bedatab[] izibuko.

Ukubala ngokuzenzekelayo ububanzi
1 - 512 bits

Ngokuzenzekelayo y bala ububanzi

Khetha indlela efunekayo ukumisela ububanzi besiphumo[] izibuko.

16 amasuntswana

Chaza ububanzi besiphumo[] izibuko.
Eli xabiso liyakusebenza kuphela xa ukhetha Nciphisa ububanzi kuHlobo lweparamitha.

4.6.2. Ngokubanzi 2 Tab

Uluhlu 10. Ngokubanzi 2 Tab

Ipharamitha

Ixabiso

Ungeniso lweDatha

Ngaba ibhasi ye-'datab' inexabiso elingaguqukiyo?

Hayi Ewe

Uhlobo lokuphindaphinda

Loluphi uhlobo lwe

Ayityikitywanga

uyafuna uphindaphindo? Isayiniwe

Ukuphunyezwa

Loluphi umiliselo oluphindaphindayo ekufuneka lusetyenziswe?

Sebenzisa ukuphunyezwa okungagqibekanga
Sebenzisa i-multiplier circuitry ezinikeleyo (Ayifumaneki kuzo zonke iintsapho)
Sebenzisa izakhi zengqiqo

Ixabiso eliMiselweyo

Inkcazo

Hayi

Khetha Ewe ukucacisa ixabiso elingaguqukiyo le

`datab' ibhasi yokufaka, ukuba ikhona.

Ayityikitywanga

Chaza ifomathi yomelo yazo zombini idata[] kunye nedatab[] igalelo.

Sebenzisa iion yomiliselo olumiselweyo

Khetha indlela efunekayo ukumisela ububanzi besiphumo[] izibuko.

4.6.3. Ithebhu yePipelining

Itheyibhile 11. Ithebhu yokuBopha

Ipharamitha

Ngaba uyafuna ukwenza umbhobho weNo

umsebenzi?

Ewe

Ixabiso

Yenza i-'aclr'

—

izibuko elicacileyo elingangqinelaniyo

Ixabiso eliMiselweyo

Inkcazo

Hayi

Khetha Ewe ukwenza irejista yombhobho isebenze kwi

imveliso yophindaphindo kwaye uchaze oyifunayo

umva wemveliso kumjikelo wewotshi. Ukuvumela i

irejista yombhobho yongeza ukubambezeleka okongeziweyo kwi

imveliso.

Ayikhange iqwalaselwe

Khetha olu khetho ukwenza i-aclr izibuko isebenzise i-asynchronous clear kwirejista yombhobho.
iqhubekile...

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 19

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

Ipharamitha
Yenza iwotshi ye-'clken' isebenze
Ukuphucula
Loluphi uhlobo lolungiselelo olufunayo?

Ixabiso -
Indawo yesantya esiMiselweyo

Ixabiso eliMiselweyo

Inkcazo

Ayikhange iqwalaselwe

Ikhankanya ikloko ephezulu esebenzayo yesibuko sewotshi yerejista yombhobho

Ukuhlala kukho

Cacisa ulungiselelo olufunekayo lwe-IP core.
Khetha uMiyo ukuvumela i-Intel Quartus Prime software ukumisela eyona ndlela ilungileyo ye-IP engundoqo.

4.7. Iiparamitha ze-Intel Stratix 10, i-Intel Arria 10, kunye ne-Intel Cyclone 10 GX izixhobo

4.7.1. Ithebhu ngokubanzi

Uluhlu 12. IThebhu ngokubanzi

Ipharamitha

Ixabiso

Ixabiso eliMiselweyo

Inkcazo

Udidi loLungiselelo lwaBaninzi
Ububanzi bePort Data

Phindaphinda-phinda igalelo elithi 'dataa' ngegalelo elithi 'datab'
Phindaphinda-phinda igalelo 'idatha' ngokwayo (umsebenzi wokuphinda-phinda)

Phindaphinda-phinda igalelo elithi 'dataa' ngegalelo elithi 'datab'

Khetha uqwalaselo olufunwayo lwesiphindaphindi.

Ububanzi bedatha

1 - 256 bits

8 amasuntswana

Chaza ububanzi bedathaa[] izibuko.

Ububanzi bedatha

1 - 256 bits

8 amasuntswana

Chaza ububanzi bedatab[] izibuko.

Kufuneka kumiselwe njani ububanzi besiphumo 'sesiphumo'?

Uhlobo

Bala ububanzi ngokuzenzekelayo
Nciphisa ububanzi

Ngokuzenzekelayo y bala ububanzi

Khetha indlela efunekayo ukumisela ububanzi besiphumo[] izibuko.

Ixabiso

1 - 512 bits

16 amasuntswana

Chaza ububanzi besiphumo[] izibuko.
Eli xabiso liyakusebenza kuphela xa ukhetha Nciphisa ububanzi kuHlobo lweparamitha.

Ububanzi besiphumo

1 - 512 bits

—

Ibonisa ububanzi obusebenzayo besiphumo[] izibuko.

4.7.2. Ngokubanzi 2 Tab

Uluhlu 13. Ngokubanzi 2 Tab

Ipharamitha

Ungeniso lweDatha

Ngaba ibhasi ye-'datab' inexabiso elingaguqukiyo?

Hayi Ewe

Ixabiso

Ixabiso eliMiselweyo

Inkcazo

Hayi

Khetha Ewe ukucacisa ixabiso elingaguqukiyo le

`datab' ibhasi yokufaka, ukuba ikhona.

iqhubekile...

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 20

Ukuzisa impendulo

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

Ipharamitha

Ixabiso

Naliphi na ixabiso elikhulu kuno-0

Uhlobo lokuphindaphinda

Loluphi uhlobo lwe

Ayityikitywanga

uyafuna uphindaphindo? Isayiniwe

Isimbo sokuSebenzisa

Loluphi umiliselo oluphindaphindayo ekufuneka lusetyenziswe?

Sebenzisa ukuphunyezwa okungagqibekanga
Sebenzisa i-multiplier circuitry ezinikeleyo
Sebenzisa izakhi zengqiqo

Ixabiso eliMiselweyo

Inkcazo

Chaza ixabiso elingaguqukiyo ledathab[] izibuko.

Ayityikitywanga

Chaza ifomathi yomelo yazo zombini idata[] kunye nedatab[] igalelo.

Sebenzisa iion yomiliselo olumiselweyo

Khetha indlela efunekayo ukumisela ububanzi besiphumo[] izibuko.

4.7.3. Ukwenziwa kwemibhobho

Itheyibhile 14. Ithebhu yokuBopha

Ipharamitha

Ixabiso

Ngaba uyafuna ukwenza umbhobho umsebenzi?

Umbhobho

Hayi Ewe

ILatency Clear Signal Type

Naliphi na ixabiso elikhulu kuno-0.
AKUKHO ACLR SCLR

Yenza iwotshi 'clken'

—

vula iwotshi

Loluphi uhlobo lolungiselelo olufunayo?

Uhlobo

Indawo yesantya esiMiselweyo

Ixabiso eliMiselweyo

Inkcazo

Hayi 1 NONE
—

Khetha Ewe ukwenza irejista yombhobho isebenze kwimveliso yophindaphindo. Ukuvumela irejista yombhobho yongeza ukulinda okongezelelweyo kwimveliso.
Cacisa umva wesiphumo esifunekayo kumjikelo wewotshi.
Cacisa uhlobo lokusetha ngokutsha kwirejista yombhobho. Khetha HAYI ukuba awusebenzisi nayiphi na irejista yombhobho. Khetha i-ACLR ukusebenzisa i-asynchronous clear kwirejista yombhobho. Oku kuya kuvelisa izibuko le-ACLR. Khetha i-SCLR ukusebenzisa i-synchronous clear kwirejista yombhobho. Oku kuya kuvelisa izibuko le-SCLR.
Ikhankanya ikloko ephezulu esebenzayo yesibuko sewotshi yerejista yombhobho

Ukuhlala kukho

Cacisa ulungiselelo olufunekayo lwe-IP core.
Khetha uMiyo ukuvumela i-Intel Quartus Prime software ukumisela eyona ndlela ilungileyo yondoqo we-IP.

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 21

683490 | 2020.10.05 Thumela iNgxelo

5. LPM_ADD_SUB (Adder/Subtractor)

Umzobo 4.

I-LPM_ADD_SUB ingundoqo ye-IP ikuvumela ukuba usebenzise i-adder okanye i-subtractor ukongeza okanye ukukhupha iiseti zedatha ukuvelisa imveliso equlethe isamba okanye umahluko wamaxabiso egalelo.

Lo mzobo ulandelayo ubonisa izibuko ze LPM_ADD_SUB IP core.

LPM_ADD_SUB Izibuko

LPM_ADD_SUB yongeza_i-cin

idatha[]

datab iwotshi clken[] aclr

iziphumo[] ukuphuphuma cout

inst

5.1. Iimpawu
I-LPM_ADD_SUB core ye-IP inikezela ngezi mpawu zilandelayo: · Ivelisa i-adder, i-subtractor, kunye ne-adder/i-subtractor elungelelanisiweyo.
imisebenzi. · Ixhasa ububanzi bedatha ye-1 bits. · Ixhasa ifomathi yokumelwa kwedatha enjengokutyikitywa nokungasayinwanga. · Ixhasa ukukhetha-ngaphakathi (ukuboleka-ngaphandle), i-asynchronous ecacileyo, kunye newotshi ivumela
izibuko zokungenisa. · Ixhasa i-optional-out-out (ukuboleka-ngaphakathi) kunye ne-overflow output port. · Ukwabela nokuba yeyiphi na yeebhasi zedatha yegalelo ukuba ibe yinto engatshintshiyo. · Ixhasa ukufakwa kwemibhobho ngokulibaziseka kwemveliso elungisekayo.

ISO 9001:2015 ibhalisiwe

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05
5.2. Verilog HDL Prototype
Le prototype ilandelayo yeVerilog HDL ibekwe kuyilo lweVerilog File (.v) lpm.v kwi ulawulo lwe-edasynthesis.
imodyuli lpm_yongeza_sub (isiphumo, cout, ukuphuphuma,yongeza_sub, cin, dataa, datab, iwotshi, clken, aclr); iparameter lpm_type = “lpm_add_sub”; ipharamitha lpm_width = 1; iparameter lpm_direction = “EZINGASETYENZISWA”; ipharamitha lpm_representation = “ISAYINIWA”; iparameter lpm_pipeline = 0; iparameter lpm_hint = “EZINGASETYENZISWA”; igalelo [lpm_width-1:0] dataa, datab; igalelo add_sub, cin; iwotshi yokufaka igalelo cliken; igalelo aclr; isiphumo [lpm_width-1:0]; ukuphuma kwemveliso, ukuphuphuma; endmodule
5.3. Isibhengezo seCandelo leVHDL
Isibhengezo secandelo leVHDL sikwi-VHDL Design File (.vhd) LPM_PACK.vhd kwi iilayibrarivhdllpm ulawulo.
icandelo LPM_ADD_SUB elenziwe lafana nelo (LPM_WIDTH : yendalo;
LPM_DIRECTION : umtya := “ENGASETYENZISWAYO”; LPM_REPRESENTATION: umtya := “ISAYINIWA”; LPM_PIPELINE : kwendalo := 0; LPM_TYPE : umtya := L_ADD_SUB; LPM_HINT : umtya := "ENGASETYENZISWAYO"); izibuko (IDATAA : kwi std_logic_vector(LPM_WIDTH-1 downto 0); DATAB : kwi std_logic_vector(LPM_WIDTH-1 downto 0); ACLR : in std_logic := '0'; CLOCK : in std_logic := '0' kwi CLK_logic: std_logic := '1'; CIN : in std_logic := 'Z' : in std_logic := '1' isiphelo secandelo;
5.4. VHDL LIBRARY_USE isiBhengezo
Isibhengezo se-VHDL LIBRARY-USE asiyomfuneko ukuba usebenzisa i-VHDL Component Declaration.
Ithala leencwadi lpm; SEBENZISA lpm.lpm_components.all;
5.5. Amazibuko
Ezi theyibhile zilandelayo dwelisa igalelo kunye nemveliso yezibuko LPM_ADD_SUB IP core.

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 23

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05

Itheyibhile 15. LPM_ADD_SUB IP Ungeniso lweZibuko ezingundoqo

Igama lePort

Kufuneka

Inkcazo

cin

Hayi

Ngena kwi-bit ephantsi. Kumsebenzi wokongezwa, ixabiso elimiselweyo ngu-0. Kuba

ukuthabatha, ixabiso elimiselweyo ngu-1.

idatha[]

Ewe

Ukufakwa kwedatha. Ubungakanani bezibuko longeniso luxhomekeke kwixabiso leparameter ye LPM_WIDTH.

idathab[]

Ewe

Ukufakwa kwedatha. Ubungakanani bezibuko longeniso luxhomekeke kwixabiso leparameter ye LPM_WIDTH.

add_sub

Hayi

Ukhetho lokungenisa izibuko ukwenza utshintsho oluguquguqukayo phakathi kwe-adder kunye ne-subtractor

imisebenzi. Ukuba iparameter ye LPM_DIRECTION isetyenzisiwe, add_sub ayinakusetyenziswa. Ukuba

ikhutshiwe, ixabiso elimiselweyo yi ADD. I-Intel icebisa ukuba usebenzise i

LPM_DIRECTION iparameter ukucacisa ukusebenza kwe LPM_ADD_SUB umsebenzi,

endaweni yokwabela into engatshintshiyo kwizibuko lokudibanisa_esezantsi.

iwotshi

Hayi

Igalelo lokusetyenziswa kwemibhobho. Isibuko sewotshi sibonelela ngegalelo lewotshi yombhobho

ukusebenza. Kumaxabiso e-LPM_PIPELINE ngaphandle kwe-0 (ehlala ikho), izibuko lewotshi kufuneka libe

yenziwe yasebenza.

iqhosha

Hayi

Iwotshi ivuleleke ukuze isetyenziswe ngemibhobho. Xa izibuko le-clken libanga phezulu, i-adder/

umsebenzi wokuthabatha uyenzeka. Xa isignali iphantsi, akukho msebenzi wenziwayo. Ukuba

Ishiyiwe, ixabiso elimiselweyo ngu-1.

aclr

Hayi

I-asynchronous clear kusetyenziso lwemibhobho. Umbhobho uqalisa ukuya kokungachazwanga (X)

inqanaba lengqiqo. Izibuko le aclr lingasetyenziswa nangaliphi na ixesha ukuseta ngokutsha umbhobho kubo bonke oo-0,

ngokungqameneyo kwisignali yewotshi.

Itheyibhile 16. LPM_ADD_SUB IP Core Output Ports

Igama lePort

Kufuneka

Inkcazo

iziphumo[]

Ewe

Imveliso yedatha. Ubungakanani bezibuko lemveliso lixhomekeke kwi LPM_WIDTH iparamitha

ixabiso.

Cout

Hayi

Ukukhupha (ukuboleka-ngaphakathi) kweyona nto ibalulekileyo (MSB). Izibuko le cout linomzimba

Ukutolikwa njengokuqhutywa (ukuboleka) kwe-MSB. Izibuko le-out liyabhaqa

ukuphuphuma kwimisebenzi ENGUNGASAYINWAYO. I-out port isebenza ngendlela efanayo

Imisebenzi ESAYINWAYO kunye ENGINGASAYINWA.

phuphuma

Hayi

Ukhetho lokuphuma ngaphandle kokuphuphumayo. Izibuko eliphuphumayo linotoliko olubonakalayo njenge

i-XOR yokuthwala ungene kwi-MSB ngokuqhutywa kwe-MSB. Izibuko lokuphuphuma

Ibango xa iziphumo zigqithise ukuchaneka okukhoyo, kwaye isetyenziswa kuphela xa i

LPM_REPRESENTATION ixabiso lepharamitha SIGNED.

5.6. Iiparameter

Le theyibhile ilandelayo idwelisa LPM_ADD_SUB IP core parameters.

Itheyibhile 17. LPM_ADD_SUB IP Core Parameters

Igama leParameter LPM_WIDTH

Chwetheza Inani elipheleleyo

Uyafuneka Ewe

Inkcazo
Ixela ububanzi bedatha[], idathab[], kunye neziphumo[] amazibuko.

LPM_DIRECTION

Umtya

Hayi

Amaxabiso ADD, SUB, kunye UNGASETYENZISWA. Ukuba ishiyiwe, ixabiso elingagqibekanga ngu-DEFAULT, elathisa iparameter ukuthatha ixabiso layo kwi-addd_sub port. I-add_sub port ayinakusetyenziswa ukuba i-LPM_DIRECTION isetyenzisiwe. I-Intel icebisa ukuba usebenzise i-LPM_DIRECTION iparamitha ukucacisa ukusebenza komsebenzi we-LPM_ADD_SUB, kunokuba unikeze ngokuqhubekayo kwizibuko le-ad_sub.
iqhubekile...

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 24

Ukuzisa impendulo

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05

Igama leParameter LPM_REPRESENTATION LPM_PIPELINE LPM_HINT LPM_TYPE ONE_INPUT_IS_CONSTANT MAXIMIZE_SPEED
INTENDED_DEVICE_FAMILY

Uhlobo lwe-String Integer ye-String Integer
Umtya

Kufuneka Hayi Hayi Hayi Hayi Hayi Hayi Hayi
Hayi

Inkcazo
Ixela uhlobo lodibaniso olwenziweyo. Iinqobo ezisemgangathweni zisayiniwe kwaye AYISAYINWA. Ukuba ishiyiwe, ixabiso elimiselweyo SAYINWE. Xa le parameter imiselwe UKUSAYINWA, i-adder/i-subtractor itolika igalelo ledatha njengoko kusayiniweyo ukuhambelana kwezimbini.
Ixela inani lemijikelo yewotshi yokulinda ehambelana nesiphumo[] isiphumo. Ixabiso lika-zero (0) libonisa ukuba akukho latency ikhona, kwaye umsebenzi odityanisiweyo kuphela uya kuqinisekiswa. Ukuba ishiyiwe, ixabiso elimiselweyo ngu-0 (ayifakwanga).
Ikuvumela ukuba uchaze iiparamitha ze-Intel ezikhethekileyo kuyilo lweVHDL files (.vhd). Ixabiso elimiselweyo AYISETYENZISWA.
Ichonga igama lequmrhu lethala leencwadi leemodyuli ezineparameterized (LPM) kuyilo lweVHDL files.
Intel-specific parameter. Kufuneka usebenzise i LPM_HINT iparamitha ukucacisa i ONE_INPUT_IS_CONSTANT iparamitha kuyilo lwe VHDL files. Amaxabiso ngu-EWE, HAYI, kwaye UNGASETYENZISWA. Ibonelela ngokwandisa okukhulu ukuba igalelo elinye lihlala lihleli. Ukuba ishiyiwe, ixabiso elimiselweyo nguNO.
Intel-specific parameter. Kufuneka usebenzise i LPM_HINT iparamitha ukucacisa MAXIMIZE_SPEED iparamitha kuyilo lwe VHDL files. Ungakhankanya ixabiso phakathi kwe-0 kunye ne-10. Ukuba isetyenzisiwe, i-Intel Quartus Prime software izama ukunyusa umzekelo othile we-LPM_ADD_SUB umsebenzi wesantya kunokuba usebenze, kwaye ibeka ngaphezulu ukusetwa koBuchule bokuLungisa ukhetho lwengqiqo. Ukuba MAXIMIZE_SPEED ayisetyenziswanga, ixabiso loKhetho loBuchule olusetyenziswa endaweni yalo. Ukuba isicwangciso se-MAXIMIZE_SPEED yi-6 okanye ngaphezulu, uMhlanganisi ulungiselela undoqo we-LPM_ADD_SUB IP ngesantya esiphezulu usebenzisa ikhonkco lokuthwala; ukuba isicwangciso si-5 okanye ngaphantsi, uMqulunqi uphumeza uyilo ngaphandle kwamakhonkco okuthwala. Le parameter kufuneka icaciswe kwiCyclone, iStratix, kunye neStratix GX izixhobo kuphela xa izibuko le add_sub lingasetyenziswa.
Le parameter isetyenziselwa imodeli kunye neenjongo zokulinganisa ukuziphatha. Umhleli weparameter ubala ixabiso lale parameter.

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 25

683490 | 2020.10.05 Thumela iNgxelo

6. LPM_COMPARE (Isithelekisi)

Umzobo 5.

I-LPM_COMPARE IP core ithelekisa ixabiso leseti ezimbini zedatha ukumisela ubudlelwane phakathi kwazo. Kweyona ndlela ilula, ungasebenzisa isango-OKANYE isango ukumisela ukuba amasuntswana amabini edatha ayalingana.

Lo mzobo ulandelayo ubonisa izibuko ze LPM_COMPARE IP engundoqo.

LPM_COMPARE Amazibuko

LPM_COMPARE

iqhosha

ialb

aeb

idatha[]

agb

idathab[]

ixeshab

iwotshi

aneb

aclr

aleb

inst

6.1. Iimpawu
I-LPM_COMPARE engundoqo ye-IP inikezela ngezi mpawu zilandelayo: · Ivelisa umsebenzi wokuthelekisa ukuthelekisa iiseti ezimbini zedatha · Ixhasa ububanzi bedatha yeebhithi ze-1 · Ixhasa ifomathi yokumelwa kwedatha efana nesayinwe kwaye ingasayinwanga · Ivelisa ezi ndidi zilandelayo zemveliso:
— alb (igalelo A lingaphantsi kwegalelo B) — aeb (igalelo A lilingana negalelo B) — agb (igalelo A likhulu kunegalelo B) — i-ageb (igalelo A likhulu okanye lilingana negalelo B) — aneb ( igalelo A alilingani negalelo B) — aleb (igalelo A lingaphantsi okanye lilingana negalelo B) · Ixhasa igalelo elikhethiweyo elilinganayo kunye newotshi livumela amazibuko engeniso · Inika idathab[] igalelo ngokungaguqukiyo · Ixhasa ukufakwa kwemibhobho ngokucokisekileyo kwemveliso.

ISO 9001:2015 ibhalisiwe

6. LPM_COMPARE (Umthelekisi) 683490 | 2020.10.05
6.2. Verilog HDL Prototype
Le prototype ilandelayo yeVerilog HDL ibekwe kuyilo lweVerilog File (.v) lpm.v kwi ulawulo lwe-edasynthesis.
imodyuli lpm_thelekisa ( alb, aeb, agb, aleb, aneb, ageb, dataa, datab, clock, clken, aclr ); ipharamitha lpm_type = “lpm_compare”; ipharamitha lpm_width = 1; ipharamitha lpm_representation = “AKUSAYINWA”; iparameter lpm_pipeline = 0; iparameter lpm_hint = “EZINGASETYENZISWA”; igalelo [lpm_width-1:0] dataa, datab; iwotshi yokufaka igalelo cliken; igalelo aclr; imveliso alb, aeb, agb, aleb, aneb, ageb; endmodule
6.3. Isibhengezo seCandelo leVHDL
Isibhengezo secandelo leVHDL sikwi-VHDL Design File (.vhd) LPM_PACK.vhd kwi iilayibrarivhdllpm ulawulo.
icandelo LPM_COMPARE elenziwe lafana nelo (LPM_WIDTH : yendalo;
LPM_REPRESENTATION : umtya := "OKUNGASAYINWA"; LPM_PIPELINE : kwendalo := 0; LPM_TYPE: umtya := L_COMPARE; LPM_HINT : umtya := “ENGASETYENZISWA”); izibuko (IDATAA : kwi std_logic_vector(LPM_WIDTH-1 downto 0); DATAB : kwi std_logic_vector(LPM_WIDTH-1 downto 0); ACLR : in std_logic := '0'; CLOCK : in std_logic := '0' kwi CLK_logic: std_logic := '1' AGB : out std_logic : out std_logic; isiphelo secandelo;
6.4. VHDL LIBRARY_USE isiBhengezo
Isibhengezo se-VHDL LIBRARY-USE asiyomfuneko ukuba usebenzisa i-VHDL Component Declaration.
Ithala leencwadi lpm; SEBENZISA lpm.lpm_components.all;
6.5. Amazibuko
Ezi theyibhile zilandelayo dwelisa igalelo kunye nemveliso yezibuko LMP_COMPARE IP core.

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 27

6. LPM_COMPARE (Umthelekisi) 683490 | 2020.10.05

Itheyibhile 18. LPM_COMPARE IP core Input Ports

Igama lePort

Kufuneka

Inkcazo

idatha[]

Ewe

Ukufakwa kwedatha. Ubungakanani bezibuko longeniso luxhomekeke kwixabiso leparameter ye LPM_WIDTH.

idathab[]

Ewe

Ukufakwa kwedatha. Ubungakanani bezibuko longeniso luxhomekeke kwixabiso leparameter ye LPM_WIDTH.

iwotshi

Hayi

Ukufakwa kwewotshi kusetyenziso lwemibhobho. Izibuko lewotshi libonelela ngegalelo lewotshi yombhobho

ukusebenza. Kumaxabiso e-LPM_PIPELINE ngaphandle kwe-0 (ehlala ikho), izibuko lewotshi kufuneka libe

yenziwe yasebenza.

iqhosha

Hayi

Iwotshi ivuleleke ukuze isetyenziswe ngemibhobho. Xa izibuko le-clken kuthiwa liphezulu, i

umsebenzi wothelekiso lwenzeka. Xa isignali iphantsi, akukho msebenzi wenziwayo. Ukuba

Ishiyiwe, ixabiso elimiselweyo ngu-1.

aclr

Hayi

I-asynchronous clear kusetyenziso lwemibhobho. Umbhobho uqalisa kwingqiqo engachazwanga (X).

inqanaba. Izibuko le aclr lingasetyenziswa nangaliphi na ixesha ukuseta ngokutsha umbhobho kubo bonke oo-0,

ngokungqameneyo kwisignali yewotshi.

Itheyibhile 19. LPM_COMPARE IP core Outputs Ports

Igama lePort

Kufuneka

Inkcazo

ialb

Hayi

Izibuko lemveliso yomthelekisi. Kuyacelwa ukuba igalelo A lingaphantsi kwegalelo B.

aeb

Hayi

Izibuko lemveliso yomthelekisi. Kuyacelwa ukuba igalelo A lilingana negalelo B.

agb

Hayi

Izibuko lemveliso yomthelekisi. Kuyacelwa ukuba igalelo A likhulu kunegalelo B.

ixeshab

Hayi

Izibuko lemveliso yomthelekisi. Kuyacelwa ukuba igalelo A likhulu kuno okanye lilingana negalelo

aneb

Hayi

Izibuko lemveliso yomthelekisi. Kuyacelwa ukuba igalelo A alilingani negalelo B.

aleb

Hayi

Izibuko lemveliso yomthelekisi. Kuyacelwa ukuba igalelo A lingaphantsi okanye lilingana negalelo B.

6.6. Iiparameter

Le theyibhile ilandelayo idwelisa iiparamitha ze LPM_COMPARE IP core.

Itheyibhile 20. LPM_COMPARE IP core Parameters

Igama leParameter

Uhlobo

Kufuneka

LPM_WIDTH

Inani elipheleleyo Ewe

LPM_REPRESENTATION

Umtya

Hayi

LPM_PIPELINE

Inani elipheleleyo

LPM_HINT

Umtya

Hayi

Inkcazo
Ixela ububanzi bedatha[] kunye nedatab[] namazibuko.
Ixela uhlobo lothelekiso olwenziweyo. Iinqobo ezisemgangathweni zisayiniwe kwaye AYISAYINWA. Ukuba ishiyiwe, ixabiso elimiselweyo AYISAYINWE. Xa eli xabiso leparameter limiselwe UKUSAYINWA, umthelekisi utolika igalelo ledatha njengoko kusayiniwe ukuhambelana kwezimbini.
Ixela inani leewotshi zeewotshi eziyanyaniswa nealb, aeb, agb, ageb, aleb, okanye imveliso yeaneb. Ixabiso lika-zero (0) libonisa ukuba akukho latency ikhona, kwaye umsebenzi odityanisiweyo kuphela uya kuqinisekiswa. Ukuba ishiyiwe, ixabiso elimiselweyo ngu-0 (ayinambhobho).
Ikuvumela ukuba uchaze iiparamitha ze-Intel ezikhethekileyo kuyilo lweVHDL files (.vhd). Ixabiso elimiselweyo AYISETYENZISWA.
iqhubekile...

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 28

Ukuzisa impendulo

6. LPM_COMPARE (Umthelekisi) 683490 | 2020.10.05
Igama leParameter LPM_TYPE INTENDED_DEVICE_FAMILY
ONE_INPUT_IS_CONSTANT

Uhlobo lwentambo yomtya
Umtya

Inombolo efunekayo
Hayi

Inkcazo
Ichonga igama lequmrhu lethala leencwadi leemodyuli ezineparameterized (LPM) kuyilo lweVHDL files.
Le parameter isetyenziselwa imodeli kunye neenjongo zokulinganisa ukuziphatha. Umhleli weparameter ubala ixabiso lale parameter.
Intel-specific parameter. Kufuneka usebenzise i LPM_HINT iparamitha ukucacisa i ONE_INPUT_IS_CONSTANT iparamitha kuyilo lwe VHDL files. Amaxabiso ngu-EWE, HAYI, okanye UNGASETYENZISWA. Ibonelela ngokwandisa okukhulu ukuba igalelo lihlala lihleli. Ukuba ishiyiwe, ixabiso elimiselweyo nguNO.

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 29

683490 | 2020.10.05 Thumela iNgxelo

7. I-ALTECC (Ikhowudi yoLungiso lwempazamo: I-Encoder / Decoder) IP Core

Umzobo 6.

I-Intel ibonelela ngesiseko se-ALTECC IP ukuphumeza ukusebenza kwe-ECC. I-ECC ibona idatha eyonakeleyo eyenzeka kwicala lomamkeli ngexesha lokuhanjiswa kwedatha. Le ndlela yokulungisa imposiso ifaneleke kakhulu kwiimeko apho iimpazamo zenzeke ngokungacwangciswanga kunokugqabhuka.

I-ECC ibona iimpazamo ngokusebenzisa inkqubo yokufakwa kweekhowudi kunye nokuchazwa kwedatha. Umzekeloample, xa i-ECC isetyenziswa kwisicelo sothumelo, idatha efundwe kumthombo ifakwe kwikhowudi ngaphambi kokuba ithunyelwe kumamkeli. Imveliso (ikhowudi yegama) evela kwi-encoder iquka idatha ekrwada edityaniswe nenani lamasuntswana okulingana. Elona nani lichanekileyo lamasuntswana okulingana ahlonyelweyo lixhomekeke kwinani lamasuntswana kwidatha yegalelo. Igama lekhowudi elenziweyo lithunyelwa kwindawo ekuyiwa kuyo.

Umamkeli ufumana igama lekhowudi kwaye alicazulule. Ulwazi olufunyenwe sisidikhowuda lumisela ukuba kufunyaniswe impazamo. Idikhowuda ibona iimpazamo zebit enye kunye ne-double-bit, kodwa inokulungisa kuphela iimpazamo zebit enye kwidatha eyonakeleyo. Olu hlobo lwe-ECC luphawu olulodwa lolungiso lwempazamo oluphindiweyo (SECDED).

Ungaqwalasela umsebenzi we-encoder kunye ne-decoder ye-ALTECC IP engundoqo. Ukufakwa kwedatha kwi-encoder kufakwe kwikhowudi ukuvelisa igama lekhowudi elidityanisiweyo lokufakwa kwedatha kunye neebhithi eziveliswayo zokulingana. Igama lekhowudi elenziweyo ligqithiselwa kwimodyuli yedikhowuda ukuze iguqulwe nje phambi kokufikelela kwindawo ekuyiwa kuyo. I-decoder ivelisa i-syndrome vector ukujonga ukuba kukho nayiphi na impazamo kwigama lekhowudi elifunyenweyo. Idekhowuda ilungisa idatha kuphela ukuba impazamo yesuntswana elinye isuka kumasuntswana edatha. Akukho phawu luphawulwayo ukuba impazamo yesuntswana elinye isuka kwimilinganiselo yokulinganisa. Idikhowuda nayo ineempawu zeflegi ezibonisa ubume bedatha efunyenweyo kunye nesenzo esithathwe sisidikhowuda, ukuba sikhona.

La manani alandelayo abonisa izibuko ze-ALTECC IP engundoqo.

I-ALTECC Encoder Ports

ALTECC_ENCODER

idatha[]

q[]

iwotshi

aclr

inst

ISO 9001:2015 ibhalisiwe

7. I-ALTECC (Ikhowudi yoLungiso lwempazamo: I-Encoder/Decoder) IP Core 683490 | 2020.10.05

Umzobo 7. I-ALTECC i-Decoder Ports

ALTECC_DECODER

idatha[] iwotshi

q[] err_ichongiwe err_corrected
impazamo_ebulalayo

aclr

inst

7.1. Iimpawu ze-Encoder ze-ALTECC

I-IP encoder ye-ALTECC ingundoqo inikezela ngezi mpawu zilandelayo: · Yenza ukufakwa kwekhowudi yedatha usebenzisa i-Hamming Coding scheme · Ixhasa ububanzi bedatha yeebhithi ezingama-2 · Ixhasa ifomathi yokumelwa kwedatha esayiniweyo nengatyikitywanga · Inkxaso yokwenziwa kwemibhobho ngemveliso yokubaleka komjikelo wewotshi enye okanye emibini · Ixhasa ngokuzithandela. i-asynchronous ecacileyo kunye newotshi yenza amazibuko

I-ALTECC encoder IP core ithatha kwaye ifake ikhowudi yedatha usebenzisa i-Hamming Coding scheme. Iskimu seKhowudi yeHamming sifumana amasuntswana okulingana kwaye sidibanisa kwidatha yoqobo ukuvelisa igama lekhowudi yemveliso. Inani lamasuntswana okulingana ahlonyelweyo lixhomekeke kububanzi bedatha.

Le theyibhile ilandelayo idwelisa inani lamasuntswana okulingana adityaniselwe uluhlu olwahlukeneyo lobubanzi bedatha. Ikholamu yeeBits iyonke imele inani elipheleleyo lamasuntswana edatha efakiweyo kunye neebhithi ezihlonyelweyo.

Uluhlu loku-21.

Inani leeBits zeParity kunye neKhowudi yeLizwi Ngokuhambelana nobubanzi beDatha

Ububanzi bedatha

Inani leeBits zeParity

Amasuntswana ewonke (Ikhowudi yegama)

2-4

3+1

6-8

5-11

4+1

10-16

12-26

5+1

18-32

27-57

6+1

34-64

58-64

7+1

66-72

I-parity bit derivation isebenzisa ujongo olulinganayo. I-1 bit eyongezelelweyo (eboniswe kwitheyibhile njenge +1) idityaniselwe kumasuntswana okulingana njenge-MSB yegama lekhowudi. Oku kuqinisekisa ukuba igama lekhowudi linenani elilinganayo lika-1's. UmzekeloampLe, ukuba ububanzi bedatha yi-4 bits, i-4 i-parity bits ihlonyelwe kwidatha ukuze ibe ligama lekhowudi kunye ne-8 bits iyonke. Ukuba iibits ezisi-7 kwi-LSB ye-8-bit code code zinenani elingumnqakathi lika-1, i-bit ye-8 (MSB) yegama lekhowudi ngu-1 yenza inani elipheleleyo lika-1 kwikhowudi yegama elilinganayo.
Lo mzobo ulandelayo ubonisa igama lekhowudi elenziweyo kunye nolungiselelo lwamasuntswana okulingana kunye neebhithi zedatha kwi-8-bit data input.

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 31

7. I-ALTECC (Ikhowudi yoLungiso lwempazamo: I-Encoder/Decoder) IP Core 683490 | 2020.10.05

Umzobo 8.

I-Parity Bits kunye noLungiselelo lweeBits kwi-8-Bit Generated Code Word

I-MSB

LSB

4 amasuntswana okulingana

4 amasuntswana edatha

I-ALTECC encoder IP core yamkela kuphela igalelo lobubanzi obuyi-2 ukuya kwi-64 bits ngexesha elinye. Ububanzi begalelo leebhithi ezili-12, iibhithi ezingama-29, kunye namasuntswana angama-64, alungele ngokufanelekileyo izixhobo ze-Intel, zivelisa iziphumo zeebhithi ezili-18, iibhithi ezingama-36, kunye namasuntswana angama-72 ngokulandelelanayo. Ungalawula umda we-bitselection kumhleli weparameter.

7.2. I-Verilog HDL Prototype (ALTECC_ENCODER)
Le prototype ilandelayo yeVerilog HDL ibekwe kuyilo lweVerilog File (.v) lpm.v kwi ulawulo lwe-edasynthesis.
imodyuli altecc_encoder #( iparameter target_device_family = “engasetyenziswanga”, parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = “altecc_encoder”, parameter lpm_hint = “unused awireclr, input input clock iwashi yocingo, i-input wire [width_dataword-1:0] data, i-output wire [width_codeword-1:0] q); endmodule

7.3. Verilog HDL iPrototype (ALTECC_DECODER)
Le prototype ilandelayo yeVerilog HDL ibekwe kuyilo lweVerilog File (.v) lpm.v kwi ulawulo lwe-edasynthesis.
imodyuli altecc_decoder #( iparameter target_device_family = “engasetyenziswanga”, parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = “altecc_decoder”, parameter lpm_hint = “unused awireclr, input input clock ucingo kloko, iingcingo zocingo [width_codeword-1:0] data, output wire err_corrected, output wire err_detected, outout wire err_fatal, output wire [width_dataword-1:0] q); endmodule

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 32

Ukuzisa impendulo

7. I-ALTECC (Ikhowudi yoLungiso lwempazamo: I-Encoder/Decoder) IP Core 683490 | 2020.10.05
7.4. I-VHDL Component Declaration (ALTECC_ENCODER)
Isibhengezo secandelo leVHDL sikwi-VHDL Design File (.vhd) altera_mf_components.vhd kwi librariesvhdlaltera_mf ulawulo.
icandelo altecc_encoder generic ( target_device_family: umtya := "engasetyenziswanga"; lpm_pipeline:natural := 0; width_codeword:natural := 8; width_dataword:natural:= 8; lpm_hint:string := "UN=USED":cclpalte ”); izibuko ( aclr: in std_logic := '0'; iwotshi:in std_logic := '0'; iwotshi:in std_logic := '1'; data:in std_logic_vector(width_dataword-1 downto 0); q:out std_logic_vector(width_codeword) -1 ukuya kutsho ku-0)); isiphelo secandelo;
7.5. iVHDL Component Declaration (ALTECC_DECODER)
Isibhengezo secandelo leVHDL sikwi-VHDL Design File (.vhd) altera_mf_components.vhd kwi librariesvhdlaltera_mf ulawulo.
component altecc_decoder generic ( target_device_family:string := "engasetyenziswanga"; lpm_pipeline:natural := 0; width_codeword:natural := 8; width_dataword:natural := 8; lpm_hint:string := "UN=USED":cclpalte ”); izibuko ( aclr: in std_logic := '0'; iwotshi: in std_logic := '0'; iwotshi:in std_logic := '1'; data: in std_logic_vector(width_codeword-1 downto 0); err_corrected: out std_logic; err_detected : ngaphandle std_logic; q:out std_logic_vector(width_dataword-1 downto 0) isiphelo secandelo;
7.6. VHDL LIBRARY_USE isiBhengezo
Isibhengezo se-VHDL LIBRARY-USE asiyomfuneko ukuba usebenzisa i-VHDL Component Declaration.
Ithala leencwadi litshintshile_mf; SEBENZISA ialtera_mf.altera_mf_components.all;
7.7. Encoder Ports
Ezi theyibhile zilandelayo zidwelisa igalelo kunye nemveliso yezibuko ze ALTECC encoder IP core.

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 33

7. I-ALTECC (Ikhowudi yoLungiso lwempazamo: I-Encoder/Decoder) IP Core 683490 | 2020.10.05

Itheyibhile 22. I-ALTECC Encoder Input Ports

Igama lePort

Kufuneka

Inkcazo

idatha[]

Ewe

Indawo yokufaka idatha. Ubungakanani bezibuko longeniso luxhomekeke kwi WIDTH_DATAWORD

ixabiso lepharamitha. Idatha[] izibuko iqulathe idatha ekrwada ekufuneka ifakwe kwikhowudi.

iwotshi

Ewe

Isiqhagamshelanisi sewotshi esibonelela ngomqondiso wewotshi ukulungelelanisa umsebenzi wokhowudo.

Isibane sewotshi siyafuneka xa ixabiso le-LPM_PIPELINE likhulu kuno-0.

iwotshi

Hayi

Ikloko ivuleleke. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-1.

aclr

Hayi

Igalelo elicacileyo elingena-synchronous. Uphawu olusebenzayo lwe-aclr oluphezulu lunokusetyenziswa nangaliphi na ixesha

Sula ngokulandelelanayo iirejista.

Itheyibhile 23. I-ALTECC Encoder Output Ports

Igama lezibuko q[]

Uyafuneka Ewe

Inkcazo
I-Encoded data output port. Ubungakanani bezibuko lemveliso lixhomekeke kwixabiso leparameter WIDTH_CODEWORD.

7.8. Amazibuko edikhowuda

Ezi theyibhile zilandelayo zidwelisa igalelo kunye nemveliso yezibuko ze-ALTECC idikhowuda engundoqo we IP.

Itheyibhile 24. I-ALTECC iZibuko zokuNgenisa iDikhowuda

Igama lePort

Kufuneka

Inkcazo

idatha[]

Ewe

Indawo yokufaka idatha. Ubungakanani bezibuko longeniso luxhomekeke kwixabiso lepharamitha WIDTH_CODEWORD.

iwotshi

Ewe

Isiqhagamshelanisi sewotshi esibonelela ngomqondiso wewotshi ukulungelelanisa umsebenzi wokhowudo. Isibane sewotshi siyafuneka xa ixabiso le-LPM_PIPELINE likhulu kuno-0.

iwotshi

Hayi

Ikloko ivuleleke. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-1.

aclr

Hayi

Igalelo elicacileyo elingena-synchronous. Isiginali ye-aclr ephezulu esebenzayo ingasetyenziswa nangaliphi na ixesha ukucima iirejista ngokungafaniyo.

Itheyibhile 25. I-ALTECC iZibuko zokuPhuma iDikhowuda

Igama lezibuko q[]

Uyafuneka Ewe

Inkcazo
I-decoded data output port. Ubungakanani bezibuko lemveliso lixhomekeke kwixabiso leparameter WIDTH_DATAWORD.

Err_chongiwe Ewe

Uphawu lweflegi ukubonisa ubume bedatha efunyenweyo kwaye ichaze naziphi na iimpazamo ezifunyenweyo.

err_right Ewe d

Umqondiso weflegi ukubonisa ubume bedatha efunyenweyo. Ichaza impazamo yebit enye efunyenwe yaza yalungiswa. Ungasebenzisa idatha kuba sele ilungisiwe.

impazamo_ebulalayo

Ewe

Umqondiso weflegi ukubonisa ubume bedatha efunyenweyo. Ichaza impazamo ye bit-bit efunyenweyo, kodwa ayilungiswanga. Akufunekanga usebenzise idatha ukuba olu phawu lubasiwe.

syn_e

Hayi

Isignali yemveliso eya kuya phezulu nanini na xa kubhaqwe impazamo yesuntswana elinye kwi-parity

amasuntswana.

7.9. Iiparamitha ze-Encoder
Le theyibhile ilandelayo idwelisa iiparameters ze-ALTECC encoder IP core.

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 34

Ukuzisa impendulo

7. I-ALTECC (Ikhowudi yoLungiso lwempazamo: I-Encoder/Decoder) IP Core 683490 | 2020.10.05

Itheyibhile 26. I-ALTECC Encoder Parameters

Igama leParameter

Uhlobo

Kufuneka

Inkcazo

WIDTH_DATAWORD

Inani elipheleleyo Ewe

Ixela ububanzi bedatha ekrwada. Amaxabiso asuka ku-2 ukuya ku-64. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-8.

WIDTH_CODEWORD

Inani elipheleleyo Ewe

Ixela ububanzi begama lekhowudi elihambelanayo. Amaxabiso asebenzayo asuka ku-6 ukuya ku-72, ngaphandle ko-9, 17, 33, no-65. Ukuba akafakwanga, ixabiso elimiselweyo ngu-13.

LPM_PIPELINE

Inani elipheleleyo

Ikhankanya umbhobho wesekethe. Amaxabiso avela ku-0 ukuya ku-2. Ukuba ixabiso ngu-0, amazibuko awabhaliswanga. Ukuba ixabiso ngu-1, izibuko zemveliso zibhalisiwe. Ukuba ixabiso ngu-2, igalelo kunye nemveliso izibuko zibhalisiwe. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-0.

7.10. Iiparamitha zedekhowuda

Le theyibhile ilandelayo idwelisa i-ALTECC decoder IP core parameters.

Itheyibhile 27. ALTECC Decoder Parameters

Igama leParameter WIDTH_DATAWORD

Chwetheza Inani elipheleleyo

Kufuneka

Inkcazo

Ewe

Ixela ububanzi bedatha ekrwada. Amaxabiso ngu-2 ukuya ku-64

ixabiso elimiselweyo ngu-8.

WIDTH_CODEWORD

Inani elipheleleyo

Ewe

Ixela ububanzi begama lekhowudi elihambelanayo. Amaxabiso ngu-6

ukuya ku-72, ngaphandle ko-9, 17, 33, kunye no-65. Ukuba ayifakwanga, ixabiso elimiselweyo

yi 13.

LPM_PIPELINE

Inani elipheleleyo

Hayi

Ichaza irejista yesekethe. Amaxabiso asuka ku-0 ukuya ku-2. Ukuba i

ixabiso ngu-0, akukho rejista iphunyeziweyo. Ukuba ixabiso ngu-1, i

imveliso ibhalisiwe. Ukuba ixabiso ngu-2, zombini igalelo kunye ne

imveliso ibhalisiwe. Ukuba ixabiso likhulu kuno-2, olongezelelweyo

iirejista ziphunyezwa kwisiphumo sokongezwa

ukubambezeleka. Ukuba ayifakwanga, ixabiso elimiselweyo ngu-0.

Yenza izibuko 'syn_e'

Inani elipheleleyo

Hayi

Vula le parameter ukwenza i-sync_e port.

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 35

683490 | 2020.10.05 Thumela iNgxelo

8. Intel FPGA Yandisa iAdder IP Core

Umzobo 9.

I-Intel FPGA Multiply Adder (Intel Stratix 10, Intel Arria 10, kunye ne-Intel Cyclone 10 izixhobo ze-GX) okanye i-ALTERA_MULT_ADD (i-Arria V, i-Stratix V, kunye nezixhobo ze-Cyclone V) i-IP core ikuvumela ukuba uphumeze i-adder-adder.

Lo mzobo ulandelayo ubonisa izibuko ze-Intel FPGA Phinda-phinda i-Adder okanye i-ALTERA_MULT_ADD engundoqo we-IP.

I-Intel FPGA Phinda-phinda iAdder okanye ALTERA_MULT_ADD Iizibuko

Intel FPGA Phinda-phinda iAdder okanye ALTERA_MULT_ADD

dataa[] signa datab[] signb datac[] coefsel0[] coefsel1[] coefsel2[] coefsel3[] addnsub1 addnsub3 aclr/sclr[] scanina[] iwotshi0 iwotshi1 iwotshi2 ena0 ena1 ena2 sload_accum
accum_sload chain[]

scanouta[] iziphumo[]

acl0 acl1

inst
I-multiplier-adder yamkela izibini zamagalelo, iphinda-phinda amaxabiso kunye ize yongeze okanye isuse kwiimveliso zazo zonke ezinye izibini.
Ukuba zonke iinkcukacha zegalelo ububanzi ziyi-9-bits ububanzi okanye encinci, umsebenzi usebenzisa i-9 x 9 bit input multiplier uqwalaselo kwibhloko ye-DSP yezixhobo ezixhasa i-9 x 9 uqwalaselo. Ukuba akunjalo, ibhloko ye-DSP isebenzisa i-18 × 18-bit yokuphindaphinda igalelo ukucubungula idatha kunye nobubanzi phakathi kweebhithi ezili-10 kunye ne-18. Ukuba ezininzi ze-Intel FPGA Ziphindaphinda iAdder okanye ALTERA_MULT_ADD IP cores zenzeka kuyilo, imisebenzi isasazwa njenge

ISO 9001:2015 ibhalisiwe

8. Intel FPGA Yandisa iAdder IP Core 683490 | 2020.10.05
iibhloko ezininzi ezahlukeneyo ze-DSP kangangoko ukuze indlela eya kwezibhloko ibe bhetyebhetye. Abaphindaphindi abambalwa ngebhloko ye-DSP bavumela ukhetho oluninzi lwendlela kwibhloko ngokunciphisa iindlela ukuya kwesinye isixhobo.
Iirejista kunye neerejista zemibhobho eyongezelelweyo kule miqondiso ilandelayo nazo zibekwe ngaphakathi kwibhloko ye-DSP: · Ukufakwa kwedatha · Isayinwe okanye engasayinwanga ekhethiweyo · Yongeza okanye uthabathe khetha · Iimveliso zabaphindaphindi.
Kwimeko yesiphumo sesiphumo, irejista yokuqala ifakwe kwibhloko ye-DSP. Nangona kunjalo iirejista ze-latency ezongezelelweyo zibekwe kwizinto ezinengqondo ngaphandle kwebhloko. I-Peripheral kwi-block ye-DSP, kubandakanywa igalelo ledatha kwi-multiplier, iingeniso zesignali zokulawula, kunye neziphumo ze-adder, sebenzisa umzila oqhelekileyo wokunxibelelana kunye nesixhobo sonke. Lonke unxibelelwano kumsebenzi lusebenzisa indlela ezinikeleyo ngaphakathi kwebhloko ye-DSP. Le ndlela inikezelweyo ibandakanya amakhonkco erejista yeshifti xa ukhetha ukhetho lokutshintsha idatha yegalelo ebhalisiweyo yophindaphindi ukusuka kwisiphindaphindi esinye ukuya kwisiphindaphindi esikufuphi.
Ngolwazi oluthe vetshe malunga neebhloko ze-DSP nakweyiphi na i-Stratix V, kunye nothotho lwesixhobo se-Arria V, jonga kwi-DSP Blocks isahluko seencwadi eziziincwadi ezifanelekileyo kwiphepha le-Literature and Technical Documentation.
Ulwazi oluNxulumeneyo AN 306: Ukuzalisekisa iziphindaphindi kwizixhobo zeFPGA
Ibonelela ngolwazi oluthe kratya malunga nokuphunyezwa kokuphindaphinda usebenzisa i-DSP kunye neebhloko zememori kwizixhobo ze-Intel FPGA.
8.1. Iimpawu
I-Intel FPGA Multiply Adder okanye ALTERA_MULT_ADD IP core inikezela ngezi mpawu zilandelayo: · Ivelisa isiphindaphinda ukwenza imisebenzi yophindaphindo emibini entsonkothileyo.
Amanani Qaphela: Xa usakha iziphindaphindi ezinkulu kunobungakanani obuxhaswe ngokwemveli kukho/
iya kuba yimpembelelo yokusebenza ephuma kwi-cascading yeebhloko ze-DSP. · Ixhasa ububanzi bedatha ye-1 256 bits · Ixhasa ifomathi yokumelwa kwedatha esayiniweyo nengasayinwanga · Ixhasa ukufakwa kwemibhobho ngocoselelo lwegalelo elimiselweyo · Inika ukhetho lokutshintshela ngokuguquguqukayo phakathi kwenkxaso yedatha esayiniweyo nengatyikitywanga. ngokuzikhethela i-asynchronous kunye ne-synchronous ecacileyo kunye newotshi yenza amazibuko okufakwayo · Ixhasa imo yerejista yokulibaziseka kwe-systolic · Ixhasa i-adder yangaphambili nge-8 coefficients yokulayisha kwangaphambili ngophindaphindo ngalunye · Ixhasa ukulayisha kwangaphambili okungaguqukiyo ukuhambelana nempendulo ye-accumulator

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Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 37

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8.1.1. I-pre-adder
Nge-pre-adder, ukongezwa okanye ukuthabatha kwenziwa ngaphambi kokutyisa umphindaphindi.
Kukho iindlela ezintlanu ze-adder yangaphambili: · Imo elula · Imo ebambeneyo · Imo yokufaka · Imo yesikwere · Imowudi rhoqo

Phawula:

Xa i-pre-adder isetyenziswa (i-pre-adder coefficient/input/square mode), onke amagalelo edatha kwi-multiplier kufuneka abe nokusetwa kwewotshi efanayo.

8.1.1.1. I-Pre-adder Imowudi elula

Kule mowudi, zombini ii-operands ziphuma kumazibuko egalelo kwaye i-adder yangaphambili ayisetyenziswa okanye ayigqithwanga. Le yindlela emiselweyo.

Umzobo 10. I-Pre-adder Indlela elula
uya0 b0

Mult0

isiphumo

8.1.1.2. Imowudi ye-adder yangaphambili
Kule ndlela, enye i-operand yophindaphinda iphuma kwi-adder yangaphambili, kwaye enye i-operand iphuma kwi-coefficient yokugcina yangaphakathi. I-coefficient yogcino ivumela ukuya kuthi ga kwi-8 esele isetwe ngokusisigxina. Iimpawu zokukhetha i-coefficient yi-coefsel[0..3].
Le ndlela ibonakaliswe kule nxaki ilandelayo.

Oku kulandelayo kubonisa imowudi ye-adder yangaphambili yesiphindaphindi.

Umzobo 11. I-Pre-adder Coefficient Mode

Preadder

Mult0

+/-

isiphumo

coefsel0 inkomo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 38

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8. Intel FPGA Yandisa iAdder IP Core 683490 | 2020.10.05
8.1.1.3. Imo yoNgeniso ye-adder yangaphambili Kule mowudi, enye i-operand yophinda-phindo ivela kwi-adder yangaphambili, kwaye enye i-operand ifumana kwi-datac[] igalelo lokufaka izibuko. Le ndlela ibonakaliswe kule nxaki ilandelayo.

Oku kulandelayo kubonisa indlela yokufaka i-pre-adder yesiphindaphindi.

Umzobo 12. Imo Yokufaka i-adder yangaphambili
uya0 b0

Mult0

+/-

isiphumo

8.1.1.4. Imo ye-Adder ye-Square yangaphambili Le ndlela ibonakaliswe kule nxaki ilandelayo.

Oku kulandelayo kubonisa indlela yesikwere se-pre-adder yeziphindaphindi ezimbini.

Umzobo 13. I-Pre-adder Square Mode
uya0 b0

Mult0

+/-

isiphumo

8.1.1.5. Imowudi ye-adder rhoqo
Kule modi, enye i-operand yophindaphinda iphuma kwi-port yongeniso, kwaye enye i-operand iphuma kwi-coefficient yokugcina yangaphakathi. Ugcino lwe-coefficient luvumela ukuya kuthi ga kwi-8 esele isetwe ngokusisigxina. Iimpawu zokukhetha i-coefficient yi-coefsel[0..3].
Le ndlela ibonakaliswe kule nxaki ilandelayo.

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Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 39

8. Intel FPGA Yandisa iAdder IP Core 683490 | 2020.10.05

Lo mzobo ulandelayo ubonisa imowudi ye-adder eqhubekayo yesiphindaphindi.

Umzobo 14. I-Pre-adder Constant Mode
a0

Mult0

isiphumo

coefsel0
ikofu
8.1.2. Irejista yokulibaziseka kweSystolic
Kwi-architecture ye-systolic, idatha yegalelo ifakwe kwi-cascade yeerejista ezisebenza njenge-buffer data. Irejista nganye inikezela ngegalelo sample kwisiphindaphindi apho siphinda-phinda nge-coefficient efanelekileyo. I-chain adder igcina iziphumo ezidityanisiweyo ngokuthe ngcembe ukusuka kwi-multiplier kunye nesiphumo esibhalisiweyo sangaphambili ukusuka kwi-chainin[] izibuko lokufaka ukwenza isiphumo sokugqibela. Isiqalelo ngasinye sophinda-phinda-phinda-phinda kufuneka sibambezeleke ngomjikelo omnye ukuze iziphumo zihambelane ngokufanelekileyo xa zidityaniswe kunye. Ulibaziso ngalunye olulandelelanayo lusetyenziselwa ukulungisa zombini i-coefficient memory kunye ne-data buffer yezinto zazo eziphindaphindayo-zokongeza. UmzekeloampLe, ulibaziseko olunye lwesibini lophinda-phindeneyo longeza isiqalelo, ulibaziseko olubini lwesithathu lophinda-phinda-dibanisa isiqalelo, njalo njalo.
Umzobo 15. Iirejista zeSystolic
Iirejista zeSystolic

x(t) c(0)

S -1

c(1)

S -1

c(2)

S -1

c(N-1)

S -1

S -1 y(t)

x(t) imele iziphumo ezisuka kuluhlu oluqhubekayo lwegalelo samples kunye no y(t)
imele isishwankathelo seseti yegalelo samples, kwaye ekuhambeni kwexesha, anda ngabo
i-coefficients ngokufanelekileyo. Zombini igalelo kunye nesiphumo iziphumo zihamba ukusuka ekhohlo ukuya ekunene. I-c(0) ukuya ku-c(N-1) ibonisa i-coefficients. Iirejista zokulibaziseka kwe-systolic zibonakaliswa yi-S-1, ngelixa i-1 imele ukulibaziseka kwewotshi enye. Iirejista zokulibaziseka kweSystolic zongezwa apha
amagalelo kunye neziphumo zokwenziwa kwemibhobho ngendlela eqinisekisa iziphumo ezivela kwi
i-multiplier operand kunye nezibalo eziqokelelweyo zihlala zihambelana. Le nto yokucubungula
iyaphindwa ukwenza isekethe ebala umsebenzi wokucoca. Lo msebenzi ngu
ibonakaliswe kule nxaki ilandelayo.

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 40

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8. Intel FPGA Yandisa iAdder IP Core 683490 | 2020.10.05

U-N umele inani lemijikelo yedatha engenileyo kwi-accumulator, u-y(t) umele imveliso ngexesha t, A(t) imele igalelo ngexesha t, kunye no-B(i) zii-coefficients. I-t kunye no-i kwi-equation zihambelana nethutyana elithile ngexesha, ukuze kubalwe imveliso s.ample y(t) ngexesha t, iqela legalelo sampukuncipha ku-N amanqaku ahlukeneyo ngexesha, okanye A(n), A(n-1), A(n-2), … A(n-N+1) iyafuneka. Iqela le-N igaleloampii-les ziphindaphindwa ngo-N coefficient kwaye zishwankathelwe kunye ukwenza isiphumo sokugqibela ngu-y.
Uyilo lwerejista ye-systolic ifumaneka kuphela kwi-sum-of-2 kunye ne-sum-of-4 iindlela. Kuzo zombini iindlela zoyilo lwerejista ye-systolic, umqondiso wokuqala we-chainin kufuneka ubotshwe ku-0.
Lo mfanekiso ulandelayo ubonisa ukuphunyezwa kwerejista yokulibaziseka kwe-systolic ye-2 yokuphindaphinda.
Umzobo 16. Irejista yokulibazisa iSystolic Ukuphunyezwa kwe-2 yokuphindaphinda
ikhonkco

Mult0

+/-

Mult1

+/-

isiphumo
Isimbuku sokuphindaphinda ezibini sibonakaliswa kule nxaki ilandelayo.
Lo mfanekiso ulandelayo ubonisa ukuphunyezwa kwerejista yokulibaziseka kwe-systolic ye-4 yokuphindaphinda.

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Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 41

8. Intel FPGA Yandisa iAdder IP Core 683490 | 2020.10.05

Umzobo 17. Irejista yokulibazisa iSystolic Ukuphunyezwa kwe-4 yokuphindaphinda
ikhonkco

Mult0

+/-

Mult1

+/-

Mult2

+/-

Mult3

+/-

isiphumo
Isimbuku seziphindaphinda ezine sichazwe kule nxaki ilandelayo. Umzobo 18. Isimbuku se-4 yokuphindaphinda
Oku kulandelayo kudwelisa i-advantagUkuphunyezwa kwerejista ye-systolic: · Ukunciphisa ukusetyenziswa kwezixhobo ze-DSP.

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 42

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8. Intel FPGA Yandisa iAdder IP Core 683490 | 2020.10.05

8.1.3. Ukulayisha kwangaphambili rhoqo
Ukulayisha kwangaphambili rhoqo kulawula i-accumulator operand kwaye izalisekisa ingxelo ye-accumulator. I-LOADCONST_VALUE esebenzayo ukusuka ku-0. Ixabiso elingaguqukiyo lilingana no-64N, apho N = LOADCONST_VALUE. Xa i LOADCONST_VALUE icwangciswe ku 2, ixabiso elingaguqukiyo lilingana no 64. Lo msebenzi ungasetyenziswa njengokurhangqa okucalanye.
Lo mzobo ulandelayo ubonisa ukuphunyezwa komthwalo wangaphambili.
Umzobo 19. Ukulayisha kwangaphambili rhoqo

Ingxelo ye-Accumulator

rhoqo

Mult0

+/-

Mult1

+/b1

isiphumo

accum_sload sload_accum

Jonga kwezi ngundoqo ze-IP zilandelayo zolunye umiliselo oluphindaphindayo: · ALTMULT_ACCUM · ALTMEMMULT · LPM_MULT
8.1.4. I-Accumulator ephindwe kabini
I-double accumulator feature yongeza irejista eyongezelelweyo kwindlela yempendulo ye-accumulator. Irejista ye-accumulator ephindwe kabini ilandela irejista yemveliso, ebandakanya iwotshi, iwashi ivumela, kunye ne-aclr. Irejista ye-accumulator eyongezelelweyo ibuyisela iziphumo kunye nokulibaziseka komjikelo omnye. Eli nqaku likuvumela ukuba ube namajelo amabini e-accumulator anenani elifanayo lobutyebi.
Lo mfanekiso ulandelayo ubonisa ukuphunyezwa kwe-accumulator kabini.

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 43

8. Intel FPGA Yandisa iAdder IP Core 683490 | 2020.10.05

Umzobo 20. I-Double Accumulator

Yenza iRejista ye-Accu ye-mulator

Accu mulator ingxelo ck

Mult0

+/-

Mult1

+/b1

Iziphumo zeRejista yeZiphumo

8.2. Verilog HDL Prototype
Ungafumana i-Intel FPGA yokuphindaphinda iAdder okanye ALTERA_MULT_ADD Verilog HDL prototype file (altera_mult_add_rtl.v) kwi iilayibrari zemegafunctions directory.
8.3. Isibhengezo seCandelo leVHDL
Isibhengezo secandelo le-VHDL sifumaneka kwi-altera_lnsim_components.vhd kwi iilayibrarivhdl altera_lnsim ulawulo.
8.4. VHDL LIBRARY_USE isiBhengezo
Isibhengezo se-VHDL LIBRARY-USE asiyomfuneko ukuba usebenzisa i-VHDL Component Declaration.
Ithala leencwadi litshintshile_mf; SEBENZISA ialtera_mf.altera_mf_components.all;

8.5. Iimpawu

Ezi theyibhile zilandelayo dwelisa igalelo kunye nemveliso iimpawu ze-Multiply Adder Intel FPGA IPor ALTERA_MULT_ADD IP core.

Itheyibhile 28. Phindaphinda iAdder Intel FPGA IPor ALTERA_MULT_ADD Iimpawu zoNgeniso

Umqondiso

Kufuneka

Inkcazo

idathaa_0[]/dataa_1[]/

Ewe

idathaa_2[]/dataa_3[]

Ungeniso lwedatha kwisiphindaphindi. Faka izibuko [NUMBER_OF_MULTIPLIERS * WIDTH_A – 1 … 0] ububanzi
iqhubekile...

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 44

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8. Intel FPGA Yandisa iAdder IP Core 683490 | 2020.10.05

Idathab_0[]/idathab_1[]/ idathab_2[]/idathab_3[] idathac_0[] /datac_1[]/ idathac_2[]/idatha_3[] iwotshi[1:0] aclr[1:0] sclr[1:0] ena [1:0] umqondiso
uphawu
scanina[] accum_sload

Kuyafuneka Ewe Hayi
Hayi Hayi Hayi Hayi Hayi
Hayi
Hayi hayi

Inkcazo
Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kule miqondiso. Xa unikezela ngexabiso le-X kule miqondiso, ixabiso le-X lisasazwa kwiimpawu zemveliso.
Ungeniso lwedatha kwisiphindaphindi. Isignali yongeniso [NUMBER_OF_MULTIPLIERS * WIDTH_B – 1 … 0] ububanzi Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kule miqondiso. Xa unikezela ngexabiso le-X kule miqondiso, ixabiso le-X lisasazwa kwiimpawu zemveliso.
Ungeniso lwedatha kwisiphindaphindi. Isignali yongeniso [NUMBER_OF_MULTIPLIERS * WIDTH_C – 1, … 0] banzi Khetha INPUT ye Khetha imo ye preadder iparameter ukwenza le miqondiso. Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kule miqondiso. Xa unikezela ngexabiso le-X kule miqondiso, ixabiso le-X lisasazwa kwiimpawu zemveliso.
I-Clock input port kwirejista ehambelanayo. Lo mqondiso unokusetyenziswa yiyo nayiphi na irejista kwi-IP core. Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kule miqondiso. Xa unikezela ngexabiso le-X kule miqondiso, ixabiso le-X lisasazwa kwiimpawu zemveliso.
Asynchronous igalelo elicacileyo kwirejista ehambelanayo. Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kule miqondiso. Xa unikezela ngexabiso le-X kule miqondiso, ixabiso le-X lisasazwa kwiimpawu zemveliso.
I-synchronous igalelo elicacileyo kwirejista ehambelanayo. Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga X kule miqondiso. Xa unikezela ngexabiso le-X kule miqondiso, ixabiso le-X lisasazwa kwiimpawu zemveliso
Yenza igalelo lomqondiso kwirejista ehambelanayo. Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kule miqondiso. Xa unikezela ngexabiso le-X kule miqondiso, ixabiso le-X lisasazwa kwiimpawu zemveliso.
Ixela inani lokumelwa kwegalelo lophinda-phindo A. Ukuba uphawu lophawu luphezulu, isiphindaphindi siphatha igalelo lesiphindaphindayo Umqondiso njengenombolo esayiniweyo. Ukuba isignali yomqondiso iphantsi, isiphindaphindi siphatha igalelo lesiphindaphindayo Umqondiso njengenombolo engasayinwanga. Khetha VARIABLE kuba Yeyiphi ifomathi yokubonisa yaMagalelo Aphindaphindayo iparamitha ukwenza olu phawu. Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kulo mqondiso. Xa unikezela ngexabiso le-X kweli galelo, ixabiso le-X lisasazwa kwiimpawu zemveliso.
Ixela inani lokumelwa kwegalelo lophindaphindi uphawu B. Ukuba umqondiso womqondiso uphezulu, isiphindaphindi siphatha isiphindaphindi segalelo elinguB njengenombolo ehambelana nesibini esayiniweyo. Ukuba umqondiso womqondiso uphantsi, isiphindaphindi siphatha isiphindaphindi segalelo lophawu B njengenani elingatyikitywanga. Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kulo mqondiso. Xa unikezela ngexabiso le-X kweli galelo, ixabiso le-X lisasazwa kwiimpawu zemveliso.
Igalelo letsheyini yokuskena A. Isignali yokufaka [WIDTH_A – 1, … 0] ububanzi. Xa INPUT_SOURCE_A iparameter inexabiso le SCANA, iscanina[] isignali iyafuneka.
Ixela ngamandla ukuba ixabiso le-accumulator lihlala lihleli. Ukuba isignali ye-accum_sload iphantsi, ngoko i-multiplier output ilayishwa kwi-accumulator. Musa ukusebenzisa i-accum_sload kunye ne-sload_accum ngaxeshanye.
iqhubekile...

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8. Intel FPGA Yandisa iAdder IP Core 683490 | 2020.10.05

Umqondiso sload_acum
chainin[] addnsub1
addnsub3
coefsel0[] coefsel1[] coefsel2[] coefsel3[]

iNombolo efunekayo
Hayi hayi
Hayi
Hayi Hayi Hayi Hayi

Inkcazo
Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kulo mqondiso. Xa unikezela ngexabiso le-X kweli galelo, ixabiso le-X lisasazwa kwiimpawu zemveliso.
Ixela ngamandla ukuba ixabiso le-accumulator lihlala lihleli. Ukuba isignali ye-sload_acum iphezulu, ngoko imveliso yophindaphinda ilayishwe kwi-accumulator. Musa ukusebenzisa i-accum_sload kunye ne-sload_accum ngaxeshanye. Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kulo mqondiso. Xa unikezela ngexabiso le-X kweli galelo, ixabiso le-X lisasazwa kwiimpawu zemveliso.
Ibhasi yegalelo lesiphumo seAdder ukusuka kwixesha elandulelayotage. Isiginali yongeniso [WIDTH_CHAININ – 1, … 0] ububanzi.
Yenza ukudibanisa okanye ukuthabatha kwiziphumo ukusuka kwiperi yokuqala yeziphindaphindi. Igalelo 1 kwisignali yokudibanisansub1 ukongeza iziphumo ezisuka kwiperi yokuqala yeziphindaphindi. Igalelo elingu-0 kwisignali ye-adnsub1 ukuthabatha iziphumo kwiperi yokuqala yabaphindaphindi. Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kulo mqondiso. Xa unikezela ngexabiso le-X kweli galelo, ixabiso le-X lisasazwa kwiimpawu zemveliso.
Yenza ukudibanisa okanye ukuthabatha kwiziphumo ukusuka kwiperi yokuqala yeziphindaphindi. Igalelo 1 kwisignali yokongezansub3 ukongeza iziphumo ezisuka kwisibini sesibini sabaphindi. Igalelo elingu-0 kwisignali ye-adnsub3 ukuthabatha iziphumo kwiperi yokuqala yabaphindaphindi. Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kulo mqondiso. Xa unikezela ngexabiso le-X kweli galelo, ixabiso le-X lisasazwa kwiimpawu zemveliso.
Umqondiso wegalelo elilinganayo[0:3] kwisiphindaphindi sokuqala. Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kulo mqondiso. Xa unikezela ngexabiso le-X kweli galelo, ixabiso le-X lisasazwa kwiimpawu zemveliso.
Umqondiso wegalelo elilinganayo[0:3] kwisiphindaphindi sesibini. Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kulo mqondiso. Xa unikezela ngexabiso le-X kweli galelo, ixabiso le-X lisasazwa kwiimpawu zemveliso.
Umqondiso wegalelo elilinganayo[0:3] ukuya kwisiphindaphindi sesithathu. Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kulo mqondiso. Xa unikezela ngexabiso le-X kweli galelo, ixabiso le-X lisasazwa kwiimpawu zemveliso.
Isiginali yegalelo elingumlinganiso [0:3] ukuya kwisiphindaphindi sesine. Imodeli yokulinganisa le IP ixhasa ixabiso legalelo elingamiselwanga (X) kulo mqondiso. Xa unikezela ngexabiso le-X kweli galelo, ixabiso le-X lisasazwa kwiimpawu zemveliso.

Itheyibhile 29. Phindaphinda i-Adder Intel FPGA IP Output Signals

Umqondiso

Kufuneka

Inkcazo

iziphumo []

Ewe

Isiginali yemveliso yokuphindaphinda. Umqondiso wemveliso [WIDTH_RESULT – 1 … 0] ububanzi

Imodeli yokulinganisa le IP ixhasa ixabiso lemveliso elingamiselwanga (X). Xa unikezela ngexabiso le-X njengegalelo, ixabiso le-X liyasasazwa kulo mqondiso.

scanouta []

Hayi

Imveliso yetsheyini yokuskena A. Umqondiso wemveliso [WIDTH_A – 1..0] ububanzi.

Khetha ngaphezu kwe-2 yamanani abaphindaphindi kwaye ukhethe igalelo lekhonkco lokuskena le Yintoni igalelo A lophindaphindo oluqhagamshelwe kwiparameter ukwenza olu phawu.

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 46

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8.6. Iiparameter

8.6.1. Ithebhu ngokubanzi

Uluhlu 30. IThebhu ngokubanzi

Ipharamitha

IP Eveliswe iParameter

Ixabiso

Lithini inani leziphindaphindi?

inani_le_m 1 – 4 ultipliers

Kufuneka ububanzi bebhasi ye-A bube ngakanani?

1 – 256

Kufuneka ububanzi B ububanzi_b iibhasi zokungenisa?

1 – 256

Kufuneka ibe banzi kangakanani ibhasi yemveliso 'yesiphumo'?

ububanzi_isiphumo

1 – 256

Yenza iwotshi enxulumeneyo yenza ukuba iwotshi nganye isebenze

gui_associate On d_clock_enable Cima e

8.6.2. Iindlela ezongezelelweyo Tab

Uluhlu 31. Iindlela ezongezelelweyo Ithebhu

Ipharamitha

IP Eveliswe iParameter

Ixabiso

Uqwalaselo Lweziphumo

Bhalisa imveliso yeyunithi yeentlanzi

gui_output_re Vula

igister

Cimile

Uthini umthombo wokufakwa kwewotshi?

gui_output_re gister_clock

Clock0 Clock1 Clock2

Uthini umthombo wegalelo elicacileyo elingavumelaniyo?

gui_output_re gister_aclr

AKUKHO ACLR0 ACLR1

Uthini umthombo wegalelo elicacileyo lolungelelwaniso?

gui_output_re gister_sclr

AKUKHO SCLR0 SCLR1

Ukusebenza kweAdder

Ngowuphi umsebenzi ekufuneka wenziwe kwiziphumo zesibini sokuqala sokuphindaphinda?

gui_multiplier 1_direction

YONGEZA, NGAPHANTSI, VARIABLE

Ixabiso eliMiselweyo 1
16

Inkcazo
Inani leziphindaphindi eziya kudityaniswa kunye. Amaxabiso yi-1 ukuya ku-4. Chaza ububanzi bedathaa[] port.

Chaza ububanzi bedatab[] izibuko.

Chaza ububanzi besiphumo[] izibuko.

Cimile

Khetha olu khetho ukwenza iwotshi isebenze

ngewotshi nganye.

Ixabiso eliMiselweyo

Inkcazo

Iwashi elivaliweyo0
NONE NONE

Khetha olu khetho ukwenza irejista yemveliso yemodyuli yeadder.
Khetha iClock0, iClock1 okanye iClock2 ukwenza kwaye ucacise umthombo wewotshi yeerejista zemveliso. Kufuneka ukhethe Bhalisa imveliso yeyunithi ye-adder ukwenza le parameter.
Ikhankanya umthombo ocacileyo ongahambelaniyo werejista yemveliso ye-adder. Kufuneka ukhethe Bhalisa imveliso yeyunithi ye-adder ukwenza le parameter.
Ichaza umthombo ocacileyo ohambelanayo werejista yemveliso ye-adder. Kufuneka ukhethe Bhalisa imveliso yeyunithi ye-adder ukwenza le parameter.

YONZA

Khetha umsebenzi wokudibanisa okanye wokuthabatha ukuze wenzele iziphumo phakathi kwesiphindaphindi sokuqala nesesibini.
· Khetha ADD ukwenza umsebenzi wokongeza.
· Khetha i-SUB ukwenza umsebenzi wokuthabatha.
· Khetha IVARIABLE ukusebenzisa i-adnsub1 port yolawulo lokudibanisa/lokuthabatha oluguquguqukayo.
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Ipharamitha

IP Eveliswe iParameter

Ixabiso

Bhalisa igalelo elithi 'adnsub1'

gui_addnsub_ Kwi-multiplier_reg Cima ister1

Uthini umthombo wokufakwa kwewotshi?

gui_addnsub_ multiplier_reg ister1_clock

Clock0 Clock1 Clock2

Uthini umthombo wegalelo elicacileyo elingavumelaniyo?

gui_addnsub_ multiplier_aclr 1

AKUKHO ACLR0 ACLR1

Uthini umthombo wegalelo elicacileyo lolungelelwaniso?

gui_addnsub_ multiplier_sclr 1

AKUKHO SCLR0 SCLR1

Ngowuphi umsebenzi ekufuneka wenziwe kwiziphumo zesibini sesibini sokuphindaphinda?

gui_multiplier 3_direction

YONGEZA, NGAPHANTSI, VARIABLE

Bhalisa igalelo elithi 'adnsub3'

gui_addnsub_ Kwi-multiplier_reg Cima ister3

Uthini umthombo wokufakwa kwewotshi?

gui_addnsub_ multiplier_reg ister3_clock

Clock0 Clock1 Clock2

Ixabiso eliMiselweyo
Iwashi elivaliweyo0 AKUKHO ONGEZIWEYO
Iwashi elivaliweyo0

Inkcazo
Xa ixabiso VARIABLE likhethiwe: · Qhuba umqondiso we-adnsub1 ukuya phezulu ukuze
umsebenzi wokongeza. · Qhuba umqondiso we-addnsub1 uye phantsi
umsebenzi wokuthabatha. Kufuneka ukhethe ngaphezulu kwesibini sokuphindaphinda ukwenza le parameter.
Khetha olu khetho ukwenza irejista yegalelo ye-adnsub1 izibuko. Kufuneka ukhethe UKUBALULEKILE kuMphi umsebenzi ekufuneka wenziwe kwiziphumo zesibini sokuqala sokuphindaphinda ukwenza le parameter.
Khetha Ikloko 0 , Ikloko1 okanye ikloko2 ukucacisa isignali yewotshi yegalelo kwirejista ye-adnsub1. Kufuneka ukhethe Bhalisa 'i-addnsub1' igalelo ukwenza le parameter.
Ikhankanya umthombo ocacileyo ongahambelaniyo werejista ye-adnsub1. Kufuneka ukhethe Bhalisa 'i-addnsub1' igalelo ukwenza le parameter.
Ikhankanya umthombo ocacileyo wolungelelwaniso lwerejista ye-adnsub1. Kufuneka ukhethe Bhalisa 'i-addnsub1' igalelo ukwenza le parameter.
Khetha umsebenzi wokudibanisa okanye wokuthabatha ukuze wenzele iziphumo phakathi kweziphindaphindi zesithathu nezesine. · Khetha ADD ukwenza udibaniso
ukusebenza. · Khetha i-SUB ukwenza ukuthabatha
ukusebenza. · Khetha IYAHLUKA ukusebenzisa i-adnsub1
izibuko lokudibanisa okuguquguqukayo/ulawulo lokuthabatha. Xa ixabiso le-VARIABLE likhethiwe: · Qhuba umqondiso we-adnsub1 ukuya phezulu ukuze usebenze. · Qhuba umqondiso we-addnsub1 uye ezantsi ukuze usebenze ngokuthabatha. Kufuneka ukhethe ixabiso 4 kuba Yintoni inani labaphindaphindi? ukwenza le parameter.
Khetha olu khetho ukwenza irejista yegalelo isebenze isiginali ye-adnsub3. Kufuneka ukhethe I-VARIABLE kuba Nguwuphi umsebenzi omawenziwe kwiziphumo zesibini sesibini sophindaphindo ukwenza le parameter.
Khetha iClock0, iClock1 okanye iClock2 ukucacisa isignali yewotshi yegalelo kwirejista ye-adnsub3. Kufuneka ukhethe Bhalisa 'addnsub3′ igalelo ukwenza le parameter.
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Ipharamitha
Uthini umthombo wegalelo elicacileyo elingavumelaniyo?

IP Eveliswe iParameter

Ixabiso

gui_addnsub_ multiplier_aclr 3

AKUKHO ACLR0 ACLR1

Uthini umthombo wegalelo elicacileyo lolungelelwaniso?

gui_addnsub_ multiplier_sclr 3

AKUKHO SCLR0 SCLR1

I-Polarity yenza `usetyenziso_oluncinci'

gui_use_subn Vula

yongeza

Cimile

8.6.3. Iziphindaphindi Tab

Itheyibhile 32. Ithebhu yokuphindaphinda

Ipharamitha

IP Eveliswe iParameter

Ixabiso

Yintoni i

gui_represent

ifomathi yomelo_a

kuZiphindaphindeko A amagalelo?

ISAYINWE, AYISAYINWA, IYAHLUKA

Bhalisa igalelo `lophawu'

gui_register_s Ivuliwe

igna

Cimile

Uthini umthombo wokufakwa kwewotshi?

gui_register_s igna_clock

Clock0 Clock1 Clock2

Uthini umthombo wegalelo elicacileyo elingavumelaniyo?

gui_register_s igna_aclr

AKUKHO ACLR0 ACLR1

Uthini umthombo wegalelo elicacileyo lolungelelwaniso?

gui_register_s igna_sclr

AKUKHO SCLR0 SCLR1

Yintoni i

gui_represent

ifomathi yomelo_b

ngamagalelo eZiphindaphinda B?

ISAYINWE, AYISAYINWA, IYAHLUKA

Bhalisa igalelo elithi `signb'

gui_register_s Ivuliwe

igb

Cimile

Ixabiso eliMiselweyo AYIKHO
AKUKHO

Inkcazo
Ikhankanya umthombo ocacileyo ongahambelaniyo werejista ye-adnsub3. Kufuneka ukhethe Bhalisa 'i-addnsub3' igalelo ukwenza le parameter.
Ikhankanya umthombo ocacileyo wolungelelwaniso werejista ye-adnsub3. Kufuneka ukhethe Bhalisa 'addnsub3′ igalelo ukwenza le parameter.

Cimile

Khetha olu khetho ukubuyisela umva umsebenzi

ye-addansub port port.

Qhuba i-adnsub ukuya phezulu ukuze usebenze ngokuthabatha.

Qhuba i-adnsub ukuya phantsi ukuze usebenze ukongeza.

Ixabiso eliMiselweyo

Inkcazo

UNGASAYINWA Cacisa ifomathi yomelo yesiphindaphindi igalelo A.

Cimile

Khetha olu khetho ukwenza umqondiso usebenze

bhalisa.

Kufuneka ukhethe ARIABLE ixabiso le Yintoni ifomathi yokumelwa kumanqaku aphindaphindayo A? iparameter ukwenza olu khetho.

Ikloko0

Khetha Ikloko 0 , Ikloko1 okanye ikloko 2 ukuze uvule kwaye uchaze isignali yewotshi yegalelo kwirejista yomqondiso.
Kufuneka ukhethe Bhalisa `uphawu' igalelo ukwenza le parameter.

AKUKHO

Ikhankanya umthombo ocacileyo ongahambelaniyo werejista yomqondiso.
Kufuneka ukhethe Bhalisa `uphawu' igalelo ukwenza le parameter.

AKUKHO

Ikhankanya umthombo ocacileyo wolungelelwaniso lwerejista yomqondiso.
Kufuneka ukhethe Bhalisa `uphawu' igalelo ukwenza le parameter.

ANGASAYINWA Cacisa ifomathi yomelo yegalelo le-multiplier B.

Cimile

Khetha olu khetho ukwenza signb isebenze

bhalisa.

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Ipharamitha

IP Eveliswe iParameter

Ixabiso

Ixabiso eliMiselweyo

Uthini umthombo wokufakwa kwewotshi?

gui_register_s ignb_clock

Clock0 Clock1 Clock2

Ikloko0

Uthini umthombo wegalelo elicacileyo elingavumelaniyo?

gui_register_s ignb_aclr

AKUKHO ACLR0 ACLR1

Uthini umthombo wegalelo elicacileyo lolungelelwaniso?

gui_register_s ignb_sclr

AKUKHO SCLR0 SCLR1

Uqwalaselo Lwegalelo
Bhalisa igalelo A lokuphindaphinda
Uthini umthombo wokufakwa kwewotshi?

gui_input_reg Vula

ister_a

Cimile

gui_input_reg ister_a_clock

Clock0 Clock1 Clock2

NONE NONE
Iwashi elivaliweyo0

Uthini umthombo wegalelo elicacileyo elingavumelaniyo?

gui_input_reg ister_a_aclr

AKUKHO ACLR0 ACLR1

Uthini umthombo wegalelo elicacileyo lolungelelwaniso?

gui_input_reg ister_a_sclr

AKUKHO SCLR0 SCLR1

Bhalisa igalelo B le-multiplier
Uthini umthombo wokufakwa kwewotshi?

gui_input_reg Vula

ister_b

Cimile

gui_input_reg ister_b_clock

Clock0 Clock1 Clock2

NONE NONE Off Clock0

Uthini umthombo wegalelo elicacileyo elingavumelaniyo?

gui_input_reg ister_b_aclr

AKUKHO ACLR0 ACLR1

AKUKHO

Uthini umthombo wegalelo elicacileyo lolungelelwaniso?

gui_input_reg ister_b_sclr

AKUKHO SCLR0 SCLR1

AKUKHO

Lithini igalelo A lesiphindaphindi esiqhagamshelwe kulo?

gui_multiplier Multiplier igalelo Multiplier

_igalelo

Ungeniso lwekhonkco lokuskena

Inkcazo
Kufuneka ukhethe i-VARIABLE ixabiso le Yintoni ifomathi yokumelwa kwamagalelo aManinzi B? iparameter ukwenza olu khetho.
Khetha Ikloko 0 , Ikloko1 okanye ikloko 2 ukuze uvule kwaye uchaze isignali yewotshi yegalelo kwirejista yophawu. Kufuneka ukhethe Bhalisa `uphawu lwegalelo' ukwenza le parameter isebenze.
Ikhankanya umthombo ocacileyo ongahambelaniyo werejista yophawu. Kufuneka ukhethe Bhalisa `uphawu lwegalelo' ukwenza le parameter isebenze.
Ikhankanya umthombo ocacileyo wolungelelwaniso lwerejista yophawu. Kufuneka ukhethe Bhalisa `uphawu lwegalelo' ukwenza le parameter isebenze.
Khetha olu khetho ukwenza irejista yengeniso yebhasi yongeniso lwedata.
Khetha iClock0, iClock1 okanye iClock2 ukunika amandla kunye nokuchaza isignali yekloko yobhaliso yekloko yedatha yebhasi. Kufuneka ukhethe Bhalisa igalelo A lesiphindaphindi ukuze usebenze le parameter.
Ikhankanya irejista yomthombo ocacileyo wedataa yokufakwa kwebhasi. Kufuneka ukhethe Bhalisa igalelo A lesiphindaphindi ukuze usebenze le parameter.
Ikhankanya umthombo ocacileyo werejista yedataa yokufakwa kwebhasi. Kufuneka ukhethe Bhalisa igalelo A lesiphindaphindi ukuze usebenze le parameter.
Khetha olu khetho ukwenza irejista yegalelo yedatab yongeniso lwebhasi.
Khetha iClock0, iClock1 okanye iClock2 ukunika amandla kunye nokuchaza isignali yekloko yobhaliso yekloko yedatab yokufakwa kwebhasi. Kufuneka ukhethe Bhalisa igalelo B le-multiplier ukwenza le parameter isebenze.
Ikhankanya irejista yomthombo ocacileyo wedatab yongeniso lwebhasi. Kufuneka ukhethe Bhalisa igalelo B le-multiplier ukwenza le parameter isebenze.
Ikhankanya umthombo ocacileyo werejista yedatab yongeniso lwebhasi. Kufuneka ukhethe Bhalisa igalelo B le-multiplier ukwenza le parameter isebenze.
Khetha umthombo wongeniso wegalelo A lophindaphindo.
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Ipharamitha

IP Eveliswe iParameter

Ixabiso

Scanout Uqwalaselo lweRejista

Bhalisa iziphumo zetsheyini yokuskena

gui_scanouta Vula

_bhalisa

Cimile

Uthini umthombo wokufakwa kwewotshi?

gui_scanouta _register_kloko k

Clock0 Clock1 Clock2

Uthini umthombo wegalelo elicacileyo elingavumelaniyo?

gui_scanouta _register_aclr

AKUKHO ACLR0 ACLR1

Uthini umthombo wegalelo elicacileyo lolungelelwaniso?

gui_scanouta _register_sclr

AKUKHO SCLR0 SCLR1

8.6.4. Preadder Tab

Uluhlu 33. Preadder Tab

Ipharamitha

IP Eveliswe iParameter

Ixabiso

Khetha imo yepreader

preadder_mo de

LULULE, I-COEF, IGALELO, ISIkwere, NGQONDO

Ixabiso eliMiselweyo

Inkcazo
Khetha igalelo laBaninzi ukusebenzisa ibhasi yokufakwa kwedatha njengomthombo wesiphindaphindi. Khetha Ungeniso lwekhonkco lokuskena ukusebenzisa ibhasi yokufaka i-scan njengomthombo wesiphindaphindi kwaye uvule ukuphuma kwebhasi yescanout. Le parameter iyafumaneka xa ukhetha 2, 3 okanye 4 kuba Yintoni inani labaphindaphindi? ipharamitha.

Iwashi elivaliweyo0 NONE NONE

Khetha olu khetho ukwenza irejista yemveliso yescanouta yebhasi yemveliso.
Kufuneka ukhethe igalelo lekhonkco lokuskena le Yintoni igalelo A lesiphindaphindi esiqhagamshelwe kulo? iparameter ukwenza olu khetho.
Khetha iClock0, iClock1 okanye iClock2 ukwenza kwaye uchaze isignali yewotshi yerejista yescanouta yebhasi ephumayo.
Kufuneka uvule Bhalisa isiphumo sekhonkco lokuskena iparameter ukwenza olu khetho.
Ikhankanya irejista yomthombo ocacileyo ongahambelaniyo webhasi yemveliso yescanouta.
Kufuneka uvule Bhalisa isiphumo sekhonkco lokuskena iparameter ukwenza olu khetho.
Ikhankanya irejista yomthombo ocacileyo wescanouta.
Kufuneka ukhethe Bhalisa imveliso yeparamitha yekhonkco lokuskena ukwenza olu khetho.

Ixabiso eliMiselweyo
LULU

Inkcazo
Ixela indlela yokusebenza yemodyuli yepreadder. LULULE: Le mowudi idlula kwipredider. Le yindlela emiselweyo. I-COEF: Le mowudi isebenzisa imveliso yepreadder kunye ne-coefsel input bus njengamagalelo kwi-multiplier. IINPUT: Le ndlela isebenzisa imveliso yepreadder kunye ne-datac input bus njengamagalelo kwi-multiplier. I-SQUARE: Le ndlela isebenzisa imveliso yepreadder njengamagalelo omabini kwisiphindaphindi.
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Ipharamitha

IP Eveliswe iParameter

Ixabiso

Khetha indlela yepread

gui_preadder ADD,

_umkhombandlela

I-SUB

Kufuneka zibe ububanzi bebhasi ye-C width_c?

1 – 256

Uqwalaselo lweRejista yeNgeniso yeDatha C

Bhalisa igalelo ledatha

gui_datac_inp Ivuliwe

ut_bhalisa

Cimile

Uthini umthombo wokufakwa kwewotshi?

gui_datac_inp ut_register_cl ock

Clock0 Clock1 Clock2

Uthini umthombo wegalelo elicacileyo elingavumelaniyo?

gui_datac_inp ut_register_a clr

AKUKHO ACLR0 ACLR1

Uthini umthombo wegalelo elicacileyo lolungelelwaniso?

gui_datac_inp ut_register_sc lr

AKUKHO SCLR0 SCLR1

Ii-Coefficients
Kufuneka ububanzi bekofu bube ngakanani?

wide_coef

1 – 27

Uqwalaselo lweRejista yeCoef

Bhalisa igalelo le-coefsel

gui_coef_regi Vula

ster

Cimile

Uthini umthombo wokufakwa kwewotshi?

gui_coef_regi ster_clock

Clock0 Clock1 Clock2

Ixabiso eliMiselweyo
YONZA
16

Inkcazo
I-CONSTANT: Le mowudi isebenzisa ibhasi yongeniso lwedatha ene-preadder edlulayo kunye ne-coefsel i-bus yokufakwayo njengamagalelo kwi-multiplier.
Ixela ukusebenza kwepredider. Ukwenza le parameter isebenze, khetha oku kulandelayo ukwenzela Khetha indlela yepreadder: · COEF · Igalelo · SQUARE okanye · CONSTANT
Ixela inani leebhithi zeC yebhasi yokufaka. Kufuneka ukhethe INPUT yokuKhetha imo yepreadder ukwenza le parameter.

NgeClock0 NONE NONE

Khetha olu khetho ukwenza irejista yegalelo yedatac ibhasi yongeniso. Kufuneka usete INPUT ukuKhetha imo ye preadder iparameter ukwenza olu khetho.
Khetha Ikloko 0 , Ikloko1 okanye ikloko 2 ukucacisa isignali yewotshi yegalelo kwirejista yokufakwa kwedatha. Kufuneka ukhethe Bhalisa igalelo ledatac ukwenza le parameter.
Ikhankanya umthombo ocacileyo ongahambelaniyo werejista yokufakwa kwedatha. Kufuneka ukhethe Bhalisa igalelo ledatac ukwenza le parameter.
Ikhankanya umthombo ocacileyo wongqamaniso werejista yokufaka idatac. Kufuneka ukhethe Bhalisa igalelo ledatac ukwenza le parameter.

Ixela inani lamasuntswana e

ibhasi yokufaka icoefsel.

Kufuneka ukhethe i-COEF okanye i-CONSTANT yemowudi yepreadder ukwenza le parameter.

KwiClock0

Khetha olu khetho ukwenza irejista yegalelo lebhasi yecoefsel isebenze. Kufuneka ukhethe i-COEF okanye i-CONSTANT yemowudi yepreader ukwenza le parameter isebenze.
Khetha Ikloko 0 , Ikloko1 okanye ikloko 2 ukucacisa isignali yewotshi yongeniso yerejista yokufakwa kwecoefsel. Kufuneka ukhethe Bhalisa igalelo le-coefsel ukwenza le parameter.
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Ipharamitha
Uthini umthombo wegalelo elicacileyo elingavumelaniyo?

IP Eveliswe iParameter

Ixabiso

gui_coef_regi ster_aclr

AKUKHO ACLR0 ACLR1

Yintoni umthombo wegalelo elicacileyo elihambelanayo

gui_coef_regi ster_sclr

AKUKHO SCLR0 SCLR1

Ulungelelwaniso_0

coef0_0 ukuya kwicoef0_7

0x00000 0xFFFFFF

Ulungelelwaniso_1

coef1_0 ukuya kwicoef1_7

0x00000 0xFFFFFF

Ulungelelwaniso_2

coef2_0 ukuya kwicoef2_7

0x00000 0xFFFFFF

Ulungelelwaniso_3

coef3_0 ukuya kwicoef3_7

0x00000 0xFFFFFF

8.6.5. Ithebhu ye-Accumulator

Uluhlu 34. Ithebhu ye-Accumulator

Ipharamitha

IP Eveliswe iParameter

Ixabiso

Yenza i-accumulator?

i-accumulator

EWE HAYI

Loluphi uhlobo lomsebenzi we-accumulator?

accum_directi ADD,

I-SUB

Ixabiso eliMiselweyo AYIKHO
AKUKHO
0x0000000 0
0x0000000 0
0x0000000 0
0x0000000 0

Inkcazo
Ikhankanya umthombo ocacileyo ongahambelaniyo werejista yegalelo le-coefsel. Kufuneka ukhethe Bhalisa igalelo le-coefsel ukwenza le parameter.
Ikhankanya umthombo ocacileyo wongqamaniso werejista yegalelo le-coefsel. Kufuneka ukhethe Bhalisa igalelo le-coefsel ukwenza le parameter.
Ixela amaxabiso e-coefficient yesi siphindaphindi sokuqala. Inani leebhithi kufuneka lilingane njengoko lichaziwe kububanzi bekofu kufuneka bube ngakanani? ipharamitha. Kufuneka ukhethe i-COEF okanye i-CONSTANT yemowudi yepreader ukwenza le parameter isebenze.
Ixela amaxabiso e-coefficient yesi siphindaphindi sesibini. Inani leebhithi kufuneka lilingane njengoko lichaziwe kububanzi bekofu kufuneka bube ngakanani? ipharamitha. Kufuneka ukhethe i-COEF okanye i-CONSTANT yemowudi yepreader ukwenza le parameter isebenze.
Ixela amaxabiso e-coefficient yesi siphindaphindi sesithathu. Inani leebhithi kufuneka lilingane njengoko kuchaziweyo Ububanzi bekofu kufuneka bube ngakanani? ipharamitha. Kufuneka ukhethe i-COEF okanye i-CONSTANT yemowudi yepreader ukwenza le parameter isebenze.
Ixela amaxabiso e-coefficient yesi siphindaphindi sesine. Inani leebhithi kufuneka lilingane njengoko kuchaziweyo Ububanzi bekofu kufuneka bube ngakanani? ipharamitha. Kufuneka ukhethe i-COEF okanye i-CONSTANT yemowudi yepreader ukwenza le parameter isebenze.

Ixabiso elimiselweyo NO
YONZA

Inkcazo
Khetha u-EWE ukwenza isiqokeleli sisebenze. Kufuneka ukhethe Bhalisa imveliso ye-adder xa usebenzisa i-accumulator feature.
Ikhankanya ukusebenza kwe-accumulator: · ADD kumsebenzi wokongeza · SUB ukwenzela umsebenzi wokuthabatha. Kufuneka ukhethe u-EWE ukuze uvule isiqokeleli? iparameter ukwenza olu khetho.
iqhubekile...

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 53

8. Intel FPGA Yandisa iAdder IP Core 683490 | 2020.10.05

Ipharamitha
Layisha kwangaphambili Ngokuqhubekayo Vula ukulayisha kwangaphambili rhoqo

IP Eveliswe iParameter

Ixabiso

gui_ena_prelo On

i-ad_const

Cimile

Yintoni igalelo lezibuko eliqokelelweyo eliqhagamshelwe kulo?

gui_accumula ACCUM_SLOAD, khetha_izibuko_khetha SLOAD_ACCUM

Khetha ixabiso lokulayisha kwangaphambili loadconst_val 0 - 64

rhoqo

Uthini umthombo wokufakwa kwewotshi?

gui_accum_sl oad_register_ iwotshi

Clock0 Clock1 Clock2

Uthini umthombo wegalelo elicacileyo elingavumelaniyo?

gui_accum_sl oad_register_ aclr

AKUKHO ACLR0 ACLR1

Uthini umthombo wegalelo elicacileyo lolungelelwaniso?

gui_accum_sl oad_register_ sclr

AKUKHO SCLR0 SCLR1

Yenza i-accumulator ephindwe kabini

gui_double_a Vula

ccm

Cimile

Ixabiso eliMiselweyo

Inkcazo

Cimile

Yenza i accum_sload okanye

sload_accum imiqondiso kunye nerejista yokufaka

Ukukhetha ngamandla igalelo kwi

i-accumulator.

Xa i-accum_sload iphantsi okanye i-sload_accum, imveliso yophindaphinda isondlo kwi-accumulator.

Xa i-accum_sload iphezulu okanye i-sload_accum, umsebenzisi ochaziweyo wokulayisha kwangaphambili rhoqo uyondla kwi-accumulator.

Kufuneka ukhethe u-EWE ukuze uvule isiqokeleli? iparameter ukwenza olu khetho.

ACCUM_SL OAD

Ixela indlela yokuziphatha kwe-accum_sload/ sload_accum isiginali.
ACCUM_SLOAD: Qhuba accum_sload low ukulayisha imveliso yophindaphindo kwi-accumulator.
SLOAD_ACCUM: Qhuba i-sload_accum phezulu ukuze ulayishe imveliso yophindaphinda kwi-accumulator.
Kufuneka ukhethe Yenza ukulayisha kwangaphambili ukhetho oluqhubekayo ukwenza le parameter.

Cacisa ixabiso elimiselweyo eliqhubekayo.

Eli xabiso linokuba ngu-2N apho i-N iyixabiso elicwangcisiweyo eliqhubekayo.

Xa i-N=64, imele i-zero engatshintshiyo.

Kufuneka ukhethe Yenza ukulayisha kwangaphambili ukhetho oluqhubekayo ukwenza le parameter.

Ikloko0

Khetha iClock0 , iClock1 okanye iClock2 ukucacisa isignali yewotshi yegalelo yerejista yekloko ye-accum_sload/sload_accum.
Kufuneka ukhethe Yenza ukulayisha kwangaphambili ukhetho oluqhubekayo ukwenza le parameter.

AKUKHO

Ikhankanya umthombo ocacileyo ongahambelaniyo werejista ye-accum_sload/sload_accum.
Kufuneka ukhethe Yenza ukulayisha kwangaphambili ukhetho oluqhubekayo ukwenza le parameter.

AKUKHO

Ikhankanya umthombo ocacileyo wolungelelwaniso lwerejista ye-accum_sload/sload_accum.
Kufuneka ukhethe Yenza ukulayisha kwangaphambili ukhetho oluqhubekayo ukwenza le parameter.

Cimile

Yenza irejista ye-accumulator ephindwe kabini.

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 54

Ukuzisa impendulo

8. Intel FPGA Yandisa iAdder IP Core 683490 | 2020.10.05

8.6.6. Ithebhu yeSystolic/Chainout

Itheyibhile 35. I-Systolic / Chainout Adder Tab

Iparameter Vumela i-chainout adder

IP Eveliswe iParameter

Ixabiso

chainout_yongeza EWE,

HAYI

Loluphi uhlobo lomsebenzi we-chainout adder?

chainout_yongeza i-ADD,

er_direction

I-SUB

Yenza `ukuchasa' igalelo le-chainout adder?

Port_negate

PORT_USED, PORT_UNUSED

Bhalisa igalelo elithi `chasa'? negate_regist er

AYIBHALISIWEYO, IXESHA0, IXESHA1, IXESHA2, IXESHA3

Uthini umthombo wegalelo elicacileyo elingavumelaniyo?

yala_aclr

AKUKHO ACLR0 ACLR1

Uthini umthombo wegalelo elicacileyo lolungelelwaniso?

negate_sclr

AKUKHO SCLR0 SCLR1

Ukulibaziseka kweSystolic
Yenza iirejista zokulibaziseka kwe-systolic

gui_systolic_d Vula

Elay

Cimile

Uthini umthombo wokufakwa kwewotshi?

gui_systolic_d IXESHA0,

elay_clock

IWASHI1,

Ixabiso eliMiselweyo
HAYI

Inkcazo
Khetha EWE ukwenza imodyuli yeadder yechainout.

YONZA

Ixela umsebenzi we-adder ye-chainout.
Kumsebenzi wokuthabatha, KUSAYINIWE kufuneka kukhethelwe ukuba Yintoni ifomathi yokubonakalisa igalelo laMagalelo amaninzi? kwaye Ithini ifomathi yokumelwa kwamagalelo aZiphindaphindayo B? kwi-Multipliers Tab.

PORT_UN ESETYENZISWAYO

Khetha PORT_USED ukunika amandla isignali yokuchasa.
Le parameter ayisebenzi xa i-chainout adder ivaliwe.

UNGABHALISI ERED

Ukuvumela irejista yongeniso yesignali yokuchasa igalelo kwaye ichaze isignali yewotshi yegalelo yerejista echasayo.
Khetha OKUNGABHALISIWEYO ukuba irejista yegalelo ayifunwa
Le parameter ayisebenzi xa ukhetha:
· HAYI ukwenzela ukuba uvule i-chainout adder okanye
· PORT_UNUSED for Vulela 'negate' igalelo lechainout adder? iparameter okanye

AKUKHO

Ikhankanya umthombo ocacileyo ongahambelaniyo werejista echasayo.
Le parameter ayisebenzi xa ukhetha:
· HAYI ukwenzela ukuba uvule i-chainout adder okanye
· PORT_UNUSED for Vulela 'negate' igalelo lechainout adder? iparameter okanye

AKUKHO

Ikhankanya umthombo ocacileyo ohambelanayo werejista echasayo.
Le parameter ayisebenzi xa ukhetha:
· HAYI ukwenzela ukuba uvule i-chainout adder okanye
· PORT_UNUSED for Vulela 'negate' igalelo lechainout adder? iparameter okanye

IWASHI evaliweyo0

Khetha olu khetho ukwenza indlela yesystolic. Le parameter iyafumaneka xa ukhetha u-2, okanye u-4 kuba Leliphi inani labaphindaphindi? ipharamitha. Kufuneka wenze iRejista yemveliso yeyunithi ye-adder ukusebenzisa iirejista zokulibaziseka kwe-systolic.
Ixela igalelo lophawu lwewotshi yerejista yokulibaziseka kwesystolic.
iqhubekile...

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 55

8. Intel FPGA Yandisa iAdder IP Core 683490 | 2020.10.05

Ipharamitha

IP Eveliswe iParameter

Ixabiso

IWASHI2,

Uthini umthombo wegalelo elicacileyo elingavumelaniyo?

gui_systolic_d elay_aclr

AKUKHO ACLR0 ACLR1

Uthini umthombo wegalelo elicacileyo lolungelelwaniso?

gui_systolic_d elay_sclr

AKUKHO SCLR0 SCLR1

Ixabiso eliMiselweyo
AKUKHO
AKUKHO

Inkcazo
Kufuneka ukhethe ukwenza iirejista zokulibaziseka kwesystolic ukwenza olu khetho.
Ikhankanya umthombo ocacileyo ongahambelaniyo werejista yokulibaziseka kwesystolic. Kufuneka ukhethe ukwenza iirejista zokulibaziseka kwesystolic ukwenza olu khetho.
Ikhankanya umthombo ocacileyo wolungelelwaniso werejista yokulibaziseka kwesystolic. Kufuneka ukhethe ukwenza iirejista zokulibaziseka kwesystolic ukwenza olu khetho.

8.6.7. Ithebhu yePipelining

Itheyibhile 36. Ithebhu yokuBopha

Uqwalaselo loMbhobho weParameter

IP Eveliswe iParameter

Ixabiso

Ngaba uyafuna ukongeza irejista yombhobho kwigalelo?

gui_pipelining Hayi, Ewe

Ixabiso eliMiselweyo
Hayi

Nceda ucacise i

ukubambezeleka

inani lewotshi yokulinda

imijikelo

Naliphi na ixabiso elikhulu kuno-0

Uthini umthombo wokufakwa kwewotshi?

gui_input_late ncy_clock

IWASHI0, IXESHA1, IXESHA2

Uthini umthombo wegalelo elicacileyo elingavumelaniyo?

gui_input_late ncy_aclr

AKUKHO ACLR0 ACLR1

Uthini umthombo wegalelo elicacileyo lolungelelwaniso?

gui_input_late ncy_sclr

AKUKHO SCLR0 SCLR1

WOSHI0 NONE NONE

Inkcazo
Khetha Ewe ukwenza inqanaba elongezelelweyo lerejista yombhobho kwiisiginali zongeniso. Kufuneka uchaze ixabiso elikhulu kuno 0 ngokuba Nceda ucacise inani leeparamitha zewotshi yokulinda.
Ixela ixesha elifunekayo kumjikelo wewotshi. Inqanaba elinye lerejista yombhobho = 1 latency kumjikelo wewotshi. Kufuneka ukhethe u-EWE ukwenzela Ngaba uyafuna ukongeza irejista yombhobho kwigalelo? ukwenza olu khetho.
Khetha iClock0, iClock1 okanye iClock2 ukunika amandla kunye nokucacisa isignali yewotshi yerejista yombhobho. Kufuneka ukhethe u-EWE ukwenzela Ngaba uyafuna ukongeza irejista yombhobho kwigalelo? ukwenza olu khetho.
Ikhankanya irejista yomthombo ocacileyo werejista eyongezelelweyo yombhobho. Kufuneka ukhethe u-EWE ukwenzela Ngaba uyafuna ukongeza irejista yombhobho kwigalelo? ukwenza olu khetho.
Ichaza umthombo ocacileyo werejista yerejista yombhobho eyongezelelweyo. Kufuneka ukhethe u-EWE ukwenzela Ngaba uyafuna ukongeza irejista yombhobho kwigalelo? ukwenza olu khetho.

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 56

Ukuzisa impendulo

683490 | 2020.10.05 Thumela iNgxelo

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core

Ingqalelo:

I-Intel iyisusile inkxaso yale IP kwi-Intel Quartus Prime Pro Edition version 20.3. Ukuba undoqo we-IP kuyilo lwakho lujolise kwizixhobo kwi-Intel Quartus Prime Pro Edition, unokutshintsha i-IP nge-LPM_MULT Intel FPGA IP okanye uphinde uvelise i-IP kwaye uqokelele uyilo lwakho usebenzisa isoftware ye-Intel Quartus Prime Standard Edition.

Undoqo we-ALTMEMMULT IP usetyenziselwa ukudala ukuphindaphinda okusekwe kwimemori usebenzisa iibhloko zememori ze-onchip ezifumaneka kwi-Intel FPGAs (kunye ne-M512, M4K, M9K, kunye neebhloko zememori ze-MLAB). Lo ngundoqo we-IP uluncedo ukuba awunazixhobo ezaneleyo zokuphumeza iziphinda-phindo kwizinto zengqiqo (LEs) okanye oovimba abazinikeleyo abaphindaphindayo.
I-ALTMEMMULT IP core ngumsebenzi ohambelanayo ofuna iwotshi. Undoqo we-ALTMEMMULT IP usebenzisa umphindi kunye neyona nto incinci yokudlula kunye ne-latency enokwenzeka kwiseti enikeziweyo yeeparitha kunye neenkcukacha.
Lo mzobo ulandelayo ubonisa izibuko ze-ALTMEMMULT IP engundoqo.

Umzobo 21. I-ALTMEMMULT Ports

ALTMEMMULT

idatha_kwi[] sload_data coeff_in[]

isiphumo[] isiphumo_umthwalo osebenzayo_wenziwe

sload_coeff

iwotshi yesclr
inst

Iinkcukacha Eziyeleleneyo kwiphepha lama-71

9.1. Iimpawu
Undoqo we-ALTMEMMULT IP unika ezi mpawu zilandelayo: · Yenza kuphela iziphindaphindi ezisekwe kwinkumbulo usebenzisa iibhloko zememori ezikwi-chip ezifunyenwe
I-Intel FPGAs · Ixhasa ububanzi bedatha yeebhithi eziyi-1 · Ixhasa ifomati yokumelwa kwedatha esayiniweyo nengatyikitywanga.

ISO 9001:2015 ibhalisiwe

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05
· Igcina ii-multiples constants kwimemori yofikelelo olungakhethiyo (RAM)
· Inika ukhetho lokukhetha uhlobo lwebhloko ye-RAM
· Ixhasa i-synchronous ekhethiweyo ecacileyo kunye ne-load-control input port
9.2. Verilog HDL Prototype
Le prototype ilandelayo yeVerilog HDL ibekwe kuyilo lweVerilog File (.v) altera_mf.v kwi Uluhlu lwe-eda lwe-synthesis.
imodyuli altmemmult #( iparamitha coeff_representation = “ISAYINISIWE”, iparameter coefficient0 = “AKUSETYENZISWA”, parameter data_representation = “SIGNED”, iparameter target_device_family = “engasetyenziswanga”, iparameter max_clock_cycles_per_result = 1, iparameter inombolo_ye_TO_isiphumo = 1, iparameter inombolo_ye_TO_isixhobo = 1, ipharamitha iparamitha_inombolo_yesithintelo total_latency = 1, iparameter width_c = 1, iparameter width_d = 1, iparameter width_r = 1, iparameter width_s = 1, iparameter lpm_type = "altmemmult", ipharamitha lpm_hint = "engasetyenziswanga") ( ikloko yocingo lokufaka, ucingo lokufaka [ububanzi_c-0: 1]i-coeff_in, i-input wire [width_d-0:1] data_in, i-output wire load_done, i-output wire [ububanzi_r-0:1] isiphumo, i-output wire result_valid, i-input wire sclr, i-input wire [width_s-0:1] sel, input ucingo sload_coeff, igalelo wire sload_data)/* synthesis syn_black_box=XNUMX */; endmodule
9.3. Isibhengezo seCandelo leVHDL
Isibhengezo secandelo leVHDL sikwi-VHDL Design File (.vhd) altera_mf_components.vhd kwi librariesvhdlaltera_mf ulawulo.
component altmemmult generic ( coeff_representation: umtya := “SIGNED”; coefficient0:string := “UNUSED”; data_representation:string := “SIGNED”; purpose_device_family: umtya := “engasetyenziswanga”; max_clock_cycles_per_result:_results_per_result: := 1; ram_block_type := “AUTO”; ububanzi_c:indalo; "altmemmult"); izibuko ( iwotshi: in std_logic; coeff_in: in std_logic_vector (width_c-1 downto 1) := (abanye => '1'); idatha_in:in std_logic_vector(width_d-0 downto 0);

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 58

Ukuzisa impendulo

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

load_wenziwe: ngaphandle std_logic; iziphumo: ngaphandle std_logic_vector(width_r-1 downto 0); result_valid:out std_logic; sclr:in std_logic := '0'; sel:in std_logic_vector(width_s-1 downto 0) := (abanye => '0'); sload_coeff:in std_logic := '0'; sload_data:in std_logic := '0'); isiphelo secandelo;

9.4. Amazibuko

Ezi theyibhile zilandelayo dwelisa igalelo kunye nemveliso yezibuko ze-ALTMEMMULT IP engundoqo.

Itheyibhile 37. I-ALTMEMMULT ye-Input Ports

Igama lePort

Kufuneka

Inkcazo

iwotshi

Ewe

Ungeniso lwewotshi kwisiphindaphindi.

coeff_in[]

Hayi

I-coefficient port port ye-multiplier. Ubungakanani bezibuko longeniso luxhomekeke kwixabiso lepharamitha WIDTH_C.

idatha_kwi[]

Ewe

I-port yedata kwi-multiplier. Ubungakanani bezibuko longeniso luxhomekeke kwixabiso lepharamitha WIDTH_D.

sclr

Hayi

Igalelo elicacileyo longqamaniso. Ukuba ayisetyenziswanga, ixabiso elimiselweyo liyasebenza phezulu.

thengisa[]

Hayi

Ukukhetha i-coefficient esisigxina. Ubungakanani bezibuko longeniso luxhomekeke kwi WIDTH_S

ixabiso lepharamitha.

sload_coeff

Hayi

Izibuko longeniso lomlinganiso olungelelanisiweyo. Ibuyisela ixabiso langoku elikhethiweyo le-coefficient yangoku ngexabiso elichazwe kwi-coeff_in input.

idatha_yesilayidi

Hayi

Izibuko lokufaka idatha yomthwalo ohambelanayo. Umqondiso ochaza uphinda-phindo olutsha kwaye ucima naluphi na uphinda-phindo olukhoyo. Ukuba i-MAX_CLOCK_CYCLES_PER_RESULT iparamitha inexabiso elingu-1, i-port ye-sload_data ayinakwaho.

Uluhlu 38. I-ALTMEMMULT iZibuko zokuPhuma

Igama lePort

Kufuneka

Inkcazo

iziphumo[]

Ewe

Izibuko lemveliso yokuphindaphinda. Ubungakanani bezibuko longeniso luxhomekeke kwixabiso lepharamitha WIDTH_R.

isiphumo_siyasebenza

Ewe

Ibonisa xa isiphumo sisisiphumo esisebenzayo sophindaphindo olupheleleyo. Ukuba i-MAX_CLOCK_CYCLES_PER_RESULT iparamitha inexabiso elingu-1, i- result_valid output port ayisetyenziswa.

load_yenziwe

Hayi

Ibonisa xa i-coefficient entsha igqibile ukulayisha. I-load_done signal iqinisekisa xa i-coefficient entsha igqibile ukulayisha. Ngaphandle kokuba isignali ye-load_done iphezulu, akukho xabiso le-coefficient lingalayishwa kwimemori.

9.5. Iiparameter

Le theyibhile ilandelayo idwelisa iiparamitha ze-ALTMEMMULT IP core.

Uluhlu loku-39.
WIDTH_D WIDTH_C

Iiparamitha ze-ALTMEMMULT
Igama leParameter

Uhlobo olufunekayo

Inkcazo

Inani elipheleleyo Ewe

Ixela ububanzi bedatha_kwi[] izibuko.

Inani elipheleleyo Ewe

Ixela ububanzi be-coeff_in[] izibuko. iqhubekile...

Ukuzisa impendulo

Intel FPGA Integer Arithmetic IP Cores Isikhokelo somsebenzisi 59

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

Igama leParameter WIDTH_R WIDTH

Amaxwebhu / Izibonelelo

Intel FPGA Integer Arithmetic IP Cores [pdf] Isikhokelo somsebenzisi
FPGA Integer Arithmetic IP Cores, Integer Arithmetic IP Cores, Arithmetic IP Cores, IP Cores

Iimbekiselo

Incwadi yokusebenzisa

FPGA Integer Arithmetic IP Cores

Amaxwebhu / Izibonelelo

Iimbekiselo

Shiya uluvo

Rhoxisa impendulo