F Tile Serial Lite IV Intel FPGA IP User Guide

Imixholo fihla

1 F Tile Uthotho Lite IV Intel FPGA IP

2 Amaxwebhu / Izibonelelo

2.1 Iimbekiselo

3 Izithuba eziyeleleneyo

F Tile Uthotho Lite IV Intel FPGA IP

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F-Tile Serial Lite IV Intel® FPGA IP User Guide
Ihlaziywe kwi-Intel® Quartus® Prime Design Suite: 22.1 IP Version: 5.0.0

Online Version Thumela Impendulo

UG-20324

ID: 683074 Inguqulelo: 2022.04.28

Imixholo
Imixholo
1. Malunga neF-Tile Serial Lite IV Intel® FPGA IP User Guide………………………………………….. 4
2. F-Tile Uthotho Lite IV Intel FPGA IP Overview………………………………………………………………. 6 2.1. IiNkcukacha ngoNcedo………………………………………………………………………………..7 2.2. Iimpawu ezixhaswayo…………………………………………………………………………………….. 7 2.3. INqanaba leNkxaso yeNguqulelo ye-IP……………………………………………………………………………..8 2.4. iDevice Speed Grade Support…………………………………………………………………………..8 2.5. UkuSetyenziswa kweZibonelelo kunye neLatency………………………………………………………………………… I-Bandwidth Efficiency……………………………………………………………………………………. 9
3. Ukuqalisa………………………………………………………………………………………………. 11 3.1. Ukufakela kunye nokukhutshwa kweLayisenisi ye-Intel FPGA IP Cores…………………………………………………………… Imowudi yoVavanyo lwe-IP ye-Intel FPGA……………………………………………………………. 11 3.1.1. Ukucacisa i-IP Parameters and Options ……………………………………………………………………………… Yenziwe File Ubume……………………………………………………………………………………………………… Ukulinganisa i-Intel FPGA IP Cores………………………………………………………………………………… Ukulinganisa kunye nokuQinisekisa uYilo…………………………………………………….. 14 3.4. Ukudityaniswa kwee-IP Cores kwezinye iziXhobo ze-EDA…………………………………………………………. 16 3.4.1. Ukuqulunqa uYilo olupheleleyo…………………………………………………………………………..17
4. INkcazelo yoMsebenzi…………………………………………………………………………………….. 19 4.1. I-TX Datapath……………………………………………………………………………………..20 4.1.1. Iadaptha ye-TX MAC………………………………………………………………………….. 21 4.1.2. Ukufakwa kwegama eliLawulayo (CW) ………………………………………………………………………… 23 4.1.3. I-TX CRC…………………………………………………………………………………………28 4.1.4. I-TX MII Encoder…………………………………………………………………………….29 4.1.5. I-TX PCS kunye ne-PMA………………………………………………………………………….. 30 4.2. I-RX Datapath……………………………………………………………………………………………. 30 4.2.1. RX PCS kunye ne-PMA………………………………………………………………………….. 31 4.2.2. Idekhowuda ye-RX MII………………………………………………………………………………………………………… RX CRC………………………………………………………………………………….. 31 4.2.3. RX Deskew………………………………………………………………………………….31 4.2.4. Ukususwa kwe-RX CW…………………………………………………………………………………32 4.2.5. F-Tile Serial Lite IV Intel FPGA IP Clock Architecture……………………………………………. 35 4.3. Ukuseta ngokutsha kunye nokuQalisa uQhagamshelwano………………………………………………………………………..36 4.4. TX Ukuseta ngokutsha kunye nokuQalisa ulandelelwano……………………………………………………. 37 4.4.1. Ukuseta ngokutsha i-RX kunye nolandelelwano lokuQalisa……………………………………………………. 38 4.4.2. Ireyithi yoQhagamshelwano kunye neBandwidth efficient Ukubala ………………………………………………….. 39
5. Iiparamitha……………………………………………………………………………………………………. 42
6. F-Tile Series Lite IV Intel FPGA IP Interface Signals…………………………………………….. 44 6.1. Iimpawu zeewotshi……………………………………………………………………………………….44 6.2. Hlela kwakhona iiSayini…………………………………………………………………………………………………… Iimpawu ze-MAC……………………………………………………………………………………….. 44 6.3. Iimpawu zoLungiselelo lweTransceiver…………………………………………………………………… 45 6.4. Iimpawu ze-PMA……………………………………………………………………………………….. 48

I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 2

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7. Ukuyila nge-F-Tile Serial Lite IV Intel FPGA IP……………………………………………………… 51 7.1. Seta ngokutsha iziKhokelo………………………………………………………………………………….. 51 7.2. Izikhokelo zokuphatha iimpazamo…………………………………………………………………………..51
8. I-F-Tile Serial Lite IV Intel FPGA IP IsiKhokelo soMsebenzisi ooVimba ……………………………………………. 52 9. Imbali yoHlaziyo loXwebhu lwe-F-Tile Series Lite IV Intel FPGA IP User Guide ………53

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I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 3

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1. Malunga neF-Tile Serial Lite IV Intel® FPGA IP User Guide

Olu xwebhu luchaza iimpawu ze-IP, inkcazo yezakhiwo, amanyathelo okuvelisa, kunye nezikhokelo zokuyila i-F-Tile Serial Lite IV Intel® FPGA IP usebenzisa i-F-tile transceivers kwi-Intel Agilex TM izixhobo.

Abaphulaphuli ekujoliswe kubo

Olu xwebhu lulungiselelwe aba basebenzisi balandelayo:
· Yila abayili bezakhiwo ukwenza ukhetho lwe-IP ngexesha lenqanaba loyilo loyilo lwenqanaba lenkqubo
· Abayili bezixhobo zokusebenza xa bedibanisa i-IP kuyilo lwenqanaba lenkqubo yabo
· Iinjineli zokuqinisekisa ngexesha lenqanaba lenkqubo yokulinganisa kunye nezigaba zokuqinisekiswa kwehardware

Amaxwebhu anxulumeneyo

Le theyibhile ilandelayo idwelisa amanye amaxwebhu ereferensi anxulumene ne-F-Tile Serial Lite IV Intel FPGA IP.

Uluhlu loku-1.

Amaxwebhu anxulumeneyo

Isalathiso

F-Tile Serial Lite IV Intel FPGA IP Design Example Isikhokelo somsebenzisi

Iphepha leDatha leSixhobo se-Intel Agilex

Inkcazo
Olu xwebhu lubonelela ngesizukulwana, izikhokelo zokusetyenziswa, kunye nenkcazo esebenzayo ye-F-Tile Serial Lite IV Intel FPGA IP yoyilo exampLes kwizixhobo ze-Intel Agilex.
Olu xwebhu luchaza iimpawu zombane, iimpawu zokutshintsha, iinkcukacha zokucwangciswa, kunye nexesha lezixhobo ze-Intel Agilex.

Uluhlu loku-2.
I-CW RS-FEC PMA TX RX PAM4 NRZ

Akhronimi kunye noLuhlu lweeNkcukacha zeNkcazo
Isifinyezo

Ulawulo Lolwandiso lwe-Word Reed-Solomon Phambili Imposiso ULungiso loMzimba oluPhakathi oluNxulutywayo oluNxulumanisa isamkeli sePulse-Amplitude Modulation 4-Inqanaba lokungabuyi-ku-zero

iqhubekile...

Intel Corporation. Onke Amalungelo Agciniwe. I-Intel, ilogo ye-Intel, kunye nezinye iimpawu ze-Intel ziimpawu zorhwebo ze-Intel Corporation okanye iinkampani eziphantsi kwayo. I-Intel iqinisekisa ukusebenza kweFPGA yayo kunye neemveliso zesemiconductor kwiinkcukacha zangoku ngokuhambelana newaranti esemgangathweni ye-Intel, kodwa inelungelo lokwenza utshintsho kuzo naziphi na iimveliso kunye neenkonzo nangaliphi na ixesha ngaphandle kwesaziso. I-Intel ayithathi xanduva okanye ityala elivela kwisicelo okanye ukusetyenziswa kwalo naluphi na ulwazi, imveliso, okanye inkonzo echazwe apha ngaphandle kokuba kuvunyelwene ngokubhaliweyo yi-Intel. Abathengi be-Intel bayacetyiswa ukuba bafumane inguqulelo yamva nje yeenkcazo zesixhobo ngaphambi kokuba baxhomekeke kulo naluphi na ulwazi olupapashiweyo naphambi kokubeka iiodolo zeemveliso okanye iinkonzo. *Amanye amagama kunye neempawu zingabangwa njengempahla yabanye.

ISO 9001:2015 ibhalisiwe

1. Malunga neF-Tile Serial Lite IV Intel® FPGA IP User Guide 683074 | 2022.04.28

I-PCS MII XGMII

Isifinyezo

Ukwandiswa kweKhowudi yoMzimba iSudlaya yeMedia esiZimeleyo isiNxulumano esiZimeleyo 10 Gigabit Media isiNxulumano esiZimeleyo

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I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 5

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2. F-Tile Uthotho Lite IV Intel FPGA IP Overview

Umzobo 1.

I-F-Tile Serial Lite IV Intel FPGA IP ilungele unxibelelwano lwedatha ephezulu ye-chip-to-chip, ibhodi ukuya kwibhodi, kunye nezicelo ze-backplane.

I-F-Tile Serial Lite IV Intel FPGA IP idibanisa ulawulo lokufikelela kwimidiya (MAC), i-sublayer yekhowudi yomzimba (i-PCS), kunye neebhloko ze-attachment media (PMA). I-IP isekela isantya sokudlulisa idatha ukuya kwi-56 Gbps ngomzila kunye nobuninzi beendlela ezine ze-PAM4 okanye i-28 Gbps ngomzila kunye nobuninzi beendlela ze-16 ze-NRZ. Le IP inikezela nge-bandwidth ephezulu, iifreyimu ezisezantsi ezisezantsi, ukubala kwe-I / O ephantsi, kwaye ixhasa ukulinganisa okuphezulu kwiinombolo zombini kunye nesantya. Le IP iphinda ihlengahlengiswe ngokulula kunye nenkxaso yoluhlu olubanzi lweereyithi zedatha kunye nemodi ye-Ethernet PCS ye-F-tile transceiver.

Le IP ixhasa iindlela ezimbini zothumelo:
· Imowudi esisiseko-Le yimowudi yokusasaza esulungekileyo apho idatha ithunyelwa ngaphandle kwepakethi yokuqala, umjikelo ongenanto, kunye nokuphela kwepakethi ukunyusa i-bandwidth. I-IP ithatha idatha yokuqala esebenzayo njengesiqalo sokugqabhuka.
· Imo egcweleyo–Le yimowudi yokudlulisa ipakethi. Kule ndlela, i-IP ithumela ukuqhuma kunye nomjikelezo wokuvumelanisa ekuqaleni nasekupheleni kwepakethi njenge-delimiters.

F-Tile Serial Lite IV High Level Block Diagram

I-Avalon Streaming Interface TX

F-Tile Uthotho Lite IV Intel FPGA IP
I-MAC TX
TX USRIF_CTRL

64*n imizila bits (NRZ mode)/ 2*n imizila bits (imo yePAM4)

TX MAC

Iadaptha FAKA

MII ENCODE

I-PCS eyenzekileyo

TX PCS

TX MII

EMIB ENCODE SCRAMBLER FEC

TX PMA

IiBits zeeNdlela zeNdlela (imo yePAM4)/ n IiBits zeeNdlela (imo ye-NRZ)
TX Uthotho lweNdibaniselwano

I-Avalon Streaming Interface RX
64*n imizila bits (NRZ mode)/ 2*n imizila bits (imo yePAM4)

RX PCS

CW RMV

IDESKEW

MII

& LULUNGISA IKHOWUDI

RX MII

I-EMIB

I-DECODE BLOCK SYNC & FEC DESCRAMBLER

RX PMA

CSR

Amasuntswana eeNdlela ze-2n (imo ye-PAM4)/ n Amasuntswana eeNdlela (imowudi ye-NRZ) Ujongano lweRX Uthotho
I-Avalon Memory-Mapped Interface Register Config

Intsomi

Ingqiqo ethambileyo

Ingqiqo enzima

ISO 9001:2015 ibhalisiwe

2. F-Tile Uthotho Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

Uyakwazi ukuvelisa i-F-Tile Serial Lite IV Intel FPGA IP yoyilo exampLes ukufunda ngakumbi malunga neempawu ze-IP. Jonga kwi-F-Tile Serial Lite IV Intel FPGA IP Design Example Isikhokelo somsebenzisi.
Ulwazi oluyeleleneyo · Ingcaciso eSebenzayo kwiphepha 19 · F-Tile uthotho Lite IV Intel FPGA IP Design Example Isikhokelo somsebenzisi

2.1. NONE

Iinguqulelo ze-Intel FPGA IP zihambelana ne-Intel Quartus® Prime Design Suite iinguqulelo zesoftware de kube v19.1. Ukuqala kwi-Intel Quartus Prime Design Suite software version 19.2, i-Intel FPGA IP ineskimu esitsha soguqulelo.

Inombolo ye-Intel FPGA IP (XYZ) inokutshintsha ngoguqulelo ngalunye lwe-Intel Quartus Prime software. Utshintsho kwi:

· X ibonisa uhlaziyo olukhulu lwe IP. Ukuba uhlaziya i-Intel Quartus Prime software, kufuneka uhlaziye i-IP.
· I-Y ibonisa i-IP ibandakanya izinto ezintsha. Hlaziya i-IP yakho ukuze ibandakanye ezi mpawu zintsha.
· U-Z ubonisa ukuba i-IP ibandakanya utshintsho olungephi. Hlaziya i-IP yakho ukubandakanya olu tshintsho.

Uluhlu loku-3.

F-Tile Uthotho Lite IV Intel FPGA IP Ukukhutshwa Ulwazi

Into ye-IP Version ye-Intel Quartus Prime Version yokuKhupha iKhowudi yoku-odola yoMhla

5.0.0 22.1 2022.04.28 IP-SLITE4F

Inkcazo

2.2. Iimpawu ezixhaswayo
Le theyibhile ilandelayo idwelisa iimpawu ezikhoyo kwi-F-Tile Serial Lite IV Intel FPGA IP:

Ukuzisa impendulo

I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 7

2. F-Tile Uthotho Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

Uluhlu loku-4.

F-Tile Uthotho Lite IV Intel FPGA IP Iimpawu

Uphawu

Inkcazo

Ukugqithiselwa kwedatha

· Kwimowudi yePAM4:
- I-FHT isekela kuphela i-56.1, i-58, kunye ne-116 Gbps ngomzila kunye nobuninzi beendlela ze-4.
- I-FGT ixhasa ukuya kuthi ga kwi-58 Gbps kwilayini nganye enobuninzi beendlela ezili-12.
Jonga kwiThebhile 18 kwiphepha lama-42 ngeenkcukacha ezithe vetshe malunga nemilinganiselo yedatha ye-transceiver exhaswayo ye-PAM4 mode.
· Kwimowudi ye-NRZ:
- I-FHT isekela kuphela i-28.05 kunye ne-58 Gbps ngomzila kunye nobuninzi beendlela ze-4.
- I-FGT ixhasa ukuya kuthi ga kwi-28.05 Gbps kwindlela nganye enobuninzi beendlela ezili-16.
Jonga kwiThebhile 18 kwiphepha lama-42 ngeenkcukacha ezithe vetshe malunga nemilinganiselo yedatha ye-transceiver exhaswayo yemowudi ye-NRZ.
· Ixhasa ustrimisho oluqhubekayo (EsiSiseko) okanye iindlela zepakethe (Egcweleyo).
· Ixhasa iipakethi zefreyimu ephantsi.
· Ixhasa ukuhanjiswa kwe-byte granularity kuyo yonke isayizi yokugqabhuka.
· Ixhasa ulungelelwaniso oluqalwa ngumsebenzisi okanye oluzenzekelayo.
· Ixhasa ixesha lolungelelwaniso olucwangcisekileyo.

PCS

· Isebenzisa ingqiqo ye-IP enzima edibana ne-Intel Agilex F-tile ii-transceivers zokunciphisa izixhobo ezithambileyo.
· Ixhasa i-PAM4 imowudi yokumodareyitha ye-100GBASE-KP4 yokucaciswa. I-RS-FEC isoloko ivuliwe kule modulation mode.
· Ixhasa i-NRZ ngemowudi yomoduli ye-RS-FEC ekhethiweyo.
· Ixhasa i-64b/66b encoding decoding.

Ukufunyanwa kwemposiso kunye nokuPhathwa

· Ixhasa impazamo ye-CRC yokujonga kwi-TX kunye neendlela zedatha ye-RX. · Ixhasa ujongo lwempazamo yekhonkco le-RX. · Ixhasa i-RX PCS yokubona iimpazamo.

Ujongano

· Ixhasa kuphela ukuhanjiswa kwepakethi ye-duplex epheleleyo ngamakhonkco azimeleyo.
· Isebenzisa i-point-to-point interconnect kwizixhobo ezininzi zeFPGA ezine-latency yokudlulisa ephantsi.
· Ixhasa imiyalelo echazwe ngumsebenzisi.

2.3. IP Inguqulelo yeNqanaba leNkxaso

Isoftware ye-Intel Quartus Prime kunye nenkxaso yesixhobo se-Intel FPGA ye-F-Tile Serial Lite IV Intel FPGA IP imi ngolu hlobo lulandelayo:

Uluhlu loku-5.

IP Version kunye neNqanaba leNkxaso

Intel Quartus Prime 22.1

Isixhobo Intel Agilex F-tile transceivers

IP Version Ukulinganisa Compilation Hardware Design

5.0.0

2.4. Isixhobo iSpeed Grade Support
I-F-Tile Serial Lite IV Intel FPGA IP ixhasa amabakala esantya alandelayo kwi-Intel Agilex F-tile izixhobo: · Ibanga lesantya seTransceiver: -1, -2, kunye -3 · Ibanga lesantya seCore: -1, -2, kunye - 3

I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 8

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2. F-Tile Uthotho Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

Ulwazi olunxulumeneyo
I-Intel Agilex iDevice Device Sheet Ulwazi oluninzi malunga nezinga ledatha exhaswayo kwi-Intel Agilex F-tile transceivers.

2.5. UkuSetyenziswa kweziBonelelo kunye nokubambezeleka

Izixhobo kunye ne-latency ye-F-Tile Serial Lite IV Intel FPGA IP yafunyanwa kwi-Intel Quartus Prime Pro Edition software version 22.1.

Uluhlu loku-6.

Intel Agilex F-Tile Serial Lite IV Intel FPGA IP Resource Utilization
Umlinganiselo we-latency usekelwe kwi-latency yohambo olujikelezayo ukusuka kwi-TX core input ukuya kwi-RX core output.

Uhlobo lweTransceiver

Ukwahluka

Inani leNdlela yeeNdlela zeDatha RS-FEC ALM

Latency (TX core clock cycle)

FGT

28.05 Gbps NRZ 16

Isiseko sabakhubazekileyo 21,691 65

Abakhubazekileyo ngokupheleleyo 22,135 65

Okusisiseko kunikwe amandla 21,915 189

Isebenza ngokupheleleyo 22,452 189

58 Gbps PAM4 12

Okusisiseko kunikwe amandla 28,206 146

Isebenza ngokupheleleyo 30,360 146

FHT

58 Gbps NRZ

Okusisiseko kunikwe amandla 15,793 146

Isebenza ngokupheleleyo 16,624 146

58 Gbps PAM4 4

Okusisiseko kunikwe amandla 15,771 154

Isebenza ngokupheleleyo 16,611 154

116 Gbps PAM4 4

Okusisiseko kunikwe amandla 21,605 128

Isebenza ngokupheleleyo 23,148 128

2.6. I-Bandwidth Efficiency

Uluhlu loku-7.

I-Bandwidth Efficiency

Iimowudi zeTransceiver eziguquguqukayo

PAM4

Imowudi yostrimisho RS-FEC

Inikwe amandla ngokupheleleyo

Isiseko sinikwe amandla

Uthotho lwebit interface kwiGbps (RAW_RATE)
Ubungakanani bokugqabhuka kodluliselo kwinani legama (BURST_SIZE) (1)
Ixesha lolungelelwaniso kumjikelo wewotshi (SRL4_ALIGN_PERIOD)

56.0 2,048 4,096

56.0 4,194,304 4,096

Iisetingi

NRZ

Igcwele

Kukhubazekile

Ivuliwe

28.0

2,048

4,096

Isiseko sabakhubazekileyo 28.0

Isebenza 28.0

4,194,304

4,096

4,096 iqhubekile...

(1) I-BURST_SIZE yendlela yeSiseko isondela ngokungapheliyo, kungoko inani elikhulu liyasetyenziswa.

Ukuzisa impendulo

I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 9

2. F-Tile Uthotho Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

Izinto eziguquguqukayo

Iisetingi

64/66b ikhowudi

0.96969697 0.96969697 0.96969697 0.96969697 0.96969697 0.96969697

Umphezulu wobukhulu obugqabhukileyo ngokwenani legama (BURST_SIZE_OVHD)

2 (2)

0 (3)

2 (2)

0 (3)

Ulungelelwaniso lwexesha lokumakisha 81,915 kumjikelo wewotshi (ALIGN_MARKER_PERIOD)

81,915

81,916

Ulungelelwaniso lwesiphawuli ububanzi kwisi-5

umjikelo wewotshi

(ALIGN_MARKER_WIDTH)

Ukusebenza kakuhle kobubanzi (4)

0.96821788 0.96916433 0.96827698 0.96822967 0.96922348 0.96917616

Ireyithi esebenzayo (Gbps) (5)

54.2202012 54.27320236 27.11175544 27.11043076 27.13825744 27.13693248

Ubuninzi bewotshi yabasebenzisi (MHz) (6)

423.59532225 424.00939437 423.62117875 423.6004806 424.0352725 424.01457

Ulwazi oluNxulumeneyo loQhagamshelwano loQhagamshelwano kunye ne-Bandwidth eFaneyo ngokubala kwiphepha lama-40

(2) Kwimo egcweleyo, ubungakanani beBURST_SIZE_OVHD buquka START/END Amagama oLawulo adityanisiweyo kumjelo wedatha.
(3) Kwimowudi esisiseko, BURST_SIZE_OVHD ngu-0 kuba akukho START/END ngexesha lostrimisho.
(4) Jonga kwiNqanaba loQhagamshelwano kunye neBandwidth Efficiency Calculation kubalwa kwe-bandwidth esebenzayo.
5
(6) Jonga kwiNqanaba loQhagamshelwano kunye neBandwidth Efficiency Calculation for the maximum user clock frequency calculation.

I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 10

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3. Ukuqalisa

3.1. Ukufakela kunye neLayisensi ye-Intel FPGA IP Cores

Ufakelo lwesoftware ye-Intel Quartus Prime luquka ithala leencwadi le-Intel FPGA IP. Eli thala leencwadi libonelela ngee-IP ezininzi eziluncedo kusetyenziso lwakho lwemveliso ngaphandle kwesidingo selayisenisi eyongezelelweyo. Ezinye ze-Intel FPGA IP cores zifuna ukuthengwa kwelayisensi eyahlukileyo yokusetyenziswa kwemveliso. I-Intel FPGA IP Evaluation Mode ikuvumela ukuba uvavanye ezi zilayisenisi ze-Intel FPGA IP ngokulinganisa kunye ne-hardware, ngaphambi kokuba uthathe isigqibo sokuthenga ilayisensi epheleleyo ye-IP engundoqo. Kufuneka uthenge kuphela ilayisenisi epheleleyo yemveliso yee-Intel IP cores ezinelayisensi emva kokuba ugqibezele uvavanyo lwe-hardware kwaye ulungele ukusebenzisa i-IP kwimveliso.

Isoftware ye-Intel Quartus Prime ifaka ii-IP cores kwezi ndawo zilandelayo ngokungagqibekanga:

Umzobo 2.

Indlela yokuFakela i-IP Core
intelFPGA (_pro) quartus - Iqulethe i-Intel Quartus Prime software ip-Iqulethe ithala leencwadi le-Intel FPGA IP kunye neqela lesithathu le-IP cores altera-Iqulethe ikhowudi yomthombo wethala leencwadi le-Intel FPGA IP -Iqulethe umthombo we-IP we-Intel FPGA files

Uluhlu loku-8.

Iindawo zoFakelo lwe-IP Core

Indawo

Isoftware

:intelFPGA_proquartusipaltera

Intel Quartus Prime Pro Edition

:/intelFPGA_pro/quartus/ip/altera Intel Quartus Prime Pro Edition

Iqonga leWindows* Linux*

Phawula:

I-Intel Quartus Prime software ayixhasi izithuba kwindlela yokufaka.

3.1.1. Intel FPGA IP Evaluation Mode
Imowudi yoVavanyo lwe-IP ye-Intel FPGA yasimahla ikuvumela ukuba uvavanye iicores ze-Intel FPGA IP ezinelayisenisi kukulinganisa kunye nehardware phambi kokuthenga. I-Intel FPGA IP Evaluation Mode ixhasa olu vavanyo lulandelayo ngaphandle kwelayisensi eyongezelelweyo:
· Xelisa indlela yokuziphatha ye-Intel FPGA IP enelayisensi engundoqo kwinkqubo yakho. · Qinisekisa ukusebenza, ubungakanani, kunye nesantya sondoqo we-IP ngokukhawuleza nangokulula. · Veza inkqubo yesixhobo esinexesha elilinganiselweyo files yoyilo olubandakanya ii-IP cores. · Cwangcisa isixhobo ngondoqo we-IP yakho kwaye uqinisekise uyilo lwakho kwihardware.

ISO 9001:2015 ibhalisiwe

3. Ukuqalisa
683074 | 2022.04.28
I-Intel FPGA IP Evaluation Mode ixhasa ezi ndlela zokusebenza zilandelayo:
· Ixhunyiwe–Ivumela ukuqhutywa koyilo oluqulathe ilayisensi ye-Intel FPGA IP ngokungenasiphelo ngodibaniso phakathi kwebhodi yakho kunye nekhompyutha engumamkeli. Imowudi edityanisiweyo ifuna iqela lesenzo sovavanyo oludibeneyo (JTAG) intambo eqhagamshelwe phakathi kweJTAG izibuko kwibhodi yakho kunye nekhompyuter yenginginya, eqhuba i-Intel Quartus Prime Programmer kangangexesha lovavanyo lwehardware. UMcwangcisi ufuna kuphela ufakelo oluncinci lwe-Intel Quartus Prime software, kwaye ayifuni ilayisenisi ye-Intel Quartus Prime. Ikhompyutha ebamba umkhosi ilawula ixesha lovavanyo ngokuthumela uphawu lwexesha kwisixhobo ngeJTAG izibuko. Ukuba zonke iikhowudi ze-IP ezinelayisenisi kwimowudi yoyilo yenkxaso edibeneyo, ixesha lokuvavanya liqhuba kude kube naluphi na uvavanyo lwe-IP olungundoqo luphelelwa. Ukuba zonke ii-IP cores zixhasa ixesha lovavanyo olungenamkhawulo, isixhobo asiphelelwa lixesha.
· Ayifakwanga–Ivumela ukuqhutywa koyilo oluqulathe i-IP enelayisensi okwexeshana. Undoqo we-IP ubuyela kwimowudi engafakwanga ukuba isixhobo siqhawuka kwikhompyuter yenginginya eqhuba isoftware ye-Intel Quartus Prime. Undoqo we-IP uphinda ubuyele kwimowudi engafakwanga ukuba nayiphi na enye ingundoqo ye-IP enelayisensi kuyilo ayixhasi imo edityanisiweyo.
Xa ixesha lokuvavanya liphelile kuyo nayiphi na ilayisensi ye-Intel FPGA IP kuyilo, uyilo luyayeka ukusebenza. Zonke ii-IP cores ezisebenzisa i-Intel FPGA IP Evaluation Mode ixesha liphuma ngaxeshanye xa nayiphi na i-IP engundoqo kumaxesha oyilo ngaphandle. Xa ixesha lovavanyo liphelile, kufuneka uphinde udwelise isixhobo seFPGA phambi kokuba uqhubeke noqinisekiso lwehardware. Ukwandisa ukusetyenziswa kwe-IP core kwimveliso, thenga ilayisensi epheleleyo yokuvelisa i-IP core.
Kufuneka uthenge ilayisenisi kwaye wenze isitshixo selayisensi yokuvelisa ngokupheleleyo phambi kokuba wenze inkqubo yesixhobo esingathintelwanga file. Ngexesha le-Intel FPGA IP Evaluation Mode, uMhlanganisi uvelisa kuphela inkqubo yesixhobo esilinganiselweyo file ( _time_limited.sof) ephelelwa lixesha.

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Umzobo 3.

Intel FPGA IP Evaluation Mode Flow
Faka i-Intel Quartus Prime Software nge-Intel FPGA IP Library

Parameterize kwaye umisele iLayisenisi ye-Intel FPGA IP Core

Qinisekisa i-IP kwiSifanisi esixhaswayo

Qokelela uYilo kwi-Intel Quartus Prime Software

Ukuvelisa iNkqubo yeSixhobo esiNcinyiweyo File

Inkqubo yesixhobo se-Intel FPGA kwaye uqinisekise ukusebenza kwiBhodi
Akukho IP elungele ukusetyenziswa kweMveliso?
Ewe Thenga iMveliso epheleleyo
IP Ilayisensi

Phawula:

Bandakanya iLayisenisi ye-IP kwiiMveliso zoRhwebo
Jonga kwisikhokelo somsebenzisi se-IP nganye ngamanyathelo eparameterization kunye neenkcukacha zokuphunyezwa.
Iilayisensi ze-Intel ze-IP cores kwisihlalo ngasinye, ngokusisigxina. Umrhumo wephepha-mvume ubandakanya ugcino kunye nenkxaso yonyaka wokuqala. Kufuneka uhlaziye ikhontrakthi yokulungisa ukuze ufumane uhlaziyo, ukulungiswa kweempazamo, kunye nenkxaso yobugcisa ngaphaya konyaka wokuqala. Kufuneka uthenge ilayisensi epheleleyo yemveliso ye-Intel FPGA IP cores ezifuna ilayisenisi yokuvelisa, ngaphambi kokuvelisa inkqubo files onokuyisebenzisa ixesha elingasikelwanga mda. Ngexesha le-Intel FPGA IP Evaluation Mode, uMhlanganisi uvelisa kuphela inkqubo yesixhobo esilinganiselweyo file ( _time_limited.sof) ephelelwa lixesha. Ukufumana izitshixo zelayisenisi yakho yemveliso, ndwendwela Intel FPGA Self-Service Licensing Centre.
IziVumelwano zeLayisensi yeSoftware ye-Intel FPGA zilawula ukufakwa kunye nokusetyenziswa kweecore ze-IP ezinelayisensi, i-Intel Quartus Prime software design, kunye nazo zonke ii-IP cores ezingenalayisenisi.

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Ulwazi oluyeleleneyo · Iziko leNkxaso le-Intel FPGA yeLayisensi · Intshayelelo yoFakelo lweSoftware ye-Intel FPGA kunye neLayisensi
3.2. Ukuchaza iiParameters ze-IP kunye noKhetho
Umhleli weparamitha ye-IP ikuvumela ukuba uqwalasele ngokukhawuleza ukwahluka kwe-IP yakho. Sebenzisa la manyathelo alandelayo ukucacisa iinketho ze-IP kunye neeparamitha kwi-software ye-Intel Quartus Prime Pro Edition.
1. Ukuba awunayo iprojekthi ye-Intel Quartus Prime Pro Edition yokudibanisa i-F-Tile Serial Lite IV Intel FPGA IP, kufuneka udale enye. a. Kwi-Intel Quartus Prime Pro Edition, cofa File IWizard yeProjekthi eNtsha yokudala iprojekthi entsha yeQuartus Prime, okanye File Vula iProjekthi yokuvula iprojekthi ekhoyo yeQuartus Prime. Iwizard ikwenza ukuba uchaze isixhobo. b. Cacisa usapho lwesixhobo se-Intel Agilex kwaye ukhethe isixhobo se-F-tile sokuvelisa esihlangabezana neemfuno zebakala lesantya se-IP. c. Cofa Gqiba.
2. Kwikhathalogu ye-IP, khangela kwaye ukhethe i-F-Tile Serial Lite IV Intel FPGA IP. Iwindow entsha yoKwahluka kwe-IP ibonakala.
3. Cacisa igama elikwinqanaba eliphezulu lokwahluka kwe-IP yakho entsha. Umhleli weparameter ugcina useto loguqulo lwe IP kwi file igama .ip.
4. Cofa u-Kulungile. Umhleli weparameter uyavela. 5. Cacisa iiparamitha zokwahluka kwe-IP yakho. Jonga icandelo leParameter ye
ulwazi malunga F-Tile Serial Lite IV Intel FPGA IP parameters. 6. Ngokuzikhethela, ukuvelisa i-testbench yokulinganisa okanye ukuhlanganiswa kunye noyilo lwe-hardware
example, landela imiyalelo kuYilo Example Isikhokelo somsebenzisi. 7. Cofa ukuvelisa i-HDL. Ibhokisi yencoko yababini yesiZukulwana iyavela. 8. Chaza isiphumo file iinketho zokuvelisa, kwaye emva koko ucofe ukuvelisa. Ukwahluka kwe-IP
files velisa ngokweenkcukacha zakho. 9. Cofa Gqiba. Umhleli weparameter wongeza inqanaba eliphezulu .ip file ukuya okwangoku
iprojekthi ngokuzenzekelayo. Ukuba uyacelwa ukuba wongeze ngesandla i.ip file kwiprojekthi, cofa iProjekthi Yongeza/Susa Files kwiProjekthi yokongeza i file. 10. Emva kokuvelisa kunye nokumisela ukwahluka kwe-IP yakho, yenza izabelo ezifanelekileyo ze-pin ukuze udibanise amazibuko kwaye usete naziphi na iiparamitha ze-RTL ezifanelekileyo.
Iiparamitha zolwazi olunxulumeneyo kwiphepha lama-42
3.3. Yenziwe File Ulwakhiwo
Isoftware ye-Intel Quartus Prime Pro Edition ivelisa le mveliso ilandelayo ye-IP file isakhiwo.
Ngolwazi malunga ne file ubume boyilo example, bhekisa kwi F-Tile Serial Lite IV Intel FPGA IP Design Example Isikhokelo somsebenzisi.

I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 14

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Umzobo 4. F-Tile Serial Lite IV Intel FPGA IP Yenziwe Files
.ip - udibaniso lwe-IP file

IP eyahlukileyo files

_ IP eyahlukileyo files

example_design

.cmp – isibhengezo secandelo le-VHDL file _bb.v – Verilog HDL ibhokisi emnyama EDA synthesis file _inst.v kunye .vhd – Sample templates instantiation .xml- XML ingxelo file

Example indawo IP yakho core uyilo example files. Indawo emiselweyo ngumxample_design, kodwa uyacelwa ukuba uchaze indlela eyahlukileyo.

.qgsimc – Udwelisa iiparamitha zokulinganisa ukuxhasa uhlaziyo olongezelelekileyo .qgsynthc – Udwelisa iiparamitha ze-synthesis ukuxhasa uhlaziyo olongezelelekileyo

.qip – Udwelisa IP synthesis files

_generation.rpt- IP yokuvelisa ingxelo

.sopcinfo- Udibaniso lwesixhobo se-software file .html- Uqhagamshelwano kunye nedatha yemephu yememori

.csv – Pin isabelo file

.spd – Idibanisa imibhalo yokulinganisa yodwa

sim Ukulinganisa files

IP synthesis files

.v Ukulinganisa okukwinqanaba eliphezulu file

.v Umyinge ophezulu we-IP synthesis file

Izikripthi zokulinganisa

Amathala eencwadi angaphantsi

i-synth
I-subcore synthesis files

sim
Ukulinganisa okungaphantsi files

Uluhlu loku-9.

F-Tile Uthotho Lite IV Intel FPGA IP Yenziwe Files

File Igama

Inkcazo

.ip

Inkqubo yoMyili wePlatform okanye ukuhluka kwe-IP ephezulu file. ligama onike lona IP umahluko.

.cmp

I-VHDL Component Declaration (.cmp) file sisicatshulwa file equlathe igeneric yobulali kunye neenkcazelo zezibuko onokuzisebenzisa kuyilo lweVHDL files.

.html

Ingxelo equlethe ulwazi loqhagamshelwano, imephu yememori ebonisa idilesi yekhoboka ngalinye ngokubhekiselele kwinkosi nganye edibeneyo, kunye nezabelo zeparameter.

_isizukulwana.rpt

IP okanye iPlatform Designer log yokuvelisa file. Isishwankathelo semiyalezo ngexesha lesizukulwana se-IP.

.qgsimc

Udwelisa iiparamitha zokulinganisa ukuxhasa ukuvuselelwa ngokutsha.

.qgsynthc

Udwelisa iiparamitha zokudibanisa ukuxhasa uhlaziyo olongezelelweyo.

.qip

Iqulethe lonke ulwazi olufunekayo malunga necandelo le-IP ukudibanisa kunye nokudibanisa icandelo le-IP kwi-Intel Quartus Prime software.
iqhubekile...

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File Igama .sopcinfo
.csv .spd _bb.v _inst.v okanye _inst.vhd .regmap
.svd
.v okanye .vhd umcebisi/ synopsys/vcs/ synopsy/vcsmx/ xcelium/ submodules/ /

Inkcazo
Ichaza uqhagamshelo kunye neeparamitha zecandelo le-IP kwinkqubo yakho yoMyili weQonga. Ungacazulula imixholo yayo ukufumana iimfuno xa uphuhlisa abaqhubi besoftware kumacandelo e-IP. Izixhobo ezisezantsi ezifana ne-Nios® II tool chain zisebenzisa oku file. I .sopcinfo file kunye nenkqubo.h file eveliswe kwitsheyini yesixhobo ye-Nios II ibandakanya ulwazi lwemephu yedilesi yesalamane sekhoboka ngalinye kwinkosi nganye efikelela kwikhoboka. Iinkosi ezahlukeneyo zinokuba nemephu yeedilesi eyahlukileyo ukufikelela kwicandelo elithile lamakhoboka.
Iqulethe ulwazi malunga nesimo sophuculo lwecandelo le-IP.
Ungeniso olufunekayo file ye-ip-make-simscript ukuvelisa izikripthi zokulinganisa izifanisi ezixhaswayo. I.spd file iqulathe uluhlu lwe files yenzelwe ukulinganisa, kunye nolwazi malunga neenkumbulo onokuthi uziqalise.
Ungasebenzisa iVerilog emnyama-ibhokisi (_bb.v) file njengesibhengezo esingenanto somnqongo wokusetyenziswa njengebhokisi emnyama.
HDL example instantiation template. Ungakopa kwaye uncamathisele imixholo yoku file kwi-HDL yakho file Ukuqinisekisa ukwahluka kwe-IP.
Ukuba i-IP iqulethe ulwazi lwerejista, .regmap file ivelisa. I-.regmap file ichaza ulwazi lwemephu yerejista yenkosi kunye nojongano lwekhoboka. Oku file igcwalisa .sopcinfo file ngokubonelela ngolwazi oluthe vetshe ngerejista malunga nesistim. Oku kwenza umboniso werejista views kunye neenkcukacha-manani ezinokwenziwa ngokwezifiso kwiNkqubo yeConsole.
Ivumela isixokelelwano somqhubekekisi oqinileyo (HPS) izixhobo zokulungisa iimpazamo kwiNkqubo view iimephu zerejista yeeperipherals eziqhagamshelwe kwi-HPS kwinkqubo yoMyili wePlatform. Ngexesha lokudibanisa, i.svd files yojongano lwekhoboka olubonakalayo kwiSystem Console iinkosi zigcinwe kwi .sof file kwicandelo lolungiso lweempazamo. Inkqubo yeConsole ifunda eli candelo, apho uMyili weQonga angabuza malunga nolwazi lwemephu yokubhalisa. Kumakhoboka enkqubo, uMyili wePlatform unokufikelela kwiirejista ngamagama.
HDL files eziqinisekisa imodyuli nganye engaphantsi okanye i-IP yomntwana yokudibanisa okanye ukulinganisa.
Iqulethe iModeliSim*/QuestaSim* iskripthi se-msim_setup.tcl sokuseta kunye nokuqhuba ukulinganisa.
Iqulethe umbhalo weqokobhe we-vcs_setup.sh wokuseta kwaye usebenzise ukulinganisa kweVCS*. Iqulethe umbhalo weqokobhe we-vcsmx_setup.sh kunye ne-synopsy_sim.setup file ukuseta kwaye usebenzise ukulinganisa kweVCS MX.
Iqulathe umbhalo weqokobhe xcelium_setup.sh kunye nolunye ucwangciso files ukuseta kwaye usebenzise ukulinganisa kwe-Xcelium*.
Iqulethe HDL files yee-IP submodules.
Kuluhlu ngalunye lwe-IP lomntwana oluvelisiweyo, uMyili weQonga uvelisa i-synth/ kunye ne-sim/ sub-directory.

3.4. Ukulinganisa i-Intel FPGA IP Cores
I-Intel Quartus Prime software ixhasa ukulinganisa kwe-IP engundoqo ye-RTL kwii-simulators ze-EDA ezithile. Ukuveliswa kwe-IP ngokuzikhethela kudala ukulinganisa files, kubandakanywa imodeli yokulinganisa esebenzayo, nayiphi na i-testbench (okanye example uyilo), kunye nomthengisi-specific isifanisi imibhalo yokuseta kumbindi ngamnye we-IP. Ungasebenzisa imodeli yokulinganisa esebenzayo kunye nayiphi na i-testbench okanye i-example uyilo lokulinganisa. Imveliso yokuvelisa i-IP inokubandakanya izikripthi zokuqokelela kunye nokuqhuba nayiphi na i-testbench. Izikripthi dwelisa yonke imifuziselo okanye amathala eencwadi owafunayo ukulinganisa undoqo we-IP yakho.

I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 16

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I-Intel Quartus Prime software ibonelela ngokudityaniswa kunye ne-simulators ezininzi kwaye ixhasa ukuhamba kokulinganisa okuninzi, kubandakanywa ukuhamba kwakho okubhaliweyo kunye nesiko lokulinganisa. Nokuba yeyiphi na indlela yokuhamba oyikhethayo, ukulinganisa okungundoqo kwe-IP kubandakanya la manyathelo alandelayo:
1. Yenza i-IP HDL, i-testbench (okanye i-example uyilo), kunye nescript sokuseta isifanisi files.
2. Cwangcisa indawo yakho ye-simulator kunye naziphi na izikripthi zokulinganisa.
3. Qokelela amathala eencwadi emodeli yokulinganisa.
4. Qhuba isifanisi sakho.

3.4.1. Ukulinganisa kunye nokuqinisekisa uYilo

Ngokungagqibekanga, umhleli weparameter uvelisa ukulinganisa okushicilelweyo okungqalileyo okuqulathe imiyalelo yokuqokelela, ukucacisa, kunye nokulinganisa imifuziselo ye-Intel FPGA IP kunye nethala leencwadi lokulinganisa. files. Ungakopa imiyalelo kwiskripthi sakho sokulinganisa testbench, okanye uhlele ezi files ukongeza imiyalelo yokuqulunqa, ukucacisa, kunye nokulinganisa uyilo lwakho kunye nebhentshi yovavanyo.

Itheyibhile 10. Intel FPGA IP Core Ukulinganisa okushicilelweyo

Isifanisi

File Uluhlu

ImodeliSim

_sim/umcebisi

QuestaSim

VCS

_sim/synopsy/vcs

VCS MX

_sim/synopsy/vcsmx

Xcelium

_sim/xcelium

Ushicilelo msim_setup.tcl (7)
vcs_setup.sh vcsmx_setup.sh synopsys_sim.setup xcelium_setup.sh

3.5. Ukudibanisa i-IP Cores kwezinye iziXhobo ze-EDA
Ngokuzithandela, sebenzisa esinye isixhobo esixhaswayo se-EDA ukudibanisa uyilo olubandakanya i-Intel FPGA IP cores. Xa uvelisa i-IP core synthesis files yokusetyenziswa kunye neqela lesithathu le-EDA izixhobo zokudityaniswa, ungenza indawo kunye netlist yoqikelelo lwexesha. Ukuvumela ukuvelisa, vula Yenza ixesha kunye noqikelelo lwezixhobo zeqela lesithathu le-EDA izixhobo zokuhlanganisa xa ulungiselela ukwahluka kwe-IP yakho.
Indawo kunye noluhlu loqikelelo lwexesha luchaza uqhagamshelo olungundoqo lwe-IP kunye nolwakhiwo, kodwa alubandakanyi iinkcukacha malunga nokusebenza kokwenyani. Olu lwazi luvumela izixhobo ezithile zeqela lesithathu ukwenza ingxelo engcono kwindawo kunye noqikelelo lwexesha. Ukongeza, izixhobo ze-synthesis zinokusebenzisa ulwazi lwexesha ukufezekisa ulungelelwaniso oluqhutywa lixesha kunye nokuphucula umgangatho weziphumo.
Isoftware ye-Intel Quartus Prime ivelisa i _syn.v uluhlu lomnatha file kwiVerilog HDL ifomathi, nokuba yeyiphi na imveliso file ifomathi oyichazayo. Ukuba usebenzisa olu luhlu lwenethi kuqulunqo, kufuneka uquke i IP engundoqo esongayo file .v okanye .vhd kwiprojekthi yakho ye-Intel Quartus Prime.

(7) Ukuba awusetanga isixhobo se-EDA esikhethwayo– esenza ukwazi ukuqalisa iqela lesithathu le-EDA simulators ukusuka kwi-Intel Quartus Prime software–sebenzisa esi script kwi-ModelSim okanye i-QuestaSim simulator Tcl console (hayi kwi-Intel Quartus Prime software. Tcl console) ukunqanda naziphi na iimpazamo.

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I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 17

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3.6. Ukuqulunqa uYilo olupheleleyo
Ungasebenzisa umyalelo woQoqosho lokuQalisa kwimenyu yoLungiselelo kwisoftware ye-Intel Quartus Prime Pro Edition ukuqokelela uyilo lwakho.

I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 18

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683074 | 2022.04.28 Thumela iNgxelo

4. Inkcazo esebenzayo

Umzobo 5.

I-F-Tile Serial Lite IV Intel FPGA IP iquka i-MAC kunye ne-Ethernet PCS. I-MAC inxibelelana ne-PCS yesiko ngokusebenzisa ujongano lwe-MII.

I-IP ixhasa iindlela ezimbini zokumodareyitha:
· PAM4–Ibonelela ngenani eli-1 ukuya kwi-12 leendlela zokukhetha. I-IP isoloko iqinisekisa amajelo amabini e-PCS kumzila ngamnye kwi-PAM4 imo yokumodareyitha.
· I-NRZ–Ibonelela nge-1 ukuya kwi-16 inani leendlela zokukhetha.

Imowudi nganye yokumodareyitha ixhasa iindlela ezimbini zedatha:
· Imowudi esisiseko-Le yimowudi yokusasaza esulungekileyo apho idatha ithunyelwa ngaphandle kwepakethi yokuqala, umjikelo ongenanto, kunye nokuphela kwepakethi ukunyusa i-bandwidth. I-IP ithatha idatha yokuqala esebenzayo njengesiqalo sokugqabhuka.

Ugqithiso lweNkcukacha yeNdlela eSisiseko tx_core_clkout tx_avs_ready

tx_avs_valid tx_avs_data rx_core_clkout rx_avs_ready

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_data rx_avs_esebenzayo

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

ISO 9001:2015 ibhalisiwe

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Umzobo 6.

· Imo egcweleyo–Le yimowudi yogqithiso lwedata. Kule ndlela, i-IP ithumela ukuqhuma kunye nomjikelezo wokuvumelanisa ekuqaleni kunye nokuphela kwepakethi njenge-delimiters.

Ugqithiso lweNkcukacha yeMowudi epheleleyo tx_core_clkout

tx_avs_ready tx_avs_valid tx_avs_startofpacket tx_avs_endofpacket
tx_avs_data rx_core_clkout rx_avs_ready rx_avs_valid rx_avs_startofpacket rx_avs_endofpacket

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

Ulwazi Oluyeleleneyo · F-Tile Uthotho Lite IV Intel FPGA IP Overview kwiphepha 6 · F-Tile Uthotho Lite IV Intel FPGA IP Design Example Isikhokelo somsebenzisi

4.1. Uluhlu lwedatha yeTX
I-TX datapath inala macandelo alandelayo: · Iadaptha ye-MAC · Ibhloko yolawulo lofakelo lwamagama · CRC · i-encoder ye-MII · ibhloko ye-PCS · ibhloko ye-PMA

I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 20

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Umzobo 7. I-TX Datapath

Ukusuka kwingqiqo yomsebenzisi

TX MAC

I-Avalon Streaming Interface

Iadaptha ye-MAC

Lawula uFako lwegama

CRC

I-MII Encoder

I-MII Interface Custom PCS
I-PCS kunye ne-PMA

TX Uthotho Ujongano Kwisinye Isixhobo seFPGA

4.1.1. Iadaptha ye-TX MAC
I-adapter ye-TX MAC ilawula ukuhanjiswa kwedatha kwingqiqo yomsebenzisi usebenzisa i-interface ye-Avalon® yokusakaza. Le block ixhasa ukuhanjiswa kolwazi oluchazwe ngumsebenzisi kunye nolawulo lokuhamba.

Ukudluliselwa kolwazi oluchazwe nguMsebenzisi

Kwimo egcweleyo, i-IP inikezela nge-tx_is_usr_cmd isignali onokuyisebenzisa ukuqalisa umjikelezo wolwazi oluchazwe ngumsebenzisi olufana nokuhanjiswa kwe-XOFF/XON kwingqiqo yomsebenzisi. Ungaqalisa umjikelo wothumelo oluchazwe ngumsebenzisi ngokuqinisekisa lo mqondiso kwaye udlulisele ulwazi usebenzisa i-tx_avs_data kunye nokuqinisekisa kwe-tx_avs_startofpacket kunye neempawu ze-tx_avs_valid. Ibhloko ke idese i-tx_avs_ready kwimijikelo emibini.

Phawula:

Ulwazi oluchazwe ngumsebenzisi lufumaneka kuphela kwimo egcweleyo.

Ukuzisa impendulo

I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 21

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Umzobo 8.

Ulawulo lokuqukuqela

Kukho iimeko apho i-TX MAC ingakulungele ukufumana idatha kwi-logic yomsebenzisi njengexesha lenkqubo yokulungelelanisa kwakhona ikhonkco okanye xa kungekho datha ekhoyo yokudluliselwa kwi-logic yomsebenzisi. Ukuze ugweme ukulahleka kwedatha ngenxa yale miqathango, i-IP isebenzisa i-tx_avs_ready signal ukulawula ukuhamba kwedatha kwi-logic yomsebenzisi. I-IP ikhupha isignali xa iimeko ezilandelayo zisenzeka:
· Xa i-tx_avs_startofpacket isenziwa, tx_avs_ready iyakhutshwa kumjikelo wewotshi enye.
· Xa i-tx_avs_endofpacket ithi, tx_avs_ready iyakhutshwa kumjikelo wewotshi enye.
· Xa naziphi na ii-CWs ezidityanisiweyo zibasiwe tx_avs_ready is desserated for two clocks cycles.
· Xa ukufakwa kophawu lolungelelwaniso lwe-RS-FEC lusenzeka kujongano lwe-PCS yesiko, i-tx_avs_ready ikhutshwa kumjikelo wewotshi emine.
· Yonke imijikelo yewotshi eyi-17 ye-Ethernet engundoqo kwimowudi yokumodareyitha ye-PAM4 kunye nayo yonke imijikelo yewotshi eyi-33 ye-Ethernet engundoqo kwimowudi yokumodareyitha ye-NRZ. I-tx_avs_ready ikhutshwa kumjikelo wewotshi enye.
· Xa logic yomsebenzisi desserts tx_avs_valid ngexesha kungekho ugqithiso lwedatha.

Le mizobo ilandelayo yexesha i-exampiadaptha ye-TX MAC isebenzisa i-tx_avs_ready kulawulo lokuhamba kwedatha.

Ulawulo lokuqukuqela nge-tx_avs_valid Dessertion kunye START/END nee-CW ezidityanisiweyo

tx_core_clkout

tx_avs_valid tx_avs_data

D1 D2 D3

Iidessert ezisebenzayo

I-D5 D6

tx_avs_ready tx_avs_startofpacket

Umqondiso olungele iidesethi zemijikelo emibini yokufaka END-STRT CW

tx_avs_endofpacket

usrif_data

D1 D2 D3

CW_data

I-DN PHELA i-STRT D0 D1 D2 D3 AYINANTO D4

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Umzobo 9.

Ulawulo lokuqukuqela ngokuFakelo lweSiphawuli soLungelelaniso
tx_core_clkout tx_avs_valid

tx_avs_data tx_avs_ready

DN-5 DN-4 DN-3 DN-2 DN-1

DN+1

01234

tx_avs_startofpacket tx_avs_endofpacket

idatha_ye-usrif CW_idatha CRC_idatha yeMII_data

DN-1 DN DN DN DN

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

I-DN-1

DN+1

i_sl_tx_mii_c[7:0]

0x0

i_sl_tx_mii_am

01234

i_sl_tx_mii_am_pre3

01234

Umzobo 10.

Ulawulo lokuqukuqela nge-START/END ii-CW ezidityanisiweyo zingqinelaniswa noFakelo lweMarker yoLungelelaniso

tx_core_clkout tx_avs_valid

tx_avs_data

DN-5 DN-4 DN-3 DN-2 DN-1

tx_avs_ready

012 345 6

tx_avs_startofpacket

tx_avs_endofpacket

usrif_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

CW_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

CRC_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

MII_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

I-DN-1

PHELA I-STRT D0

i_sl_tx_mii_c[7:0]

0x0

i_sl_tx_mii_am i_sl_tx_mii_am_pre3

01234

4.1.2. Lawula Igama (CW) Ukufakwa
I-F-Tile Serial Lite IV Intel FPGA IP yakha ii-CWs ngokusekelwe kwiimpawu zegalelo ezivela kwingqiqo yomsebenzisi. Ii-CWs zibonisa i-packet delimiters, ulwazi lwesimo sokudluliselwa okanye idatha yomsebenzisi kwibhloko ye-PCS kwaye ziphuma kwiikhowudi zokulawula ze-XGMII.
Le theyibhile ilandelayo ibonisa inkcazo yee-CWs ezixhaswayo:

Ukuzisa impendulo

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Uluhlu loku-11.
QALA ISIPHELO LULUNGISA

Inkcazo yee-CWs ezixhaswayo

Inani laMagama (igama eli-1

= 64 bits)

Ewe

EMPTY_CYC

Ewe

I-IDLE

Hayi

IDATHA

Ewe

Kwibhanti

Inkcazo
Ukuqala kwe-data delimiter. Isiphelo somdawuli wedatha. Lawula igama (CW) lolungelelwaniso lwe-RX. Umjikelo ongenanto kudluliselo lwedatha. I-IDLE (ngaphandle kwebhendi). Ukuhlawula.

Itheyibhile 12. CW Inkcazo yeNdawo
Indawo yeRSVD inani_valid_bytes_eob
I-EMPTY eop sop seop lungelelanisa i-CRC32 usr

Inkcazo
Indawo egciniweyo. Ingasetyenziselwa ukwandiswa kwexesha elizayo. Ibotshelelwe ku-0.
Inani leebhayithi ezisebenzayo kwigama lokugqibela (64-bit). Eli lixabiso le-3bit. · 3'b000: 8 bytes · 3'b001: 1 byte · 3'b010: 2 byte · 3'b011: 3 bytes · 3'b100: 4 bytes · 3'b101: 5 byte · 3'b110: 6 bytes · 3'b111: 7 iibhayithi
Inani lamagama anganyanisekanga ekupheleni kokugqabhuka.
Ibonisa ujongano lokusasaza lwe-RX Avalon ukuze iqinisekise isiginali yokuphela kwepakethi.
Ibonisa ujongano lokusasaza lwe-RX Avalon ukuze iqinisekise isiginali yokuqalisa kwepakethi.
Ibonisa i-interface ye-RX Avalon yokusasaza ukuze iqinisekise ukuqala kwepakethi kunye nesiphelo sepakethi kumjikelo ofanayo.
Jonga ulungelelwaniso lwe-RX.
Amaxabiso e-CRC ebaliwe.
Ibonisa ukuba igama lolawulo (CW) liqulethe ulwazi oluchazwe ngumsebenzisi.

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4.1.2.1. Ukuqala kokugqabhuka kweCW

Umzobo 11. Ukuqalisa kokugqabhuka kweFomathi yeCW

QALA

63:56

RSVD

55:48

RSVD

47:40

RSVD

idatha

39:32 31:24

RSVD RSVD

23:16

i-sop ulungelelaniso lwe-usr=0 seop

15:8

ijelo

7:0

'hFB(QALA)

ulawulo 7:0

Uluhlu loku-13.

Kwimo egcweleyo, ungafaka i- START CW ngokuqinisekisa i-tx_avs_startofpacket isignali. Xa ubanga kuphela isignali ye-tx_avs_startofpacket, isuntswana le-sop liyasetwa. Xa uqinisekisa ukuba zombini i-tx_avs_startofpacket kunye ne-tx_avs_endofpacket iimpawu, i-bit ye-seop iyasetwa.

QALA CW amaxabiso eNdawo
I-sop yasendle/seop
usr (8)
lungelelanisa

Ixabiso

Kuxhomekeke kwi-tx_is_usr_cmd isignali:

1: Xa tx_is_usr_cmd = 1

0: Xa tx_is_usr_cmd = 0

Kwimowudi yeSiseko, i-MAC ithumela i-START CW emva kokuba ukusetha kwakhona kususiwe. Ukuba akukho datha ikhoyo, i-MAC isoloko ithumela EMPTY_CYC edityaniswe ne-END kunye ne- START CWs ude uqale ukuthumela idatha.

4.1.2.2. Ukuphela kokuqhuma kweCW

Umzobo 12. Ukuphela kokuqhuma kweCW yeFomathi

ISIPHELO

63:56

'hFD

55:48

CRC32[31:24]

47:40

CRC32[23:16]

idatha 39:32 31:24

CRC32[15:8] CRC32[7:0]

23:16 eop=1 RSVD RSVD RSVD

RSVD

15:8

RSVD

AYINANTO

7:0

RSVD

num_valid_bytes_eob

ulawulo

7:0

(8) Oku kuxhaswa kuphela kwimodi egcweleyo.
Ukuzisa impendulo

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Uluhlu loku-14.

I-MAC ifaka i-END CW xa i-tx_avs_endofpacket ibasiwe. I-END CW iqulethe inani leebhayithi ezisebenzayo kwigama lokugqibela ledatha kunye nolwazi lwe-CRC.

Ixabiso le-CRC sisiphumo se-32-bit CRC sedatha phakathi kwe- START CW kunye negama ledatha phambi kwe-END CW.

Le theyibhile ilandelayo ibonisa amaxabiso emihlaba kwi-END CW.

PHELA CW amaxabiso eNdawo
Indawo eop CRC32 num_valid_bytes_eob

Ixabiso 1
CRC32 ixabiso elibaliweyo. Inani leebhayithi ezisebenzayo kwigama lokugqibela ledatha.

4.1.2.3. Ulungelelwaniso oludityanisiweyo lweCW

Umzobo 13. Ulungelelwaniso oludityanisiweyo lweFomathi yeCW

LUNGISELELA I-CW Ngamabini nge-START/END

64+8bits XGMII Interface

QALA

63:56

RSVD

55:48

RSVD

47:40

RSVD

idatha

39:32 31:24

RSVD RSVD

23:16 eop=0 isop=0 usr=0 lungelelanisa=1 isephu=0

15:8

RSVD

7:0

'hFB

ulawulo 7:0

64+8bits XGMII Interface

ISIPHELO

63:56

'hFD

55:48

RSVD

47:40

RSVD

idatha

39:32 31:24

RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

ulawulo 7:0

I-ALIGN CW yi-CW edityanisiweyo ene-START/END okanye END/START CWs. Ungafaka i-ALIGN edityaniswe CW ngokuqinisekisa i-tx_link_reinit isignali, ukuseta ikhawunta yeXesha loLungelelwaniso, okanye uqalise ukuseta kwakhona. Xa i-ALIGN edityanisiweyo ye-CW ifakiwe, indawo yokulungelelanisa imiselwe ku-1 ukuqalisa ibhloko yolungelelwaniso lommkeli ukujonga ulungelelwaniso lwedatha kuyo yonke imizila.

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Uluhlu loku-15.

LUNGISELELA Amaxabiso eNdawo yeCW
Ulungelelwaniso lommandla
eop sop usr seop

Ixabiso 1 0 0 0 0

4.1.2.4. Umjikelo ongenanto CW

Umzobo 14. IFomathi yeCW yomjikelo ongenanto

EMPTY_CYC Nqana ne-END/START

64+8bits XGMII Interface

ISIPHELO

63:56

'hFD

55:48

RSVD

47:40

RSVD

idatha

39:32 31:24

RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

ulawulo 7:0

64+8bits XGMII Interface

QALA

63:56

RSVD

55:48

RSVD

47:40

RSVD

idatha

39:32 31:24

RSVD RSVD

23:16

sop=0 usr=0 lungelelanisa=0 seop=0

15:8

RSVD

7:0

'hFB

ulawulo 7:0

Uluhlu loku-16.

Xa ukhupha i-tx_avs_valid kwimijikelo yeewotshi ezimbini ngexesha lokugqabhuka, i-MAC ifaka i-EMPTY_CYC CW edityaniswe END/START CWs. Ungasebenzisa le CW xa kungekho datha ikhoyo yokuhanjiswa okomzuzwana.

Xa ususa tx_avs_valid kumjikelo omnye, i-IP deasserts tx_avs_valid kangangexesha eliphindiweyo tx_avs_valid deassertion ukwenza iperi ye END/START CWs.

EMPTY_CYC CW Amaxabiso ommandla
Ulungelelwaniso lommandla
eop

Ixabiso 0 0

iqhubekile...

Ukuzisa impendulo

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Ummandla wesop usr seop

Ixabiso 0 0 0

4.1.2.5. I-CW ayisebenzi

Umzobo 15. I-Idle CW Ifomathi

I-IDLE CW

63:56

'h07

55:48

'h07

47:40

'h07

idatha

39:32 31:24

'h07'h07

23:16

'h07

15:8

'h07

7:0

'h07

ulawulo 7:0

I-MAC ifaka i-IDLE CW xa kungekho lugqithiso. Ngeli xesha, uphawu lwe-tx_avs_valid luphantsi.
Ungasebenzisa i-IDLE CW xa ukuhanjiswa kokuqhuma kugqityiwe okanye ukuhanjiswa kukwimeko engasebenziyo.

4.1.2.6. ILizwi leDatha

Igama ledatha ngumthwalo wepakethi. Iibits zolawulo ze-XGMII zonke zisetelwe ku-0 kwifomati yegama ledatha.

Umzobo 16. Idatha yeFomathi yeLizwi

64+8 bits XGMII Interface

IGAMA LEDATHA

63:56

iinkcukacha zomsebenzisi 7

55:48

iinkcukacha zomsebenzisi 6

47:40

iinkcukacha zomsebenzisi 5

idatha

39:32 31:24

iinkcukacha zomsebenzisi 4 iinkcukacha zomsebenzisi 3

23:16

iinkcukacha zomsebenzisi 2

15:8

iinkcukacha zomsebenzisi 1

7:0

iinkcukacha zomsebenzisi 0

ulawulo 7:0

4.1.3. TX CRC
Unokwenza ibhlokhi ye-TX CRC usebenzisa i-Yenza i-parameter ye-CRC kwi-IP Parameter Editor. Olu phawu luxhaswa kwiimowudi eziSiseko kunye neziPheleleyo.

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I-MAC yongeza ixabiso le-CRC kwi-END CW ngokuqinisekisa uphawu lwe-tx_avs_endofpacket. Kwimo ye-BASIC, kuphela i-ALIGN CW edityaniswe ne-END CW equlethe indawo esebenzayo ye-CRC.
Ibhloko ye-TX CRC idibanisa kunye ne-TX Control Word Insertion kunye ne-TX MII Encode block. Ibhloko ye-TX CRC ibala ixabiso le-CRC kwixabiso le-64-bit ixabiso lomjikelo ngamnye ukusuka kwi-START CW ukuya kwi-END CW.
Unokuthi crc_error_inject uphawu ukonakalisa ngabom idata kwindlela ethile ukwenza iimpazamo CRC.

4.1.4. TX MII Encoder

I-encoder ye-TX MII iphatha ukuhanjiswa kwepakethi ukusuka kwi-MAC ukuya kwi-TX PCS.

Lo mfanekiso ulandelayo ubonisa ipateni yedatha kwibhasi ye-MII ye-8-bit kwimodi yokumodareyitha ye-PAM4. I-START kunye ne-END CW zivela kube kanye kwiindlela ezimbini ze-MII.

Umzobo 17. PAM4 Modulation Mode MII Data Pattern

UMJIKELO 1

UMJIKELO 2

UMJIKELO 3

UMJIKELO 4

UMJIKELO 5

SOP_CW

DATA_1

DATA_9 DATA_17

I-IDLE

DATA_DUMMY SOP_CW
DATA_DUMMY

DATA_2 DATA_3 DATA_4

DATA_10 DATA_11 DATA_12

DATA_18 DATA_19 DATA_20

EOP_CW I-IDLE
EOP_CW

SOP_CW

DATA_5 DATA_13 DATA_21

I-IDLE

DATA_DUMMY DATA_6 DATA_14 DATA_22 EOP_CW

SOP_CW DATA_DUMMY

DATA_7 DATA_8

DATA_15 DATA_16

DATA_23 DATA_24

IDLE EOP_CW

Lo mfanekiso ulandelayo ubonisa ipateni yedatha kwibhasi ye-MII ye-8-bit kwimowudi yokumodareyitha ye-NRZ. I-START kunye ne-END CW zivela kuzo zonke iindlela ze-MII.

Ukuzisa impendulo

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Umzobo 18. Ipateni yedatha ye-NRZ ye-MII yedatha

UMJIKELO 1

UMJIKELO 2

UMJIKELO 3

SOP_CW

DATA_1

DATA_9

SOP_CW

DATA_2 DATA_10

SOP_CW SOP_CW

DATA_3 DATA_4

DATA_11 DATA_12

SOP_CW

DATA_5 DATA_13

SOP_CW

DATA_6 DATA_14

SOP_CW

DATA_7 DATA_15

SOP_CW

DATA_8 DATA_16

CYCLE 4 DATA_17 DATA_18 DATA_19 DATA_20 DATA_21 DATA_22 DATA_23 DATA_24

CYCLE 5 EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW

4.1.5. I-TX PCS kunye ne-PMA
I-F-Tile Serial Lite IV Intel FPGA IP iqwalasela i-F-tile transceiver kwimowudi ye-Ethernet PCS.

4.2. Uluhlu lwedatha ye-RX
I-datapath ye-RX iquka la macandelo alandelayo: · Ibhloko ye-PMA · ibhloko ye-PCS · idikhowuda ye-MII · CRC · ibhloko yeDeskew · Ibhloko yokuLawula i-Word

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Umzobo 19. I-RX Datapath

Kwingqiqo yomsebenzisi i-Avalon Streaming Interface
RX MAC
Lawula Ukususwa Kwamagama
Deskew

CRC

Idekhowuda yeMII

I-MII Interface Custom PCS
I-PCS kunye ne-PMA

Ujongano lweRX Uthotho olusuka kwesinye isixhobo seFPGA
4.2.1. I-RX PCS kunye ne-PMA
I-F-Tile Serial Lite IV Intel FPGA IP iqwalasela i-F-tile transceiver kwimowudi ye-Ethernet PCS.
4.2.2. Idekhowuda ye-RX MII
Le bloko ichonga ukuba idatha engenayo iqulethe igama lolawulo kunye namanqaku okulungelelanisa. Idekhowuda ye-RX MII ikhupha idatha ngokohlobo lwe-1-bit esebenzayo, isalathisi se-1-bit esimakishayo, isalathisi esi-1 solawulo, kunye nedatha ye-64-bit ngomzila ngamnye.
4.2.3. RX CRC
Unokwenza ibhlokhi ye-TX CRC usebenzisa i-Yenza i-parameter ye-CRC kwi-IP Parameter Editor. Olu phawu luxhaswa kwiimowudi eziSiseko kunye neziPheleleyo. Ibhloko ye-RX CRC idibanisa kunye ne-RX Control Word Removal kunye neebhloko ze-RX MII Decoder. I-IP ithi rx_crc_error signal xa kusenzeka impazamo ye-CRC.

Ukuzisa impendulo

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I-IP isusa i-rx_crc_error kuyo yonke into entsha. Sisiphumo kwingqiqo yomsebenzisi yokuphatha impazamo yengqiqo yomsebenzisi.
4.2.4. RX Deskew
I-block ye-deskew ye-RX ibona iimpawu zokulungelelaniswa kwendlela nganye kwaye iphinde ilungelelanise idatha ngaphambi kokuyithumela kwi-block ye-RX CW yokususa.
Unokukhetha ukuvumela i-IP core ukulungelelanisa idatha kumzila ngamnye ngokuzenzekelayo xa impazamo yokulungelelanisa isenzeka ngokucwangcisa i-Parameter ye-Auto Alignment parameter kwi-IP parameter Editor. Ukuba ukhubaza ulungelelwaniso oluzenzekelayo, undoqo we-IP uqinisekisa i-rx_error signal ukubonisa impazamo yolungelelwaniso. Kufuneka uthi rx_link_reinit ukuqalisa inkqubo yolungelelwaniso lwelayini xa kusenzeka impazamo yolungelelwaniso lwendlela.
I-deskew ye-RX ibona iimpawu zokulungelelanisa ngokusekelwe kumatshini karhulumente. Lo mzobo ulandelayo ubonisa amazwe kwi-RX deskew block.

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Umzobo 20.

I-RX Deskew Lane Ukulungelelaniswa koMshini woRhulumente kunye noLungelelwaniso oluzenzekelayo oluVunyiweyo lweTshati yokuHamba
Qala

I-IDLE

Seta kwakhona = 1 ewe hayi

Zonke iiPCS

Hayi

iindlela zilungile?

Ewe

YIMA

Zonke iziphawuli zongqamaniso inomb
Ibhaqiwe?
Ewe
YOLA

Hayi
ewe Ixesha liphelile?

Ewe
Ilahlekile kukulungelelaniswa?
akukho End

Ukuzisa impendulo

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Umzobo 21.

I-RX Deskew Lane Ukulungelelaniswa koMshini woRhulumente kunye noLungelelwaniso oluzenzekelayo lweTshati yokuQuquza okuKhubazekileyo
Qala

I-IDLE

Seta kwakhona = 1 ewe hayi

Zonke iiPCS

Hayi

iindlela zilungile?

Ewe

Ewe
rx_link_reinit =1
akukho MPHAZAMO

hayi ewe Ixesha liphelile?

YIMA
hayi Zonke iziphawuli zongqamaniso
Ibhaqiwe?
ewe LUNGISA

Ewe
Ilahlekile kukulungelelaniswa?
Hayi
Isiphelo
1. Inkqubo yokulungelelanisa iqala nge-IDLE state. Ibhloko ishukuma iye kwimo ye-WAIT xa zonke iindlela ze-PCS zilungile kwaye i-rx_link_reinit isusiwe.
2. Kwimeko ye-WAIT, ibhloko ijonga zonke izimakishi ezichongiweyo ziqinisekiswa kumjikelo ofanayo. Ukuba le meko iyinyani, ibhloko ishukuma iye kwimo ELUNGISELWEYO.
3. Xa ibhloko ikwimo ELUNGISELELWEYO, ibonisa ukuba iindlela zilungelelanisiwe. Kule meko, ibhloko iyaqhubeka nokubeka esweni ulungelelwaniso lwendlela kwaye ukhangele ukuba ngaba bonke abamakishi bakhona kumjikelo ofanayo. Ukuba noko isiphawuli esinye akakho kumjikelo ofanayo kwaye Yenza Ulungelelwaniso oluzenzekelayo iparamitha iseti, ibhloko iya kwi

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I-IDLE state ukuqalisa kwakhona inkqubo yolungelelwaniso. Ukuba Ulungelelwaniso oluzenzekelayo lwe-Auto alucwangciswanga kwaye noko isiphawuli esinye asikho kumjikelo ofanayo, ibhloko iya kwi-ERROR imeko kwaye ilindele ingqiqo yomsebenzisi ukuba aqinisekise i-rx_link_reinit isignali ukuqalisa inkqubo yolungelelwaniso lwelayini.

Umzobo 22. Ulungelelwaniso lweNdlela kunye nokuVumela ulungelelwaniso oluzenzekelayo lunikwe amandla rx_core_clk

rx_link_phezulu

rx_link_reinit

kunye_zonke_iziphawuli

Deskew State

I-ALGNED

I-IDLE

YIMA

I-ALGNED

I-AUTO_ALIGN = 1

Umzobo 23. Ulungelelwaniso lweNdlela kunye nokuVumela ulungelelwaniso oluzenzekelayo lukhubazekile rx_core_clk

rx_link_phezulu

rx_link_reinit

kunye_zonke_iziphawuli

Deskew State

I-ALGNED

Imposiso

I-IDLE

YIMA

I-ALGNED

I-AUTO_ALIGN = 0
4.2.5. Ukususwa kwe-RX CW
Le bloko ichaza ii-CWs kwaye ithumela idatha kwingqiqo yomsebenzisi usebenzisa i-interface ye-Avalon yokusakaza emva kokususwa kwee-CW.
Xa kungekho datha isebenzayo ekhoyo, ibhloko yokususa i-RX CW ikhupha i-rx_avs_valid isignali.
Kwimo ESIPHELELEYO, ukuba i-bit yomsebenzisi isetiwe, le bhloko iqinisekisa i-rx_is_usr_cmd isignali kunye nedatha kumjikelo wewotshi yokuqala isetyenziswe njengolwazi oluchazwe ngumsebenzisi okanye umyalelo.
Xa i-rx_avs_ready dessserts kunye ne-rx_avs_valid asserts, ibhloko yokususa ye-RX CW ivelisa imeko yempazamo kwingqiqo yomsebenzisi.
Imiqondiso yostrimisho yeAvalon enxulumene nale block ilandelayo: · rx_avs_startofpacket · rx_avs_endofpacket · rx_avs_channel · rx_avs_empty · rx_avs_data

Ukuzisa impendulo

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· rx_avs_valid
· rx_num_valid_bytes_eob
· rx_is_usr_cmd (ifumaneka kuphela kwimo egcweleyo)
4.3. F-Tile Serial Lite IV Intel FPGA IP Clock Architecture
I-F-Tile Serial Lite IV Intel FPGA IP inamagalelo ewotshi ezine enza iiwotshi kwiibhloko ezahlukeneyo: · Iwotshi yereferensi yeTransceiver (xcvr_ref_clk)–Ikloko yokufakwa kwiwotshi yangaphandle.
iitshiphusi okanye ii-oscillators ezivelisa iiwotshi ze-TX MAC, i-RX MAC, kunye ne-TX kunye ne-RX iibhloko zePCS zesiko. Jonga kwiiParameters zoluhlu lwamaza axhasiweyo. · Iwotshi ye-TX engundoqo (tx_core_clk)–Le wotshi ithathwe kwi-transceiver PLL isetyenziselwa i-TX MAC. Le wotshi ikwayiwotshi yokuphuma kwi-F-tile transceiver ukuxhuma kwi-logic yomsebenzisi we-TX. · I-RX core clock (rx_core_clk)–Le wotshi ithathwe kwi-transceiver PLL isetyenziselwa i-RX deskew FIFO kunye ne-RX MAC. Le wotshi ikwayiwotshi yokuphuma kwi-F-tile transceiver ukuqhagamshela kwi-RX logic yomsebenzisi. · Ikloko ye-transceiver reconfiguration interface (reconfig_clk)-iwotshi yokufakwayo evela kwiisekethe zewotshi zangaphandle okanye ii-oscillators ezivelisa iiwotshi ze-F-tile transceiver reconfiguration interface kuzo zombini i-TX kunye ne-RX datapaths. Amaxesha ewotshi yi-100 ukuya kwi-162 MHz.
Lo mzobo ulandelayo webhloko ubonisa iF-Tile Serial Lite IV Intel FPGA IP clock domains kunye noqhagamshelwano ngaphakathi kwe IP.

I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 36

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Umzobo 24.

F-Tile Serial Lite IV Intel FPGA IP Clock Architecture

I-oscillator

FPGA1
I-F-Tile Serial Lite IV Intel FPGA IP Transceiver Reconfiguration Clock Interface
(reconfig_clk)

tx_core_clkout (qhagamshela kwingqiqo yomsebenzisi)

tx_core_clk= clk_pll_div64[mid_ch]

FPGA2

F-Tile Uthotho Lite IV Intel FPGA IP

IClock ye-Transceiver Reconfiguration Interface

(reconfig_clk)

I-oscillator

rx_core_clk= clk_pll_div64[mid_ch]

rx_core_clkout (qhagamshela kwingqiqo yomsebenzisi)

clk_pll_div64[mid_ch] clk_pll_div64[n-1:0]

I-Avalon Streaming Interface TX Data
TX MAC

ikhonkco_lothotho[n-1:0]

Deskew

FIFO

I-Avalon Streaming Interface RX Data RX MAC

Idatha ye-Avalon Streaming Interface RX
RX MAC

Deskew FIFO

rx_core_clkout (qhagamshela kwingqiqo yomsebenzisi)

rx_core_clk= clk_pll_div64[mid_ch]

I-PCS eyenzekileyo

ikhonkco_lothotho[n-1:0]

TX MAC

I-Avalon Streaming Interface TX Data

tx_core_clk= clk_pll_div64[mid_ch]

tx_core_clkout (qhagamshela kwingqiqo yomsebenzisi)

IClock ye-Transceiver Ref (xcvr_ref_clk)
IClock ye-Transceiver Ref (xcvr_ref_clk)

I-oscillator*

Intsomi

isixhobo seFPGA
TX isizinda iwotshi engundoqo
Indawo yewotshi engundoqo ye-RX
Idomeyini yewotshi yereferensi yeTransceiver Isixhobo sangaphandle Imiqondiso yedatha

4.4. Ukuseta kwakhona kunye nokuQalisa ikhonkco
I-MAC, i-F-tile Hard IP, kunye neebhloko zohlengahlengiso zineempawu ezahlukeneyo zokusetha kwakhona: · Iibhloko ze-TX kunye ne-RX MAC zisebenzisa i-tx_core_rst_n kunye ne-rx_core_rst_n iimpawu zokusetha kwakhona. · tx_pcs_fec_phy_reset_n kunye rx_pcs_fec_phy_reset_n ukuseta kwakhona iimpawu drive
isilawuli sokusetha kwakhona esithambileyo ukuseta kwakhona i-F-tile Hard IP. · Ibhloko yohlengahlengiso isebenzisa isignali yokuseta ngokutsha reconfig_reset.

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I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 37

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Umzobo 25. Seta kwakhona i-Architecture
I-Avalon Streaming Interface TX Data
IMAC
Avalon Streaming SYNC Interface RX Data

FPGA F-tile Uthotho Lite IV Intel FPGA IP

tx_mii rx_mii
phy_ehip_ready phy_rx_pcs_ready

F-tile Hard IP

TX Uthotho Data RX Uthotho Data

tx_core_rstn rx_core_rstn tx_pcs_fec_phy_reset_n rx_pcs_fec_phy_reset_n reconfig_reset

Seta kwakhona iNgqiqo
Ulwazi oluyeleleneyo · Hlela kwakhona iziKhokelo kwiphepha 51 · F-Tile Serial Lite IV Intel FPGA IP Design Example Isikhokelo somsebenzisi
4.4.1. Ukusetha kwakhona kwe-TX kunye nokuQalisa ngokulandelelana
I TX seta ngokutsha ulandelelwano lwe F-Tile Uthotho Lite IV Intel FPGA IP ngolu hlobo lulandelayo: 1. Assert tx_pcs_fec_phy_reset_n, tx_core_rst_n, kwaye reconfig_reset
ngaxeshanye ukuseta kwakhona F-tile nzima IP, MAC, kunye neebhloko uqwalaselo ngokutsha. Khupha i-tx_pcs_fec_phy_reset_n kunye nokusetwa kwakhona kwakhona emva kokulinda i-tx_reset_ack ukuqinisekisa ukuba iibhloko zisetwe ngokufanelekileyo. 2. I-IP ke ithi i-phy_tx_lanes_stable, tx_pll_locked, kunye neempawu ze-phy_ehip_ready emva kokuba i-tx_pcs_fec_phy_reset_n isetyenzisiwe, ukubonisa ukuba i-TX PHY ilungele ukudluliselwa. 3. I-tx_core_rst_n i-desserts yesignali emva kokuba i-phy_ehip_ready isignali iphezulu. 4. I-IP iqala ukuthumela iimpawu ze-IDLE kwi-interface ye-MII emva kokuba i-MAC iphelile. Akukho mfuneko yolungelelwaniso lwendlela ye-TX kunye ne-skewing kuba zonke iindlela zisebenzisa iwotshi enye. 5. Ngelixa uthumela iimpawu ze-IDLE, i-MAC iqinisekisa i-tx_link_up signal. 6. I-MAC emva koko iqala ukuthumela i-ALIGN idityaniswe ne-START/END okanye END/START CW ngexesha elimiselweyo ukuqalisa inkqubo yolungelelwaniso lwendlela yomamkeli oqhagamshelweyo.

I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 38

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Umzobo 26.

Ukusetha kwakhona kwe-TX kunye nokuQalisa uMzobo weXesha
reconfig_sl_clk

reconfig_clk

tx_core_rst_n

tx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

tx_reset_ack

tx_pll _tshixiwe

phy_tx_lanes_stable

phy_ehip_ready

tx_li nk_up

7
5 6 8

4.4.2. Ukuseta kwakhona kwe-RX kunye nokuQalisa ngokulandelelana
I-RX yokusetha kwakhona ulandelelwano lwe-F-Tile Serial Lite IV Intel FPGA IP lulandelayo:
1. Assert rx_pcs_fec_phy_reset_n, rx_core_rst_n, kwaye reconfig_reset ngaxeshanye ukuseta kwakhona i-F-tile hard IP, MAC, kunye neebhloko zohlengahlengiso. Khupha i-rx_pcs_fec_phy_reset_n kunye nohlengahlengiso lohlengahlengiso emva kokulinda i-rx_reset_ack ukuqinisekisa ukuba iibhloko zisetwe ngokufanelekileyo.
2. I-IP ke iqinisekisa i-phy_rx_pcs_ready isignali emva kokukhululwa kwe-PCS yesiko, ukubonisa i-RX PHY ilungele ukudluliselwa.
3. Isiginali ye-rx_core_rst_n dessserts emva kokuba i-phy_rx_pcs_ready isignali iye phezulu.
4. I-IP iqala inkqubo yokulungelelaniswa komzila emva kokuba i-RX MAC iphinda ikhutshwe kwaye emva kokufumana i-ALIGN idibaniswe ne-START/END okanye END/START CW.
5. Ibhlokhi ye-deskew ye-RX iqinisekisa i-rx_link_up isignali xa ulungelelwaniso lwazo zonke iindlela lugqityiwe.
6. I-IP ke ithi rx_link_up isignali kwingqiqo yomsebenzisi ukubonisa ukuba ikhonkco le-RX likulungele ukuqalisa ulwamkelo lwedatha.

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I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 39

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Umzobo 27. Ukusetha kwakhona kwe-RX kunye nokuQalisa uMzobo weXesha
reconfig_sl_clk

reconfig_clk

rx_core_rst_n

rx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

rx_reset_ack

rx_cdr_lock

rx_block_lock

rx_pcs_ready

rx_link_phezulu

3 3 3 2

4 5 5

6 7

4.5. Ireyithi yeNxulumaniso kunye neBandwidth Efficiency Calculation

Ubalo lwe-F-Tile Serial Lite IV Intel FPGA IP bandwidth esebenzayo lunje ngezantsi:

Ubuchule bomthamo = ireyithi_eluhlaza * 64/66 * (burst_size - burst_size_ovhd)/burst_size * [align_marker_period / (align_marker_period + align_marker_width)] * [(srl4_align_period – 2) / srl4_align_period

Itheyibhile 17. UkuSebenza ngokuSebenza kweBandwidth Iiguquguquko

Iyaguquguquka

Inkcazo

ireyithi_ekrwada burst_size

Eli liqondo lebit eliphunyezwe lujongano lothotho. raw_rate = SEDES ububanzi * transceiver clock frequency Eksample: iraw_rate = 64 * 402.812500 Gbps = 25.78 Gbps
Ixabiso lobukhulu obugqabhukileyo. Ukubala umndilili we-bandwidth esebenzayo, sebenzisa ixabiso eliqhelekileyo lokugqabhuka kwesayizi. Ngomlinganiselo ophezulu, sebenzisa ixabiso lesayizi ephezulu yokugqabhuka.

burst_size_ovhd

Ixabiso elingaphezulu kwesayizi yogqabhuko.
Kwimo egcweleyo, i-burst_size_ovhd ixabiso libhekisa kwi-START kunye ne-END ezidityanisiweyo CWs.
Kwimo yoSiseko, akukho burst_size_ovhd kuba akukho START kwaye END iiCWs ezidityanisiweyo.

lungelelanisa_ixesha_lophawu

Ixabiso lethuba apho isiphawuli solungelelwaniso sifakwa khona. Ixabiso yi-81920 clock cycle yokuhlanganiswa kunye ne-1280 yokulinganisa ngokukhawuleza. Eli xabiso lifunyenwe kwi-PCS hard logic.

align_marker_width srl4_align_period

Inani lemijikelo yewotshi apho isiphawuli solungelelwaniso esisebenzayo sibanjwe phezulu.
Inani lemijikelo yewotshi phakathi kweziphawuli ezimbini zolungelelwaniso. Ungacwangcisa eli xabiso usebenzisa iParameter yeXesha loLungelelaniso kwiParamitha ye-IP Umhleli.

I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 40

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Ubalo lwereyithi yekhonkco lungezantsi: Ireyithi esebenzayo = ukusebenza kakuhle kwe-bandwidth * raw_rate Ungafumana obona buninzi bewotshi yomsebenzisi ngale equation ilandelayo. Obona buninzi bamaza obuninzi bobalo lwewotshi luthatha ustrimisho lwedatha oluqhubekayo kwaye akukho mjikelo we-IDLE owenzekayo kwingqiqo yomsebenzisi. Lo mlinganiselo ubalulekile xa kuyilwa i-logic yomsebenzisi i-FIFO ukunqanda ukuphuphuma kwe-FIFO. Elona xesha liphezulu lomsebenzisi = isantya esisebenzayo / 64

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5. Iiparameter

Itheyibhile 18. F-Tile Serial Lite IV Intel FPGA IP Parameter Inkcazo

Ipharamitha

Ixabiso

Ukuhlala kukho

Inkcazo

Iinketho zoYilo ngokubanzi

Uhlobo lokumodareyitha lwe-PMA

· PAM4 · NRZ

PAM4

Khetha imo yokumodareyitha ye-PCS.

Uhlobo lwe-PMA

· FHT · FGT

FGT

Ikhetha uhlobo lwesidluliseli.

Ireyithi yedatha ye-PMA

· Kwimowudi yePAM4:
- Uhlobo lwe-FGT ye-transceiver: 20 Gbps 58 Gbps
-I-FHT uhlobo lwe-transceiver: 56.1 Gbps, 58 Gbps, 116 Gbps
· Kwimowudi ye-NRZ:
- Uhlobo lwe-FGT ye-transceiver: 10 Gbps 28.05 Gbps
- Uhlobo lwe-transceiver ye-FHT: 28.05 Gbps, 58 Gbps

56.1 (FGT/FHT PAM4)
28.05 Gbps (FGT/FHT NRZ)

Ichaza ireyithi yedatha esebenzayo kwimveliso ye-transceiver ebandakanya ukuhanjiswa kunye nezinye ii-overheads. Ixabiso libalwa nge-IP ngokusondeza ukuya kwi-1 indawo yokugqibela kwiyunithi ye-Gbps.

Imo ye-PMA

· Duplex · Tx · Rx

I-Duplex

Kuhlobo lwe-FHT ye-transceiver, isalathiso esixhaswayo yi-duplex kuphela. Kuhlobo lwe-FGT ye-transceiver, isalathiso esixhaswayo yi-Duplex, Tx, kunye ne-Rx.

Inani le-PMA

· Kwimowudi yePAM4:

iindlela

— 1 ukuya kwi-12

· Kwimowudi ye-NRZ:

— 1 ukuya kwi-16

Khetha inani leendlela. Kuyilo olulula, inani elixhaswayo leendlela yi-1.

PLL ireferensi iwotshi frequency

· Kuhlobo lwe-transceiver ye-FHT: 156.25 MHz
· Kuhlobo lwe-FGT ye-transceiver: 27.5 MHz 379.84375 MHz, kuxhomekeke kwireyithi yedatha ye-transceiver ekhethiweyo.

· Kuhlobo lwe-transceiver ye-FHT: 156.25 MHz
· Kuba FGT uhlobo transceiver: 165 MHz

Ixela amaza ewotshi yereferensi yesidluliseli.

Inkqubo yePLL

iwotshi yereferensi

rhoqo

170 MHz

Ifumaneka kuphela ngohlobo lwe-FHT ye-transceiver. Ixela iWotshi yereferensi yeNkqubo ye-PLL kwaye iya kusetyenziswa njengegalelo le-F-Tile Reference kunye neNkqubo yePLL Iiwotshi ze-Intel FPGA IP ukuvelisa iwotshi yeNkqubo ye-PLL.

Inkqubo ye-PLL rhoqo
Ixesha lokulungelelanisa

— 128 65536

Yenza i-RS-FEC isebenze

Vulela

876.5625 MHz 128 Yenza

Ikhankanya amaza ewotshi yeNkqubo ye-PLL.
Ikhankanya ixesha elimakishayo lolungelelwaniso. Ixabiso kufuneka libe ngu-x2. Layita ukuze uvule umsebenzi we-RS-FEC.
iqhubekile...

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Ipharamitha

Ixabiso

Ukuhlala kukho

Inkcazo

Khubaza

Kwimowudi yokumodareyitha ye-PAM4 PCS, i-RS-FEC ihlala ivuliwe.

Indawo yomsebenzisi

Imowudi yostrimisho

· NGOKUPHELELEYO · ISISEKO

Igcwele

Khetha ustrimisho lwedatha ye IP.

Igcwele: Le mowudi ithumela ukuqala kwepakethi kunye nokuphela komjikelo wepakethi ngaphakathi kwesakhelo.

Isiseko: Le yindlela ecocekileyo yokusakaza apho idatha ithunyelwa ngaphandle kwepakethi yokuqala, engenanto, kunye nokuphela kwepakethi yokwandisa i-bandwidth.

Vula i-CRC

Yenziwe yasebenza ayasebenza

Khubaza

Layita ukuze uvule ubhaqo lwempazamo ye-CRC kunye nolungiso.

Yenza ulungelelwaniso oluzenzekelayo lusebenze

Yenziwe yasebenza ayasebenza

Khubaza

Layita ukuze uvule ulungelelwaniso lwendlela oluzenzekelayo.

Yenza isiphelo solungiso lweempazamo

Yenziwe yasebenza ayasebenza

Khubaza

Xa ON, i-F-Tile Serial Lite IV Intel FPGA IP iquka i-Embedded Debug Endpoint edibanisa ngaphakathi kwi-interface ye-Avalon memory-mapped. I-IP inokwenza iimvavanyo ezithile kunye nemisebenzi yokucoca nge-JTAG usebenzisa iConsole yeNkqubo. Ixabiso elimiselweyo Licinyiwe.

Ukudityaniswa kweSimplex (Olu seto lweparamitha lufumaneka kuphela xa ukhetha iFGT uyilo olubini olulula.)

RSFEC yenziwe kwelinye iSerial Lite IV Simplex IP ibekwe kwijelo leFGT elinye(s)

Yenziwe yasebenza ayasebenza

Khubaza

Vula olu khetho ukuba ufuna umxube woqwalaselo nge RS-FEC enikwe amandla kwaye ikhubaziwe kwi F-Tile Serial Lite IV Intel FPGA IP kuyilo olubini olulula lwe NRZ indlela yokudlulisa, apho zombini iTX kunye ne RX zibekwe kwi FGT enye. i(s).

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I-F-Tile Serial Lite IV Intel® FPGA IP User Guide 43

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6. F-Tile Uthotho Lite IV Intel FPGA IP Interface Iimpawu

6.1. Iimpawu zewotshi

Uluhlu 19. Iimpawu zewotshi

Igama

Umkhombandlela obanzi

Inkcazo

tx_core_clkout

Iwotshi engundoqo ye-TX yemveliso ye-TX yesiko le-PCS ujongano, i-TX MAC kunye neengqiqo zomsebenzisi

indlela yedatha yeTX.

Le wotshi yenziwe kwibhloko yePCS yesiko.

rx_core_clkout

Iwotshi engundoqo ye-RX ye-RX yojongano lwe-PCS yesiko, i-RX deskew FIFO, i-RX MAC

kunye neengqiqo zomsebenzisi kwi-datapath ye-RX.

Le wotshi yenziwe kwibhloko yePCS yesiko.

xcvr_ref_clk
reconfig_clk reconfig_sl_clk

Iwotshi yereferensi yokufaka iTransceiver.

Xa uhlobo lwe-transceiver lusetelwe kwi-FGT, qhagamshela le wotshi kwisignali yokuphuma (out_refclk_fgt_0) ye-F-Tile Reference kunye neNkqubo yePLL Iiwotshi ze-Intel FPGA IP. Xa uhlobo lwe-transceiver lusetelwe kwi-FHT, qhagamshela

le wotshi kumqondiso wemveliso (out_fht_cmmpll_clk_0) ye-F-Tile Reference kunye neNkqubo yePLL Iiwotshi ze-Intel FPGA IP.

Jonga kwiiParameters zoluhlu lwamaza axhasiweyo.

Iwotshi yokufaka igalelo lojongano loqwalaselo ngokutsha lwe-transceiver.

Amaxesha ewotshi yi-100 ukuya kwi-162 MHz.

Qhagamshela lo mqondiso wewotshi yegalelo kwiisekethe zewotshi yangaphandle okanye ii-oscillators.

Iwotshi yokufaka igalelo lojongano loqwalaselo ngokutsha lwe-transceiver.

Amaxesha ewotshi yi-100 ukuya kwi-162 MHz.

Qhagamshela lo mqondiso wewotshi yegalelo kwiisekethe zewotshi yangaphandle okanye ii-oscillators.

out_systempll_clk_ 1

Igalelo

Iwotshi ye-PLL yeNkqubo.
Qhagamshela le wotshi kwisignali yokuphuma (out_systempll_clk_0) ye-F-Tile Reference kunye neNkqubo yePLL Iiwotshi ze-Intel FPGA IP.

Iiparamitha zolwazi olunxulumeneyo kwiphepha lama-42

6.2. Seta kwakhona Iimpawu

Itheyibhile 20. Hlela kwakhona Iimpawu

Igama

Umkhombandlela obanzi

tx_core_rst_n

Igalelo

Clock Domain Asynchronous

rx_core_rst_n

Igalelo

Asynchronous

tx_pcs_fec_phy_reset_n 1

Igalelo

Asynchronous

Inkcazo

Isiginali yokusetha ngokutsha esebenzayo-phantsi. Seta kwakhona i-F-Tile Serial Lite IV TX MAC.

Isiginali yokusetha ngokutsha esebenzayo-phantsi. Seta kwakhona i-F-Tile Serial Lite IV RX MAC.

Isiginali yokusetha ngokutsha esebenzayo-phantsi.

iqhubekile...

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Igama

I-Width Direction Clock Domain

Inkcazo

Seta kwakhona i-F-Tile Serial Lite IV TX isiko PCS.

rx_pcs_fec_phy_reset_n 1

Igalelo

Asynchronous

Isiginali yokusetha ngokutsha esebenzayo-phantsi. Seta kwakhona i-F-Tile Serial Lite IV RX isiko PCS.

reconfig_reset

Igalelo

reconfig_clk Isiginali yokusetha ngokutsha esebenzayo-phezulu.

Iseta kwakhona ibhlokhi yoqwalaselo lwenkumbulo ye-Avalon enemephu yojongano ngokutsha.

reconfig_sl_reset

Igalelo reconfig_sl_clk Isiginali yokusetha ngokutsha esebenzayo-phezulu.

Iseta kwakhona ibhlokhi yoqwalaselo lwenkumbulo ye-Avalon enemephu yojongano ngokutsha.

6.3. Iimpawu zeMAC

Uluhlu loku-21.

Iimpawu zeTX MAC
Kule theyibhile, N imele inani leendlela ezibekwe kumhleli weparameter ye IP.

Igama

Ububanzi

Umkhombandlela Clock Domain

Inkcazo

tx_avs_ready

Isiphumo tx_core_clkout Isiginali yostrimisho yeAvalon.

Xa kubangwa, kubonisa ukuba i-TX MAC ikulungele ukwamkela idatha.

tx_avs_data

· (64*N)*2 (PAM4 indlela)
· 64*N (imowudi ye-NRZ)

Igalelo

tx_core_clkout uphawu lokusasaza lweAvalon. Idatha yeTX.

tx_avs_channel

Igalelo tx_core_clkout Isiginali yostrimisho yeAvalon.

Inombolo yetshaneli yedatha egqithiselwayo kumjikelo wangoku.

Lo mqondiso awufumaneki kwimo yoSiseko.

tx_avs_valid

Igalelo tx_core_clkout Isiginali yostrimisho yeAvalon.

Xa ibasiwe, ibonisa isignali yedatha ye-TX iyasebenza.

tx_avs_startofpacket

Igalelo tx_core_clkout Isiginali yostrimisho yeAvalon.

Xa ibasiwe, ibonisa ukuqala kwepakethi yedatha yeTX.

Ibango lomjikelo wewotshi enye kuphela kwipakethi nganye.

Lo mqondiso awufumaneki kwimo yoSiseko.

tx_avs_endofpacket

Igalelo tx_core_clkout Isiginali yostrimisho yeAvalon.

Xa ibasiwe, ibonisa isiphelo sepakethi yedatha yeTX.

Ibango lomjikelo wewotshi enye kuphela kwipakethi nganye.

Lo mqondiso awufumaneki kwimo yoSiseko.

tx_avs_ayinanto

Igalelo tx_core_clkout Isiginali yostrimisho yeAvalon.

Ibonisa inani lamagama angengawo asemthethweni kugqabhuko lokugqibela lwedatha ye-TX.

Lo mqondiso awufumaneki kwimo yoSiseko.

tx_num_valid_bytes_eob

Igalelo

tx_core_clkout

Ibonisa inani leebhayithi ezisebenzayo kwigama lokugqibela lokugqabhuka kokugqibela. Lo mqondiso awufumaneki kwimo yoSiseko.
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Igama tx_is_usr_cmd
tx_link_up tx_link_reinit
crc_error_inject tx_error

Ububanzi 1
1 1
N 5

Umkhombandlela Clock Domain

Inkcazo

Igalelo

tx_core_clkout

Xa kubangwa, lo mqondiso uqalisa umjikelo wolwazi oluchazwe ngumsebenzisi.
Banga olu phawu kumjikelo wewotshi efanayo tx_startofpacket assertion.
Lo mqondiso awufumaneki kwimo yoSiseko.

Imveliso tx_core_clkout Xa ibasiwe, ibonisa ikhonkco ledatha yeTX ilungele ukuhanjiswa kwedatha.

Isiphumo

tx_core_clkout

Xa kuthiwa, lo mqondiso uqalisa ulungelelwaniso lweendlela.
Faka olu phawu kumjikelo wewotshi enye ukuqalisa i-MAC ukuthumela i-ALIGN CW.

Igalelo

tx_core_clkout Xa ibasiwe, i-MAC igalela impazamo ye-CRC32 kwiindlela ezikhethiweyo.

Imveliso tx_core_clkout Ayisetyenziswanga.

Lo mzobo ulandelayo wexesha ubonisa i-example ye-TX ugqithiso lwedatha yamagama ali-10 ukusuka kwingqiqo yomsebenzisi kwiindlela ezilandelelanayo ezili-10 zeTX.

Umzobo 28.

I-TX Data Transmission Time Diagram
tx_core_clkout

tx_avs_valid

tx_avs_ready

tx_avs_startofpackets

tx_avs_endofpackets

tx_avs_data

0,1..,19 10,11…19 …… N-10..

0,1,2,,,9

… N-10..

Indlela 0

……………

I-STRT 0 10

N-10 ISIPHELO STT 0

Indlela 1

……………

I-STRT 1 11

N-9 ISIPHELO STT 1

N-10 PHELA I-IDLE IDLE N-9 PHELA I-IDLE IDLE

Indlela 9

……………

I-STRT 9 19

N-1 ISIPHELO STT 9

N-1 PHELA I-IDLE IDLE

Uluhlu loku-22.

Iimpawu zeRX MAC
Kule theyibhile, N imele inani leendlela ezibekwe kumhleli weparameter ye IP.

Igama

Ububanzi

Umkhombandlela Clock Domain

Inkcazo

rx_avs_ready

Igalelo rx_core_clkout Isiginali yostrimisho yeAvalon.

Xa ibasiwe, ibonisa ukuba ingqiqo yomsebenzisi ikulungele ukwamkela idatha.

rx_avs_data

(64*N)*2 (PAM4 indlela)
64*N (imowudi ye-NRZ)

Isiphumo

rx_core_clkout uphawu lokusasaza lweAvalon. Idatha ye-RX.

rx_avs_channel

Isiphumo rx_core_clkout Isiginali yostrimisho yeAvalon.

Inombolo yetshaneli yedatha

ifunyenwe kumjikelo wangoku.

Lo mqondiso awufumaneki kwimo yoSiseko.

rx_avs_valid

Isiphumo rx_core_clkout Isiginali yostrimisho yeAvalon.

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Igama

Ububanzi

Umkhombandlela Clock Domain

Inkcazo

Xa ibasiwe, ibonisa isignali yedatha ye-RX iyasebenza.

rx_avs_startofpacket

Isiphumo rx_core_clkout Isiginali yostrimisho yeAvalon.

Xa ibasiwe, ibonisa ukuqala kwepakethi yedatha ye-RX.

Ibango lomjikelo wewotshi enye kuphela kwipakethi nganye.

Lo mqondiso awufumaneki kwimo yoSiseko.

rx_avs_endofpacket

Isiphumo rx_core_clkout Isiginali yostrimisho yeAvalon.

Xa ibasiwe, ibonisa isiphelo sepakethi yedatha ye-RX.

Ibango lomjikelo wewotshi enye kuphela kwipakethi nganye.

Lo mqondiso awufumaneki kwimo yoSiseko.

rx_avs_ayinanto

Isiphumo rx_core_clkout Isiginali yostrimisho yeAvalon.

Ibonisa inani lamagama angengawo asemthethweni kugqabhuko lokugqibela lwedatha ye-RX.

Lo mqondiso awufumaneki kwimo yoSiseko.

rx_num_valid_bytes_eob

Isiphumo

rx_core_clkout Ibonisa inani leebhayithi ezisebenzayo kwigama lokugqibela lokugqabhuka kokugqibela.
Lo mqondiso awufumaneki kwimo yoSiseko.

rx_is_usr_cmd

Imveliso rx_core_clkout Xa ibasiwe, olu phawu luqalisa umsebenzisi-

umjikelo wolwazi ochaziweyo.

Banga olu phawu kumjikelo wewotshi efanayo tx_startofpacket assertion.

Lo mqondiso awufumaneki kwimo yoSiseko.

rx_link_phezulu

Imveliso rx_core_clkout Xa ibasiwe, ibonisa ikhonkco ledatha ye-RX

ilungele ulwamkelo lwedatha.

rx_link_reinit

Igalelo rx_core_clkout Xa kubasiwe, olu phawu luqalisa iindlela

ukulungelelaniswa kwakhona.

Ukuba uyacima ukwenza ulungelelwaniso oluzenzekelayo, misela olu phawu kumjikelo wewotshi enye ukuqalisa i-MAC ukulungelelanisa iindlela. Ukuba i-Yenza ulungelelwaniso oluzenzekelayo lusetwe, i-MAC ilungelelanisa iindlela ngokuzenzekelayo.

Sukumisela lo mqondiso xa u Lungelelaniso oluzenzekelayo lusetwe.

rx_impazamo

(N*2*2)+3 (PAM4 indlela)
(N*2)*3 (imowudi ye-NRZ)

Isiphumo

rx_core_clkout

Xa kugxininiswa, kubonisa iimeko zempazamo ezenzeka kwi-datapath ye-RX.
· [(N*2+2):N+3] = Ibonisa impazamo yePCS yendlela ethile.
· [N+2] = Ibonisa impazamo yolungelelwaniso. Lungiselela kwakhona ulungelelwaniso lwendlela ukuba le bit iyabaniswa.
· [N+1]= Ibonisa idatha ithunyelwe kwingqiqo yomsebenzisi xa ingqiqo yomsebenzisi ingekalungi.
· [N] = Ibonisa ukulahleka kolungelelwaniso.
· [(N-1):0] = Ibonisa idatha iqulethe impazamo yeCRC.

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6.4. Iimpawu zoLungiselelo lweTransceiver

Uluhlu loku-23.

PCS imiqondiso yoqwalaselo ngokutsha
Kule theyibhile, N imele inani leendlela ezibekwe kumhleli weparameter ye IP.

Igama

Ububanzi

Umkhombandlela Clock Domain

Inkcazo

reconfig_sl_funda

Ngena reconfig_sl_ PCS uqwalaselo ngokutsha lomyalelo wokufunda

clk

iimpawu.

reconfig_sl_write

Ngena reconfig_sl_ PCS uqwalaselo ngokutsha ukubhala

clk

iimpawu zomyalelo.

reconfig_sl_idilesi

14 amasuntswana + clogb2N

Igalelo

reconfig_sl_ clk

Ixela uqwalaselo ngokutsha lwe-PCS idilesi ye-Avalon yenkumbulo-maphu yojongano kwindlela ekhethiweyo.
Indlela nganye inamasuntswana ali-14 kwaye amasuntswana angaphezulu abhekiselele kwi-offset yelayini.
Example, kuyilo lwemizila emi-4 ye-NRZ/PAM4, kunye ne-reconfig_sl_address[13:0] ibhekisa kwixabiso ledilesi:
· reconfig_sl_address[15:1 4] isete ku-00 = idilesi yelayini engu-0.
· reconfig_sl_address[15:1 4] isete ku-01 = idilesi yelayini engu-1.
· reconfig_sl_address[15:1 4] isete ku-10 = idilesi yelayini engu-2.
· reconfig_sl_address[15:1 4] isete ku-11 = idilesi yelayini engu-3.

reconfig_sl_readdata

Imveliso reconfig_sl_ Ikhankanya idatha yoqwalaselo ngokutsha lwePCS

clk

ifundwe ngumjikelo osele ulungile kwi a

indlela ekhethiweyo.

reconfig_sl_waitrequest

Imveliso reconfig_sl_ Imele uqwalaselo ngokutsha lwePCS

clk

I-Avalon memory-mapped interface

uphawu lokuma kwindlela ekhethiweyo.

reconfig_sl_writedata

Igalelo reconfig_sl_ Ikhankanya idatha yoqwalaselo ngokutsha lwePCS

clk

ukubhalwa kumjikelo wokubhala a

indlela ekhethiweyo.

reconfig_sl_readdata_vali

Isiphumo

reconfig_sl_ Ikhankanya uqwalaselo ngokutsha lwePCS

clk

idata efunyenweyo iyasebenza kwindawo ekhethiweyo

indlela.

Uluhlu loku-24.

Imiqondiso ye-F-Tile eNzima ye-IP yokuLungiselela kwakhona
Kule theyibhile, N imele inani leendlela ezibekwe kumhleli weparameter ye IP.

Igama

Ububanzi

Umkhombandlela Clock Domain

Inkcazo

reconfig_funda

Igalelo reconfig_clk PMA uqwalaselo ngokutsha lufundwe

iimpawu zomyalelo.

reconfig_bhala

Ngena reconfig_clk bhala uqwalaselo ngokutsha lwe-PMA

iimpawu zomyalelo.

reconfig_idilesi

I-18 bits + i-clog2bN

Igalelo

reconfig_clk

Ixela idilesi yojongano lwe-PMA Avalon yenkumbulo kwindlela ekhethiweyo.
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Igama
reconfig_readdata reconfig_waitrequest reconfig_writedata reconfig_readdatavalid

Ububanzi
32 1 32 1

Umkhombandlela Clock Domain

Inkcazo

Kuzo zombini iindlela ze-PAM4 zentengiso ye-NRZ, indlela nganye ineebhithi ezili-18 kwaye amasuntswana aphezulu aseleyo abhekisa kwindlela yokucima.
Example, kuyilo lweendlela ezi-4:
· reconfig_address[19:18] isetelwe ku-00 = idilesi yelayini engu-0.
· reconfig_address[19:18] isetelwe ku-01 = idilesi yelayini engu-1.
· reconfig_address[19:18] isetelwe ku-10 = idilesi yelayini engu-2.
· reconfig_address[19:18] isetelwe ku-11 = idilesi yelayini engu-3.

Isiphumo

reconfig_clk Ichaza idatha ye-PMA ukuba ifundwe ngumjikelo osele ulungile kwindlela ekhethiweyo.

Isiphumo

i-reconfig_clk Imele i-PMA ye-Avalon ye-memory ye-interface yokumisa isignali kwindlela ekhethiweyo.

Igalelo

reconfig_clk Ichaza idatha ye-PMA eza kubhalwa kumjikelo wokubhala kwindlela ekhethiweyo.

Isiphumo

reconfig_clk Ichaza uqwalaselo ngokutsha lwe-PMA idatha efunyenweyo iyasebenza kwindlela ekhethiweyo.

6.5. Iimpawu ze-PMA

Uluhlu loku-25.

Iimpawu ze-PMA
Kule theyibhile, N imele inani leendlela ezibekwe kumhleli weparameter ye IP.

Igama

Ububanzi

Umkhombandlela Clock Domain

Inkcazo

phy_tx_lanes_stable

N*2 (PAM4 indlela)
N (NRZ mode)

Isiphumo

Asynchronous Xa kutshiwo, ibonisa i-TX datapath ikulungele ukuthumela idatha.

tx_pll_tshixiwe

N*2 (PAM4 indlela)
N (NRZ mode)

Isiphumo

Asynchronous Xa kutshiwo, kubonisa ukuba i-TX PLL ifumene iwonga lokutshixa.

phy_ehip_ready

N*2 (PAM4 indlela)
N (NRZ mode)

Isiphumo

Asynchronous

Xa kutshiwo, kubonisa ukuba i-PCS yesiko igqibe ukuqalwa kwangaphakathi kwaye ilungele usasazo.
Lo mqondiso uqinisekisa emva kwe-tx_pcs_fec_phy_reset_n kunye ne-tx_pcs_fec_phy_reset_nare isusiwe.

tx_idatha_yesiriyali

Imveliso TX isiriyeli iwotshi TX izikhonkwane serial.

rx_idatha_yesiriyali

Igalelo leRX yewotshi yothotho lwezikhonkwane zeRX.

phy_rx_block_lock

N*2 (PAM4 indlela)
N (NRZ mode)

Isiphumo

I-Asynchronous Xa isithiwa, ibonisa ukuba ulungelelwaniso lwebhloko ye-66b lugqityiwe kwimizila.

rx_cdr_lock

N*2 (PAM4 indlela)

Isiphumo

Asynchronous

Xa ibasiwe, ibonisa ukuba iiwotshi ezifunyenweyo zitshixiwe kwidatha.
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Xela i-phy_rx_pcs_ready phy_rx_hi_ber

Ububanzi

Umkhombandlela Clock Domain

Inkcazo

N (NRZ mode)

N*2 (PAM4 indlela)
N (NRZ mode)

Isiphumo

Asynchronous

Xa kuqinisekiswa, kubonisa ukuba iindlela ze-RX zetshaneli ye-Ethernet ehambelanayo ihambelana ngokupheleleyo kwaye ilungele ukufumana idatha.

N*2 (PAM4 indlela)
N (NRZ mode)

Isiphumo

Asynchronous

Xa kugxininiswa, kubonisa ukuba i-RX PCS yetshaneli ye-Ethernet ehambelanayo ikwimo ye-HI BER.

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7. Ukuyila nge-F-Tile Serial Lite IV Intel FPGA IP

7.1. Seta kwakhona iziKhokelo
Landela ezi zikhokelo zokuseta ngokutsha ukuphumeza ukuseta ngokutsha kwenqanaba lenkqubo yakho.
· Hlanganisa i-tx_pcs_fec_phy_reset_n kunye ne-rx_pcs_fec_phy_reset_n iimpawu kunye kumgangatho wenkqubo ukwenzela ukuseta kwakhona i-TX kunye ne-RX PCS ngaxeshanye.
· Assert tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, tx_core_rst_n, rx_core_rst_n, kwaye reconfig_reset iimpawu ngexesha elinye. Jonga ukuseta kwakhona kunye nokuQalisa uQhagamshelwano ngolwazi oluthe kratya malunga nokusetha kwakhona kwe-IP kunye nokulandelelana kokuqalisa.
· Bamba i-tx_pcs_fec_phy_reset_n, kunye ne-rx_pcs_fec_phy_reset_n imiqondiso ephantsi, kunye nesignali ye-reconfig_reset ephezulu kwaye ulinde i-tx_reset_ack kunye ne-rx_reset_ack ukusetha ngokufanelekileyo i-F-tile hard IP kunye neebhloko zokuphinda uhlengahlengiso.
· Ukufezekisa ikhonkco elikhawulezayo phakathi kwezixhobo zeFPGA, seta kwakhona i-F-Tile Serial Lite IV Intel FPGA IPs ngexesha elinye. Jonga kwi-F-Tile Serial Lite IV Intel FPGA IP Design Example Isikhokelo somsebenzisi ngolwazi malunga nokubeka iliso kwi-IP TX kunye nekhonkco le-RX usebenzisa i-toolkit.
Ulwazi olunxulumeneyo
· Seta kwakhona kwaye uQhagamshele ukuQalisa kwiphepha lama-37
· F-Tile Serial Lite IV Intel FPGA IP Design Example Isikhokelo somsebenzisi

7.2. Izikhokelo zokuphatha imposiso

Le theyibhile ilandelayo idwelisa izikhokelo zokuphatha imposiso yeemeko zempazamo ezinokuthi zenzeke ngoyilo lwe-F-Tile Serial Lite IV Intel FPGA IP.

Uluhlu 26. Imeko yemposiso kunye neziKhokelo zokuPhatha

Imeko yempazamo
Indlela enye okanye ngaphezulu ayinakuseka unxibelelwano emva kwexesha elibekiweyo.

Izikhokelo
Sebenzisa inkqubo yokuphuma kwexesha ukuseta kwakhona ikhonkco kwinqanaba lesicelo.

Umzila ulahlekelwa lunxibelelwano emva kokuba unxibelelwano lusekiwe.
Indlela ilahlekelwa lunxibelelwano ngexesha lenkqubo yedesika.

Oku kunokwenzeka emva okanye ngexesha lezigaba zokugqithisela idatha. Phumeza ukufunyanwa kwelahleko yekhonkco kwinqanaba lesicelo kwaye usethe kwakhona ikhonkco.
Qalisa inkqubo yoqhagamshelwano lokuqaliswa kwakhona kwindlela enempazamo. Kufuneka uqinisekise ukuba indlela yebhodi ayidluli kwi-320 UI.

Ulungelelwaniso lwendlela yelahleko emva kokuba yonke imizila ilungelelanisiwe.

Oku kunokwenzeka emva okanye ngexesha lezigaba zokugqithisela idatha. Phumeza ubhaqo lwelahleko yolungelelwaniso lwendlela kwinqanaba lesicelo ukuqala ngokutsha inkqubo yolungelelwaniso lwendlela.

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8. F-Tile Uthotho Lite IV Intel FPGA IP User Guide Archives

Iinguqulelo ze-IP ziyafana ne-Intel Quartus Prime Design Suite iinguqulelo zesoftware ukuya kuthi ga kwi-v19.1. Ukusuka kwi-Intel Quartus Prime Design Suite software version 19.2 okanye kamva, ii-IP cores zineskimu esitsha soguqulelo lwe-IP.

Ukuba i-IP core version ayidweliswanga, isikhokelo somsebenzisi senguqulo yangaphambili ye-IP siyasebenza.

Intel Quartus Prime Version
21.3

IP Core Version 3.0.0

Isikhokelo somsebenzisi F-Tile Serial Lite IV Intel® FPGA IP User Guide

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9. Imbali yoHlaziyo loXwebhu lwe-F-Tile Serial Lite IV Intel FPGA IP User Guide

Ingxelo yoXwebhu 2022.04.28
2021.11.16 2021.10.22 2021.08.18

Intel Quartus Prime Version
22.1
21.3 21.3 21.2

IP Version 5.0.0
3.0.0 3.0.0 2.0.0

Iinguqu
· Itheyibhile eHlaziyiweyo: I-F-Tile Serial Lite IV Intel FPGA IP Features - Inkcazo yokuGqithiselwa kweDatha eHlaziyiweyo kunye nenkxaso ye-transceiver ye-FHT eyongezelelweyo: 58G NRZ, 58G PAM4, kunye ne-116G PAM4
· Itheyibhile eHlaziyiweyo: I-F-Tile Serial Lite IV Intel FPGA IP Parameter Inkcazo — Yongezwe iparamitha entsha · Inkqubo ye-PLL yereferensi yewotshi rhoqo · Yenza isiphelo solungiso-ziphene — Uhlaziyo lwexabiso ledatha ye-PMA — Uhlaziyo lwepharamitha yokubiza amagama ukuze ihambelane ne-GUI
· Hlaziya inkcazo yokudluliselwa kwedatha kwiThebhile: F-Tile Serial Lite IV Intel FPGA IP Features.
· Igama letheyibhile ethiywe ngokutsha kwi-F-Tile Series Lite IV Intel FPGA IP Parameter Inkcazo kwicandelo leParameters ukucaca.
· Itheyibhile eHlaziyiweyo: IP parameters: — Kongezwe iparamitha entsha–RSFEC yenziwe kwenye Uthotho Lite IV Simplex IP ibekwe kumjelo(s). — Kuhlaziywe amaxabiso angagqibekanga obuninzi bewotshi yereferensi yeTransceiver.
Ukukhutshwa kokuqala.

ISO 9001:2015 ibhalisiwe

Amaxwebhu / Izibonelelo

	Intel F Tile Uthotho Lite IV Intel FPGA IP [pdf] Isikhokelo somsebenzisi F Tile Serial Lite IV Intel FPGA IP, F Tile Serial Lite IV, Intel FPGA IP
	intel F-Tile Serial Lite IV Intel FPGA IP [pdf] Isikhokelo somsebenzisi F-Tile Serial Lite IV Intel FPGA IP, Serial Lite IV Intel FPGA IP, Lite IV Intel FPGA IP, IV Intel FPGA IP, FPGA IP, IP

Iimbekiselo

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F Tile Uthotho Lite IV Intel FPGA IP

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