Xilinx AXI4-Stream Integrated Logic Analyzer Guide
Learn how to use the Xilinx AXI4-Stream Integrated Logic Analyzer with this user guide. Monitor internal signals and interfaces of your design with customizable features, including boolean trigger equations and edge transition triggers. The ILA core offers interface debugging and monitoring capability along with protocol checking for memory-mapped AXI and AXI4-Stream. Get all the details you need in the Vivado Design Suite User Guide: Programming and Debugging (UG908). Compatible with Versal™ ACAP, this LogiCORE™ IP is a must-have for advanced logic analysis.