UG0644 DDR AXI Arbiter
Tlhahisoleseding ya Sehlahiswa
DDR AXI Arbiter ke karolo ea hardware e fanang ka a
64-bit AXI master interface ho DDR-SDRAM on-chip controller.
E sebelisoa hangata lits'ebetsong tsa video bakeng sa buffering le
ts'ebetso ea data ea pixel ea video. Bukana ea tšebeliso ea lihlahisoa e fana ka
lintlha tse qaqileng le litaelo mabapi le ts'ebetsong ea hardware,
ketsiso, le tšebeliso ea lisebelisoa.
Lisebelisoa tsa Hardware
DDR AXI Arbiter e etselitsoe ho hokahana le DDR-SDRAM
balaoli ba on-chip. E fana ka 64-bit AXI master interface
e nolofalletsang ho sebetsa ka potlako ha data ea pixel ea video. Mosebelisi oa sehlahisoa
bukana e fana ka tlhaloso e qaqileng ea moralo oa DDR AXI
Arbiter le ts'ebetsong ea eona ea hardware.
Ketsiso
Bukana ea mosebelisi oa sehlahisoa e fana ka litaelo tsa ho etsisa
DDR AXI Arbiter e sebelisa lisebelisoa tsa MSS SmartDesign le Testbench. Tsena
lisebelisoa li nolofalletsa mosebelisi ho netefatsa ho nepahala ha moralo le
netefatsa tshebetso e nepahetseng ya karolo ya hardware.
Tšebeliso ea Mehloli
DDR AXI Arbiter e sebelisa lisebelisoa tsa sistimi joalo ka logic
lisele, liboloko tsa memori, le lisebelisoa tsa ho tsamaisa. Mosebelisi oa sehlahisoa
bukana e fana ka tlaleho e qaqileng ea tšebeliso ea mehloli eo
e hlalosa litlhoko tsa lisebelisoa tsa DDR AXI Arbiter. Sena
tlhahisoleseding e ka sebelisoa ho etsa bonnete ba hore karolo ea hardware e ka
ho kengoa ts'ebetsong ka har'a lisebelisoa tse fumanehang tsa sistimi.
Litaelo tsa Tšebeliso ea Sehlahisoa
Litaelo tse latelang li fana ka tataiso mabapi le mokhoa oa ho sebelisa
DDR AXI Arbiter:
Mohato oa 1: Ts'ebetsong ea Hardware
Kenya tšebetsong karolo ea DDR AXI Arbiter ho sehokelo
ka DDR-SDRAM on-chip controller. Latela moralo
tlhaloso e fanoeng bukeng ea tšebeliso ea lihlahisoa ho netefatsa hore e nepahetse
phethahatso ea karolo ea hardware.
Mohato oa 2: Ketsiso
Etsisa moralo oa DDR AXI Arbiter o sebelisa MSS SmartDesign le
Lisebelisoa tsa Testbench. Latela litaelo tse fanoeng sehlahisoa
bukana ea mosebelisi ho netefatsa ho nepahala ha moralo le ho netefatsa
tshebetso e nepahetseng ya karolo ya hardware.
Mohato oa 3: Tšebeliso ea Lisebelisoa
Review tlaleho ea tšebeliso ea lisebelisoa e fanoeng sehlahisoa
bukana ea mosebelisi ho fumana litlhoko tsa lisebelisoa tsa DDR AXI
Arbiter. Etsa bonnete ba hore karolo ea hardware e ka kenngoa ts'ebetsong
ka har'a lisebelisoa tse fumanehang tsa sistimi.
Ka ho latela litaelo tsena, u ka sebelisa DDR ka katleho
Karolo ea lisebelisoa tsa AXI Arbiter bakeng sa ho boloka data ea pixel ea video le
ho sebetsa lits'ebetsong tsa video.
Tataiso ea mosebelisi ea UG0644
DDR AXI Arbiter
Hlakola 2018
DDR AXI Arbiter
Litaba
1 Revision History …………………………………………………………………………………………………………………….. 1
1.1 Phetolelo ea 5.0 ……………………………………………………………………………………………………………………………………………………………………………… 1 1.2 Phetolelo ea 4.0 …………………………………………………………………………………………………………………………………………………………………………………… 1 1.3 Phetolelo ea 3.0 ……………………………………………………………………………………………………………………………………………………………………………………… 1 1.4 Phetolelo ea 2.0 …………………………………………………………………………………………………………………………………………………………………………………… 1 1.5 Phetolelo ea 1.0 ……………………………………………………………………………………………………………………………………………………………………………………… 1
2 Selelekela ……………………………………………………………………………………………………………………….. 2 3 Hardware Ho kenngwa tshebetsong ………………………………………………………………………………………………………
3.1 ……………………………………………………………………………………………………………….. 3 3.2 Liparamente tsa Configuration ……… …………………………………………………………………………………………………. 5 3.3 Diagrams tsa Nako 13 3.4 Testbench …………………………………………………………………………………………………………………………….. 14
3.5.1 Ho etsisa MSS SmartDesign ………………………………………………………………………………………………………. 25 3.5.2 Simulating Testbench ……………………………………………………………………………………………………………. 30 3.6 Tšebeliso ea Mehloli ……………………………………………………………………………………………………………….. 31
Phetolelo ea Tataiso ea Basebelisi ea UG0644 5.0
DDR AXI Arbiter
1
Nalane ea Phetoho
Nalane ea ntlafatso e hlalosa liphetoho tse kentsoeng tšebetsong tokomaneng. Liphetoho li thathamisitsoe ka ntlafatso, ho qala ka khatiso ea morao-rao.
1.1
Phetolelo ea 5.0
Tokollong ea 5.0 ea tokomane ena, karolo ea Tšebeliso ea Mehloli le Tlaleho ea Tšebeliso ea Mehloli
li ntlafalitsoe. Ho fumana lintlha tse ling, sheba Tšebeliso ea Mehloli (sheba leqephe la 31).
1.2
Phetolelo ea 4.0
Se latelang ke kakaretso ea liphetoho tse nchafatsong ea 4.0 ea tokomane ena.
E kentse litekanyetso tsa tlhophiso ea testbench tafoleng. Bakeng sa tlhaiso-leseling e batsi, sheba Litlhophiso tsa Litlhophiso (sheba leqephe la 16) Ho fumana lintlha tse ling, sheba Testbench (sheba leqephe la 16). E ntlafalitse Tšebeliso ea Lisebelisoa bakeng sa boleng ba DDR AXI Arbiter tafoleng. Ho fumana lintlha tse ling, sheba Tšebeliso ea Mehloli (sheba leqephe la 31).
1.3
Phetolelo ea 3.0
Se latelang ke kakaretso ea liphetoho tse nchafatsong ea 3.0 ea tokomane ena.
Tlhahisoleseding e ekeditsweng ya 8-bit bakeng sa ho ngola kanale 1 le 2. Ho fumana lesedi le fetang lena, sheba Tlhaloso ya Moralo (sheba leqephe la 3). Karolo e ntlafalitsoeng ea Testbench. Ho fumana lintlha tse ling, sheba Testbench (sheba leqephe la 16).
1.4
Phetolelo ea 2.0
Phetolelong ea 2.0 ea tokomane ena, lipalo le litafole li ile tsa ntlafatsoa karolong ea Testbench.
Ho fumana lintlha tse ling, sheba Testbench (sheba leqephe la 16).
1.5
Phetolelo ea 1.0
Revision 1.0 e bile khatiso ea pele ea tokomane ena
Phetolelo ea Tataiso ea Basebelisi ea UG0644 5.0
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DDR AXI Arbiter
2
Selelekela
Mehopolo ke karolo ea bohlokoa ea ts'ebeliso efe kapa efe e tloaelehileng ea video le litšoantšo. Li sebelisetsoa ho boloka data ea pixel ea video. E 'ngoe e tloaelehileng ea buffer exampLe ke li-buffer tsa foreimi eo ho eona data e felletseng ea pixel ea video bakeng sa foreime e kenngoeng mohopolong.
Dual data rate (DDR) -synchronous DRAM (SDRAM) ke e 'ngoe ea mehopolo e sebelisoang hangata lits'ebetsong tsa video bakeng sa ho buffer. SDRAM e sebelisoa ka lebaka la lebelo la eona le hlokahalang bakeng sa ts'ebetso e potlakileng lits'ebetsong tsa video.
Setšoantšo se latelang se bontša motho oa mehlengample setšoantšo sa boemo ba sistimi sa DDR-SDRAM se hokahanang le ts'ebeliso ea video.
Setšoantšo sa 1 · DDR-SDRAM Memory Interfacing
Ho Microsemi SmartFusion®2 System-on-Chip (SoC), ho na le li-controller tse peli tsa on-chip tsa DDR tse nang le 64-bit advanced extensible interface (AXI) le 32-bit e tsoetseng pele ea ts'ebetso e phahameng ea libese (AHB) lihokelo tsa makhoba tse lebisang lebaleng le ka lokisoang. lesela la heke (FPGA) lesela. Khokahano e kholo ea AXI kapa AHB ea hlokahala ho bala le ho ngola memori ea DDR-SDRAM e hokahantsoeng le balaoli ba on-chip DDR.
Phetolelo ea Tataiso ea Basebelisi ea UG0644 5.0
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DDR AXI Arbiter
3
Lisebelisoa tsa Hardware
3.1
Tlhaloso ea Moralo
DDR AXI Arbiter e fana ka 64-bit AXI master interface ho DDR-SDRAM on-chip controller ea.
Lisebelisoa tsa SmartFusion2. DDR AXI Arbiter e na le liteishene tse 'ne tse baloang le liteishene tse peli tsa ho ngola tse lebisang ho
mohopolo oa mosebelisi. The block arbitrates between the four read channels ho fana ka phihlello ea ho bala AXI
mocha ka mokhoa o chitja. Ha feela kopo ea ho bala ea mocha oa 1 e le holimo, AXI
bala kanale e abetsoe ho eona. Buka ea 1 ea ho bala e na le bophara bo tsitsitseng ba data ea 24-bit. Bala likanale 2, 3,
'me 4 e ka hlophisoa e le bophara ba 8-bit, 24-bit, kapa 32-bit ea tlhahiso ea data. Sena se khethoa ke lefats'e
tlhophiso parameter.
The block e boetse e arbitrates lipakeng tsa liteishene tse peli tsa ho ngola ho fana ka phihlello ea mocha oa ho ngola oa AXI ka mokhoa o pota-potileng. Likanale ka bobeli li na le bohlokoa bo lekanang. Ngola kanale 1 le 2 e ka hlophisoa hore e be bophara ba data ea 8-bit, 24-bit, kapa 32-bit.
Phetolelo ea Tataiso ea Basebelisi ea UG0644 5.0
3
DDR AXI Arbiter
Setšoantšo se latelang se bontša setšoantšo sa boemo bo holimo sa pin-out sa DDR AXI Arbiter. Setšoantšo sa 2 · Setšoantšo sa Block-Level Block Diagram ea DDR AXI Arbiter Block
Phetolelo ea Tataiso ea Basebelisi ea UG0644 5.0
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DDR AXI Arbiter
Setšoantšo se latelang se bonts'a setšoantšo sa "block block" ea boemo bo holimo ea sistimi e nang le block ea DDR AXI Arbiter e kentsoeng sesebelisoa sa SmartFusion2. Setšoantšo sa 3 · Setšoantšo sa Block-Level Block Diagram ea DDR AXI Arbiter ho SmartFusion2 Device
3.2
Lintho tse kenang le tse hlahisoang
Tafole e latelang e thathamisa likou tsa ho kenya le tse tsoang ho DDR AXI Arbiter.
Letlapa la 1 · Maeke a Kenyellelitsoeng le a Liphetho a DDR AXI Arbiter
Lebitso la Letsoao RESET_N_I
Mokhoa oa ho kenya
Bophara
SYS_CLOCK_I BUFF_READ_CLOCK_I
Kenyo
rd_req_1_i rd_ack_o
Khumo ea ho kenya
rd_done_1_o qala_read_addr_1_i
Keletso Input
li-byte_to_bala_1_i
Kenyeletso
video_rdata_1_o
Sephetho
[(g_AXI_AWIDTH-1):0] [(g_RD_CHANNEL1_AXI_BUFF_ AWIDTH + 3) – 1 : 0] [(g_RD_CHANNEL1_VIDEO_DATA_WIDTH1):0]Tlhaloso
Lets'oao le sebetsang le tlase la asynchronous reset ho moralo
Ts'ebetso ea nako
Ngola oache ea ho bala ea "buffer" ea kahare, e tlameha ho ba habeli ho feta SYS_CLOCK_I
Bala kopo e tsoang ho Master 1
Kamohelo ea Arbiter ea ho bala kopo e tsoang ho Master 1
Bala phetho ho Master 1
Aterese ea DDR moo ho lokelang ho qaloa ho baloa mocha oa 1
Li-byte li tla baloa ho tsoa ho mocha oa 1
Tlhahiso ea data ea video ho tsoa ho mocha oa 1
Phetolelo ea Tataiso ea Basebelisi ea UG0644 5.0
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DDR AXI Arbiter
Lebitso la Letshwao rdata_valid_1_o rd_req_2_i rd_ack_2_o
rd_done_2_o qala_read_addr_2_i
li-byte_to_bala_2_i
video_rdata_2_o
rdata_valid_2_o rd_req_3_i rd_ack_3_o
rd_done_3_o qala_read_addr_3_i
li-byte_to_bala_3_i
video_rdata_3_o
rdata_valid_3_o rd_req_4_i rd_ack_4_o
rd_done_4_o qala_read_addr_4_i
li-byte_to_bala_4_i
video_rdata_4_o
rdata_valid_4_o wr_req_1_i wr_ack_1_o
wr_done_1_o qala_write_addr_1_i
li-byte_ho_ngola_1_i
video_wdata_1_i
wdata_valid_1_i wr_req_2_i
Taelo Output Input
Keletso Input
Kenyeletso
Sephetho
Sehlahisoa se Hlahang
Keletso Input
Kenyeletso
Sephetho
Sehlahisoa se Hlahang
Keletso Input
Kenyeletso
Sephetho
Sehlahisoa se Hlahang
Keletso Input
Kenyeletso
Kenyeletso
Kenyo
Bophara
[(g_AXI_AWIDTH-1):0] [(g_RD_CHANNEL2_AXI_BUFF_AWIDTH + 3) – 1 : 0] [(g_RD_CHANNEL2_VIDEO_DATA_WIDTH1):0] [(g_AXI_AWIDTH-1)_FFRID_0):3] – 3 : 1] [(g_RD_CHANNEL0_VIDEO_DATA_WIDTH3 ):1] [(g_AXI_AWIDTH-0):1] [(g_RD_CHANNEL0_AXI_BUFF_AWIDTH + 4) – 3 : 1] [(g_RD_CHANNEL0_VIDEO_DATA_WIDTH4):1] [(g_AXI_AWIDR_AWIDTH_FF_0) + 1) - 0: 1 ] [(g_WR_CHANNEL3_VIDEO_DATA_WIDTH1):0]
Tlhaloso Bala data e sebetsang ho tsoa ho kanaleng e baloang 1 Bala kopo ho tsoa ho Master 2 Arbiter acknowledgement ho bala kopo ho tsoa ho Master 2 Read completion to Master 2 DDR address ho tloha moo ho baloang ho tlamehang ho qalisoa bakeng sa ho baloa kanale 2 Byte ho baloa ho tsoa ho data ea kanale ea 2 Video tlhahiso ho tswa ho kanale e balwang 2 Bala data e sebetsang ho tswa ho kanaleng e balwang 2 Bala kopo ho tswa ho Master 3 Arbiter acknowledgment ho bala kopo ho tswa ho Master 3 Read completion to Master 3 DDR address ho tloha moo ho lokelang ho qaloa ho bala mocha 3 Byte ho baloa ho tsoa ho bala kanale 3 Poelo ya data ya video ho tswa ho kanale e balwang 3 Bala data e sebetsang ho tswa ho kanaleng e balwang 3 Bala kopo ho tswa ho Master 4 Arbiter acknowledgment ho bala kopo ho tswa ho Master 4 Read completion to Master 4 DDR address ho tloha moo ho baloang ho tlamehang ho qalisoa bakeng sa ho bala mocha 4 Byte ho ba bala ho tsoa ho bala mocha 4 Video data output from read channel 4 Bala data e nepahetseng ho tloha ho bala mocha 4 Ngola kopo e tsoang ho Master 1 Arbiter acknowledgment ea ho ngola kopo e tsoang ho Master 1 Ngola phetho ho Master 1 DDR aterese eo ho ngola ho lokelang ho etsahala ho tloha ho ngola mocha 1 Li-byte tse tla ngoloa ho tsoa ho kanale ea ho ngola 1 Lintlha tsa video Kenyo ea ho ngola kanale 1
Ngola data e sebetsang ho ngola kanale 1 Ngola kopo ho tsoa ho Master 1
Phetolelo ea Tataiso ea Basebelisi ea UG0644 5.0
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DDR AXI Arbiter
Lebitso la Letshwao wr_ack_2_o
Sephetho sa Tataiso
wr_done_2_o qala_write_addr_2_i
Keletso Input
li-byte_ho_ngola_2_i
Kenyeletso
video_wdata_2_i
Kenyeletso
wdata_valid_2_i AXI I/F matshwao Bala Aterese Channel m_arid_o
Khumo ea ho kenya
m_araddr_o
Sephetho
m_arlen_o
Sephetho
m_arsize_o m_arburst_o
Sephetho
m_arlock_o
Sephetho
m_arcache_o
Sephetho
m_arprot_o
Sephetho
Bophara
[(g_AXI_AWIDTH-1):0] [(g_WR_CHANNEL2_AXI_BUFF_AWIDTH + 3) – 1 : 0] [(g_WR_CHANNEL2_VIDEO_DATA_WIDTH1):0]
Tlhaloso ea Arbiter tumello ea ho ngola kopo e tsoang ho Master 2 Ngola phetho ho Master 2 DDR aterese eo ho ngolloang ho lokelang ho etsahala ho tloha ho ngola mocha 2 Byte e lokelang ho ngoloa ho tloha ho ngola mocha 2 Boitsebiso ba video Input ho ngola mocha 2
Ngola lintlha tse loketseng ho ngola mocha oa 2
Bala ID ea aterese. Boitsebiso tag bakeng sa sehlopha sa liaterese se baloang sa matšoao.
Bala aterese. E fana ka aterese ea pele ea khoebo e baloang. Ke feela aterese ea ho qala ea ho phatloha ho fanoang.
Bolelele ba ho phatloha. E fana ka palo e nepahetseng ea phetisetso ka ho phatloha. Lintlha tsena li lekanya palo ea phetisetso ea data e amanang le aterese
Boholo ba ho phatloha. Boholo ba phetiso e 'ngoe le e 'ngoe ka ho phatloha
Mofuta oa ho phatloha. Ha mmoho le tlhahisoleseling ea boholo, lintlha tsa hore na aterese ea phetiso e 'ngoe le e' ngoe ka har'a ho phatloha e baloa joang.
E tsitsitse ho 2'b01 à Ho phatloha ha aterese ea Keketso
Mofuta oa senotlolo. E fana ka lintlha tse eketsehileng mabapi le litšobotsi tsa athomo tsa phetiso.
E tsitsitse ho 2'b00 à Tloaelo ea Phihlello
Mofuta oa cache. E fana ka tlhahisoleseding e eketsehileng mabapi le likarolo tsa cacheable tsa phetisetso.
E tsepamisitsoe ho 4'b0000 à Non-cacheable le non-bufferable
Mofuta oa tšireletso. E fana ka tlhaiso-leseling ea yuniti ea ts'ireletso bakeng sa khoebo.
E tsitsitse ho 3'b000 à Tloaelehileng, phihlello e sireletsehileng ea data
Phetolelo ea Tataiso ea Basebelisi ea UG0644 5.0
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DDR AXI Arbiter
Lebitso la Letshwao m_arvalid_o
Sephetho sa Tataiso
Bophara
m_arready_ke
Kenyeletso
Bala Lenaneo la Boitsebiso
m_rid_i
Kenyeletso
[3:0]m_rdata_i m_rresp_i
m_rlast_i m_rvalid_i
Kenyo
[(g_AXI_DWIDTH-1):0] [1:0]Kenyo
m_ready_o
Sephetho
Ngola Aterese Channel
m_awid_o
Sephetho
m_awaddr_o
Sephetho
[3:0] [(g_AXI_AWIDTH-1):0]Phetolelo ea Tataiso ea Basebelisi ea UG0644 5.0
Tlhaloso Bala aterese e nepahetse.
Ha HIGH, aterese e baloang le tlhaiso-leseling ea taolo e nepahetse 'me e lula e le holimo ho fihlela letšoao la ho amohela aterese, m_arready, le phahame.
`1' = Boitsebiso ba aterese le taolo bo nepahetse
`0′ = Boitsebiso ba aterese le taolo ha bo sebetse. Bala aterese e lokile. Lekhoba le itokiselitse ho amohela aterese le matšoao a amanang le taolo:
1 = lekhoba le itokisitse
0 = lekhoba le sa itokisetsa.
Bala ID tag. ID tag ea sehlopha sa data se baloang sa matšoao. Theko ea m_rid e hlahisoa ke Lekhoba 'me e tlameha ho ts'oana le boleng ba m_rid ea transaction e baloang eo le e arabelang. Bala data. Bala karabo.
Boemo ba phetiso e balwang. Likarabo tse lumelletsoeng ke OK, EXOKAY, SLVERR, le DECRR. Bala qetellong.
Phetisetso ea ho qetela ka ho phatloha ho hoholo. Bala ho nepahetse. Lintlha tse hlokahalang tsa ho bala lia fumaneha, 'me phetisetso ea ho bala e ka phethela:
1 = bala lintlha tse fumanehang
0 = bala data ha e fumanehe. Bala o itokisitse. Master a ka amohela lintlha tse baloang le tlhaiso-leseling ea karabo:
1= monghali o itokisitse
0 = monghali ha a itokisetsa.
Ngola aterese ea ID. Boitsebiso tag bakeng sa sehlopha sa liaterese tsa ho ngola sa matšoao. Ngola aterese. E fana ka aterese ea phetisetso ea pele molemong oa ho ngola. Lipontšo tse amanang le taolo li sebelisoa ho fumana liaterese tsa phetisetso e setseng nakong ea ho phatloha.
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DDR AXI Arbiter
Lebitso la Letshwao m_awlen_o
Sephetho sa Tataiso
Bophara [3:0]
m_awsize_o
Sephetho
[2:0]m_awburst_o
Sephetho
[1:0]m_awlock_o
Sephetho
[1:0]m_awcache_o
Sephetho
[3:0]m_awprot_o
Sephetho
[2:0]m_awvalid_o
Sephetho
Tlhaloso
Bolelele ba ho phatloha. E fana ka palo e nepahetseng ea phetisetso ka ho phatloha. Lintlha tsena li lekanya palo ea phetisetso ea data e amanang le aterese.
Boholo ba ho phatloha. Boholo ba phetiso e 'ngoe le e 'ngoe ka ho phatloha. Li-byte lane strobe li bontša hantle hore na ke litsela life tse lokelang ho ntlafatsoa.
E tsitsitse ho 3'b011 à 8 byte ka phetiso ea data kapa phetiso ea 64-bit
Mofuta oa ho phatloha. Ha mmoho le tlhahisoleseling ea boholo, lintlha tsa hore na aterese ea phetiso e 'ngoe le e' ngoe ka har'a ho phatloha e baloa joang.
E tsitsitse ho 2'b01 à Ho phatloha ha aterese ea Keketso
Mofuta oa senotlolo. E fana ka lintlha tse eketsehileng mabapi le litšobotsi tsa athomo tsa phetiso.
E tsitsitse ho 2'b00 à Tloaelo ea Phihlello
Mofuta oa cache. E bonts'a lintho tse ka khonehang, tse ka bolokoang, tse ngoloang, ho ngola, le ho fana ka litšobotsi tsa khoebo.
E tsepamisitsoe ho 4'b0000 à Non-cacheable le non-bufferable
Mofuta oa tšireletso. E bonts'a boemo bo tloaelehileng, bo khethehileng, kapa bo sireletsehileng ba ts'ireletso ea khoebo le hore na khoebo ke phihlello ea data kapa phihlello ea litaelo.
E tsitsitse ho 3'b000 à Tloaelehileng, phihlello e sireletsehileng ea data
Ngola aterese e nepahetse. E bontša hore aterese e nepahetseng ea ho ngola le taolo
lintlha li teng:
1 = aterese le tlhaiso-leseling e fumanehang
0 = aterese le tlhaiso-leseling ea taolo ha e fumanehe. Aterese le lintlha tsa taolo li lula li tsitsitse ho fihlela aterese e amohela letšoao, m_awready, e ea HIGH.
Phetolelo ea Tataiso ea Basebelisi ea UG0644 5.0
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DDR AXI Arbiter
Lebitso la Letshwao m_awready_i
Mokhoa oa ho kenya
Bophara
Ngola Data Channel
m_wid_o
Sephetho
[3:0]m_wdata_o m_wstrb_o
Sephetho
[(g_AXI_DWIDTH-1):0]AXI_DWDITH parameter[7:0]
m_wlast_o m_wvalid_o
Sephetho
m_wready_i
Kenyeletso
Ngola Lipontšo tsa Channel ea Karabo
m_bid_i
Kenyeletso
[3:0]m_bresp_i m_bvalid_i
Kenyeletso
[1:0]Kenyeletso
m_breaddy_o
Sephetho
Tlhaloso Ngola aterese e lokile. E bontša hore lekhoba le se le loketse ho amohela aterese le matšoao a amanang le taolo:
1 = lekhoba le itokisitse
0 = lekhoba le sa itokisetsa.
Ngola ID tag. ID tag ea phetiso ea data. Theko ea m_wid e tlameha ho ts'oana le boleng ba m_awid ba transashene e ngoloang. Ngola lintlha
Ngola strobes. Letšoao lena le bontša hore na ke litsela life tse lokelang ho ntlafatsoa mohopolong. Ho na le strobe e le 'ngoe bakeng sa likotoana tse robeli tsa bese ea data Ngola ho qetela. Phetiso ea ho qetela ka ho phatloha ho hoholo. Ngola e nepahetse. Lintlha tse nepahetseng tsa ho ngola le li-strobe lia fumaneha:
1 = ngola data le strobes fumaneha
0 = ngola data le strobes ha li fumanehe. Ngola o itokisitse. Lekhoba le ka amohela lintlha tsa ho ngola: 1 = lekhoba le itokisitse
0 = lekhoba le sa itokisetsa.
ID ea karabo. Boitsebiso tag ea karabo ea ho ngola. Theko ea m_bid e tlameha ho lumellana le boleng ba m_awid ba transaction e ngotsoeng eo lekhoba le arabelang ho eona. Ngola karabo. Boemo ba ho ngola transaction. Likarabo tse lumelletsoeng ke OK, EXOKAY, SLVERR, le DECRR. Ngola karabo e nepahetse. Karabo e nepahetseng ea ho ngola e teng:
1 = ngola karabo e fumanehang
0 = ho ngola karabo ha e fumanehe. Karabo e lokile. Monghali a ka amohela lintlha tsa karabo.
1 = monghali o itokisitse
0 = monghali ha a itokisetsa.
Setšoantšo se latelang se bontša setšoantšo sa block block sa DDR AXI arbiter.
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Setšoantšo se latelang se bontša setšoantšo sa block block sa DDR AXI arbiter. Setšoantšo sa 4 · Setšoantšo sa Block Block sa DDR AXI Arbiter
Seteishene se seng le se seng se baloang sea qala ha se fumana lets'oao le phahameng la ho kenya ho read_req_(x)_i input. Ebe joale
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Seteishene se seng le se seng se baloang sea qala ha se fumana lets'oao le phahameng la ho kenya ho read_req_(x)_i input. Joale e sampka tlase ho aterese ea AXI e qalang le li-byte tsa ho bala lintho tse kentsoeng tse tsoang ho master ea kantle. Lenaneo le ananela molaoli oa kantle ka ho toggle read_ack_(x)_o. Seteishene se sebetsana le lintho tse kenang 'me se hlahisa litšebelisano tse hlokahalang tsa AXI ho bala data ho tsoa ho DDR-SDRAM. Lintlha tse baloang ka sebopeho sa 64-bit AXI li bolokoa ka har'a buffer ea kahare. Ka mor'a hore lintlha tse hlokahalang li baloe 'me li bolokoe ka har'a buffer e ka hare, mojule oa un-packer oa lumelloa. Mojule oa un-packer o manolla lentsoe le leng le le leng la 64-bit ho bolelele ba bonyenyane ba data bo hlokehang bakeng sa kanale eo bakeng sa ex.ample haeba kanale e hlophisitsoe joalo ka bophara ba data ea 32-bit, lentsoe le leng le le leng la 64-bit le romelloa joalo ka mantsoe a mabeli a tlhahiso ea 32-bit. Bakeng sa kanale ea 1 e leng kanale ea 24-bit, un-packer e manolla lentsoe le leng le le leng la 64-bit ho data ea tlhahiso ea 24-bit. Kaha 64 ha se palo ea 24, un-packer bakeng sa mocha o baloang oa 1 o kopanya sehlopha sa mantsoe a mararo a 64-bit ho hlahisa mantsoe a robeli a 24-bit. Sena se beha tšitiso ho mocha o baloang oa 1 hore li-byte tsa data tse kopiloeng ke mong'a kantle li lokela ho aroloa ka 8. Bala likanale 2, 3, le 4 li ka hlophisoa joalo ka bophara ba data ba 8-bit, 24bit le 32-bit, e leng. e khethoa ke g_RD_CHANNEL(X) _VIDEO_DATA_WIDTH paramethara ea tlhophiso. Haeba li hlophisitsoe e le 24-bit, lithibelo tse boletsoeng ka holimo li tla sebetsa ho e 'ngoe le e 'ngoe ea tsona. Empa haeba li hlophisitsoe joalo ka 8-bit kapa 32-bit, ha ho na tšitiso e joalo kaha 64 e atisa ho 32 le 8. Maemong ana, lentsoe le leng le le leng la 64-bit le thathamisitsoe ho mantsoe a mabeli a 32-bit kapa a robeli 8. -bit data mantsoe.
Bala Channel 1 e notlolla mantsoe a data a 64-bit a baloang ho DDR-SDRAM ho isa ho mantsoe a data a 24-bit ka lihlopha tsa mantsoe a 48 64-bit, e leng nako le nako ha mantsoe a 48 64-bit a fumaneha ka har'a buffer ea kahare ea mocha oa 1, un-packer e qala ho li phutha ho fana ka data ea 24-bit ea tlhahiso. Haeba li-byte tsa data tse kopiloeng hore li baloe li le ka tlase ho mantsoe a 48 64-bit, "un-packer" e lumelloa feela kamora hore data e felletseng e baloe ho DDR-SDRAM. Ho liteishene tse tharo tse setseng tse baloang, motho ea sa paketeng o qala ho romella data e baloang feela kamora hore palo e felletseng ea li-byte e baloe ho tsoa ho DDR-SDRAM.
Ha mocha oa ho bala o lokiselitsoe bophara ba 24-bit, aterese ea ho qala ho bala e tlameha ho amahanngoa le moeli oa 24-byte. Sena sea hlokeha ho khotsofatsa tšitiso ea hore motho ea sa paketeng a lokolle sehlopha sa mantsoe a mararo a 64-bit ho hlahisa mantsoe a robeli a 24-bit.
Liteishene tsohle tse baloang li hlahisa sephetho se baloang ho mong'a kantle ka mor'a hore li-byte tse kopiloeng li romelloe ho master ea kantle.
Tabeng ea liteishene tsa ho ngola, monghali oa kantle o tlameha ho kenya data e hlokahalang mocha o itseng. Seteishene sa ho ngola se nka data e kentsoeng ebe se e paka mantsoeng a 64-bit ebe se e boloka polokelong ea kahare. Kamora hore data e hlokahalang e bolokoe, monghali oa kantle o tlameha ho fana ka kopo ea ho ngola hammoho le aterese ea ho qala le li-byte ho ngola. Ho sampling tse kenyang tsena, mocha oa ho ngola o amohela monghali oa kantle. Kamora sena, seteishene se hlahisa li-transaction tsa AXI ho ngola data e bolokiloeng ho DDR-SDRAM. Liteishene tsohle tsa ho ngola li hlahisa mongolo o entsoeng ho mong'a kantle hang ha li-byte tse kopiloeng li ngotsoe ho DDR-SDRAM. Ka mor'a hore kopo ea ho ngola e fuoe mocha ofe kapa ofe oa ho ngola, lintlha tse ncha ha lia lokela ho ngoloa seteisheneng sa ho ngola, ho fihlela phetiso ea hona joale ea transaction e bontšoa ke wr_done_(x)_o
Ngola mecha ea 1 le ea 2 e ka hlophisoa hore e be 8-bit, 24-bit, le 32-bit bophara ba data, e lekanyelitsoeng ke g_WR_CHANNEL(X)_VIDEO_DATA_WIDTH paramethara ea linetefatso tsa lefatše. Haeba li hlophisitsoe e le 24bit, joale li-byte tse lokelang ho ngoloa li tlameha ho ba tse ngata ho tse robeli kaha sephutheloana sa ka hare se paka mantsoe a robeli a 24-bit ho hlahisa mantsoe a mararo a 64-bit. Empa haeba li hlophisitsoe joalo ka 8-bit kapa 32-bit, ha ho na tšitiso e joalo.
Bakeng sa kanale ea 32-bit, bonyane mantsoe a mabeli a 32-bit a tlameha ho baloa. Bakeng sa kanale ea 8-bit, bonyane mantsoe a 8-bit a hloka ho baloa, hobane ha ho na padding e fanoeng ke mojule oa arbiter. Likanaleng tsohle tsa ho bala le ho ngola, botebo ba li-buffers tse ka hare ke tse ngata ho feta bophara bo otlolohileng ba pontšo. Botebo ba ka hare ba buffer bo baloa ka tsela e latelang:
g_RD_CHANNEL(X)_HORIZONTAL_RESOLUTION* g_RD_CHANNEL(X)_VIDEO_DATA_WIDTH * g_RD_CHANNEL(X)_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Moo, X = Nomoro ea kanale
Bophara ba buffer ea ka hare bo khethoa ke AXI data bus wide ke hore, paramethara ea tlhophiso
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Bophara ba buffer ea kahare bo khethoa ke AXI data bus wide, ke hore, paramethara ea tlhophiso g_AXI_DWIDTH.
Litšebelisano tsa AXI tsa ho bala le ho ngola li etsoa ho latela litlhaloso tsa ARM AMBA AXI. Boholo ba transaction bakeng sa phetiso e 'ngoe le e' ngoe ea data bo tsitsitse ho 64-bit. Sebaka se hlahisa litšebelisano tsa AXI tsa bolelele bo tsitsitseng ba li-beats tse 16. Sebaka se boetse se hlahloba hore na ho phatloha ho hong ho tšela moeli oa aterese ea AXI ea 4 KByte. Haeba ho phatloha ho le leng ho tšela moeli oa 4 KByte, ho phatloha ho aroloa ka 2 ho phatloha moeling oa 4 KByte.
3.3
Li-Parameters tsa Tlhophiso
Tafole e latelang e thathamisa mekhahlelo ea tlhophiso e sebelisoang ts'ebetsong ea hardware ea DDR AXI Arbiter. Tsena ke li-parameter tse akaretsang 'me li ka fapana ho latela litlhoko tsa kopo.
Letlapa la 2 · Litlhophiso tsa ho hlophisa
Lebitso g_AXI_AWIDTH g_AXI_DWIDTH g_RD_CHANNEL1_AXI_BUFF_AWIDTH
g_RD_CHANNEL2_AXI_BUFF_AWIDTH
g_RD_CHANNEL3_AXI_BUFF_AWIDTH
g_RD_CHANNEL4_AXI_BUFF_AWIDTH
g_WR_CHANNEL1_AXI_BUFF_AWIDTH
g_WR_CHANNEL2_AXI_BUFF_AWIDTH
g_RD_CHANNEL1_HORIZONTAL_RESOLUTION g_RD_CHANNEL2_HORIZONTAL_RESOLUTION g_RD_CHANNEL3_HORIZONTAL_RESOLUTION g_RD_CHANNEL4_HORIZONTAL_RESOLUTION g_WR_CHANNEL1_HORIZONTAL_RESOLUTION g_RD_CHANNEL2_HORIZONTAL_RESOLUTION g_WR_CHANNEL1_HORIZONTAL_RESOLUTION_RESOLUTION RD_CHANNEL2_VIDEO_DATA_WIDTH g_RD_CHANNEL3_VIDEO_DATA_WIDTH g_RD_CHANNEL4_VIDEO_DATA_WIDTH g_RD_CHANNEL1_VIDEO_DATA_WIDTH g_WR_CHANNEL2_VIDEO_DATA_WIDTH_WIDTH_CHANNELD_CHANNELD_VIDEO_VIDEO_WIDTH g_WR_CHANNELD_CHANNEL1 LILEMO
Tlhaloso
AXI aterese bophara ba libese
AXI data bese bophara ba
Bophara ba libese bakeng sa buffer ea kahare ea Channel 1, e bolokang data e baloang ea AXI.
Bophara ba libese bakeng sa buffer ea kahare ea Channel 2, e bolokang data e baloang ea AXI.
Bophara ba libese bakeng sa buffer ea kahare ea Channel 3, e bolokang data e baloang ea AXI.
Bophara ba libese bakeng sa buffer ea kahare ea Channel 4, e bolokang data e baloang ea AXI.
Bophara ba libese bakeng sa buffer ea kahare ea Channel 1, e bolokang data ea ho ngola ea AXI.
Bophara ba libese bakeng sa buffer ea kahare ea Channel 2, e bolokang data ea ho ngola ea AXI.
Pontšo ea video e otlolohileng bakeng sa ho baloa Channel 1
Pontšo ea video e otlolohileng bakeng sa ho baloa Channel 2
Pontšo ea video e otlolohileng bakeng sa ho baloa Channel 3
Pontšo ea video e otlolohileng bakeng sa ho baloa Channel 4
Pontšo ea video e otlolohileng bakeng sa ho ngola Channel 1
Pontšo ea video e otlolohileng bakeng sa ho ngola Channel 2
Bala Channel 1 video output bit wide
Bala Channel 2 video output bit wide
Bala Channel 3 video output bit wide
Bala Channel 4 video output bit wide
Ngola Channel 1 video Input bit width.
Ngola Channel 2 video Input bit width.
Botebo ba "buffer" ea kahare bakeng sa ho baloa Channel 1 ho latela palo ea mela e tšekaletseng ea pontšo. Botebo ba "buffer" ke g_RD_CHANNEL1_HORIZONTAL_RESOLUTION * g_RD_CHANNEL1_VIDEO_DATA_WIDTH * g_RD_CHANNEL1_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
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3.4
Lebitso g_RD_CHANNEL2_BUFFER_LINE_STORAGE g_RD_CHANNEL3_BUFFER_LINE_STORAGE g_RD_CHANNEL4_BUFFER_LINE_STORAGE g_WR_CHANNEL1_BUFFER_LINE_STORAGE g_WR_CHANNEL2_BUFFER_LINE_STORAGE
Tlhaloso
Botebo ba "buffer" ea kahare bakeng sa ho baloa Channel 2 ho latela palo ea mela e tšekaletseng ea pontšo. Botebo ba "buffer" ke g_RD_CHANNEL2_HORIZONTAL_RESOLUTION * g_RD_CHANNEL2_VIDEO_DATA_WIDTH * g_RD_CHANNEL2_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Botebo ba "buffer" ea kahare bakeng sa ho baloa Channel 3 ho latela palo ea mela e tšekaletseng ea pontšo. Botebo ba "buffer" ke g_RD_CHANNEL3_HORIZONTAL_RESOLUTION * g_RD_CHANNEL3_VIDEO_DATA_WIDTH * g_RD_CHANNEL3_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Botebo ba "buffer" ea kahare bakeng sa ho baloa Channel 4 ho latela palo ea mela e tšekaletseng ea pontšo. Botebo ba "buffer" ke g_RD_CHANNEL4_HORIZONTAL_RESOLUTION * g_RD_CHANNEL4_VIDEO_DATA_WIDTH * g_RD_CHANNEL4_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Botebo ba buffer ea ka hare bakeng sa ho ngola Channel 1 ho latela palo ea mela e tšekaletseng ea pontšo. Botebo ba "buffer" ke g_WR_CHANNEL1_HORIZONTAL_RESOLUTION * g_WR_CHANNEL1_VIDEO_DATA_WIDTH * g_WR_CHANNEL1_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Botebo ba buffer ea ka hare bakeng sa ho ngola Channel 2 ho latela palo ea mela e tšekaletseng ea pontšo. Botebo ba "buffer" ke g_WR_CHANNEL2_HORIZONTAL_RESOLUTION * g_WR_CHANNEL2_VIDEO_DATA_WIDTH * g_WR_CHANNEL2_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Litšoantšo tsa Nako
Palo e latelang e bonts'a khokahano ea lintlha tsa kopo ea ho bala le ho ngola, aterese ea memori ea ho qala, li-byte tsa ho bala kapa ho ngola lintlha tse tsoang ho master ea kantle, kananelo ea ho bala kapa ho ngola, le ho bala kapa ho ngola liphetho tse felletseng tse fanoeng ke mohanyetsi.
Setšoantšo sa 5 · Sets'oants'o sa Nako bakeng sa Lipontšo tse Sebelisitsoeng ho Ngola/Ho bala ka AXI Interface
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Setšoantšo se latelang se bontša kamano pakeng tsa boitsebiso ba ho ngola boitsebiso bo tsoang ho monghali oa kantle hammoho le boitsebiso ba data bo sebetsang bakeng sa liteishene tse peli tsa ho ngola. Setšoantšo sa 6 · Sets'oants'o sa Nako bakeng sa ho Ngola polokelong ea ka Hare
Setšoantšo se latelang se bontša kamano pakeng tsa tlhahiso ea data e baloang ho ea ho mong'a kantle hammoho le tlhahiso ea data e sebetsang bakeng sa liteishene tsohle tse baloang 2, 3, le 4. Setšoantšo sa 7 · Sets'oants'o sa Nako bakeng sa Boitsebiso bo Amoheletsoeng ka DDR AXI Arbiter bakeng sa Liteishene tse Baloang 2, 3. , le 4
Setšoantšo se latelang se bontša kamano pakeng tsa tlhahiso ea data e baloang bakeng sa Channel 1 e baloang ha g_RD_CHANNEL 1_HORIZONTAL_RESOLUTION e feta 128 (tabeng ena = 256). Setšoantšo sa 8 · Sets'oants'o sa Nako bakeng sa Lintlha tse Fumanetsoeng ka DDR AXI Arbiter Bala Channel 1 (e kholo ho feta 128 byte)
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Setšoantšo se latelang se bontša kamano pakeng tsa tlhahiso ea data e baloang bakeng sa Channel 1 e baloang ha g_RD_CHANNEL 1_HORIZONTAL_RESOLUTION e ka tlase ho kapa e lekana le 128 (tabeng ena = 64). Setšoantšo sa 9 · Sets'oants'o sa Nako bakeng sa Boitsebiso bo Amoheletsoeng ka DDR AXI Arbiter Bala Channel 1 (e ka tlaase ho kapa e lekanang le 128 byte)
3.5
Testbench
Ho fanoa ka testbench ho lekola ts'ebetso ea mantlha ea DDR Arbiter. Tafole e latelang e thathamisa liparamente tse ka hlophisoang ho latela ts'ebeliso.
Letlapa la 3 · Litekanyetso tsa Configuration tsa Testbench
Lebitso IMAGE_1_FILE_NAME IMAGE_2_FILE_NAME g_DATA_WIDTH WIDTH BOEMO
Tlhaloso Kenyeletso file lebitso la setšoantšo se tla ngoloa ke kanale ea ho ngola 1 Kenyo file lebitso bakeng sa setšoantšo se lokelang ho ngoloa ke mocha oa ho ngola 2 Bophara ba data ea video ea mocha oa ho bala kapa oa ho ngola Qeto e otlolohileng ea setšoantšo e lokelang ho ngoloa le ho baloa ke mecha ea ho ngola le ho bala Qeto e otlolohileng ea setšoantšo e lokelang ho ngoloa le ho baloa ke mongolo le ho bala. dikanale
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Mehato e latelang e hlalosa hore na testbench e sebelisoa joang ho etsisa mantlha ka Libero SoC. 1. Fesetereng ya Phallo ya Moralo, tobetsa ka ho le letona ho Create SmartDesign ebe o tobetsa Matha ho theha SmartDesign.
Setšoantšo sa 10 · Etsa SmartDesign
2. Kenya lebitso la moralo o mocha e le video_dma ka lebokoseng la puisano la Create New SmartDesign ebe o tobetsa OK. SmartDesign e entsoe, 'me seile se hlahisoa ka ho le letona la fenstere ea Phallo ea Moralo.
Setšoantšo sa 11 · Ho reha SmartDesign
3. Fensetereng ea Catalog, atolosa Tharollo-Video le hula-le-ho theola SF2 DDR Memory Arbiter ho SmartDesign canvas.
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Setšoantšo sa 12 · DDR Memory Arbiter ho Libero SoC Catalog
DDR Memory Arbiter Core e bonts'itsoe, joalo ka ha ho bonts'itsoe setšoantšong se latelang. Tobetsa habeli konokono ho lokisa arbiter haeba ho hlokahala.
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Setšoantšo sa 13 · DDR Memory Arbiter Core ho SmartDesign Canvas
4. Khetha likou tsohle tsa mantlha 'me u tobetse ka ho le letona ebe u tobetsa Promote to Top Level, joalokaha ho bontšitsoe ho
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4. Khetha likou tsohle tsa mantlha 'me u tobetse ka ho le letona ebe u tobetsa Khothalletsa ho Boemo bo Phahameng, joalokaha ho bontšitsoe setšoantšong se latelang. Setšoantšo sa 14 · Phahamisa ho Khetho ea Boemo bo Phahameng
Netefatsa hore o phahamiselitse likou tsohle ho ea maemong a holimo pele o tobetsa lets'oao le hlahisang karolo ho toolbar.
5. Tobetsa letšoao la Hlahisa Karolo ka har'a toolbar ea SmartDesign, joalokaha ho bontšitsoe setšoantšong se latelang.
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5. Tobetsa letšoao la Hlahisa Karolo ka har'a toolbar ea SmartDesign, joalokaha ho bontšitsoe setšoantšong se latelang. Karolo ea SmartDesign e entsoe. Setšoantšo sa 15 · Hlahisa Karolo
6. Tsamaisa ho View > Windows > Files. The Files lebokose la puisano le bonts'itsoe. 7. Tobetsa ka ho le letona foldareng ea ketsiso ebe o tobetsa Import Files, joalokaha ho bontšitsoe setšoantšong se latelang.
Setšoantšo sa 16 · Ho kenya File
8. Ho Import sets'oants'o sa setšoantšo file, tsamaea le ho lata e 'ngoe ea tse latelang files ebe o tobetsa Open.
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8. Ho Import sets'oants'o sa setšoantšo file, tsamaea le ho lata e 'ngoe ea tse latelang files ebe o tobetsa Open. a. A sample RGB_in.txt file e fanoa le testbench ka tsela e latelang:
..Project_namecomponentMicrosemiSolutionCore ddr_memory_arbiter 2.0.0Stimulus
Ho kenya sampsetšoantšo sa tlhahiso ea benche ea liteko, sheba ho sampsetšoantšo sa tlhahiso ea testbench file, ebe o tobetsa Open, joalokaha ho bontšitsoe setšoantšong se latelang. Setšoantšo sa 17 · Setšoantšo sa ho Kena File Khetho
b. Ho kenya sets'oants'o se fapaneng, sheba foldareng e nang le setšoantšo se batloang file, ebe o tobetsa Open. Tšusumetso ea setšoantšo se tsoang kantle ho naha file e thathamisitsoe tlas'a buka ea ketsiso, joalo ka ha ho bonts'itsoe setšoantšong se latelang. Setšoantšo sa 18 · Setšoantšo sa Kena File ho Bukana ea Ketsiso
9. Kenya ddr BFM files. Tse peli files tse lekanang le
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9. Kenya ddr BFM files. Tse peli files tse lekanang le DDR BFM - ddr3.v le ddr3_parameters.v li fanoa ka testbench ka tsela e latelang: ..Project_namecomponentMicrosemiSolutionCoreddr_memory_arbiter 2.0.0Stimulus. Tobetsa foldareng ea stimulus ka ho le letona ebe u khetha Import Files, ebe u khetha BFM e boletsoeng ka holimo files. DDR BFM e tsoang kantle ho naha files li thathamisitsoe tlas'a tšusumetso, joalokaha ho bontšitsoe setšoantšong se latelang. Setšoantšo sa 19 · E tsoa kantle ho naha File
10. Tsamaisa ho File > Fumana > Tse ding. The Import Files lebokose la puisano le bonts'itsoe. Setšoantšo sa 20 · Kenya Testbench File
11. Kenya testbench le karolo ea MSS files (top_tb.cxf, mss_top_sb_MSS.cxf, mss_top.cxf, le mss
..Project_namecomponentMicrosemiSolutionCoreddr_memory_arbiter 2.0.0Stimulus
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Setšoantšo sa 21 · Kenya Testbench le Karolo ea MSS Files
Setšoantšo sa 22 · top_tb E thehiloe
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3.5.1
Ho etsisa MSS SmartDesign
Litaelo tse latelang li hlalosa mokhoa oa ho etsisa MSS SmartDesign:
1. Tobetsa tab ya Hierarchy ya Moralo mme o kgethe Karolo ho tswa lenaneng le theohang la pontsho. MSS SmartDesign e tsoang kantle e ea hlaha.
2. Tobetsa ka ho le letona mss_top tlas'a Work ebe o tobetsa Open Component, joalokaha ho bontšitsoe setšoantšong se latelang. Karolo ea mss_top_sb_0 e hlahisoa.
Setšoantšo sa 23 · Bula Karolo
3. Tobetsa ka ho le letona karolo ea mss_top_sb_0 ebe u tobetsa Configure, joalokaha ho bontšitsoe setšoantšong se latelang.
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3. Tobetsa ka ho le letona karolo ea mss_top_sb_0 ebe u tobetsa Configure, joalokaha ho bontšitsoe setšoantšong se latelang. Setšoantšo sa 24 · Lokisa Karolo
Fesetere ea Tlhophiso ea MSS e tla hlahisoa, joalo ka ha ho bonts'itsoe setšoantšong se latelang. Setšoantšo sa 25 · Fensetere ea Tlhophiso ea MSS
4. Tobetsa E latelang ho li-tab tsohle tsa tlhophiso, joalo ka ha ho bonts'itsoe setšoantšong se latelang.
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4. Tobetsa E latelang ho li-tab tsohle tsa tlhophiso, joalo ka ha ho bonts'itsoe setšoantšong se latelang. Setšoantšo sa 26 · Litabo tsa Tlhophiso
MSS e lokisoa ka mor'a hore tab ea Interrupts e lokisoe. Setšoantšo se latelang se bontša tsoelo-pele ea MSS Configuration. Setšoantšo sa 27 · Fensetere ea Tlhophiso ea MSS Ka mor'a Tlhophiso
5. Tobetsa E latelang ka mor'a hore tlhophiso e phethoe. Fesetere ea 'Mapa oa Memori e tla hlaha, joalo ka ha ho bonts'itsoe setšoantšong se latelang.
Setšoantšo sa 28 · 'Mapa oa Memori
6. Tobetsa Qetella.
7. Tobetsa Hlahisa Karolo ho tsoa ho sesebelisoa sa SmartDesign ho hlahisa MSS, joalo ka ha ho bonts'itsoe ho
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7. Tobetsa Hlahisa Karolo ho tsoa ho sesebelisoa sa lisebelisoa tsa SmartDesign ho hlahisa MSS, joalokaha ho bontšitsoe setšoantšong se latelang. Setšoantšo sa 29 · Hlahisa Karolo
8. Fensetereng ea Tsamaiso ea Moralo, tobetsa ka ho le letona mss_top tlas'a Work ebe o tobetsa Set As Root, joalokaha ho bontšitsoe setšoantšong se latelang. Setšoantšo sa 30 · Beha MSS joalo ka Motso
9. Fensetereng ea Phallo ea Moralo, atolosa Verify Pre-synthesized Design ka tlas'a Create Design, tobetsa ka ho le letona.
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9. Fensetereng ea Phallo ea Moralo, atolosa Netefatsa Moralo o hlophisitsoeng tlas'a Design Design, tobetsa ka ho le letona Etsisa ebe o tobetsa Open Interactively. E etsisa MSS. Setšoantšo sa 31 · Etsisa Moqapi o entsoeng Pele
10. Tobetsa Che haeba molaetsa oa tlhokomeliso o hlaha o amahanya le tsusumetso ea Testbench le MSS. 11. Koala fensetere ea Modelsim ka mor'a hore papiso e phethoe.
Setšoantšo sa 32 · Fensetere ea Ketsiso
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3.5.2
Ho etsisa Testbench
Litaelo tse latelang li hlalosa mokhoa oa ho etsisa testbench:
1. Khetha top_tb SmartDesign Testbench 'me u tobetse Hlahisa Karolo ho tswa ho sesebelisoa sa SmartDesign ho hlahisa testbench, joalokaha ho bontšitsoe setšoantšong se latelang.
Setšoantšo sa 33 · Ho Hlahisa Karolo
2. Fesetereng ya Stimulus Hierarchy, tobetsa ka ho le letona top_tb (top_tb.v) testbench file ebe o tobetsa Seta joalo ka tšusumetso e sebetsang. Stimulus e kentsoe tšebetsong top_tb testbench file.
3. Fesetereng ya Stimulus Hierarchy, tobetsa ka ho le letona top_tb (
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DDR AXI Arbiter
3. Fesetereng ya Stimulus Hierarchy, tobetsa ka ho le letona top_tb (top_tb.v) testbench file ebe o tobetsa Open Interactively ho tloha Simulate Pre-Synth Design. Sena se etsisa mantlha bakeng sa foreimi e le 'ngoe. Setšoantšo sa 34 · Ho etsisa Moqapi oa Pele ho Synthesis
4. Haeba ketsiso e sitisoa ka lebaka la moeli oa nako ea ho sebetsa ho DO file, sebelisa run -all command ho phethela papiso. Ka mor'a hore ketsiso e phethoe, etela ho View > Files > ketsiso ho view setšoantšo sa tlhahiso ea benche ea teko file foldareng ea ketsiso.
Tlhahiso ea papiso e lekanang le foreimi e le 'ngoe ea setšoantšo, e bolokiloe ho mongolo oa Read_out_rd_ch(x).txt file ho ipapisitsoe le kanale e baloang e sebelisitsoeng. Sena se ka fetoloa setšoantšo 'me sa bapisoa le setšoantšo sa pele.
3.6
Tšebeliso ea Mehloli
Sebaka sa DDR Arbiter se kengoa ts'ebetsong ho M2S150T SmartFusion®2 System-on-Chip (SoC) FPGA ho
Sephutheloana sa FC1152) le PolarFire FPGA (MPF300TS_ES - 1FCG1152E sephutheloana).
Letlapa la 4 · Tšebeliso ea Lisebelisoa bakeng sa DDR AXI Arbiter
Lisebelisoa tsa DFFs 4-input LUTs MACC RAM1Kx18
Tšebeliso 2992 4493 0 20
(Bakeng sa:
g_RD_CHANNEL(X)_HORIZONTAL_RESOLUTION = 1280
g_RD_CHANNEL(X)_BUFFER_LINE_STORAGE = 1
g_WR_CHANNEL(X)_BUFFER_LINE_STORAGE = 1
g_AXI_DWIDTH = 64
g_RD_CHANNEL(X)_VIDEO_DATA_WIDTH = 24
RAM64x18
g_WR_CHANNEL(X)_VIDEO_DATA_WIDTH = 32) 0
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50200644
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Litokomane / Lisebelisoa
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Microchip UG0644 DDR AXI Arbiter [pdf] Bukana ea Mosebelisi UG0644 DDR AXI Arbiter, UG0644, DDR AXI Arbiter, AXI Arbiter |
