Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi

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FPGA Integer Arithmetic IP Cores

Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi
E ntlafalitsoe bakeng sa Intel® Quartus® Prime Design Suite: 20.3

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UG-01063

ID: 683490 Version: 2020.10.05

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1. Intel FPGA Integer Arithmetic IP Cores……………………………………………………………….. 5
2. LPM_COUNTER (Counter) IP Core………………………………………………………………………….. 7 2.1. Likarolo…………………………………………………………………………………………………………… Verilog HDL Prototype………………………………………………………………………………….. 7 2.2. Phatlalatso ea Karolo ea VHDL………………………………………………………………………….8 2.3. VHDL LIBRARY_USE Declaration…………………………………………………………………………………… Maemakepe…………………………………………………………………………………………………………..8 2.4. Liparamente……………………………………………………………………………………………………………
3. LPM_DIVIDE (Divider) Intel FPGA IP Core…………………………………………………………….. 12 3.1. Likaroloana………………………………………………………………………………………………. 12 3.2. Verilog HDL Prototype……………………………………………………………………………………… 12 3.3. Phatlalatso ea Karolo ea VHDL……………………………………………………………………….. 13 3.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 13 3.5. Maemakepe………………………………………………………………………………………………………………………………………………………………………………………………………………… Liparamente……………………………………………………………………………………………………………
4. LPM_MULT (Multiplier) IP Core………………………………………………………………………………. 16 4.1. Likaroloana………………………………………………………………………………………………. 16 4.2. Verilog HDL Prototype……………………………………………………………………………………… 17 4.3. Phatlalatso ea Karolo ea VHDL………………………………………………………………………….. 17 4.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 17 4.5. Lipontšo………………………………………………………………………………………………………………………………………………………………………………………………………… Liparamente tsa Stratix V, Arria V, Cyclone V, le Intel Cyclone 18 LP Devices ……………… 4.6 10. Lethathamo la Kakaretso………………………………………………………………………………………18 Kakaretso 4.6.1 Taba………………………………………………………………………………………………………… Pipelining Tab……………………………………………………………………………………… 18 4.6.2. Liparamente tsa Intel Stratix 2, Intel Arria 19, le Intel Cyclone 4.6.3 GX Devices ……….. 19 4.7. Lethathamo la Kakaretso…………………………………………………………………………………………10 Kakaretso 10 Taba………………………………………………………………………………………………… Ho kenya lipeipi…………………………………………………………………………………………
5. LPM_ADD_SUB (Adder/Subtractor)……………………………………………………………………… 22 5.1. Likaroloana………………………………………………………………………………………………. 22 5.2. Verilog HDL Prototype……………………………………………………………………………………… 23 5.3. Phatlalatso ea Karolo ea VHDL……………………………………………………………………….. 23 5.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 23 5.5. Maemakepe……………………………………………………………………………………………………………………………………………………………………………………………………………… Liparamente…………………………………………………………………………………………………………
6. LPM_COMPARE (Mopapi)……………………………………………………………………………………………………………………………………………………………………………… Likaroloana………………………………………………………………………………………………. 26 6.1. Verilog HDL Prototype……………………………………………………………………………………… 26 6.2. Phatlalatso ea Karolo ea VHDL………………………………………………………………………….. 27 6.3. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 27 6.4. Maemakepe…………………………………………………………………………………………………………………………………………………………………………………………………………………… Liparamente…………………………………………………………………………………………………………

Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi 2

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7. ALTECC (Khoutu ea Phoso ea Phoso: Encoder/Decoder) IP Core………………………………………… 30
7.1. ALTECC Encoder Features………………………………………………………………………………..31 7.2. Verilog HDL Prototype (ALTECC_ENCODER)…………………………………………………………. 32 7.3. Verilog HDL Prototype (ALTECC_DECODER)…………………………………………………………. 32 7.4. Phatlalatso ea Karolo ea VHDL (ALTECC_ENCODER)…………………………………………………33 7.5. Phatlalatso ea Karolo ea VHDL (ALTECC_DECODER)…………………………………………………33 7.6. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 33 7.7. Encoder Ports……………………………………………………………………………………………… 33 7.8. Li-decoder Ports………………………………………………………………………………………………34 7.9. Encoder Parameters…………………………………………………………………………………………… 34 7.10. Li-decoder Parameters ………………………………………………………………………………………
8. Intel FPGA Multiply Adder IP Core…………………………………………………………………………. 36
8.1. Likaroloana………………………………………………………………………………………………. 37 8.1.1. Pre-adder…………………………………………………………………………………….. 38 8.1.2. Systolic Delay Register………………………………………………………………………….. 40 8.1.3. Pre-load Constant……………………………………………………………………………… 43 8.1.4. Double Accumulator…………………………………………………………………………… 43
8.2. Verilog HDL Prototype…………………………………………………………………………………… 44 8.3. Phatlalatso ea Karolo ea VHDL……………………………………………………………………….. 44 8.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 44 8.5. Lipontšo……………………………………………………………………………………………………………………………………………………………………………………………………… Liparamente………………………………………………………………………………………………………
8.6.1. Kakaretso Taba………………………………………………………………………………………47 8.6.2. Extra Modes Tab…………………………………………………………………………….. 47 8.6.3. Multipliers Tab……………………………………………………………………………….. 49 8.6.4. Preadder Tab………………………………………………………………………………………. 51 8.6.5. Accumulator Tab……………………………………………………………………………….. 53 8.6.6. Systolic/Chainout Tab…………………………………………………………………………. 55 8.6.7. Pipelining Tab ……………………………………………………………………………………… 56
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core……………………… 57
9.1. Likaroloana………………………………………………………………………………………………. 57 9.2. Verilog HDL Prototype……………………………………………………………………………………… 58 9.3. Phatlalatso ea Karolo ea VHDL……………………………………………………………………….. 58 9.4. Boema-kepe……………………………………………………………………………………………………………………………………………………………………………………………………………………… Liparamente…………………………………………………………………………………………………………
10. ALTMULT_ACCUM (Ikatise-Bokellela) IP Core…………………………………………………… 61
10.1. Likarolo…………………………………………………………………………………………………….. 62 10.2. Verilog HDL Prototype………………………………………………………………………………..62 10.3. Phatlalatso ea Karolo ea VHDL……………………………………………………………………………… 63 10.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………… Boema-kepe…………………………………………………………………………………………………………………………………………………………… 63 10.5. Li-parameter………………………………………………………………………………………………… 63
11. ALTMULT_ADD (Multiply-Adder) IP Core……………………………………………………………..69
11.1. Likarolo…………………………………………………………………………………………………….. 71 11.2. Verilog HDL Prototype………………………………………………………………………………..72 11.3. Phatlalatso ea Karolo ea VHDL…………………………………………………………………………… 72 11.4. VHDL LIBRARY_USE Declaration………………………………………………………………………

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11.5. Boema-kepe…………………………………………………………………………………………………………………………………………………………… 72 11.6. Li-parameter………………………………………………………………………………………………… 73
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core………………………………………………… 86 12.1. Katiso e rarahaneng………………………………………………………………………………… 86 12.2. Kemelo ea Mangolo………………………………………………………………………………………………………… 87 12.3. Boemeli bo tloaelehileng………………………………………………………………………… 87 12.4. Likarolo…………………………………………………………………………………………………….. 88 12.5. Verilog HDL Prototype………………………………………………………………………………..88 12.6. Phatlalatso ea Karolo ea VHDL………………………………………………………………………… 89 12.7. VHDL LIBRARY_USE Declaration……………………………………………………………………………89 12.8. Lipontšo…………………………………………………………………………………………………………. 89 12.9. Li-parameter………………………………………………………………………………………………… 90
13. ALTSQRT (Integer Square Root) IP Core…………………………………………………………………92 13.1. Likarolo…………………………………………………………………………………………………….. 92 13.2. Verilog HDL Prototype………………………………………………………………………………..92 13.3. Phatlalatso ea Karolo ea VHDL…………………………………………………………………………… 93 13.4. VHDL LIBRARY_USE Declaration……………………………………………………………………………93 13.5. Boema-kepe…………………………………………………………………………………………………………………………………………………………… 93 13.6. Li-parameter………………………………………………………………………………………………… 94
14. PARALLEL_ADD (Parallel Adder) IP Core…………………………………………………………….. 95 14.1. Sebopeho…………………………………………………………………………………………………….95 14.2. Verilog HDL Prototype………………………………………………………………………………..95 14.3. Phatlalatso ea Karolo ea VHDL…………………………………………………………………………… 96 14.4. VHDL LIBRARY_USE Declaration……………………………………………………………………………96 14.5. Boema-kepe…………………………………………………………………………………………………………………………………………………………… 96 14.6. Li-parameter………………………………………………………………………………………………… 97
15. Integer Arithmetic IP Cores User Guide Document Archives …………………………………… 98
16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide…. 99

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1. Intel FPGA Integer Arithmetic IP Cores

U ka sebelisa Intel® FPGA integer IP cores ho etsa tšebetso ea lipalo moralong oa hau.

Mesebetsi ena e fana ka logic synthesis e sebetsang hantle le ts'ebetsong ea lisebelisoa ho feta ho khouta mesebetsi ea hau. U ka etsa li-cores tsa IP ho latela litlhoko tsa hau tsa moralo.

Intel integer arithmetic IP cores e arotsoe ka mekhahlelo e 'meli e latelang: · Library of parameterized modules (LPM) IP cores · Intel-specific (ALT) IP cores

Tafole e latelang e thathamisa lipalo tse felletseng tsa IP cores.

Lethathamo la 1.

Lethathamo la IP Cores

IP Cores

LPM IP cores

LPM_COUNTER

LPM_AROA

LPM_MULT

LPM_ADD_SUB
LPM_COMPARE
Intel-specific (ALT) IP cores ALTECC

Mosebetsi Overview Counter divider Multiplier
Adder kapa subtractor Comparator
ECC Encoder/Decoder

Sesebelisoa se Tšehetsoeng
Arria® II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone® IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP,
Intel Cyclone 10 GX, MAX® II, MAX V, MAX 10, Stratix® IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V,Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V e tsoetse pele…

Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

ISO 9001:2015 E Ngolisitsoe

1. Intel FPGA Integer Arithmetic IP Cores 683490 | 2020.10.05

IP Cores Intel FPGA Multiply Adder kapa ALTERA_MULT_ADD ALTMEMMULT
ALTMULT_ACCUM ALTMULT_ADD ALTMULT_COMPLEX
ALTSQRT
PARALLEL_ADD

Mosebetsi Overview Multiplier-Adder
Memori e thehiloeng ho Constant Coefficient Multiplier
Multiplier-Accumulator Multiplier-Adder
Complex Multiplier
Integer Square-Root
Adder e Tšoanang

Sesebelisoa se Tšehetsoeng
Arria V, Stratix V, Cyclone V, Intel Stratix 10, Intel Arria 10, Intel Cyclone
10 GX
Arria II GX, Arria II GZ, Arria V, Intel Arria 10 (Intel Quartus® Prime Standard Edition), Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Cyclone 10 LP, MAX II, MAX V, MAX 10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX,Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Intel Arria 10, Arria V, Arria V GZ, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Cyclone 10 GX, Intel Cyclone 10 LP, MAX 10, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP,Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V

Lintlha Tse Amanang
· Intel FPGAs le Lintlha tsa Phatlalatso ea Lisebelisoa tse Programmable
· Selelekela ho Intel FPGA IP Cores E fana ka lintlha tse ling mabapi le Intel FPGA IP Cores.
· Floating-Point IP Cores User Guide E fana ka lintlha tse ling mabapi le Intel FPGA Floating-Point IP cores.
· Selelekela ho Intel FPGA IP Cores E fana ka leseli le akaretsang mabapi le li-cores tsohle tsa Intel FPGA IP, ho kenyeletsoa parameterizing, ho hlahisa, ho ntlafatsa, le ho etsisa li-cores tsa IP.
· Ho theha Phetolelo e Ikemetseng ea IP le Lingoliloeng tsa Ketsiso tsa Qsys Theha lingoliloeng tsa papiso tse sa hlokeng lintlafatso tsa letsoho bakeng sa lintlafatso tsa software kapa mofuta oa IP.
· Taolo ea Morero Litaelo tse Molemohali tsa Mekhoa ea Boipheliso bakeng sa taolo e ntle le ho nkeha habonolo ha projeke ea hau le IP files.
· Integer Arithmetic IP Cores User Guide Document Archives leqepheng la 98 E fana ka lethathamo la litataiso tsa basebelisi bakeng sa liphetolelo tse fetileng tsa Integer Arithmetic IP cores.

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2. LPM_COUNTER (Counter) IP Core

Setšoantšo sa 1.

LPM_COUNTER IP core ke sesebelisoa sa binary se etsang likhau tse holimo, tse tlase le tse holimo kapa tse tlase tse nang le lihlahisoa tse fihlang ho li-bits tse 256 ka bophara.

Setšoantšo se latelang se bontša likou tsa LPM_COUNTER IP core.

LPM_COUNTER Maemakepe

LPM_COUNTER

ssclr sload sset data[]

q[]

ntjhafaditswe

khothi

aclr aload aset

clk_en cnt_en cin
inst

2.1. Likarolo
LPM_COUNTER IP core e fana ka likarolo tse latelang: · E hlahisa li-counter, tlase, le holimo/tlase · E hlahisa mefuta e latelang ea li-counter:
- Binary e hlakileng - likhauntara tse eketsang ho tloha ho zero kapa ho fokotseha ho tloha ho 255
- Modulus - khaunta e eketsa kapa e fokotseha ho tsoa ho boleng ba modulus e boletsoeng ke mosebelisi ebe e pheta
· E ts'ehetsa li-ports tsa ho kenya ka boikhethelo tse hlakileng, mojaro le ho seta · E ts'ehetsa likou tsa ho kenya tse hlakileng, mojaro, le ho seta ka boikhethelo · E ts'ehetsa palo ea boikhethelo e nolofalletsa le oache e nolofalletsa likou tsa ho kenya · E ts'ehetsa likou tsa boikhethelo tsa ho kena le ho tsoa

ISO 9001:2015 E Ngolisitsoe

2. LPM_COUNTER (Counter) IP Core
683490 | 2020.10.05
2.2. Verilog HDL Prototype
Mohlala o latelang oa Verilog HDL o fumaneha ho Moralo oa Verilog File (.v) lpm.v ka edasynthesis directory.
module lpm_counter ( q, data, oache, cin, cout, clk_en, cnt_en, updown, aset, aclr, aload, sset, sclr, sload, eq ); parameter lpm_type = "lpm_counter"; parameter lpm_width = 1; parameter lpm_modulus = 0; parameter lpm_direction = "HA E SEBELISE"; paramethara lpm_avalue = "SA SEBELISE"; paramethara lpm_svalue = “HA E SEBELISE”; paramethara lpm_pvalue = "SA SEBELISE"; parameter lpm_port_updown = "PORT_CONNECTIVITY"; paramethara lpm_hint = "SA SEBELISE"; tlhahiso [lpm_width-1:0] q; sephetho sa tlhahiso; tlhahiso [15:0] eq; ho kenya letsoho; kenya [lpm_width-1:0] data; ho kenya oache, clk_en, cnt_en, holimo; input aset, aclr, aload; kenya sset, sclr, sload; endmodule
2.3. Phatlalatso ea Karolo ea VHDL
Phatlalatso ea karolo ea VHDL e fumaneha ho Moralo oa VHDL File (.vhd) LPM_PACK.vhd ho librariesvhdllpm directory.
motsoako LPM_COUNTER generic ( LPM_WIDTH : tlhaho; LPM_MODULUS : tlhaho := 0; LPM_DIRECTION : khoele := "SA SEBELISE"; LPM_AVALUE : khoele := "SA SEBELISE"; LPM_SVALUE : khoele := "SA SEBELISE"; LPM_PORTIVPD ; LPM_PVALUE : khoele := “E SA SEBELISE”; LPM_TYPE : khoele := L_COUNTER; LPM_HINT : khoele := “E SA SEBELISE”); boema-kepe (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0):= (OTHERS =>
'0'); TŠEBELETSO: ka std_logic; CLK_EN : ho std_logic := '1'; CNT_EN : ho std_logic := '1'; Ntlafatsa : ho std_logic := '1'; SLOAD : ho std_logic := '0'; SSET : ho std_logic := '0'; SCLR : ho std_logic := '0'; ALOAD : ho std_logic := '0'; ASET : ho std_logic := '0'; ACLR : ho std_logic := '0'; CIN : ho std_logic := '1'; COUT : out std_logic := '0'; P: tsoa std_logic_vector(LPM_WIDTH-1 ho ea ho 0); EQ: tsoa std_logic_vector (15 downto 0));
karolo ea ho qetela;

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2.4. VHDL LIBRARY_USE Phatlalatso
Phatlalatso ea VHDL LIBRARY-USE ha e hlokehe haeba u sebelisa Phatlalatso ea Karolo ea VHDL.
LAEBRARI lpm; SEBELISA lpm.lpm_components.all;

2.5. Maemakepe

Litafole tse latelang li thathamisitse libaka tsa ho kenya le tse tsoang ho LPM_COUNTER IP core.

Lethathamo la 2.

LPM_COUNTER Maeke a Kena

Lebitso la Port

Ho hlokahala

Tlhaloso

lintlha[]

Che

Kenyelletso ea data e tsamaisanang le k'haontareng. Boholo ba sebaka sa ho kenya se ipapisitse le boleng ba paramethara ea LPM_WIDTH.

oache

Positive- Edge-triggered clock input.

clk_en

Che

Oache e thusa ho kenya letsoho ho lumella mesebetsi eohle e lumellanang. Haeba e siiloe, boleng ba kamehla ke 1.

cnt_en

Che

Palo e thusa ho kenya letsoho ho tima palo ha e boleloa e le tlase ntle le ho ama sload, sset, kapa sclr. Haeba e siiloe, boleng ba kamehla ke 1.

ntjhafaditswe

Che

E laola tsela ea ho bala. Ha ho tiisitsoe holimo (1), tataiso ea palo e ea holimo, 'me ha e tiisitsoe tlaase (0), tsela ea ho bala e tlase. Haeba ho sebelisoa parameter ea LPM_DIRECTION, boema-kepe bo ka holimo bo ke ke ba hokela. Haeba LPM_DIRECTION e sa sebelisoe, boema-fofane bo ka holimo ke boikhethelo. Haeba e siiloe, boleng ba kamehla bo holimo (1).

cin

Che

Kena ho ea boemong bo tlaase. Bakeng sa li-counters, boitšoaro ba cin input ke

e ts'oanang le boitšoaro ba cnt_en input. Haeba e siiloe, boleng ba kamehla ke 1

(VCC).

aclr

Che

Kenyelletso e hlakileng ea Asynchronous. Haeba ka bobeli aset le aclr li sebelisoa 'me li boleloa, aclr e fetisa aset. Haeba e siiloe, boleng ba kamehla ke 0 (e holofalitsoe).

aset

Che

Asynchronous set input. E totobatsa lintlha tsa q[] joalo ka 1s kaofela, kapa ho boleng bo boletsoeng ke paramethara ea LPM_AVALUE. Haeba li-port tsa aset le aclr li sebelisoa 'me li boleloa, boleng ba boema-kepe ba aclr bo feta boleng ba boema-kepe ba thepa. Haeba e siiloe, boleng ba kamehla ke 0, bo koetsoe.

aload

Che

Kenyelletso ea mojaro oa Asynchronous e jarisang k'haontareng ka boleng ba tlhahiso ea data. Ha kou ea thepa e sebelisoa, boema-kepe[] ba data bo tlameha ho hokahana. Haeba e siiloe, boleng ba kamehla ke 0, bo koetsoe.

sclr

Che

Keno e hlakileng ea synchronous e hlakolang k'haontara moeling o latelang oa oache e sebetsang. Haeba li-port tsa sset le sclr li sebelisoa 'me ho boleloa, boleng ba sclr port bo feta boleng ba sset port. Haeba e siiloe, boleng ba kamehla ke 0, bo koetsoe.

sset

Che

Kenyelletso ea sete ea synchronous e seta khaontara moeling o latelang oa oache e sebetsang. E totobatsa boleng ba q e le 1s kaofela, kapa boleng bo boletsoeng ke paramethara ea LPM_SVALUE. Haeba li-port tsa sset le sclr li sebelisoa le ho boleloa,
boleng ba sclr port bo feta boleng ba sset port. Haeba e siiloe, boleng ba kamehla ke 0 (e holofalitsoe).

sload

Che

Kenyelletso e tsamaisanang e kenyang k'haontara ka data[] ntlheng e latelang ea oache e sebetsang. Ha sload port e sebelisoa, kou ea data[] e tlameha ho hokela. Haeba e siiloe, boleng ba kamehla ke 0 (e holofalitsoe).

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2. LPM_COUNTER (Counter) IP Core 683490 | 2020.10.05

Lethathamo la 3.

LPM_COUNTER Maemakepe a Tsoang

Lebitso la Port

Ho hlokahala

Tlhaloso

q[]

Che

Tlhahiso ea data ho tsoa khaontareng. Boholo ba boema-kepe ba tlhahiso bo itšetlehile ka

LPM_WIDTH boleng ba paramethara. Ekaba q[] kapa bonyane e 'ngoe ea likou tsa eq[15..0]

tlameha ho amana.

eq[15..0]

Che

Counter decode output. Kou ea eq[15..0] ha e fumanehe ho mohlophisi oa parameter hobane parameter e tšehetsa AHDL feela.
Ekaba boema-kepe ba q[] kapa boema-kepe ba eq[] bo tlameha ho hokela. Ho fihlela likoung tsa c eq li ka sebelisoa (0 <= c <= 15). Ke lipalo tse 16 tse tlase feela tse khethiloeng. Ha palo ea palo e le c, tlhahiso ea eqc e tiisitsoe holimo (1). Bakeng sa mohlalaample, ha palo e le 0, eq0 = 1, ha palo e le 1, eq1 = 1, 'me ha palo e le 15, eq 15 = 1. Phallo e khethiloeng bakeng sa lipalo tsa palo ea 16 kapa ho feta e hloka hore ho be le mokhoa oa ho khetholla ka ntle. Liphetho tsa eq[15..0] ha li lumellane le tlhahiso ea q[].

khothi

Che

Kou e tsamaisang ea k'haontareng ea MSB bit. E ka sebelisoa ho hokela khaontareng e 'ngoe ho theha k'haontara e kholoanyane.

2.6. di-parameter

Lethathamo le latelang le thathamisitse liparamente tsa LPM_COUNTER IP core.

Lethathamo la 4.

LPM_COUNTER Mekhatlo

Lebitso la Parameter

Mofuta

LPM_WIDTH

Palo kaofela

LPM_DIRECTION

Khoele

LPM_MODULUS LPM_AVALUE

Palo kaofela
Integer/ Khoele

LPM_SVALUE LPM_HINT

Integer/ Khoele
Khoele

LPM_TYPE

Khoele

Ho Hlokahala E Che Che Che Che
Che, No
Che

Tlhaloso
E hlalosa bophara ba data[] le q[] likou, haeba li sebelisoa.
Boleng ke HO PHAHAMA, HO TLASE, le HO SEBELISA. Haeba ho sebelisoa parameter ea LPM_DIRECTION, boema-kepe bo ka holimo bo ke ke ba hokela. Ha boema-kepe ba hodimo bo sa hokahane, boleng ba kamehla ba paramethara ya LPM_DIRECTION ke UP.
Palo e phahameng, mmoho le 'ngoe. Palo ea maemo a ikhethileng nakong ea setoko sa khaontara. Haeba boleng ba thepa bo le boholo ho feta paramethara ea LPM_MODULUS, boitšoaro ba k'haontareng ha bo boleloe.
Boleng ba kamehla bo kentsoeng ha thepa e tiisitsoe holimo. Haeba boleng bo boletsoeng bo le boholo ho feta kapa bo lekana le , boitšoaro ba khaontara ke boemo bo sa hlalosoang (X) bo utloahalang, moo ke LPM_MODULUS, ha e le teng, kapa 2 ^ LPM_WIDTH. Intel e khothaletsa hore o hlalose boleng bona joalo ka nomoro ea decimal bakeng sa meralo ea AHDL.
Boleng ba kamehla bo kentsoeng pheletsong e ntseng e phahama ea kou ea oache ha sset port e le holimo. Intel e khothaletsa hore o hlalose boleng bona joalo ka nomoro ea decimal bakeng sa meralo ea AHDL.
Ha o kenya ts'ebetso ea laeborari ea li-parameterized modules (LPM) ho Moralo oa VHDL File (.vhd), o tlameha ho sebelisa paramethara ea LPM_HINT ho hlakisa paramethara e khethehileng ea Intel. Bakeng sa mohlalaample: LPM_HINT = “CHAIN_SIZE = 8, ONE_INPUT_IS_CONSTANT = YES”
Boleng ba kamehla ke UNUSED.
E tsebahatsa lebitso la setsi la laeborari ea li-parameterized modules (LPM) ka moralo oa VHDL files.
e tsoela pele…

Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi 10

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2. LPM_COUNTER (Counter) IP Core 683490 | 2020.10.05

Lebitso la Paramethara INTENDED_DEVICE_FAMILY CARRY_CNT_EN
LABWIDE_SCLR
LPM_PORT_UPDOWN

Mofuta oa Khoele
Khoele
Khoele

Ho hlokahala No
Che
Che

Tlhaloso
Paramethara ena e sebelisetsoa merero ea ho etsa mohlala le ea boitšoaro. Paramethara ena e sebelisetsoa merero ea ho etsa mohlala le ea boitšoaro. Sehlophisi sa paramethara se bala boleng ba paramethara ena.
Intel-specific parameter. U tlameha ho sebelisa paramethara ea LPM_HINT ho hlakisa paramethara ea CARRY_CNT_EN moahong oa VHDL. files. Boleng ke SMART, ON, OFF, 'me HA SEBELISE. E nolofalletsa ts'ebetso ea LPM_COUNTER ho phatlalatsa lets'oao la cnt_en ka har'a car chain. Maemong a mang, litlhophiso tsa paramethara tsa CARRY_CNT_EN li ka ba le tšusumetso e nyane ho lebelo, kahoo u kanna oa batla ho e tima. Boleng ba kamehla ke SMART, e fanang ka phapanyetsano e ntle ka ho fetisisa lipakeng tsa boholo le lebelo.
Intel-specific parameter. U tlameha ho sebelisa paramethara ea LPM_HINT ho hlakisa LABWIDE_SCLR moralo oa VHDL. files. Boleng bo ON, TIMA, kapa HA SEBESWE. Boleng ba kamehla ke ON. E o lumella ho tima ts'ebeliso ea LABwide sclr e fumanehang malapeng a lisebelisoa tse sa sebetseng. Ho tima khetho ena ho eketsa menyetla ea ho sebelisa li-LAB tse tlatsitsoeng ka botlalo, 'me ka hona ho ka lumella mohopolo o phahameng haholo ha SCLR e sa sebetse ho LAB e felletseng. Paramethara ena e teng bakeng sa ho lumellana ka morao, 'me Intel e khothalletsa hore u se ke ua sebelisa parameter ena.
E totobatsa tšebeliso ea kou ea ho kenya holimo. Haeba e siiloe, boleng ba kamehla ke PORT_CONNECTIVITY. Ha boleng ba boema-kepe bo behiloe ho PORT_USED, boema-kepe bo nkuoa bo sebelisoa. Ha boleng ba boema-kepe bo behiloe ho PORT_UNUSED, boema-kepe bo nkuoa bo sa sebelisoe. Ha boleng ba boema-kepe bo behiloe ho PORT_CONNECTIVITY, tšebeliso ea boema-kepe e khethoa ka ho lekola khokahanyo ea boema-kepe.

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3. LPM_DIVIDE (Divider) Intel FPGA IP Core

Setšoantšo sa 2.

LPM_DIVIDE Intel FPGA IP core e sebelisa divider ho arola boleng ba ho kenya linomoro ka boleng ba kenyelletso ea denominator ho hlahisa quotient le masalla.

Setšoantšo se latelang se bontša likou tsa LPM_DIVIDE IP core.

LPM_DIVIDE Boema-kepe

LPM_AROA

nomoro[] denom[] oache

quotient[] sala[]

klk aclr

inst

3.1. Likarolo
LPM_DIVIDE IP core e fana ka likarolo tse latelang: · E hlahisa karohano e arolang boleng ba ho kenya linomoro ka ho kenya denominator.
boleng ho hlahisa quotient le masalla. · E ts'ehetsa bophara ba data ea 1 bits. · E ts'ehetsa sebopeho sa boemeli ba data se saenneng le se sa saenneng bakeng sa linomoro ka bobeli
le boleng ba denominator. · E ts'ehetsa ts'ebetso ea sebaka kapa lebelo. · E fana ka khetho ea ho hlakisa tlhahiso e ntle e setseng. · E ts'ehetsa latency ea liphaephe tse lokisehang. · E tšehetsa boikhethelo asynchronous hlakileng le oache thusa likoung.

3.2. Verilog HDL Prototype
Mohlala o latelang oa Verilog HDL o fumaneha ho Moralo oa Verilog File (.v) lpm.v ka edasynthesis directory.
module lpm_divide ( quotient, sala, numer, denom, clock, clken, aclr); parameter lpm_type = "lpm_divide"; parameter lpm_widthn = 1; parameter lpm_widthd = 1; paramethara lpm_nrepresentation = “HA E SA TSEBA”; paramethara lpm_drepresentation = "E SA SIGNENG"; parameter lpm_remainderpositive = "NETE"; parameter lpm_pipeline = 0;

ISO 9001:2015 E Ngolisitsoe

3. LPM_DIVIDE (Divider) Intel FPGA IP Core 683490 | 2020.10.05

paramethara lpm_hint = "SA SEBELISE"; oache e kenang; input clken; input aclr; kenya [lpm_widthn-1:0] nomoro; input [lpm_widthd-1:0] denom; tlhahiso [lpm_widthn-1:0] quotient; tlhahiso [lpm_widthd-1:0] e sala; endmodule

3.3. Phatlalatso ea Karolo ea VHDL
Phatlalatso ea karolo ea VHDL e fumaneha ho Moralo oa VHDL File (.vhd) LPM_PACK.vhd ho librariesvhdllpm directory.
karolo LPM_DIVIDE generic (LPM_WIDTHN : tlhaho; LPM_WIDTHD : tlhaho;
LPM_NREPRESENTATION : khoele := “E SA SIGNENG”; LPM_DREPRESENTATION : khoele := "E SA SIGNANG"; LPM_PIPELINE : tlhaho := 0; LPM_TYPE : khoele := L_DIVIDE; LPM_HINT : khoele := “HA E SEBELISE”); boema-kepe (NUMER: in std_logic_vector(LPM_WIDTHN-1 downto 0); DENOM : in std_logic_vector(LPM_WIDTHD-1 downto 0); ACLR : in std_logic := '0'; CLOCK : in std_logic := '0 logic: Cd'; := '1'; QUOTIENT : tsoa std_logic_vector(LPM_WIDTHN-1 ho ea ho 0); REMAIN : tsoa std_logic_vector(LPM_WIDTHD-1 downto 0)); karolo ea ho qetela;

3.4. VHDL LIBRARY_USE Phatlalatso
Phatlalatso ea VHDL LIBRARY-USE ha e hlokehe haeba u sebelisa Phatlalatso ea Karolo ea VHDL.
LAEBRARI lpm; SEBELISA lpm.lpm_components.all;

3.5. Maemakepe

Litafole tse latelang li thathamisitse libaka tsa ho kenya le tse tsoang ho LPM_DIVIDE IP core.

Lethathamo la 5.

LPM_DIVIDE Maeke a Kena

Lebitso la Port

Ho hlokahala

nomoro[]

denom[]

Tlhaloso
Ho kenya lintlha tsa Numerator. Boholo ba sebaka sa ho kenya se ipapisitse le boleng ba paramethara ea LPM_WIDTHN.
Kenyelletso ea data ea Denominator. Boholo ba sebaka sa ho kenya se ipapisitse le boleng ba paramethara ea LPM_WIDTHD.
e tsoela pele…

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3. LPM_DIVIDE (Divider) Intel FPGA IP Core 683490 | 2020.10.05

Port Name oache clken
aclr

Ho hlokahala No
Che

Tlhaloso
Ho kenya oache bakeng sa tšebeliso ea liphaephe. Bakeng sa LPM_PIPELINE lipalo tse ling ntle le 0 (ea kamehla), sebaka sa nako se tlameha ho lumeloa.
Oache e nolofalletsa tšebeliso ea liphaephe. Ha boema-kepe ba clken bo boleloa bo le holimo, ts'ebetso ea karohano e etsahala. Ha lets'oao le le tlase, ha ho ts'ebetso e etsahalang. Haeba e siiloe, boleng ba kamehla ke 1.
Boema-kepe bo hlakileng ba Asynchronous bo sebelisoang ka nako efe kapa efe ho seta liphaephe bocha ho '0's ka mokhoa o lumellanang ho kenyelletso ea oache.

Lethathamo la 6.

LPM_DIVIDE Boema-kepe ba Lintho

Lebitso la Port

Ho hlokahala

Tlhaloso

quotient[]

Tlhahiso ea data. Boholo ba boema-kepe ba tlhahiso bo itšetlehile ka LPM_WIDTHN

boleng ba paramethara.

sala[]

Tlhahiso ea data. Boholo ba sephutheloana sa tlhahiso bo itšetlehile ka LPM_WIDTHD

boleng ba paramethara.

3.6. di-parameter

Tafole e latelang e thathamisitse liparamente tsa LPM_DIVIDE Intel FPGA IP core.

Lebitso la Parameter

Mofuta

Ho hlokahala

Tlhaloso

LPM_WIDTHN

Palo kaofela

E hlalosa bophara ba nomoro[] le

quotient[] likoung. Boleng ke 1 ho isa ho 64.

LPM_WIDTHD

Palo kaofela

E hlalosa bophara ba lebitso[] le

sala[] koung. Boleng ke 1 ho isa ho 64.

LPM_NREPRESENTATION LPM_DREPRESENTATION

Khoele ea Khoele

Che

Kemiso ea matšoao ea mantsoe a linomoro.

Litekanyetso TSA SAINWE 'me HA LI TLA SONGWE. Ha sena

paramethara e behiloe ho SIGNED, karohano

e fetolela nomoro[] e kentsoeng joalo ka ea bobeli e saenneng

tlatsana.

Che

Kemelo ea matšoao ea kenyelletso ea denominator.

Litekanyetso TSA SAINWE 'me HA LI TLA SONGWE. Ha sena

paramethara e behiloe ho SIGNED, karohano

e toloka denom[] keno e le ea bobeli e saenneng

tlatsana.

LPM_TYPE

Khoele

Che

E hlwaya laeborari ea parameterized

li-modules (LPM) lebitso la mokhatlo moetsong oa VHDL

files (.vhd).

LPM_HINT

Khoele

Che

Ha u tiisa laebrari ea

parameterized modules (LPM) tshebetso ho a

Moqapi oa VHDL File (.vhd), o tlameha ho sebelisa

LPM_HINT parameter ho hlakisa Intel-

parameter e khethehileng. Bakeng sa mohlalaample: LPM_HINT

= “CHAIN_SIZE = 8,

ONE_INPUT_IS_CONSTANT = YES” The

boleng ba kamehla HA E SEBELE.

LPM_REMAINDERPOSITIVE

Khoele

Che

Intel-specific parameter. U tlameha ho sebelisa

LPM_HINT parameter ho hlalosa

LPM_REMAINDERPOSITIVE parameter ho

Moralo oa VHDL files. Boleng ke 'NETE kapa BOHATA.

Haeba parameter ena e behiloe ho TRUE, joale the

boleng ba boema-kepe bo setseng[] bo tlameha ho ba kholo ho feta

e tsoela pele…

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3. LPM_DIVIDE (Divider) Intel FPGA IP Core 683490 | 2020.10.05

Lebitso la Parameter

Mofuta

MAXIMIZE_SPEED

Palo kaofela

LPM_PIPELINE

Palo kaofela

INTENDED_DEVICE_FAMILY SKIP_BITS

Lenane la Khoele

Ho hlokahala No
Che, No No

Tlhaloso
hofeta kapa ho lekana le lefela. Haeba paramethara ena e behiloe ho TRUE, joale boleng ba boema-kepe bo setseng[] ke lefela, kapa boleng ke letšoao le le leng, ebang ke la 'nete kapa le lebe, joalo ka boleng ba boema-kepe ba linomoro. E le ho fokotsa sebaka le ho ntlafatsa lebelo, Intel e khothalletsa ho beha parameter ena ho TRUE ts'ebetsong moo karolo e setseng e lokelang ho ba ntle kapa moo ho setseng ho seng bohlokoa.
Intel-specific parameter. U tlameha ho sebelisa paramethara ea LPM_HINT ho hlakisa MAXIMIZE_SPEED moetso oa VHDL files. Maemo ke [0..9]. Ha e sebelisoa, software ea Intel Quartus Prime e leka ho ntlafatsa mohlala o itseng oa LPM_DIVIDE bakeng sa lebelo ho fapana le ho feto-fetoha, 'me e fetelletse maemo a khetho ea Optimization Technique logic. Haeba MAXIMIZE_SPEED e sa sebelisoe, ho tla sebelisoa boleng ba khetho ea Optimization Technique. Haeba boleng ba MAXIMIZE_SPEED e le 6 kapa ho feta, Compiler e holisa LPM_DIVIDE IP core bakeng sa lebelo le holimo ka ho sebelisa car car chain; haeba boleng bo le 5 kapa ka tlase, moqapi o sebelisa moralo ntle le liketane tsa ho jara.
E hlakisa palo ea linako tsa oache tsa latency tse amanang le quotient[] le ho sala[] liphetho. Boleng ba lefela (0) bo bontša hore ha ho latency e teng, le hore ts'ebetso e kopaneng feela e kentsoe. Haeba e siiloe, boleng ba kamehla ke 0 (ha bo na pipeline). U ke ke ua hlakisa boleng ba paramethara ea LPM_PIPELINE e holimo ho LPM_WIDTHN.
Paramethara ena e sebelisetsoa merero ea ho etsa mohlala le ea boitšoaro. Sehlophisi sa paramethara se bala boleng ba paramethara ena.
E lumella karohano e sebetsang hantle haholo ea "fractional bit" ho ntlafatsa lintlha tsa mantlha ka ho fana ka palo ea ba etellang pele GND ho LPM_DIVIDE IP core. Hlalosa palo ea GND e etellang pele ho phallo ea quotient ho parameter ena.

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4. LPM_MULT (Multiplier) IP Core

Setšoantšo sa 3.

LPM_MULT IP ea mantlha e sebelisa sehatisi ho atisa litekanyetso tse peli tsa data ho hlahisa sehlahisoa e le sehlahisoa.

Setšoantšo se latelang se bontša likou tsa LPM_MULT IP core.

LPM_Mult Ports

LPM_MULT dataa oache[] sephetho[] datab[] aclr/sclr clken
inst

Lintlha Tse Amanang le Litaba leqepheng la 71

4.1. Likarolo
LPM_MULT IP ea mantlha e fana ka lintlha tse latelang: · E hlahisa bongata bo atisang boleng ba lintlha tse peli tse kentsoeng · E tšehetsa bophara ba data ba li-bits tse 1. khetho ea ho kenya ts'ebetsong ts'ebetsong ea matšoao a dijithale (DSP)
block Circry or logic elements (LEs) Tlhokomeliso: Ha u haha li-multiplier tse kholo ho feta boholo bo tšehetsoeng ka tlhaho ho ka ba le /
e tla ba tšusumetso ea ts'ebetso e bakoang ke ho putlama ha li-block tsa DSP. · E ts'ehetsa boikhethelo bo hlakileng ba asynchronous le oache e nolofalletsa likou tsa ho kenya · E ts'ehetsa boikhethelo bo hlakileng ba synchronous bakeng sa lisebelisoa tsa Intel Stratix 10, Intel Arria 10 le Intel Cyclone 10 GX

ISO 9001:2015 E Ngolisitsoe

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05
4.2. Verilog HDL Prototype
Mohlala o latelang oa Verilog HDL o fumaneha ho Moralo oa Verilog File (.v) lpm.v ka edasynthesis directory.
module lpm_mult (sephetho, dataa, datab, sum, clock, clken, aclr ) parameter lpm_type = "lpm_mult"; parameter lpm_widtha = 1; parameter lpm_widthb = 1; parameter lpm_widths = 1; parameter lpm_widthp = 1; paramethara lpm_representation = "HA E TSEBA"; parameter lpm_pipeline = 0; paramethara lpm_hint = "SA SEBELISE"; oache e kenang; input clken; input aclr; input [lpm_widtha-1:0] dataa; kenya [lpm_widthb-1:0] datab; input [lpm_widths-1:0] kakaretso; sephetho [lpm_widthp-1:0]; endmodule
4.3. Phatlalatso ea Karolo ea VHDL
Phatlalatso ea karolo ea VHDL e fumaneha ho Moralo oa VHDL File (.vhd) LPM_PACK.vhd ho librariesvhdllpm directory.
motsoako LPM_MULT generic ( LPM_WIDTHA : natural; LPM_WIDTHB : natural; LPM_WIDTHS : tlhaho := 1; LPM_WIDTHP : tlhaho;
LPM_REPRESENTATION : khoele := “E SA SINWE”; LPM_PIPELINE : tlhaho := 0; LPM_TYPE: khoele := L_MULT; LPM_HINT : khoele := “HA E SEBELISE”); port ( DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0); DATAB : ho std_logic_vector(LPM_WIDTHB-1 downto 0); ACLR : in std_logic := '0'; CLOCK : in std_logic := '0 logic'; := '1'; SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0'); RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0)); karolo ea ho qetela;
4.4. VHDL LIBRARY_USE Phatlalatso
Phatlalatso ea VHDL LIBRARY-USE ha e hlokehe haeba u sebelisa Phatlalatso ea Karolo ea VHDL.
LAEBRARI lpm; SEBELISA lpm.lpm_components.all;

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4.5. Lipontšo

Lethathamo la 7.

LPM_MULT Lipontšo tsa ho Kena

Lebitso la Letshwao

Ho hlokahala

Tlhaloso

data[]

Kenya data.

Bakeng sa lisebelisoa tsa Intel Stratix 10, Intel Arria 10, le Intel Cyclone 10 GX, boholo ba letšoao la ho kenya le itšetlehile ka boleng ba parameter ea Dataa.

Bakeng sa lisebelisoa tsa khale le tsa Intel Cyclone 10 LP, boholo ba lets'oao la ho kenya le ipapisitse le boleng ba paramethara ea LPM_WIDTHA.

datab[]

Kenya data.

Bakeng sa lisebelisoa tsa Intel Stratix 10, Intel Arria 10, le Intel Cyclone 10 GX, boholo ba letšoao la ho kenya le itšetlehile ka boleng ba paramethara ea Datab.

Bakeng sa lisebelisoa tsa khale le tsa Intel Cyclone 10 LP, boholo ba lets'oao la ho kenya le ipapisitse le

boleng ba paramethara ea LPM_WIDTHB.

oache

Che

Ho kenya oache bakeng sa tšebeliso ea liphaephe.

Bakeng sa lisebelisoa tsa khale le tsa Intel Cyclone 10 LP, lets'oao la oache le tlameha ho bulela LPM_PIPELINE boleng ntle le 0 (ea kamehla).

Bakeng sa lisebelisoa tsa Intel Stratix 10, Intel Arria 10, le Intel Cyclone 10 GX, lets'oao la oache le tlameha ho lumelloa haeba boleng ba Latency bo le kantle ho 1 (kamehla).

klk

Che

Oache e lumelletse tšebeliso ea liphaephe. Ha lets'oao la clken le tiisitsoe holimo, the

ts'ebetso ea adder/subtractor e etsahala. Ha lets'oao le le tlase, ha ho ts'ebetso

etsahala. Haeba e siiloe, boleng ba kamehla ke 1.

aclr sclr

Che

Letšoao le hlakileng la Asynchronous le sebelisoang ka nako efe kapa efe ho seta lipeipi ho li-0s kaofela,

ka tsela e lumellanang le lesupa la oache. Pipeline e qala ho ea ho e sa hlalosoang (X)

boemo ba kelello. Liphetho ke boleng bo ts'oanang, empa ha bo na zero.

Che

Letšoao le hlakileng la synchronous le sebelisoang ka nako efe kapa efe ho seta lipeipi ho li-0s kaofela,

ka tsela e tsamaisanang le lesupa la tshupanako. Pipeline e qala ho ea ho e sa hlalosoang (X)

boemo ba kelello. Liphetho ke boleng bo ts'oanang, empa ha bo na zero.

Lethathamo la 8.

LPM_MULT Matshwao a tlhahiso

pontšo Lebitso

Ho hlokahala

Tlhaloso

sephetho[]

Tlhahiso ea data.

Bakeng sa lisebelisoa tsa khale le tsa Intel Cyclone 10 LP, boholo ba lets'oao la tlhahiso le ipapisitse le boleng ba paramethara ea LPM_WITDHP. Haeba LPM_WIDTHP < boholo (LPM_WIDTHA + LPM_WIDTHB, LPM_WIDTHS) kapa (LPM_WIDTHA + LPM_WIDTHS), ke li-MSB tsa LPM_WIDTHP feela tse teng.

Bakeng sa Intel Stratix 10, Intel Arria 10 le Intel Cyclone 10 GX, boholo ba matšoao a tlhahiso bo itšetlehile ka parameter ea bophara ba Sephetho.

4.6. Liparamente tsa Stratix V, Arria V, Cyclone V, le Intel Cyclone 10 LP Devices

4.6.1. Kakaretso Tab

Lethathamo la 9.

Kakaretso Tab

Paramethara

Boleng

Multiplier Configuration

Atisa ho kenya 'data' ka ho kenya 'datab'

Boleng ba kamehla

Tlhaloso

Atisa ho kenya 'data' ka ho kenya 'datab'

Khetha tlhophiso e lakatsehang bakeng sa multiplier.
e tsoela pele…

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Paramethara
Kenyo ea 'data' e lokela ho ba bophara bo bokae? Kenyo ea 'datab' e lokela ho ba bophara bo bokae? Bophara ba 'sephetho' bo lokela ho khethoa joang? Thibela bophara

Boleng
Atisa ho kenya 'data' ka boeona (squaring operation)
1-256 likotoana

Boleng ba kamehla

Tlhaloso

8 likotoana

Hlalosa bophara ba "port" ea data.

1-256 likotoana

8 likotoana

Hlalosa bophara ba boema-kepe ba datab[].

Ka tsela e iketsang bala bophara Thibela bophara
1-512 likotoana

Ka ho iketsa y bala bophara

Khetha mokhoa o lakatsehang ho fumana bophara ba sephetho[] kou.

16 likotoana

Hlalosa bophara ba sephetho[] kou.
Boleng bona bo tla sebetsa feela ha o khetha Thibela bophara ho Mofuta oa parameter.

4.6.2. Kakaretso 2 Tab

Letlapa la 10. Kakaretso 2 Tab

Paramethara

Boleng

Kenyelletso ea data

Na bese ea "datab" e na le boleng bo sa feleng?

Che E

Mofuta oa ho atisa

Mofuta ofe oa

E sa saena

u batla ho atisa? E saennoe

Phethahatso

Ke ts'ebetsong efe ea multiplier e lokelang ho sebelisoa?

Sebelisa ts'ebetsong ea kamehla
Sebelisa li-circuitry tse inehetseng (Ha li fumanehe bakeng sa malapa ohle)
Sebelisa lintlha tsa logic

Boleng ba kamehla

Tlhaloso

Che

Khetha E ho bolela boleng bo sa feleng ba

`datab' ho kenya bese, haeba e teng.

E sa saena

Hlalosa sebopeho sa boemeli bakeng sa lintlha tsa data[] le datab[].

Sebelisa ion ea kamehla ea ts'ebetso

Khetha mokhoa o lakatsehang ho fumana bophara ba sephetho[] kou.

4.6.3. Letlapa la Pipelining

Letlapa la 11. Letlapa la Pipelining

Paramethara

Na u batla ho kenya lipeipi tsa No

sebetsa?

Boleng

Theha 'aclr'

—

boema-kepe bo hlakileng ba asynchronous

Boleng ba kamehla

Tlhaloso

Che

Kgetha E ho nolofalletsa registara ea lipeipi ho

multiplier 'me u hlalose seo u se batlang

latency ea tlhahiso nakong ea potoloho ea oache. Ho nolofalletsa ho

pipeline register e eketsa latency e eketsehileng ho

tlhahiso.

Ha ea hlahlojoa

Khetha khetho ena ho nolofalletsa boema-kepe ba aclr ho sebelisa asynchronous clear bakeng sa rejisetara ea lipeipi.
e tsoela pele…

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Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi 19

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

Paramethara
Theha oache ea 'clken' e nolofalletsang oache
Ntlafatso
U batla ho ntlafatsa mofuta ofe?

Boleng -
Sebaka sa Default Speed

Boleng ba kamehla

Tlhaloso

Ha ea hlahlojoa

E totobatsa hore na oache e phahameng e sebetsa bakeng sa kou ea lipeipi

Ea kamehla

Hlalosa optimization e lakatsehang bakeng sa mantlha ea IP.
Khetha Default ho lumella software ea Intel Quartus Prime ho tseba hore na ts'ebetso e ntle ka ho fetisisa bakeng sa mantlha ea IP ke efe.

4.7. Liparamente tsa Intel Stratix 10, Intel Arria 10, le Intel Cyclone 10 GX Devices

4.7.1. Kakaretso Tab

Lethathamo la 12. Lethathamo la Kakaretso

Paramethara

Boleng

Boleng ba kamehla

Tlhaloso

Mofuta oa Litlhophiso tse ngata
Bophara ba Port Port

Atisa ho kenya 'data' ka ho kenya 'datab'
Atisa ho kenya 'data' ka boeona (squaring operation)

Atisa ho kenya 'data' ka ho kenya 'datab'

Khetha tlhophiso e lakatsehang bakeng sa multiplier.

Bophara ba data

1-256 likotoana

8 likotoana

Hlalosa bophara ba "port" ea data.

Bophara ba data

1-256 likotoana

8 likotoana

Hlalosa bophara ba boema-kepe ba datab[].

Bophara ba 'sephetho' bo lokela ho khethoa joang?

Mofuta

Ka tsela e iketsang bala bophara
Thibela bophara

Ka ho iketsa y bala bophara

Khetha mokhoa o lakatsehang ho fumana bophara ba sephetho[] kou.

Boleng

1-512 likotoana

16 likotoana

Hlalosa bophara ba sephetho[] kou.
Boleng bona bo tla sebetsa feela ha o khetha Thibela bophara ho Mofuta oa parameter.

Bophara ba sephetho

1-512 likotoana

—

E hlahisa bophara bo sebetsang ba sephetho[] kou.

4.7.2. Kakaretso 2 Tab

Letlapa la 13. Kakaretso 2 Tab

Paramethara

Kenyelletso ea data

Na bese ea "datab" e na le boleng bo sa feleng?

Che E

Boleng

Boleng ba kamehla

Tlhaloso

Che

Khetha E ho bolela boleng bo sa feleng ba

`datab' ho kenya bese, haeba e teng.

e tsoela pele…

Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi 20

Romella Maikutlo

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

Paramethara

Boleng

Boleng bofe kapa bofe bo fetang 0

Mofuta oa ho atisa

Mofuta ofe oa

E sa saena

u batla ho atisa? E saennoe

Mokhoa oa ho Phethahatso

Ke ts'ebetsong efe ea multiplier e lokelang ho sebelisoa?

Sebelisa ts'ebetsong ea kamehla
Sebelisa li-circuits tse ngata tse inehetseng
Sebelisa lintlha tsa logic

Boleng ba kamehla

Tlhaloso

Hlalosa boleng bo sa feleng ba boema-kepe ba datab[].

E sa saena

Hlalosa sebopeho sa boemeli bakeng sa lintlha tsa data[] le datab[].

Sebelisa ion ea kamehla ea ts'ebetso

Khetha mokhoa o lakatsehang ho fumana bophara ba sephetho[] kou.

4.7.3. Ho kenya liphaephe

Letlapa la 14. Letlapa la Pipelining

Paramethara

Boleng

A na u batla ho tsamaisa tšebetso?

Pipeline

Che E

Mofuta oa Letšoao le Hlakileng Latency

Boleng bofe kapa bofe bo fetang 0.
NTHAKO ACLR SCLR

Etsa oache ea 'clken'

—

thusa oache

U batla ho ntlafatsa mofuta ofe?

Mofuta

Sebaka sa Default Speed

Boleng ba kamehla

Tlhaloso

Che 1 HA HO MOTHO
—

Kgetha E ho dumella rejisetara ya dipeipi ho tlhahiso ya morekisi. Ho nolofalletsa rejistara ea lipeipi ho eketsa latency ho tlhahiso.
Hlalosa latency ea tlhahiso e lakatsehang nakong ea oache.
Hlalosa mofuta oa ho seta bocha bakeng sa ngoliso ea lipeipi. Khetha HONA haeba u sa sebelise rejisetara ea lipeipi. Khetha ACLR ho sebelisa asynchronous clear bakeng sa rejisetara ea lipeipi. Sena se tla hlahisa boema-kepe ba ACLR. Khetha SCLR ho sebelisa synchronous clear bakeng sa rejisetara ea lipeipi. Sena se tla hlahisa boema-kepe ba SCLR.
E totobatsa hore na oache e phahameng e sebetsa bakeng sa kou ea lipeipi

Ea kamehla

Hlalosa optimization e lakatsehang bakeng sa mantlha ea IP.
Khetha Default ho lumella software ea Intel Quartus Prime ho tseba hore na o khona ho ntlafatsa IP ea mantlha.

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5. LPM_ADD_SUB (Adder/Subtractor)

Setšoantšo sa 4.

LPM_ADD_SUB IP core e u lumella ho kenya tšebetsong adder kapa subtractor ho eketsa kapa ho tlosa sete ea data ho hlahisa tlhahiso e nang le kakaretso kapa phapang ea boleng ba tlhahiso.

Setšoantšo se latelang se bontša likou tsa LPM_ADD_SUB IP core.

LPM_ADD_SUB Boema-kepe

LPM_ADD_SUB eketsa_sub cin

data[]

clock clken datab[] aclr

sephetho[] cout e khaphatsehang

inst

5.1. Likarolo
LPM_ADD_SUB IP core e fana ka likarolo tse latelang: · E hlahisa adder, subtractor, le adder/subtractor e ka lokisoang ka matla.
mesebetsi. · E ts'ehetsa bophara ba data ea 1 bits. · E ts'ehetsa sebopeho sa boemeli ba data joalo ka se saenneng le se sa saenneng. · E ts'ehetsa boikhethelo ba ho kenya kahare (ho alima), ho hlaka ka mokhoa o hlakileng, 'me oache e thusa
likou tse kenang. · E ts'ehetsa boikhethelo ba ho tsamaisa (kalima-in) le likou tse hlahisoang ka bongata. · E abela e 'ngoe ea libese tsa data tse kenang ka nako e telele. · E ts'ehetsa liphaephe ka latency e ka lokisoang.

ISO 9001:2015 E Ngolisitsoe

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05
5.2. Verilog HDL Prototype
Mohlala o latelang oa Verilog HDL o fumaneha ho Moralo oa Verilog File (.v) lpm.v ka edasynthesis directory.
module lpm_add_sub (sephetho, cout, overflow,add_sub, cin, dataa, datab, clock, clken, aclr); paramethara lpm_type = “lpm_add_sub”; parameter lpm_width = 1; parameter lpm_direction = "HA E SEBELISE"; paramethara lpm_representation = "E SAENWA"; parameter lpm_pipeline = 0; paramethara lpm_hint = "SA SEBELISE"; kenya [lpm_width-1:0] dataa, datab; input add_sub, cin; oache e kenang; input clken; input aclr; sephetho [lpm_width-1:0]; sephetho sa tlhahiso, ho khaphatseha; endmodule
5.3. Phatlalatso ea Karolo ea VHDL
Phatlalatso ea karolo ea VHDL e fumaneha ho Moralo oa VHDL File (.vhd) LPM_PACK.vhd ho librariesvhdllpm directory.
karolo LPM_ADD_SUB generic (LPM_WIDTH : tlhaho;
LPM_DIRECTION : khoele := “HA E SEBELISE”; LPM_REPRESENTATION: khoele := "E SAINWE"; LPM_PIPELINE : tlhaho := 0; LPM_TYPE : khoele := L_ADD_SUB; LPM_HINT : khoele := “HA E SEBELISE”); boema-kepe (DATAA: in std_logic_vector(LPM_WIDTH-1 downto 0); DATAB : ho std_logic_vector(LPM_WIDTH-1 downto 0); ACLR : in std_logic:= '0'; CLOCK : in std_logic := '0' logic: CLK_logic; := '1'; CIN : in std_logic := 'Z'; ADD_SUB : in std_logic := '1'; RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0); COUT : out std_logic; OVERFLOW : out std_logic); karolo ea ho qetela;
5.4. VHDL LIBRARY_USE Phatlalatso
Phatlalatso ea VHDL LIBRARY-USE ha e hlokehe haeba u sebelisa Phatlalatso ea Karolo ea VHDL.
LAEBRARI lpm; SEBELISA lpm.lpm_components.all;
5.5. Maemakepe
Litafole tse latelang li thathamisitse libaka tsa ho kenya le tse tsoang ho LPM_ADD_SUB IP core.

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5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05

Lethathamo la 15. LPM_ADD_SUB IP Core Input Ports

Lebitso la Port

Ho hlokahala

Tlhaloso

cin

Che

Kena ho ea boemong bo tlaase. Bakeng sa ts'ebetso ea tlatsetso, boleng ba kamehla ke 0. Bakeng sa

ts'ebetso ea ho ntša, boleng ba kamehla ke 1.

data[]

Kenya data. Boholo ba sebaka sa ho kenya se ipapisitse le boleng ba paramethara ea LPM_WIDTH.

datab[]

Kenya data. Boholo ba sebaka sa ho kenya se ipapisitse le boleng ba paramethara ea LPM_WIDTH.

eketsa_sub

Che

Ka boikhethelo boema-kepe ba ho kenya ho thusa ho fetoha ho matla lipakeng tsa adder le subtractor

mesebetsi. Haeba ho sebelisoa parameter ea LPM_DIRECTION, add_sub e ke ke ea sebelisoa. Haeba

e siiloe, boleng ba kamehla ke ADD. Intel e khothalletsa hore u sebelise

LPM_DIRECTION parameter ho hlakisa ts'ebetso ea ts'ebetso ea LPM_ADD_SUB,

ho e-na le ho fana ka kamehla ho add_sub port.

oache

Che

Kenyelletso bakeng sa tšebeliso ea liphaephe. Boema-ts'oants'o ba oache bo fana ka tlhahiso ea oache bakeng sa phaephe

ts'ebetso. Bakeng sa LPM_PIPELINE lipalo tse ling ntle le 0 (kamehla), kou ea oache e tlameha ho ba

nolofalitsoe.

klk

Che

Oache e lumelletse tšebeliso ea liphaephe. Ha boema-kepe ba clken bo tiisitsoe holimo, adder/

ts'ebetso ea subtractor e etsahala. Ha lets'oao le le tlase, ha ho ts'ebetso e etsahalang. Haeba

e siiloe, boleng ba kamehla ke 1.

aclr

Che

Asynchronous clear bakeng sa tšebeliso ea liphaephe. Pipeline e qala ho ea ho e sa hlalosoang (X)

boemo ba kelello. Boema-kepe ba aclr bo ka sebelisoa ka nako efe kapa efe ho seta lipeipi ho li-0s kaofela,

ka tsela e lumellanang le lesupa la oache.

Lethathamo la 16. LPM_ADD_SUB IP Core Output Ports

Lebitso la Port

Ho hlokahala

Tlhaloso

sephetho[]

Tlhahiso ea data. Boholo ba boema-kepe bo ipapisitse le paramethara ea LPM_WIDTH

boleng.

khothi

Che

Ho etsa (ho alima) ea bohlokoa ka ho fetisisa (MSB). Cout port e na le 'mele

ho toloka joalo ka phetisetso (ho ikalima) ea MSB. Boema-kepe ba cout boa lemoha

khaphatseha lits'ebetsong tse SA TŠEBANG. Cout port e sebetsa ka mokhoa o ts'oanang bakeng sa

TS'ebetso E SAINWE LE E SA BILENG.

khaphatseha

Che

Sephetho se ikhethileng sa phallo ea phallo. Kou e khaphatsehang e na le tlhaloso ea 'mele e le

XOR ea ho kenya MSB ka ho tsoa ha MSB. Boema-kepe ba ho tlala

e tiisa ha liphetho li feta ka nepo e fumanehang, 'me e sebelisoa feela ha e

LPM_REPRESENTATION boleng ba parametha ke SIGNED.

5.6. di-parameter

Lethathamo le latelang le thathamisa LPM_ADD_SUB IP core parameters.

Lethathamo la 17. LPM_ADD_SUB IP Core Parameters

Lebitso la Parametha LPM_WIDTH

Type Integer

Ho Hlokahala E

Tlhaloso
E hlalosa bophara ba dataa[], datab[], le sephetho[] likou.

LPM_DIRECTION

Khoele

Che

Boleng ke ADD, SUB, le UNUSED. Haeba e siiloe, boleng ba kamehla ke DEFAULT, bo laelang parameter ho nka boleng ba eona ho tloha ho add_sub port. Add_sub port e ke ke ea sebelisoa haeba LPM_DIRECTION e sebelisoa. Intel e khothalletsa hore u sebelise paramethara ea LPM_DIRECTION ho hlalosa ts'ebetso ea LPM_ADD_SUB, ho e-na le ho fana ka sebaka sa kamehla ho add_sub port.
e tsoela pele…

Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi 24

Romella Maikutlo

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05

Lebitso la Paramethara LPM_REPRESENTATION LPM_PIPELINE LPM_HINT LPM_TYPE ONE_INPUT_IS_CONSTANT MAXIMIZE_SPEED
INTENDED_DEVICE_FAMILY

Type String Integer String String String Integer
Khoele

Ho hlokahala Che Che Che Che Che No No No No
Che

Tlhaloso
E totobatsa mofuta oa kenyelletso e entsoeng. Litekanyetso TSA SAINWE 'me HA LI TLA SONGWE. Haeba e siiloe, boleng ba kamehla bo TŠENWA. Ha paramethara ena e behiloe HO TŠEBELETSOE, adder/subtractor e toloka tlhahiso ea data e le tlatsetso ea tse peli tse saenneng.
E totobatsa palo ea lipoelo tsa nako ea morao-rao tse amanang le sephetho[] Boleng ba lefela (0) bo bontša hore ha ho latency e teng, le hore ts'ebetso e kopaneng feela e tla netefatsoa. Haeba e siiloe, boleng ba kamehla ke 0 (ha bo na pipeline).
E u lumella ho hlakisa li-parameter tse khethehileng tsa Intel moahong oa VHDL files (.vhd). Boleng ba kamehla ke UNUSED.
E tsebahatsa lebitso la setsi la laeborari ea li-parameterized modules (LPM) ka moralo oa VHDL files.
Intel-specific parameter. U tlameha ho sebelisa paramethara ea LPM_HINT ho hlakisa ONE_INPUT_IS_CONSTANT moralong oa VHDL. files. Boleng ke YES, CHE, le HA SEBELISE. E fana ka ntlafatso e kholoanyane haeba tlhahiso e le 'ngoe e sa fetohe. Haeba e siiloe, boleng ba kamehla ke NO.
Intel-specific parameter. U tlameha ho sebelisa paramethara ea LPM_HINT ho hlakisa MAXIMIZE_SPEED moetso oa VHDL files. O ka hlakisa boleng pakeng tsa 0 le 10. Ha e sebelisoa, software ea Intel Quartus Prime e leka ho ntlafatsa mohlala o itseng oa LPM_ADD_SUB bakeng sa lebelo ho e-na le ho fetisoa, 'me e tlose maemo a Optimization Technique logic kgetho. Haeba MAXIMIZE_SPEED e sa sebelisoe, ho tla sebelisoa boleng ba khetho ea Optimization Technique. Haeba peakanyo ya MAXIMIZE_SPEED e le 6 kapa ho feta, Compiler e hodisa LPM_ADD_SUB IP core bakeng sa lebelo le phahameng ka ho sebedisa diketane; haeba maemo a le 5 kapa ka tlase, Compiler e sebelisa moralo ntle le liketane tsa ho jara. Paramethara ena e tlameha ho hlalosoa bakeng sa lisebelisoa tsa Cyclone, Stratix, le Stratix GX ha feela boema-kepe ba add_sub bo sa sebelisoe.
Paramethara ena e sebelisetsoa merero ea ho etsa mohlala le ea boitšoaro. Sehlophisi sa paramethara se bala boleng ba paramethara ena.

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6. LPM_COMPARE (Mopapi)

Setšoantšo sa 5.

LPM_COMPARE IP core e bapisa boleng ba lihlopha tse peli tsa data ho fumana kamano e teng lipakeng tsa tsona. Ka mokhoa oa eona o bonolo, o ka sebelisa heke e ikhethileng-OR ho fumana hore na lintlha tse peli tsa data lia lekana.

Setšoantšo se latelang se bontša likou tsa LPM_COMPARE IP core.

LPM_COMPARE Boema-kepe

LPM_COMPARE

klk

alb

aeb

data[]

agb

datab[]

lilemob

oache

aneb

aclr

aleb

inst

6.1. Likarolo
LPM_COMPARE IP core e fana ka likarolo tse latelang: · E hlahisa mosebetsi oa ho bapisa ho bapisa lihlopha tse peli tsa data · E tšehetsa bophara ba data ba li-bits tse 1 · E ts'ehetsa sebopeho sa boemeli ba data joalo ka ha se saennoe le se sa saenneng · E hlahisa mefuta e latelang ea tlhahiso:
— alb (kenyo A e ka tlase ho kenyo ya B) — aeb (kenyo A e lekana le kenyo B) — agb (kenyo A e kgolo ho feta e kentsweng B) — ageb (kenyo A e kgolo ho feta kapa e lekana le input B) — aneb input A ha e lekane le input B) — aleb (kenyo A e ka tlase kapa e lekana le input B) · E tshehetsa ka boikgethelo asynchronous ho hlaka le wache e nolofalletsa dikou tsa ho kenya · E abela datab[] input ho ya kamehla · E tshehetsa phaepelining ka configurable output latency

ISO 9001:2015 E Ngolisitsoe

6. LPM_COMPARE (Comparator) 683490 | 2020.10.05
6.2. Verilog HDL Prototype
Mohlala o latelang oa Verilog HDL o fumaneha ho Moralo oa Verilog File (.v) lpm.v ka edasynthesis directory.
module lpm_compare ( alb, aeb, agb, aleb, aneb, ageb, dataa, datab, oache, clken, aclr ); parameter lpm_type = "lpm_compare"; parameter lpm_width = 1; paramethara lpm_representation = "HA E TSEBA"; parameter lpm_pipeline = 0; paramethara lpm_hint = "SA SEBELISE"; kenya [lpm_width-1:0] dataa, datab; oache e kenang; input clken; input aclr; output alb, aeb, agb, aleb, aneb, ageb; endmodule
6.3. Phatlalatso ea Karolo ea VHDL
Phatlalatso ea karolo ea VHDL e fumaneha ho Moralo oa VHDL File (.vhd) LPM_PACK.vhd ho librariesvhdllpm directory.
karolo LPM_COMPARE generic (LPM_WIDTH : tlhaho;
LPM_REPRESENTATION : khoele := “E SA SINWE”; LPM_PIPELINE : tlhaho := 0; LPM_TYPE: khoele := L_COMPARE; LPM_HINT : khoele := “HA E SEBELISE”); boema-kepe (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0); DATAB : ho std_logic_vector(LPM_WIDTH-1 downto 0); ACLR : in std_logic := '0'; CLOCK : in std_logic := '0 logic in CLK_logic'; := '1'; AGB : out std_logic; AGEB : out std_logic; AEB : out std_logic; ANEB : out std_logic; ALB : out std_logic; ALEB : out std_logic); karolo ea ho qetela;
6.4. VHDL LIBRARY_USE Phatlalatso
Phatlalatso ea VHDL LIBRARY-USE ha e hlokehe haeba u sebelisa Phatlalatso ea Karolo ea VHDL.
LAEBRARI lpm; SEBELISA lpm.lpm_components.all;
6.5. Maemakepe
Litafole tse latelang li thathamisa libaka tsa ho kenya le tse hlahisoang tsa LMP_COMPARE IP core.

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6. LPM_COMPARE (Comparator) 683490 | 2020.10.05

Lethathamo la 18. LPM_COMPARE IP core Input Ports

Lebitso la Port

Ho hlokahala

Tlhaloso

data[]

Kenya data. Boholo ba sebaka sa ho kenya se ipapisitse le boleng ba paramethara ea LPM_WIDTH.

datab[]

Kenya data. Boholo ba sebaka sa ho kenya se ipapisitse le boleng ba paramethara ea LPM_WIDTH.

oache

Che

Ho kenya oache bakeng sa tšebeliso ea liphaephe. Boema-ts'oants'o ba oache bo fana ka tlhahiso ea oache bakeng sa phaephe

ts'ebetso. Bakeng sa LPM_PIPELINE lipalo tse ling ntle le 0 (kamehla), kou ea oache e tlameha ho ba

nolofalitsoe.

klk

Che

Oache e lumelletse tšebeliso ea liphaephe. Ha boema-kepe ba clken bo boleloa bo le holimo, the

ts'ebetso ea papiso ea etsahala. Ha lets'oao le le tlase, ha ho ts'ebetso e etsahalang. Haeba

e siiloe, boleng ba kamehla ke 1.

aclr

Che

Asynchronous clear bakeng sa tšebeliso ea liphaephe. Phaephe e qala ho ea ho mohopolo o sa hlalosoang (X).

boemo. Boema-kepe ba aclr bo ka sebelisoa ka nako efe kapa efe ho seta lipeipi ho li-0s kaofela,

ka tsela e lumellanang le lesupa la oache.

Lethathamo la 19. LPM_COMPARE IP core Output Ports

Lebitso la Port

Ho hlokahala

Tlhaloso

alb

Che

Boema-kepe ba tlhahiso bakeng sa sebapi. Ho boleloa haeba tlhahiso A e ka tlase ho tlhahiso ea B.

aeb

Che

Boema-kepe ba tlhahiso bakeng sa sebapi. Ho boleloa haeba ho kenya A ho lekana le ho kenya B.

agb

Che

Boema-kepe ba tlhahiso bakeng sa sebapi. Ho boleloa haeba tlhahiso A e kholo ho feta ea B.

lilemob

Che

Boema-kepe ba tlhahiso bakeng sa sebapi. Ho tiiswa haeba ho kenya A ho hoholo kapa ho lekana le ho kenya

aneb

Che

Boema-kepe ba tlhahiso bakeng sa sebapi. Ho boleloa haeba ho kenya A ha ho lekane le ho kenya B.

aleb

Che

Boema-kepe ba tlhahiso bakeng sa sebapi. Ho boleloa haeba tlhahiso A e ka tlase ho kapa e lekana le ea B.

6.6. di-parameter

Lethathamo le latelang le thathamisitse liparamente tsa LPM_COMPARE IP core.

Lethathamo la 20. LPM_COMPARE IP core Parameters

Lebitso la Parameter

Mofuta

Ho hlokahala

LPM_WIDTH

Kakaretso E

LPM_REPRESENTATION

Khoele

Che

LPM_PIPELINE

Nomoro ea nomoro

LPM_HINT

Khoele

Che

Tlhaloso
E hlakisa bophara ba dataa[] le datab[] likou.
E totobatsa mofuta oa papiso e entsoeng. Litekanyetso TSA SAINWE 'me HA LI TLA SONGWE. Haeba e siiloe, boleng ba kamehla HA BO-SAILWE. Ha boleng bona ba paramethara bo behiloe HO SIGNED, motšoantšisi o toloka tlhahiso ea data e le tlatsetso ea tse peli tse saenneng.
E totobatsa palo ea linako tsa oache tsa latency tse amanang le alb, aeb, agb, ageb, aleb, kapa aneb tlhahiso. Boleng ba lefela (0) bo bontša hore ha ho latency e teng, le hore ts'ebetso e kopaneng feela e tla netefatsoa. Haeba e siiloe, boleng ba kamehla ke 0 (ha bo na pipeline).
E u lumella ho hlakisa li-parameter tse khethehileng tsa Intel moahong oa VHDL files (.vhd). Boleng ba kamehla ke UNUSED.
e tsoela pele…

Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi 28

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6. LPM_COMPARE (Comparator) 683490 | 2020.10.05
Lebitso la Parametha LPM_TYPE INTENDED_DEVICE_FAMILY
ONE_INPUT_IS_CONSTANT

Mofuta oa Khoele
Khoele

Ho hlokahala No
Che

Tlhaloso
E tsebahatsa lebitso la setsi la laeborari ea li-parameterized modules (LPM) ka moralo oa VHDL files.
Paramethara ena e sebelisetsoa merero ea ho etsa mohlala le ea boitšoaro. Sehlophisi sa paramethara se bala boleng ba paramethara ena.
Intel-specific parameter. U tlameha ho sebelisa paramethara ea LPM_HINT ho hlakisa ONE_INPUT_IS_CONSTANT moralong oa VHDL. files. Maemo ke YES, CHE, kapa HA SEBELISE. E fana ka ntlafatso e kholoanyane haeba tlhahiso e sa fetohe. Haeba e siiloe, boleng ba kamehla ke NO.

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7. ALTECC (Khoutu ea Phoso ea Phoso: Encoder / Decoder) IP Core

Setšoantšo sa 6.

Intel e fana ka ALTECC IP ea mantlha ho kenya tšebetsong tšebetso ea ECC. ECC e lemoha data e senyehileng e hlahang lehlakoreng la moamoheli nakong ea phetiso ea data. Mokhoa ona oa ho lokisa liphoso o loketse haholo maemong ao liphoso li etsahalang ka tšohanyetso ho fapana le ho phatloha.

ECC e bona liphoso ka ts'ebetso ea khouto ea data le decoding. Bakeng sa mohlalaample, ha ECC e sebelisoa ts'ebetsong ea phetisetso, data e baloang ho tsoa mohloling e kentsoe pele e romelloa ho moamoheli. Sephetho (lentsoe la khoutu) ho tsoa ho encoder se na le data e tala e kentsoeng le palo ea li-parity bits. Palo e nepahetseng ea li-parity bits e kenyellelitsoeng ho latela palo ea li-bits ho data e kentsoeng. Lentsoe la khoutu le hlahisoang le fetisetsoa sebakeng seo le eang ho sona.

Moamoheli o amohela lentsoe la khoutu ebe oa le hlakola. Tlhahisoleseding e fumanweng ke decoder e etsa qeto ya hore na phoso e fumanwe. Decoder e lemoha liphoso tsa karolo e le 'ngoe le tse habeli, empa e ka lokisa liphoso tsa karolo e le' ngoe feela datang e senyehileng. Mofuta ona oa ECC ke mokhoa o le mong oa ho lokisa phoso habeli (SECDED).

O ka hlophisa mesebetsi ea encoder le decoder ea ALTECC IP core. Tlhahisoleseding ea data ho encoder e kenyelelitsoe ho hlahisa lentsoe la khoutu e leng motsoako oa boitsebiso ba data le li-parity bits tse hlahisitsoeng. Lentsoe la khoutu le hlahisoang le fetisetsoa mojuleng oa li-decoder bakeng sa ho etsa decoder pele feela le fihla sebakeng seo le eang ho sona. Decoder e hlahisa "syndrome vector" ho bona hore na ho na le phoso lentsoeng le amoheloang. Decoder e lokisa data ha feela phoso e le 'ngoe e tsoa ho likotoana tsa data. Ha ho lets'oao le tšoailoeng haeba phoso e le 'ngoe e tsoa ho li-parity bits. Decoder e boetse e na le matšoao a lifolakha ho bonts'a boemo ba data e amohetsoeng le ketso e nkuoeng ke decoder, haeba e teng.

Lipalo tse latelang li bonts'a likou tsa ALTECC IP core.

ALTECC Encoder Ports

ALTECC_ENCODER

lintlha[]

q[]

oache

tshupanako

aclr

inst

ISO 9001:2015 E Ngolisitsoe

7. ALTECC (Khoutu ea Phoso ea Phoso: Encoder / Decoder) IP Core 683490 | 2020.10.05

Setšoantšo sa 7. ALTECC Decoder Ports

ALTECC_DECODER

data[] oache oache

q[] err_detected err_corrected
err_fatal

aclr

inst

7.1. ALTECC Encoder Features

ALTECC encoder IP core e fana ka lintlha tse latelang: · E etsa khouto ea data e sebelisa Hamming Coding scheme · E ts'ehetsa bophara ba data ba li-bits tse 2 · E ts'ehetsa sebopeho sa boemeli ba data e saennoeng le e sa ngolisoang · Ts'ehetso ea pipelining e nang le latency ea tlhahiso ea nako e le 'ngoe kapa tse peli. asynchronous clear le oache e nolofalletsa likou

ALTECC encoder IP core e nka le ho e khouta data e sebelisa leano la Hamming Coding. Sekema sa Hamming Coding se fumana li-parity bits mme se li kopanya ho data ea mantlha ho hlahisa lentsoe la khoutu ea tlhahiso. Palo ea li-parity bits e kenyellelitsoeng ho latela bophara ba data.

Tafole e latelang e thathamisa palo ea li-parity bits tse kenyellelitsoeng mefuteng e fapaneng ea bophara ba data. Kholomo ea Kakaretso ea Bits e emela kakaretso ea palo ea lintlha tse kentsoeng le li-parity bits tse hlomathisitsoeng.

Lethathamo la 21.

Palo ea Parity Bits le Code Word Ho latela Data Width

Bophara ba Boitsebiso

Palo ea Parity Bits

Kakaretso ea Bits (Code Word)

2-4

3+1

6-8

5-11

4+1

10-16

12-26

5+1

18-32

27-57

6+1

34-64

58-64

7+1

66-72

Parity bit derivation e sebelisa tlhahlobo ea even-parity. 1 Bit e eketsehileng (e bontšitsoeng tafoleng e le +1) e kenyelelitsoe ho li-parity bits e le MSB ea lentsoe la khoutu. Sena se tiisa hore lentsoe la khoutu le na le palo e lekanang ea 1's. Bakeng sa mohlalaample, haeba bophara ba data ke li-bits tse 4, likotoana tse 4 tsa parity li kenyellelitsoe ho data ho fetoha lentsoe la khoutu le nang le kakaretso ea likotoana tse 8. Haeba 7 bits ho tsoa ho LSB ea 8-bit code word e na le palo e sa tloaelehang ea 1's, 8th bit (MSB) ea lentsoe la khoutu ke 1 ho etsa palo eohle ea 1 lentsoeng la khoutu esita le.
Setšoantšo se latelang se bonts'a lentsoe la khoutu e hlahisitsoeng le tlhophiso ea li-parity bits le data bits ka ho kenya data ea 8-bit.

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7. ALTECC (Khoutu ea Phoso ea Phoso: Encoder / Decoder) IP Core 683490 | 2020.10.05

Setšoantšo sa 8.

Parity Bits le Data Bits Tokisetso ka 8-Bit Hlahisa Code Word

MSB

LSB

4 likotoana tse lekanang

4 lintlha tsa data

ALTECC encoder IP core e amohela feela bophara ba ho kenya 2 ho isa ho 64 bits ka nako e le 'ngoe. Bophara ba ho kenya li-bits tse 12, 29, le 64 bits, tse loketseng lisebelisoa tsa Intel, li hlahisa lihlahisoa tsa 18 bits, 36 bits, le 72 bits ka ho latellana. U ka khona ho laola moeli oa bitselection ho mohlophisi oa parameter.

7.2. Verilog HDL Prototype (ALTECC_ENCODER)
Mohlala o latelang oa Verilog HDL o fumaneha ho Moralo oa Verilog File (.v) lpm.v ka edasynthesis directory.
module altecc_encoder #( parameter purpose_device_family = “e sa sebelisoeng”, paramethara lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = “altecc_encoder”, parameter lpm_hint = “unused wireclr”) ( input wirec, input wire wire clocken, terata e kenyang [width_dataword-1:0] data, terata e tsoang [width_codeword-1:0] q); endmodule

7.3. Verilog HDL Prototype (ALTECC_DECODER)
Mohlala o latelang oa Verilog HDL o fumaneha ho Moralo oa Verilog File (.v) lpm.v ka edasynthesis directory.
module altecc_decoder #( parameter purpose_device_family = “e sa sebelisoeng”, paramethara lpm_pipeline = 0, parametha bophara_codeword = 8, parametha bophara_dataword = 8, parametha lpm_type = “altecc_decoder”, parametha lpm_hint = “unused wireclr”) ( input wirec wire clocken, input wire [width_codeword-1:0] data, output wire err_corrected, output wire err_detected, outut wire err_fatal, output wire [width_dataword-1:0] q); endmodule

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7. ALTECC (Khoutu ea Phoso ea Phoso: Encoder / Decoder) IP Core 683490 | 2020.10.05
7.4. Phatlalatso ea Karolo ea VHDL (ALTECC_ENCODER)
Phatlalatso ea karolo ea VHDL e fumaneha ho Moralo oa VHDL File (.vhd) altera_mf_components.vhd ho librariesvhdlaltera_mf directory.
component altecc_encoder generic ( target_device_family: string : = "sa sebelisoe"; lpm_pipeline: natural := 0; width_codeword: natural := 8; width_dataword: natural : = 8; lpm_hint: string := "UNUSED "alphap":cclpte ”); port( aclr: in std_logic := '0'; clock: in std_logic := '0'; clocken: in std_logic := '1'; data: in std_logic_vector(width_dataword-1 downto 0); q:out std_logic_vector(width_codeword) -1 ho ea ho 0)); karolo ea ho qetela;
7.5. Phatlalatso ea Karolo ea VHDL (ALTECC_DECODER)
Phatlalatso ea karolo ea VHDL e fumaneha ho Moralo oa VHDL File (.vhd) altera_mf_components.vhd ho librariesvhdlaltera_mf directory.
component altecc_decoder generic ( target_device_family: string : = "sa sebelisoe"; lpm_pipeline: natural := 0; width_codeword: natural := 8; width_dataword: natural : = 8; lpm_hint: string : = "UNUSED "typealp": cclpte ”); port( aclr: in std_logic := '0'; clock: in std_logic := '0'; clocken: in std_logic := '1'; data: in std_logic_vector(width_codeword-1 downto 0); err_corrected: out std_logic; err_detected : tsoa std_logic; q:out std_logic_vector(width_dataword-1 downto 0); syn_e: tsoa std_logic); karolo ea ho qetela;
7.6. VHDL LIBRARY_USE Phatlalatso
Phatlalatso ea VHDL LIBRARY-USE ha e hlokehe haeba u sebelisa Phatlalatso ea Karolo ea VHDL.
LIBRARY altera_mf; SEBELISA altera_mf.altera_mf_components.all;
7.7. Encoder Ports
Litafole tse latelang li thathamisa likou tsa ho kenya le tse hlahisoang bakeng sa konokono ea IP ea encoder ea ALTECC.

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7. ALTECC (Khoutu ea Phoso ea Phoso: Encoder / Decoder) IP Core 683490 | 2020.10.05

Letlapa la 22. ALTECC Encoder Input Ports

Lebitso la Port

Ho hlokahala

Tlhaloso

lintlha[]

Kou ea ho kenya data. Boholo ba sebaka sa ho kenya se ipapisitse le WIDTH_DATAWORD

boleng ba parameter. Boema-kepe[] ba data bo na le data e sa hlahisoang e lokelang ho khoutooa.

oache

Kou ea ho kenya oache e fanang ka lets'oao la oache ho hokahanya ts'ebetso ea khouto.

Boema-fofane boa hlokahala ha boleng ba LPM_PIPELINE bo feta 0.

tshupanako

Che

Oache e nolofalletsa. Haeba e siiloe, boleng ba kamehla ke 1.

aclr

Che

Kenyelletso e hlakileng ea Asynchronous. Letšoao le sebetsang le phahameng la aclr le ka sebelisoa neng kapa neng ho

hlakola lirejista ka mokhoa o sa tsitsang.

Letlapa la 23. ALTECC Encoder Output Ports

Lebitso la Boemakepe q[]

Ho Hlokahala E

Tlhaloso
Kou ea tlhahiso ea data e kentsoeng. Boholo ba sebaka sa tlhahiso bo itšetlehile ka boleng ba paramethara ea WIDTH_CODEWORD.

7.8. Decoder Ports

Litafole tse latelang li thathamisa likou tsa ho kenya le tse hlahisoang bakeng sa setsi sa IP sa AlTECC decoder.

Letlapa la 24. ALTECC Decoder Input Ports

Lebitso la Port

Ho hlokahala

Tlhaloso

lintlha[]

Kou ea ho kenya data. Boholo ba sebaka sa ho kenya se ipapisitse le boleng ba paramethara ea WIDTH_CODEWORD.

oache

Kou ea ho kenya oache e fanang ka lets'oao la oache ho hokahanya ts'ebetso ea khouto. Boema-fofane boa hlokahala ha boleng ba LPM_PIPELINE bo feta 0.

tshupanako

Che

Oache e nolofalletsa. Haeba e siiloe, boleng ba kamehla ke 1.

aclr

Che

Kenyelletso e hlakileng ea Asynchronous. Letšoao le sebetsang le phahameng la aclr le ka sebelisoa ka nako efe kapa efe ho hlakola lirekoto ka mokhoa o hlakileng.

Letlapa la 25. ALTECC Decoder Output Ports

Lebitso la Boemakepe q[]

Ho Hlokahala E

Tlhaloso
Decoded data output port. Boholo ba port port bo ipapisitse le boleng ba paramethara ea WIDTH_DATAWORD.

Err_detected E

Letšoao la ho tšoaea ho bonts'a boemo ba data e amohetsoeng le ho hlakisa liphoso tse fumanoeng.

err_correct E d

Letšoao la ho tšoaea ho bonts'a boemo ba data e amohetsoeng. E supa phoso ea karolo e le 'ngoe e fumanoeng le ho lokisoa. U ka sebelisa data hobane e se e lokisitsoe.

err_fatal

Letšoao la ho tšoaea ho bonts'a boemo ba data e amohetsoeng. E supa phoso e habeli e fumanoeng, empa e sa lokisoa. Ha ua tlameha ho sebelisa data haeba lets'oao lena le tiisitsoe.

syn_e

Che

Letšoao la tlhahiso le tla phahama neng kapa neng ha phoso e le 'ngoe e fumanoa ho parity

likotoana.

7.9. Encoder Parameters
Tafole e latelang e thathamisa liparamente tsa ALTECC encoder IP core.

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7. ALTECC (Khoutu ea Phoso ea Phoso: Encoder / Decoder) IP Core 683490 | 2020.10.05

Letlapa la 26. ALTECC Encoder Parameters

Lebitso la Parameter

Mofuta

Ho hlokahala

Tlhaloso

WIDTH_DATAWORD

Kakaretso E

E hlalosa bophara ba data e tala. Boleng bo tsoa ho 2 ho isa ho 64. Haeba e siiloe, boleng ba kamehla ke 8.

WIDTH_CODEWORD

Kakaretso E

E bolela bophara ba lentsoe la khoutu e tsamaellanang. Lipalo tse sebetsang li tsoa ho 6 ho isa ho 72, ho sa kenyeletsoe 9, 17, 33, le 65. Haeba e siiloe, boleng ba kamehla ke 13.

LPM_PIPELINE

Nomoro ea nomoro

E totobatsa lipeipi tsa potoloho. Litekanyetso li tsoa ho 0 ho isa ho 2. Haeba boleng bo le 0, likou ha lia ngolisoa. Haeba boleng ke 1, likou tsa lihlahisoa li ngolisitsoe. Haeba boleng bo le 2, likou tsa ho kenya le ho tsoa li ngolisitsoe. Haeba e siiloe, boleng ba kamehla ke 0.

7.10. Decoder Parameters

Tafole e latelang e thathamisa ALTECC decoder IP core parameters.

Letlapa la 27. ALTECC Decoder Parameters

Lebitso la Parametha WIDTH_DATAWORD

Type Integer

Ho hlokahala

Tlhaloso

E hlalosa bophara ba data e tala. Maemo ke 2 ho isa ho 64. The

boleng ba kamehla ke 8.

WIDTH_CODEWORD

Palo kaofela

E bolela bophara ba lentsoe la khoutu e tsamaellanang. Boleng ke 6

ho ea ho 72, ho sa kenyeletsoe 9, 17, 33, le 65. Haeba e siiloe, boleng ba kamehla

ke 13.

LPM_PIPELINE

Palo kaofela

Che

E hlalosa rejisetara ea potoloho. Maemo a tsoa ho 0 ho isa ho 2. Haeba the

boleng ke 0, ha ho ngoliso e kengoang ts'ebetsong. Haeba boleng ke 1, the

tlhahiso e ngodisitsoe. Haeba boleng ke 2, bobeli kenyeletso le the

tlhahiso ba ngolisoa. Haeba boleng bo le boholo ho feta 2, tlatsetso

li-registerers li kengoa tšebetsong ha li hlahisoa bakeng sa tlatsetso

latencies. Haeba e siiloe, boleng ba kamehla ke 0.

Theha kou ea 'syn_e'

Palo kaofela

Che

Bulela parameter ena ho theha sebaka sa syn_e.

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683490 | 2020.10.05 Romella Maikutlo

8. Intel FPGA Multiply Adder IP Core

Setšoantšo sa 9.

Intel FPGA Multiply Adder (Intel Stratix 10, Intel Arria 10, le Intel Cyclone 10 GX lisebelisoa) kapa ALTERA_MULT_ADD (Arria V, Stratix V, le Cyclone V lisebelisoa) motheo oa IP o u lumella ho kenya ts'ebetsong adder-multiplier.

Setšoantšo se latelang se bontša likou tsa Intel FPGA Multiply Adder kapa ALTERA_MULT_ADD IP core.

Intel FPGA Multiply Adder kapa ALTERA_MULT_ADD Ports

Intel FPGA Multiply Adder kapa ALTERA_MULT_ADD

dataa[] signa datab[] signb datac[] coefsel0[] coefsel1[] coefsel2[] coefsel3[] addnsub1 addnsub3 aclr/sclr[] scanina[] clock0 clock1 clock2 ena0 ena1 ena2 sload_accum
accum_sload ketane[]

scanouta[] sephetho[]

acl0 aclr1

inst
Multiplier-adder e amohela lipara tsa lintho tse kenngoeng, e atisa boleng hammoho ebe e eketsa kapa e fokotsa lihlahisoa tsa lipara tse ling kaofela.
Haeba bophara ba data e kentsoeng e le bophara ba li-bits tse 9 kapa tse nyane, ts'ebetso e sebelisa 9 x 9 bit input multiplier configuration sebakeng sa DSP bakeng sa lisebelisoa tse tšehetsang 9 x 9 tlhophiso. Haeba ho se joalo, block ea DSP e sebelisa 18 × 18-bit input multiplier ho sebetsana le data ka bophara pakeng tsa 10 bits le 18 bits. Haeba multiple Intel FPGA Multiply Adder kapa ALTERA_MULT_ADD IP cores e etsahala ka moralo, mesebetsi e abeloa joalo ka

ISO 9001:2015 E Ngolisitsoe

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05
li-blocks tse ngata tse fapaneng tsa DSP kamoo ho ka khonehang e le hore ho ea li-blocks ho bonolo haholoanyane. Li-multiplier tse fokolang ka boloko ba DSP li lumella likhetho tse ngata tsa ho tsamaisa li-block ka ho fokotsa litsela tse eang ho sesebelisoa kaofela.
Lirejisetara le lipeipi tsa tlatsetso bakeng sa matšoao a latelang le tsona li behiloe ka har'a boloko ba DSP: · Kenyeletso ea data · Khetho e saenneng kapa e sa saenoang · Eketsa kapa fokotsa khetho · Lihlahisoa tsa li-multiplier.
Tabeng ea sephetho sa sephetho, ngoliso ea pele e behiloe ho thibela DSP. Leha ho le joalo, lirejisete tse ling tsa latency li behiloe linthong tsa logic ka ntle ho block. Peripheral ho thibela DSP, ho kenyeletsoa lintlha tse kenang ho multiplier, lisebelisoa tsa pontšo ea taolo, le liphello tsa adder, sebelisa mokhoa o tloaelehileng oa ho buisana le lisebelisoa tse ling. Lihokelo tsohle tšebetsong li sebelisa litsela tse inehetseng kahare ho block ea DSP. Mokhoa ona o ikhethileng o kenyelletsa liketane tsa li-shift registering ha u khetha khetho ea ho tlosa lintlha tse ngolisitsoeng tsa ba atisang ho tloha ho se atisang ho ea ho se atisang se bapileng.
Ho fumana lintlha tse ling mabapi le li-block tsa DSP ho efe kapa efe ea Stratix V, le letoto la lisebelisoa tsa Arria V, sheba khaolo ea DSP Blocks ea libuka tse fapaneng leqepheng la Literature and Technical Documentation.
Tlhahisoleseding e Amanang le AN 306: Ho kenya tšebetsong li-multiplier ho lisebelisoa tsa FPGA
E fana ka leseli le eketsehileng mabapi le ho kenya tšebetsong li-multiplier ho sebelisa DSP le li-memory block ho lisebelisoa tsa Intel FPGA.
8.1. Likarolo
Intel FPGA Multiply Adder kapa ALTERA_MULT_ADD IP core e fana ka lintlha tse latelang: · E hlahisa se atisang ho sebetsa ka makhetlo a mabeli.
Nomoro Tlhokomeliso: Ha u haha li-multiplier tse kholo ho feta boholo bo tšehetsoeng ka tlhaho ho na le /
e tla ba tšusumetso ea ts'ebetso e bakoang ke ho putlama ha li-block tsa DSP. · E ts'ehetsa bophara ba data ba li-bits tse 1 256 · E tšehetsa sebopeho sa boemeli ba data e saennoeng le e sa saenneng · E tšehetsa pipelining ka configurable input latency · E fana ka khetho ea ho fetola ka matla pakeng tsa tšehetso ea data e saennoeng le e sa saennoeng · E fana ka khetho ea ho fetola ka matla pakeng tsa ts'ebetso ea ho eketsa le ho tlosa boikhethelo asynchronous le synchronous clear and clock thusa input ports · E ts'ehetsa mokhoa oa systolic delay register · E ts'ehetsa pre-adder ka li-coefficients tse 8 tsa pre-load ka mochini o mong le o mong.

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

8.1.1. Pre-adder
Ka pre-adder, ho eketsa kapa ho fokotsa ho etsoa pele ho fepa mochine o atisang.
Ho na le mekhoa e mehlano ea li-pre-adder: · Mokhoa o bonolo · Coefficient mode · Input mode · Square mode · Constant mode

Hlokomela:

Ha pre-adder e sebelisoa (pre-adder coefficient/input/square mode), lisebelisoa tsohle tsa data ho multiplier li tlameha ho ba le mokhoa o tšoanang oa oache.

8.1.1.1. Pre-adder Mokhoa o Bonolo

Ka mokhoa ona, li-operands ka bobeli li tsoa likoung tsa ho kenya 'me li-pre-adder ha li sebelisoe kapa tsa fetisoa. Ena ke mokhoa oa kamehla.

Setšoantšo sa 10. Pre-adder Mode o Bonolo
a0 b0

Ka bongata0

sephetho

8.1.1.2. Pre-adder Coefficient Mode
Ka mokhoa ona, operand e 'ngoe ea li-multiplier e tsoa ho pre-adder,' me operand e 'ngoe e tsoa ho polokelo ea coefficient e ka hare. Pokello ea coefficient e lumella li-constants tse 8 esale pele. Lipontšo tsa khetho ea coefficient ke coefsel[0..3].
Mokhoa ona o hlahisoa ka equation e latelang.

Se latelang se bonts'a mokhoa oa pre-adder coefficient oa multiplier.

Setšoantšo sa 11. Pre-adder Coefficient Mode

Preadder

Ka bongata0

+/-

sephetho

coefsel0 khoho

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05
8.1.1.3. Mokhoa oa ho Kena ka Pele Mokhoeng ona, opereishene e le 'ngoe e atisang ho feta e tsoa ho pre-adder, 'me operand e 'ngoe e tsoa ho "datac[] input port port. Mokhoa ona o hlahisoa ka equation e latelang.

Se latelang se bonts'a mokhoa oa ho kenya li-pre-adder oa ho atisa.

Setšoantšo sa 12. Mokhoa oa ho Kena ka Pele ho Adder
a0 b0

Ka bongata0

+/-

sephetho

8.1.1.4. Pre-adder Square Mode Mokhoa ona o hlahisoa ka equation e latelang.

Se latelang se bontša pre-adder square mode ea li-multiplier tse peli.

Setšoantšo sa 13. Pre-adder Square Mode
a0 b0

Ka bongata0

+/-

sephetho

8.1.1.5. Pre-adder Constant Mode
Ka mokhoa ona, opereishene e 'ngoe ea li-multiplier e tsoa boema-kepeng ba ho kenya,' me e 'ngoe e tsoa ho polokelo ea coefficient e ka hare. Pokello ea coefficient e lumella li-constants tse 8 esale pele. Lipontšo tsa khetho ea coefficient ke coefsel[0..3].
Mokhoa ona o hlahisoa ka equation e latelang.

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Setšoantšo se latelang se bonts'a mokhoa o tsitsitseng oa pele ho adder oa ho atisa.

Setšoantšo sa 14. Pre-adder Constant Mode
a0

Ka bongata0

sephetho

coefsel0
khofu
8.1.2. Ngoliso ea ho lieha ha Systolic
Ka meralo ea systolic, lintlha tse kentsoeng li fepeloa ka har'a lethathamo la lirekoto tse sebetsang joalo ka buffer ea data. Rejisetara e 'ngoe le e 'ngoe e fana ka tlhahiso sample ho ngatafatsi moo e atisang ho atolosoa ke coefficient e fapaneng. The chain adder e boloka liphetho tse kopantsoeng butle-butle ho tsoa ho se atisang le sephetho se ngolisitsoeng pele ho tsoa ho "chainin" port port ho etsa sephetho sa ho qetela. Karolo e 'ngoe le e 'ngoe ea ho eketsa hangata e tlameha ho lieha ka potoloho e le' ngoe e le hore liphetho li hokahane ka nepo ha li kopantsoe hammoho. Tieho e 'ngoe le e 'ngoe e latellanang e sebelisoa ho sebetsana le memori ea coefficient le buffer ea data ea likarolo tse fapaneng tsa ho eketsa hangata. Bakeng sa mohlalaample, tieho e le 'ngoe bakeng sa karolo ea bobeli ea ho atisa ho eketsa, litiehiso tse peli bakeng sa karolo ea boraro ea ho eketsa hangata, joalo-joalo.
Setšoantšo sa 15. Li-Systolic Registers
Litokomane tsa systolic

x(t) c(0)

S -1

c(1)

S -1

c(2)

S -1

c(N-1)

S -1

S -1 y(t)

x(t) e emetse liphetho ho tsoa ho molapo o tsoelang pele oa ho kenya samples le y(t)
e emela kakaretso ea sete ea ho kenya samples, 'me ha nako e ntse e ea, ea atisoa ke bona
li-coefficients tse fapaneng. Ka bobeli liphetho tsa tlhahiso le tlhahiso li phalla ho tloha ho le letšehali ho ea ho le letona. C(0) ho isa ho c(N-1) e bolela li-coefficients. Lingoliloeng tsa ho lieha ha systolic li hlalosoa ke S-1, athe 1 e emela tieho ea oache e le 'ngoe. Lirekoto tsa ho lieha ha systolic li eketsoa ho
lintho tse kenang le tse hlahisoang bakeng sa ho tsamaisa lipeipi ka mokhoa o netefatsang liphetho tse tsoang ho
multiplier operand le lipalo tse bokelletsoeng li lula li lumellana. Karolo ena ea ts'ebetso
e kopitsoa ho etsa potoloho e kopanyang mosebetsi oa ho sefa. Mosebetsi ona ke
e hlahisitsoeng ka equation e latelang.

Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi 40

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

N e emela palo ea li-cycles tsa data tse kentsoeng ho accumulator, y(t) e emetse tlhahiso ka nako t, A(t) e emetse tlhahiso ka nako t, le B(i) ke li-coefficients. T le i ho equation li tsamaellana le hang hang ka nako, kahoo ho bala tlhahiso s.ample y(t) ka nako t, sehlopha sa ho kenya sampe fokotsehile libakeng tse fapaneng tsa N ka nako, kapa A(n), A(n-1), A(n-2), … A(n-N+1) ea hlokahala. Sehlopha sa N input sampli-le li atisa ka li-coefficients tsa N 'me li akaretsoa hammoho ho etsa sephetho sa ho qetela y.
Meaho ea systolic register e fumaneha feela bakeng sa mekhoa ea kakaretso ea 2 le kakaretso ea 4. Bakeng sa mekhoa e 'meli ea meralo ea systolic, lets'oao la pele la ketane le hloka ho tlamelloa ho 0.
Setšoantšo se latelang se bontša ts'ebetsong ea ngoliso ea ho lieha ea systolic ea li-multiplier tse peli.
Setšoantšo sa 16. Systolic Delay Register Ts'ebetsong ea 2 Multipliers
ketane

Ka bongata0

+/-

Ka bongata1

+/-

sephetho
Kakaretso ea li-multiplier tse peli e hlahisoa ho equation e latelang.
Setšoantšo se latelang se bontša ts'ebetsong ea ngoliso ea ho lieha ea systolic ea li-multiplier tse peli.

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Setšoantšo sa 17. Systolic Delay Register Ts'ebetsong ea 4 Multipliers
ketane

Ka bongata0

+/-

Ka bongata1

+/-

Ka bongata2

+/-

Ka bongata3

+/-

sephetho
Kakaretso ea li-multiplier tse 'ne e hlahisoa ho equation e latelang. Setšoantšo sa 18. Kakaretso ea li-multiplier tse 4
Se latelang se thathamisa advantages of systolic registering applications

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

8.1.3. Tlanya esale pele Constant
Nako ea ho jara esale pele e laola tšebetso ea accumulator mme e tlatsa maikutlo a accumulator. LOADCONST_VALUE e nepahetseng e tloha ho 0. Theko e sa fetoheng e lekana le 64N, moo N = LOADCONST_VALUE. Ha LOADCONST_VALUE e behiloe ho 2, boleng bo sa fetoheng bo lekana le 64. Mosebetsi ona o ka sebelisoa e le ho pota-pota ka leeme.
Setšoantšo se latelang se bonts'a ts'ebetsong ea kamehla ea pele ho mojaro.
Setšoantšo sa 19. Pre-load Constant

Maikutlo a Accumulator

kamehla

Ka bongata0

+/-

Ka bongata1

+/b1

sephetho

accum_sload sload_accum

Sheba li-cores tse latelang tsa IP bakeng sa lisebelisoa tse ling tse ngatafatsang: · ALTMULT_ACCUM · ALTMEMMULT · LPM_MULT
8.1.4. Habeli Accumulator
Karolo e 'meli ea accumulator e eketsa ngoliso e eketsehileng tseleng ea maikutlo ea accumulator. Rejistara ea li-accumulator tse habeli e latela rejisetara ea tlhahiso, e kenyelletsang oache, oache e nolofalletsang, le aclr. Rejistara e eketsehileng ea accumulator e khutlisa sephetho ka tieho ea potoloho e le 'ngoe. Karolo ena e u thusa ho ba le likanale tse peli tsa accumulator tse nang le palo e tšoanang ea lisebelisoa.
Palo e latelang e bonts'a ts'ebetsong ea accumulator habeli.

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Setšoantšo sa 20. Habeli Accumulator

Etsa Rejistara ea Accu mulator

Accu mulator feedba ck

Ka bongata0

+/-

Ka bongata1

+/b1

Sephetho sa Output Register

8.2. Verilog HDL Prototype
U ka fumana mofuta oa Intel FPGA Multiply Adder kapa ALTERA_MULT_ADD Verilog HDL prototype file (altera_mult_add_rtl.v) ho lilaebrari megafunctions directory.
8.3. Phatlalatso ea Karolo ea VHDL
Phatlalatso ea karolo ea VHDL e fumaneha ho altera_lnsim_components.vhd ho librariesvhdl altera_lnsim directory.
8.4. VHDL LIBRARY_USE Phatlalatso
Phatlalatso ea VHDL LIBRARY-USE ha e hlokehe haeba u sebelisa Phatlalatso ea Karolo ea VHDL.
LIBRARY altera_mf; SEBELISA altera_mf.altera_mf_components.all;

8.5. Lipontšo

Litafole tse latelang li thathamisa matšoao a ho kenya le ho tsoa a Multiply Adder Intel FPGA IPor ALTERA_MULT_ADD IP core.

Letlapa la 28. Adder Adder Intel FPGA IPor ALTERA_MULT_ADD Lipontšo Tse Kenang

Letshwao

Ho hlokahala

Tlhaloso

dataa_0[]/dataa_1[]/

dataa_2[]/dataa_3[]

Ho kenya data ho morekisi. Kenyo ea koung [NUMBER_OF_MULTIPLIERS * WIDTH_A – 1 … 0] bophara
e tsoela pele…

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Letshwao la datab_0[]/datab_1[]/ datab_2[]/datab_3[] datac_0[] /datac_1[]/ datac_2[]/datac_3[] tshupanako[1:0] aclr[1:0] sclr[1:0] ena [1:0] pontšo
sekab
scanina[] accum_sload

Ho Hlokahala E Che
Che Che Che Che Che Che
Che
Che, No

Tlhaloso
Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba ho kenya (X) ho matšoao ana. Ha o fana ka boleng ba X ho matšoao ana, boleng ba X bo phatlalatsoa ho matšoao a tlhahiso.
Ho kenya data ho morekisi. Letšoao la ho kenya [NUMBER_OF_MULTIPLIERS * WIDTH_B – 1 … 0] ka bophara Moetso oa ketsiso oa IP ena o tšehetsa boleng bo sa tsejoeng ba ho kenya (X) ho matšoao ana. Ha o fana ka boleng ba X ho matšoao ana, boleng ba X bo phatlalatsoa ho matšoao a tlhahiso.
Ho kenya data ho morekisi. Letšoao la ho kenya [NUMBER_OF_MULTIPLIERS * WIDTH_C – 1, … 0] bophara Kgetha INPUT bakeng sa Khetha paramethara ya boemo ba preadder ho bulela matshwao ana. Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba ho kenya (X) ho matšoao ana. Ha o fana ka boleng ba X ho matšoao ana, boleng ba X bo phatlalatsoa ho matšoao a tlhahiso.
Kou ea ho kenya oache ho rejisetara e tsamaellanang. Letšoao lena le ka sebelisoa ke ngoliso efe kapa efe ho IP core. Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba ho kenya (X) ho matšoao ana. Ha o fana ka boleng ba X ho matšoao ana, boleng ba X bo phatlalatsoa ho matšoao a tlhahiso.
Kenyelletso e hlakileng ea Asynchronous ho rejisetara e tsamaellanang. Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba ho kenya (X) ho matšoao ana. Ha o fana ka boleng ba X ho matšoao ana, boleng ba X bo phatlalatsoa ho matšoao a tlhahiso.
Kenyelletso e hlakileng ea synchronous ho rejisetara e tsamaellanang. Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba X ho matšoao ana. Ha o fana ka boleng ba X ho matšoao ana, boleng ba X bo phatlalatsoa ho matšoao a tlhahiso
Numella ho kenya lets'oao ho rejisetara e tsamaellanang. Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba ho kenya (X) ho matšoao ana. Ha o fana ka boleng ba X ho matšoao ana, boleng ba X bo phatlalatsoa ho matšoao a tlhahiso.
E hlakisa kemelo ea linomoro ea kenyo e ngatafatsang A. Haeba lets'oao la lets'oao le le hodimo, morekisi o nka palo e ngatafatsang Letshwao la A e le nomoro e saennweng. Haeba lets'oao la signa le le tlase, morekisi o nka lets'oao la ho ngatafatsa A lets'oao e le nomoro e sa ngolisoang. Kgetha VARIABLE bakeng sa Sebopeho sa boemedi ba Multipliers A parameter ho etsa hore letshwao lena le kgonehe. Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba ho kenya (X) lets'oao lena. Ha o fana ka boleng ba X ho kenyelletso ena, boleng ba X bo hasoa ka matšoao a tlhahiso.
E hlakisa kemelo ea linomoro ea lets'oao la B e ngatafatsang. Haeba lets'oao la matšoao le le holimo, moreki o tšoara lets'oao la B e ngatafatsang joalo ka nomoro ea tlatsetso ea tse peli tse saenneng. Haeba lets'oao la matšoao le le tlase, moreki o nka lets'oao la B le ngatafatsang joalo ka nomoro e sa ngolisoang. Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba ho kenya (X) lets'oao lena. Ha o fana ka boleng ba X ho kenyelletso ena, boleng ba X bo hasoa ka matšoao a tlhahiso.
Kenyo bakeng sa ketane ea scan A. Letšoao la ho kenya [WIDTH_A – 1, … 0] ka bophara. Ha paramethara ea INPUT_SOURCE_A e na le boleng ba SCANA, ho tla hlokahala lets'oao la scanina[].
Ka matla e hlakisa hore na boleng ba accumulator bo lula bo le teng. Haeba lets'oao la accum_sload le le tlase, tlhahiso ea bongata e kenngoa ka har'a accumulator. Se ke oa sebelisa accum_sload le sload_accum ka nako e le 'ngoe.
e tsoela pele…

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Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi 45

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Letšoao la sload_accum
chainin[] addnsub1
tlatsetso3
coefsel0[] coefsel1[] coefsel2[] coefsel3[]

Ho hlokahala No
Che, No
Che
Che Che Che No No

Tlhaloso
Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba ho kenya (X) lets'oao lena. Ha o fana ka boleng ba X ho kenyelletso ena, boleng ba X bo hasoa ka matšoao a tlhahiso.
Ka matla e hlakisa hore na boleng ba accumulator bo lula bo le teng. Haeba lets'oao la sload_accum le phahame, joale tlhahiso ea bongata e kenngoa ka har'a accumulator. Se ke oa sebelisa accum_sload le sload_accum ka nako e le 'ngoe. Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba ho kenya (X) lets'oao lena. Ha o fana ka boleng ba X ho kenyelletso ena, boleng ba X bo hasoa ka matšoao a tlhahiso.
Bese e kenyang sephetho sa Adder ho tsoa ho tse tlang peletage. Letšoao la ho kenya [WIDTH_CHAININ – 1, … 0] ka bophara.
Eketsa kapa ho fokotsa ho tsoa ho li-multiplier tse peli. Kenya 1 ho lets'oao la addnsub1 ho eketsa liphetho ho tsoa ho li-multiplier tsa pele. Kenya 0 ho lets'oao la addnsub1 ho tlosa liphetho ho tsoa ho li-multiplier tsa pele. Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba ho kenya (X) lets'oao lena. Ha o fana ka boleng ba X ho kenyelletso ena, boleng ba X bo hasoa ka matšoao a tlhahiso.
Eketsa kapa ho fokotsa ho tsoa ho li-multiplier tse peli. Kenya 1 ho lets'oao la addnsub3 ho eketsa liphetho ho tsoa ho li-multiplier tse peli. Kenya 0 ho lets'oao la addnsub3 ho tlosa liphetho ho tsoa ho li-multiplier tsa pele. Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba ho kenya (X) lets'oao lena. Ha o fana ka boleng ba X ho kenyelletso ena, boleng ba X bo hasoa ka matšoao a tlhahiso.
Letšoao la ho kenya li-coefficient[0:3] ho sehatisi sa pele. Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba ho kenya (X) lets'oao lena. Ha o fana ka boleng ba X ho kenyelletso ena, boleng ba X bo hasoa ka matšoao a tlhahiso.
Letšoao la ho kenya li-coefficient[0:3]ho ea kabofatso ea bobeli. Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba ho kenya (X) lets'oao lena. Ha o fana ka boleng ba X ho kenyelletso ena, boleng ba X bo hasoa ka matšoao a tlhahiso.
Letšoao la ho kenya li-coefficient[0:3]ho ea ho sekatisetsa sa boraro. Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba ho kenya (X) lets'oao lena. Ha o fana ka boleng ba X ho kenyelletso ena, boleng ba X bo hasoa ka matšoao a tlhahiso.
Letšoao la ho kenya li-coefficient [0:3] ho e ngatafatsang ea bone. Moetso oa ketsiso oa IP ena o ts'ehetsa boleng bo sa tsejoeng ba ho kenya (X) lets'oao lena. Ha o fana ka boleng ba X ho kenyelletso ena, boleng ba X bo hasoa ka matšoao a tlhahiso.

Letlapa la 29. Adder Adder Intel FPGA IP Output Signals

Letshwao

Ho hlokahala

Tlhaloso

sephetho []

Letšoao la tlhahiso e ngata. Letšoao la tlhahiso [WIDTH_RESULT – 1 … 0] bophara

Moetso oa ketsiso oa IP ena o tšehetsa boleng bo sa lekanyetsoang ba tlhahiso (X). Ha o fana ka boleng ba X e le kenyelletso, boleng ba X bo phatlalatsoa ka lets'oao lena.

scanouta []

Che

Sephetho sa ketane ea scan A. Letšoao la ho tsoa [WIDTH_A – 1..0] ka bophara.

Khetha ho feta 2 bakeng sa linomoro tsa li-multiplier ebe u khetha Kenyelletso ea Scan chain bakeng sa Ke Kenyeletso efe A ea multiplier e hoketsoeng paramethareng ho nolofalletsa lets'oao lena.

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8.6. di-parameter

8.6.1. Kakaretso Tab

Lethathamo la 30. Lethathamo la Kakaretso

Paramethara

IP e hlahisitsoeng Parameter

Boleng

Palo ea li-multiplier ke eng?

palo_ea_m 1 - 4 li-ultipliers

Libese tsa A width_a li lokela ho ba bophara bo bokae?

1 - 256

Libese tse kenyang B width_b li lokela ho ba bophara bo bokae?

1 - 256

Bese ea 'sephetho' e lokela ho ba bophara bo bokae?

bophara_sephetho

1 - 256

Theha oache e amanang le eona e lumelletsoe oache ka 'ngoe

gui_associate Ka d_clock_enabl Off e

8.6.2. Tab ea Mekhoa e Eketsehileng

Letlapa la 31. Tab ea Mekhoa e Eketsehileng

Paramethara

IP e hlahisitsoeng Parameter

Boleng

Tlhophiso ea Liphetho

Ngolisa tlhahiso ea yuniti ea adder

gui_output_re Buletse

gister

E tima

Mohloli oa ho kenya oache ke ofe?

gui_output_re gister_clock

Clock0 Clock1 Clock2

Mohloli oa tlhahiso e hlakileng ea asynchronous ke ofe?

gui_output_re gister_aclr

NONE ACLR0 ACLR1

Mohloli oa ho kenya ka mokhoa o hlakileng oa synchronous ke ofe?

gui_output_re gister_sclr

HA HO MOTHO SCLR0 SCLR1

Ts'ebetso ea Adder

Ke ts'ebetso efe e lokelang ho etsoa ho liphetho tsa para ea pele ea li-multiplier?

gui_multiplier 1_direction

KENYA, SUB, ARABLE

Boleng ba mantlha 1
16

Tlhaloso
Palo ea li-multiplier tse lokelang ho kenyelletsoa hammoho. Boleng ke 1 ho isa ho 4. Hlalosa bophara ba dataa[] kou.

Hlalosa bophara ba boema-kepe ba datab[].

Hlalosa bophara ba sephetho[] kou.

E tima

Khetha khetho ena ho etsa hore oache e khonehe

bakeng sa oache ka 'ngoe.

Boleng ba kamehla

Tlhaloso

Off Clock0
HA HO MOTHO

Kgetha kgetho ena ho thusa registara ya diphetho tsa mojule wa adder.
Khetha Clock0 , Clock1 kapa Clock2 ho thusa le ho hlakisa mohloli oa oache oa lirekoto tsa tlhahiso. U tlameha ho khetha Ngolisa tlhahiso ea yuniti ea adder ho nolofalletsa paramethara ena.
E hlalosa mohloli o hlakileng oa asynchronous bakeng sa rejisetara ea tlhahiso ea adder. U tlameha ho khetha Ngolisa tlhahiso ea yuniti ea adder ho nolofalletsa paramethara ena.
E totobatsa mohloli o hlakileng oa synchronous bakeng sa rejisetara ea tlhahiso ea adder. U tlameha ho khetha Ngolisa tlhahiso ea yuniti ea adder ho nolofalletsa paramethara ena.

KENYA

Kgetha opereishene ya ho eketsa kapa ya ho ntsha ho etsa bakeng sa diphetho pakeng tsa dihatisi tsa pele le tsa bobedi.
· Khetha ADD ho etsa ts'ebetso ea tlatsetso.
· Khetha SUB ho etsa ts'ebetso ea ho ntša.
· Khetha VARIABLE ho sebelisa boema-kepe ba addnsub1 bakeng sa taolo e matla ea ho eketsa / ho tlosa.
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Paramethara

IP e hlahisitsoeng Parameter

Boleng

Ngolisa tlhahiso ea 'addnsub1'

gui_addnsub_ Ho multiplier_reg Off ister1

Mohloli oa ho kenya oache ke ofe?

gui_addnsub_ multiplier_reg ister1_clock

Clock0 Clock1 Clock2

Mohloli oa tlhahiso e hlakileng ea asynchronous ke ofe?

gui_addnsub_ multiplier_aclr 1

NONE ACLR0 ACLR1

Mohloli oa ho kenya ka mokhoa o hlakileng oa synchronous ke ofe?

gui_addnsub_ multiplier_sclr 1

HA HO MOTHO SCLR0 SCLR1

Ke ts'ebetso efe e lokelang ho etsoa ho liphetho tsa para ea bobeli ea li-multiplier?

gui_multiplier 3_direction

KENYA, SUB, ARABLE

Ngolisa tlhahiso ea 'addnsub3'

gui_addnsub_ Ho multiplier_reg Off ister3

Mohloli oa ho kenya oache ke ofe?

gui_addnsub_ multiplier_reg ister3_clock

Clock0 Clock1 Clock2

Boleng ba kamehla
Off Clock0 HA HO MOTHO EA ETSANG
Off Clock0

Tlhaloso
Ha VARIABLE boleng bo khethiloe: · Khanna letšoao la addnsub1 ho ea holimo bakeng sa
ts'ebetso ea ho eketsa. · Khanna letšoao la addnsub1 ho ea tlase bakeng sa
ts'ebetso ea ho ntša. U tlameha ho khetha li-multiplier tse fetang tse peli ho nolofalletsa paramethara ena.
Khetha khetho ena ho lumella ngoliso ea ho kenya bakeng sa portnsub1 port. U tlameha ho khetha VARIABLE bakeng sa Ke ts'ebetso efe e lokelang ho etsoa ho tsoa ho li-multiplier tsa para ea pele ho nolofalletsa paramethara ena.
Kgetha Clock0 , Clock1 kapa Clock2 ho hlakisa letshwao la watjhe la ho kenya bakeng sa rejisetara ya addnsub1. U tlameha ho khetha Ngoliso ea 'addnsub1' ho thusa paramethara ena.
E hlalosa mohloli o hlakileng oa asynchronous bakeng sa ngoliso ea addnsub1. U tlameha ho khetha Ngoliso ea 'addnsub1' ho thusa paramethara ena.
E totobatsa mohloli o hlakileng oa synchronous bakeng sa ngoliso ea addnsub1. U tlameha ho khetha Ngoliso ea 'addnsub1' ho thusa paramethara ena.
Kgetha opereishene ya ho eketsa kapa ya ho ntsha ho etsa bakeng sa diphetho pakeng tsa di-multiples tsa boraro le bone. · Khetha ADD ho etsa tlatsetso
ts'ebetso. · Khetha SUB ho tlosa
ts'ebetso. · Khetha VARIABLE ho sebelisa addnsub1
boemakepe bakeng sa taolo e matla ya tlatsetso/ho ntsha. Ha VARIABLE boleng bo khethiloe: · Khanna letšoao la addnsub1 holimo bakeng sa ts'ebetso ea ho eketsa. · Khanna letšoao la addnsub1 ho ea tlase bakeng sa ts'ebetso ea ho ntša. O tlameha ho khetha boleng ba 4 bakeng sa Palo ea li-multiplier ke eng? ho nolofalletsa parameter ena.
Khetha khetho ena ho nolofalletsa ngoliso ea ho kenya bakeng sa lets'oao la addnsub3. U tlameha ho khetha VARIABLE bakeng sa Ke ts'ebetso efe e lokelang ho etsoa ho liphetho tsa para ea bobeli ea li-multiplier ho nolofalletsa paramethara ena.
Kgetha Clock0 , Clock1 kapa Clock2 ho hlakisa letshwao la watjhe la ho kenya bakeng sa rejisetara ya addnsub3. U tlameha ho khetha Ngoliso ea 'addnsub3′ ho kenya letsoho ho thusa paramente ena.
e tsoela pele…

Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi 48

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Paramethara
Mohloli oa tlhahiso e hlakileng ea asynchronous ke ofe?

IP e hlahisitsoeng Parameter

Boleng

gui_addnsub_ multiplier_aclr 3

NONE ACLR0 ACLR1

Mohloli oa ho kenya ka mokhoa o hlakileng oa synchronous ke ofe?

gui_addnsub_ multiplier_sclr 3

HA HO MOTHO SCLR0 SCLR1

Polarity E nolofalletsa `sebelisa_subadd'

gui_use_subn On

eketsa

E tima

8.6.3. Multipliers Tab

Letlapa la 32. Multipliers Tab

Paramethara

IP e hlahisitsoeng Parameter

Boleng

Ke eng e

gui_represent

sebopeho sa boemedi_a

bakeng sa lintlha tsa Multipliers A?

E SAINWE, E SA SAINWE, E FETOHA

Ngodisa `matshwao' kenyeletso

gui_register_s On

igna

E tima

Mohloli oa ho kenya oache ke ofe?

gui_register_s igna_clock

Clock0 Clock1 Clock2

Mohloli oa tlhahiso e hlakileng ea asynchronous ke ofe?

gui_register_s igna_aclr

NONE ACLR0 ACLR1

Mohloli oa ho kenya ka mokhoa o hlakileng oa synchronous ke ofe?

gui_register_s igna_sclr

HA HO MOTHO SCLR0 SCLR1

Ke eng e

gui_represent

sebopeho sa boemedi_b

bakeng sa lintlha tsa Multipliers B?

E SAINWE, E SA SAINWE, E FETOHA

Ngodisa tlhahiso ea `signb'

gui_register_s On

igb

E tima

Boleng ba kamehla HONA
HA HO MOTHO

Tlhaloso
E hlalosa mohloli o hlakileng oa asynchronous bakeng sa ngoliso ea addnsub3. U tlameha ho khetha Ngoliso ea 'addnsub3' ho thusa paramethara ena.
E totobatsa mohloli o hlakileng oa synchronous bakeng sa ngoliso ea addnsub3. U tlameha ho khetha Ngoliso ea 'addnsub3′ ho kenya letsoho ho thusa paramente ena.

E tima

Khetha khetho ena ho khutlisa tšebetso

ea addnsub input port.

Khanna addnsub ho ea holimo bakeng sa ts'ebetso ea ho tlosa.

Tsamaisa addnsub ho ea tlase bakeng sa ts'ebetso ea ho eketsa.

Boleng ba kamehla

Tlhaloso

HA E SA NGOETSOE Hlalosa sebopeho sa kemedi bakeng sa mohatisi A.

E tima

Khetha khetho ena ho lumella lets'oao

ngodisa.

O tlameha ho khetha boleng ba VARIABLE bakeng sa Sebopeho sa boemeli bakeng sa lintlha tsa Multipliers A ke sefe? parameter ho nolofalletsa khetho ena.

Oache0

Kgetha Tshupa0 , Tshupa1 kapa Tshupa2 ho bulela le ho hlakisa letshwao la sesupa-nako bakeng sa rejisetara ya matshwao.
U tlameha ho khetha Ngoliso ea "signa" ho thusa paramethara ena.

HA HO MOTHO

E totobatsa mohloli o hlakileng o sa lumellaneng bakeng sa ngoliso ea matšoao.
U tlameha ho khetha Ngoliso ea "signa" ho thusa paramethara ena.

HA HO MOTHO

E totobatsa mohloli o hlakileng o lumellanang bakeng sa ngoliso ea matšoao.
U tlameha ho khetha Ngoliso ea "signa" ho thusa paramethara ena.

HA E SA NGOESOA Hlalosa fomete ea kemeli bakeng sa ho atisa ho kenya B.

E tima

Khetha khetho ena ho lumella signb

ngodisa.

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Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi 49

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Paramethara

IP e hlahisitsoeng Parameter

Boleng

Boleng ba kamehla

Mohloli oa ho kenya oache ke ofe?

gui_register_s ignb_clock

Clock0 Clock1 Clock2

Oache0

Mohloli oa tlhahiso e hlakileng ea asynchronous ke ofe?

gui_register_s ignb_aclr

NONE ACLR0 ACLR1

Mohloli oa ho kenya ka mokhoa o hlakileng oa synchronous ke ofe?

gui_register_s ignb_sclr

HA HO MOTHO SCLR0 SCLR1

Tlhophiso ea ho Kena
Ngolisa ho kenya A ho ngatafatsa
Mohloli oa ho kenya oache ke ofe?

gui_input_reg Bula

ister_a

E tima

gui_input_reg ister_a_clock

Clock0 Clock1 Clock2

HA HO MOTHO
Off Clock0

Mohloli oa tlhahiso e hlakileng ea asynchronous ke ofe?

gui_input_reg ister_a_aclr

NONE ACLR0 ACLR1

Mohloli oa ho kenya ka mokhoa o hlakileng oa synchronous ke ofe?

gui_input_reg ister_a_sclr

HA HO MOTHO SCLR0 SCLR1

Ngolisa input B ea ngatafatso
Mohloli oa ho kenya oache ke ofe?

gui_input_reg Bula

ister_b

E tima

gui_input_reg ister_b_clock

Clock0 Clock1 Clock2

HA HO MOTHO HA HO NONE Off Clock0

Mohloli oa tlhahiso e hlakileng ea asynchronous ke ofe?

gui_input_reg ister_b_aclr

NONE ACLR0 ACLR1

HA HO MOTHO

Mohloli oa ho kenya ka mokhoa o hlakileng oa synchronous ke ofe?

gui_input_reg ister_b_sclr

HA HO MOTHO SCLR0 SCLR1

HA HO MOTHO

Kenyeletso ea A ea morekisi e hokahaneng le eng?

gui_multiplier Multiplier input Multiplier

_a_kenyeletso

Skena tlhahiso ea ketane

Tlhaloso
O tlameha ho khetha boleng ba VARIABLE bakeng sa Sebopeho sa boemeli bakeng sa lintlha tsa Multipliers B ke sefe? parameter ho nolofalletsa khetho ena.
Kgetha Tshupa0 , Tshupa1 kapa Tshupa2 ho bulela le ho hlakisa letshwao la watjhe ya ho kenya bakeng sa rejisetara ya matshwao. U tlameha ho khetha Ngolisa `signb' ho kenya ho nolofalletsa paramethara ena.
E totobatsa mohloli o hlakileng o sa tsitsang oa rejisetara ea matšoao. U tlameha ho khetha Ngolisa `signb' ho kenya ho nolofalletsa paramethara ena.
E totobatsa mohloli o hlakileng oa synchronous bakeng sa rejisetara ea matšoao. U tlameha ho khetha Ngolisa `signb' ho kenya ho nolofalletsa paramethara ena.
Khetha khetho ena ho lumella ngoliso ea ho kenya bakeng sa bese ea dataa.
Khetha Clock0, Clock1 kapa Clock2 ho bulela le ho hlakisa lets'oao la oache e kentsoeng bakeng sa bese ea data. U tlameha ho khetha Ngoliso ea ho kenya A ea mochine o atisang ho nolofalletsa paramethara ena.
E totobatsa mohloli o hlakileng oa register bakeng sa bese ea ho kenya data. U tlameha ho khetha Ngoliso ea ho kenya A ea mochine o atisang ho nolofalletsa paramethara ena.
E totobatsa mohloli o hlakileng oa register bakeng sa bese ea ho kenya data. U tlameha ho khetha Ngoliso ea ho kenya A ea mochine o atisang ho nolofalletsa paramethara ena.
Khetha khetho ena ho lumella ngoliso ea ho kenya bakeng sa bese ea ho kenya datab.
Khetha Clock0, Clock1 kapa Clock2 ho bulela le ho hlakisa lets'oao la oache ea ho kenya ngoliso bakeng sa bese ea datab. U tlameha ho khetha Ngolisa input B ea multiplier ho nolofalletsa paramethara ena.
E totobatsa mohloli o hlakileng oa register bakeng sa bese ea ho kenya datab. U tlameha ho khetha Ngolisa input B ea multiplier ho nolofalletsa paramethara ena.
E totobatsa mohloli o hlakileng oa register bakeng sa bese ea ho kenya datab. U tlameha ho khetha Ngolisa input B ea multiplier ho nolofalletsa paramethara ena.
Kgetha mohlodi wa ho kenya bakeng sa ho kenya A ho ngatafatsa.
e tsoela pele…

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Paramethara

IP e hlahisitsoeng Parameter

Boleng

Scanout A Registering Configuration

Ngolisa tlhahiso ea ketane ea scan

gui_scanouta On

_ngolisa

E tima

Mohloli oa ho kenya oache ke ofe?

gui_scanouta _register_clock k

Clock0 Clock1 Clock2

Mohloli oa tlhahiso e hlakileng ea asynchronous ke ofe?

gui_scanouta _register_aclr

NONE ACLR0 ACLR1

Mohloli oa ho kenya ka mokhoa o hlakileng oa synchronous ke ofe?

gui_scanouta _register_sclr

HA HO MOTHO SCLR0 SCLR1

8.6.4. Preadder Tab

Letlapa la 33. Preadder Tab

Paramethara

IP e hlahisitsoeng Parameter

Boleng

Khetha mokhoa oa pread

preadder_mo de

BONOLO, COEF, KENYA, SQUARE, TSOHLE

Boleng ba kamehla

Tlhaloso
Khetha Multiplier input ho sebelisa dataa input bese e le mohloli oa ho atisa. Khetha "Scan chain input" ho sebedisa bese e kenang e le mohlodi wa sehatisi mme o dumelle bese e tswang ho scanout. Paramethara ena ea fumaneha ha u khetha 2, 3 kapa 4 bakeng sa Li-multiplier li kae? paramethara.

Off Clock0 HA HO MOTHO

Khetha khetho ena ho nolofalletsa registeri ea tlhahiso bakeng sa bese ea scanouta.
U tlameha ho khetha Kenyelletso ea ketane bakeng sa Kenyo ea A ea mochini o atisang ho hokela ho eng? parameter ho nolofalletsa khetho ena.
Khetha Clock0, Clock1 kapa Clock2 ho bulela le ho hlakisa lets'oao la oache ea ho kenya ngoliso bakeng sa bese e hlahisoang ke scanouta.
U tlameha ho bulela "Register output" ea paramethara ea skena ho etsa khetho ena.
E totobatsa mohloli o hlakileng oa rejisetara bakeng sa bese ea tlhahiso ea scanouta.
U tlameha ho bulela "Register output" ea paramethara ea skena ho etsa khetho ena.
E totobatsa mohloli o hlakileng oa rejisetara bakeng sa bese ea tlhahiso ea scanouta.
U tlameha ho khetha Ngolisa tlhahiso ea paramethara ea ketane ho etsa khetho ena.

Boleng ba kamehla
BONOLO

Tlhaloso
E hlalosa mokhoa oa ts'ebetso bakeng sa mojule oa preadder. BONOLO: Mokhoa ona o feta preadder. Ena ke mokhoa oa kamehla. COEF: Mokhoa ona o sebelisa tlhahiso ea preadder le coefsel input bese e le lintho tse kenang ho morekisi. KENYA: Mokhoa ona o sebelisa tlhahiso ea preadder le bese e kenyang datac joalo ka lintho tse kenang ho morekisi. SQUARE: Mokhoa ona o sebelisa tlhahiso ea preadder e le lisebelisoa tse peli ho ngata.
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Paramethara

IP e hlahisitsoeng Parameter

Boleng

Khetha tsela ea preadre

gui_preadder ADD,

_tataiso

SEBAKA

Libese tsa C width_c li lokela ho ba bophara bo bokae?

1 - 256

Tlhophiso ea Rejistara ea Kenyelletso ea data C

Ngolisa lintlha tsa data

gui_datac_inp E buletsoe

ut_register

E tima

Mohloli oa ho kenya oache ke ofe?

gui_datac_inp ut_register_cl ock

Clock0 Clock1 Clock2

Mohloli oa tlhahiso e hlakileng ea asynchronous ke ofe?

gui_datac_inp ut_register_a clr

NONE ACLR0 ACLR1

Mohloli oa ho kenya ka mokhoa o hlakileng oa synchronous ke ofe?

gui_datac_inp ut_register_sc lr

HA HO MOTHO SCLR0 SCLR1

Li-coefficients
Bophara ba khofu e lokela ho ba bophara bo bokae?

bophara_coef

1 - 27

Tlhophiso ea Ngoliso ea Coef

Ngolisa tlhahiso ea coefsel

gui_coef_regi On

ster

E tima

Mohloli oa ho kenya oache ke ofe?

gui_coef_regi ster_clock

Clock0 Clock1 Clock2

Boleng ba kamehla
KENYA
16

Tlhaloso
CONSTANT: Mokhoa ona o sebelisa bese e kenyang data e nang le preadder bypassed le coefsel input bese e le lintho tse kenang ho tse ngatafatsang.
E hlalosa tshebetso ya preadre. Ho nolofalletsa paramethara ena, khetha tse latelang bakeng sa Khetha mokhoa oa pread: · COEF · INPUT · SQUARE or · CONSTANT
E hlalosa palo ea li-bits bakeng sa bese ea ho kenya C. U tlameha ho khetha INPUT bakeng sa Khetha mokhoa oa preadder ho nolofalletsa paramethara ena.

Ka Clock0 HA HO MOTHO

Khetha khetho ena ho lumella ngoliso ea ho kenya bakeng sa bese ea ho kenya datac. U tlameha ho seta INPUT ho Khetha paramethara ea mokhoa oa preadder ho nolofalletsa khetho ena.
Kgetha Tshupa0, Tshupa1 kapa Tshupa2 ho hlakisa letshwao la sesupa-tshupanako bakeng sa rejisetara ya ho kenya datac. U tlameha ho khetha Ngoliso ea datac ho nolofalletsa paramethara ena.
E totobatsa mohloli o hlakileng o sa lumellaneng bakeng sa rejisetara ea ho kenya datac. U tlameha ho khetha Ngoliso ea datac ho nolofalletsa paramethara ena.
E totobatsa mohloli o hlakileng o lumellanang bakeng sa rejisetara ea ho kenya datac. U tlameha ho khetha Ngoliso ea datac ho nolofalletsa paramethara ena.

E bolela palo ea likotoana tsa

coefsel input bese.

U tlameha ho khetha COEF kapa CONSTANT bakeng sa "pread mode" ho nolofalletsa paramethara ena.

Ka Clock0

Khetha khetho ena ho lumella ngoliso ea ho kenya bakeng sa bese ea coefsel. U tlameha ho khetha COEF kapa CONSTANT bakeng sa "pread mode" ho nolofalletsa paramethara ena.
Khetha Clock0 , Clock1 kapa Clock2 ho hlakisa lets'oao la oache e kenang bakeng sa rejisetara ea ho kenya ea coefsel. U tlameha ho khetha Ngolisa tlhahiso ea coefsel ho nolofalletsa paramethara ena.
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Paramethara
Mohloli oa tlhahiso e hlakileng ea asynchronous ke ofe?

IP e hlahisitsoeng Parameter

Boleng

gui_coef_regi ster_aclr

NONE ACLR0 ACLR1

Ke mohloli ofe oa ho kenya ka mokhoa o hlakileng oa synchronous

gui_coef_regi ster_sclr

HA HO MOTHO SCLR0 SCLR1

Coefficient_0 Configuration

coef0_0 ho coef0_7

0x00000 0xFFFFFF

Coefficient_1 Configuration

coef1_0 ho coef1_7

0x00000 0xFFFFFF

Coefficient_2 Configuration

coef2_0 ho coef2_7

0x00000 0xFFFFFF

Coefficient_3 Configuration

coef3_0 ho coef3_7

0x00000 0xFFFFFF

8.6.5. Accumulator Tab

Letlapa la 34. Tab ea Accumulator

Paramethara

IP e hlahisitsoeng Parameter

Boleng

Na u lumella accumulator?

mokgoboketsi

EE, CHE

Ke mofuta ofe oa ts'ebetso ea accumulator?

accum_directi ADD,

SEBAKA

Boleng ba kamehla HONA
HA HO MOTHO
0x0000000 0
0x0000000 0
0x0000000 0
0x0000000 0

Tlhaloso
E hlakisa mohloli o hlakileng oa asynchronous bakeng sa rejisetara ea ho kenya ea coefsel. U tlameha ho khetha Ngolisa tlhahiso ea coefsel ho nolofalletsa paramethara ena.
E totobatsa mohloli o hlakileng oa synchronous bakeng sa rejisetara ea ho kenya ea coefsel. U tlameha ho khetha Ngolisa tlhahiso ea coefsel ho nolofalletsa paramethara ena.
E hlalosa boleng ba coefficient bakeng sa sehatisi sena sa pele. Palo ea li-bits e tlameha ho tšoana le e boletsoeng ho Bophara ba khoe e lokela ho ba bophara bo bokae? paramethara. U tlameha ho khetha COEF kapa CONSTANT bakeng sa "pread mode" ho nolofalletsa paramethara ena.
E hlakisa boleng ba coefficient bakeng sa katiso ena ea bobeli. Palo ea li-bits e tlameha ho tšoana le e boletsoeng ho Bophara ba khoe e lokela ho ba bophara bo bokae? paramethara. U tlameha ho khetha COEF kapa CONSTANT bakeng sa "pread mode" ho nolofalletsa paramethara ena.
E hlakisa boleng ba coefficient bakeng sa seikatisetsa sena sa boraro. Palo ea li-bits e tlameha ho tšoana le e boletsoeng ho Bophara ba khoe e lokela ho ba bophara bo bokae? paramethara. U tlameha ho khetha COEF kapa CONSTANT bakeng sa "pread mode" ho nolofalletsa paramethara ena.
E hlalosa boleng ba coefficient bakeng sa katiso ena ea bone. Palo ea li-bits e tlameha ho tšoana le e boletsoeng ho Bophara ba khoe e lokela ho ba bophara bo bokae? paramethara. U tlameha ho khetha COEF kapa CONSTANT bakeng sa "pread mode" ho nolofalletsa paramethara ena.

Boleng ba kamehla NO
KENYA

Tlhaloso
Khetha YES ho thusa accumulator. U tlameha ho khetha Ngoliso ea tlhahiso ea yuniti ea adder ha u sebelisa sesebelisoa sa accumulator.
E hlalosa ts'ebetso ea accumulator: · ADD bakeng sa ts'ebetso ea tlatsetso · SUB bakeng sa ts'ebetso ea ho tlosa. U tlameha ho khetha YES bakeng sa Enable accumulator? parameter ho nolofalletsa khetho ena.
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Paramethara
Laola esale pele kamehla Lumella ho kenya kamehla

IP e hlahisitsoeng Parameter

Boleng

gui_ena_prelo On

ad_const

E tima

Kenyeletso ea boema-kepe ba accumulate e hokahane le eng?

gui_accumula ACCUM_SLOAD, khetha_port_khetha SLOAD_ACCUM

Khetha boleng ba preload loadconst_val 0 - 64

kamehla

Mohloli oa ho kenya oache ke ofe?

gui_accum_sl oad_register_ oache

Clock0 Clock1 Clock2

Mohloli oa tlhahiso e hlakileng ea asynchronous ke ofe?

gui_accum_sl oad_register_ aclr

NONE ACLR0 ACLR1

Mohloli oa ho kenya ka mokhoa o hlakileng oa synchronous ke ofe?

gui_accum_sl oad_register_ sclr

HA HO MOTHO SCLR0 SCLR1

Lumella li-accumulator tse peli

gui_double_a On

ccum

E tima

Boleng ba kamehla

Tlhaloso

E tima

Etsa hore accum_sload kapa

sload_accum matšoao le ho kenya ngoliso

ho khetha ka matla ho kenya letsoho ho

pokello.

Ha accum_sload e le tlase kapa sload_accum, tlhahiso e ngata e kenngoa ka har'a accumulator.

Ha accum_sload e le holimo kapa sload_accum, mosebelisi ea boletsoeng esale pele o feptjoa ka har'a accumulator.

U tlameha ho khetha YES bakeng sa Enable accumulator? parameter ho nolofalletsa khetho ena.

ACCUM_SL OAD

E totobatsa boitšoaro ba accum_sload/ sload_accum signal.
ACCUM_SLOAD: Khanna accum_sload low ho kenya tlhahiso ea li-multiplier ho accumulator.
SLOAD_ACCUM: Khanna sload_accum holimo ho kenya tlhahiso ea li-multiplier ho accumulator.
U tlameha ho khetha Numella khetho e sa khaotseng ea ho kenya esale pele ho nolofalletsa paramethara ena.

Hlalosa boleng bo sa feleng bo behiloeng esale pele.

Boleng bona e ka ba 2N moo N e leng boleng bo sa feleng bo behiloeng esale pele.

Ha N=64, e emela zero e sa fetoheng.

U tlameha ho khetha Numella khetho e sa khaotseng ea ho kenya esale pele ho nolofalletsa paramethara ena.

Oache0

Khetha Clock0 , Clock1 kapa Clock2 ho hlakisa lets'oao la oache e kenang bakeng sa rejisetara ea accum_sload/sload_accum.
U tlameha ho khetha Numella khetho e sa khaotseng ea ho kenya esale pele ho nolofalletsa paramethara ena.

HA HO MOTHO

E hlalosa mohloli o hlakileng oa accum_sload/sload_accum register.
U tlameha ho khetha Numella khetho e sa khaotseng ea ho kenya esale pele ho nolofalletsa paramethara ena.

HA HO MOTHO

E hlalosa mohloli o hlakileng oa synchronous bakeng sa rejisetara ea accum_sload/sload_accum.
U tlameha ho khetha Numella khetho e sa khaotseng ea ho kenya esale pele ho nolofalletsa paramethara ena.

E tima

E nolofalletsa rejisetara e habeli ea accumulator.

Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi 54

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8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

8.6.6. Systolic / Chainout Tab

Letlapa la 35. Systolic / Chainout Adder Tab

Paramethara Numella chainout adder

IP e hlahisitsoeng Parameter

Boleng

chainout_eketsa YES,

Mofuta oa ts'ebetso ea chainout adder ke ofe?

chainout_eketsa ADD,

er_direction

SEBAKA

Na u nolofaletsa ho kenya `negate' bakeng sa chainout adder?

Port_negate

PORT_USED, PORT_UNUSED

Ngolisa 'ho hana' ho kenya? negate_regist er

E SA NGOLISETSOENG, OCHE0, OCHE1, OA2, OARA3

Mohloli oa tlhahiso e hlakileng ea asynchronous ke ofe?

negate_aclr

NONE ACLR0 ACLR1

Mohloli oa ho kenya ka mokhoa o hlakileng oa synchronous ke ofe?

negate_sclr

HA HO MOTHO SCLR0 SCLR1

Systolic Ho lieha
Lumella lirekoto tsa ho lieha ha systolic

gui_systolic_d On

elay

E tima

Mohloli oa ho kenya oache ke ofe?

gui_systolic_d CLOCK0,

elay_clock

OCHE1,

Boleng ba kamehla
NO

Tlhaloso
Kgetha YES ho thusa mojule wa chainout adder.

KENYA

E hlalosa ts'ebetso ea chainout adder.
Bakeng sa ts'ebetso ea ho ntša, SIGNED e tlameha ho khethoa bakeng sa Ke sebopeho sefe sa boemeli bakeng sa lintlha tsa Multipliers A? le Ke sebopeho sefe sa boemeli bakeng sa likenyelletso tsa Multipliers B? ho li-Multipliers Tab.

PORT_UN USED

Khetha PORT_USED ho bulela lets'oao le sa amoheleheng.
Paramethara ena ha e sebetse ha chainout adder e koetsoe.

NGOLISA ERED

Ho nolofalletsa rejisetara ea ho kenya bakeng sa lets'oao la ho hana le ho hlakisa lets'oao la oache ea ho kenya bakeng sa rejisetara e sa laoleheng.
Kgetha HA E NGOLISETSOE haeba ho sa hlokahale hore regisetere ea ho kenya e hanana le eona
Paramethara ena ha e sebetse ha o khetha:
· NO bakeng sa Enable chainout adder kapa
· PORT_UNUSED bakeng sa Numella tlhahiso ea 'negate' bakeng sa chainout adder? paramethara kapa

HA HO MOTHO

E hlalosa mohloli o hlakileng oa asynchronous bakeng sa rejisetara e sa utloahaleng.
Paramethara ena ha e sebetse ha o khetha:
· NO bakeng sa Enable chainout adder kapa
· PORT_UNUSED bakeng sa Numella tlhahiso ea 'negate' bakeng sa chainout adder? paramethara kapa

HA HO MOTHO

E totobatsa mohloli o hlakileng oa synchronous bakeng sa rejisetara e hananang.
Paramethara ena ha e sebetse ha o khetha:
· NO bakeng sa Enable chainout adder kapa
· PORT_UNUSED bakeng sa Numella tlhahiso ea 'negate' bakeng sa chainout adder? paramethara kapa

Tloha OCHE0

Khetha khetho ena ho nolofalletsa mokhoa oa systolic. Paramethara ena e fumaneha ha u khetha 2, kapa 4 bakeng sa Li-multiplier li kae? paramethara. U tlameha ho nolofalletsa Rejistara tlhahiso ea yuniti ea adder ho sebelisa lirejistara tsa tieho ea systolic.
E hlakisa lets'oao la oache e kenang bakeng sa rejisetara ea ho lieha ha systolic.
e tsoela pele…

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Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi 55

8. Intel FPGA Multiply Adder IP Core 683490 | 2020.10.05

Paramethara

IP e hlahisitsoeng Parameter

Boleng

OCHE2,

Mohloli oa tlhahiso e hlakileng ea asynchronous ke ofe?

gui_systolic_d elay_aclr

NONE ACLR0 ACLR1

Mohloli oa ho kenya ka mokhoa o hlakileng oa synchronous ke ofe?

gui_systolic_d elay_sclr

HA HO MOTHO SCLR0 SCLR1

Boleng ba kamehla
HA HO MOTHO
HA HO MOTHO

Tlhaloso
U tlameha ho khetha ho nolofalletsa lirejistara tsa ho lieha ha systolic ho nolofalletsa khetho ena.
E totobatsa mohloli o hlakileng oa asynchronous bakeng sa rejisetara ea ho lieha ea systolic. U tlameha ho khetha ho nolofalletsa lirejistara tsa ho lieha ha systolic ho nolofalletsa khetho ena.
E totobatsa mohloli o hlakileng oa synchronous bakeng sa rejisetara ea tieho ea systolic. U tlameha ho khetha ho nolofalletsa lirejistara tsa ho lieha ha systolic ho nolofalletsa khetho ena.

8.6.7. Letlapa la Pipelining

Letlapa la 36. Letlapa la Pipelining

Parameter Pipelining Configuration

IP e hlahisitsoeng Parameter

Boleng

A na u batla ho kenya registara ea lipeipi ho kenyelletso?

gui_pipelining Che, E

Boleng ba kamehla
Che

Ka kopo, hlakisa

latency

palo ea oache ea latency

lipotoloho

Boleng bofe kapa bofe bo fetang 0

Mohloli oa ho kenya oache ke ofe?

gui_input_late ncy_clock

TŠEBELETSO0, TSHOKO1, TSHEPA2

Mohloli oa tlhahiso e hlakileng ea asynchronous ke ofe?

gui_input_late ncy_aclr

NONE ACLR0 ACLR1

Mohloli oa ho kenya ka mokhoa o hlakileng oa synchronous ke ofe?

gui_input_late ncy_sclr

HA HO MOTHO SCLR0 SCLR1

TŠEBELETSO NTHO NONE

Tlhaloso
Kgetha E ho etsa hore ho be le rejisetara e eketsehileng ya dipeipi ho matshwao a kentsweng. O tlameha ho hlakisa boleng bo fetang 0 bakeng sa Ka kopo, bolela palo ea paramethara ea lioache tsa oache.
E totobatsa latency e batloang nakong ea lioache. Boemo bo le bong ba rejisetara ea lipeipi = 1 latency nakong ea oache. U tlameha ho khetha YES bakeng sa Na u batla ho kenya rejisetara ea lipeipi ho kenyelletsong? ho nolofalletsa khetho ena.
Khetha Clock0 , Clock1 kapa Clock2 ho bulela le ho hlakisa lets'oao la oache ea ho kenya ngoliso ea lipeipi. U tlameha ho khetha YES bakeng sa Na u batla ho kenya rejisetara ea lipeipi ho kenyelletsong? ho nolofalletsa khetho ena.
E totobatsa mohloli o hlakileng oa rejisetara bakeng sa rejisetara e eketsehileng ea lipeipi. U tlameha ho khetha YES bakeng sa Na u batla ho kenya rejisetara ea lipeipi ho kenyelletsong? ho nolofalletsa khetho ena.
E totobatsa mohloli o hlakileng oa rejisetara bakeng sa rejisetara ea tlatsetso ea lipeipi. U tlameha ho khetha YES bakeng sa Na u batla ho kenya rejisetara ea lipeipi ho kenyelletsong? ho nolofalletsa khetho ena.

Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi 56

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683490 | 2020.10.05 Romella Maikutlo

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core

Tlhokomeliso:

Intel e tlositse tšehetso ea IP ena ho Intel Quartus Prime Pro Edition 20.3. Haeba motheo oa IP moralong oa hau o shebile lisebelisoa ho Intel Quartus Prime Pro Edition, o ka nkela IP sebaka ka LPM_MULT Intel FPGA IP kapa oa hlahisa IP bocha 'me oa hlophisa moralo oa hau u sebelisa software ea Intel Quartus Prime Standard Edition.

AlTMEMMULT IP ea mantlha e sebelisoa ho theha li-multiplier tse thehiloeng mohopolong li sebelisa li-block tsa memori tsa onchip tse fumanehang ho Intel FPGAs (e nang le li-memori tsa M512, M4K, M9K, le MLAB). Setsi sena sa IP se na le thuso haeba u sena lisebelisoa tse lekaneng tsa ho kenya tšebetsong li-multiplier ho logic elements (LEs) kapa lisebelisoa tse ngata tse inehetseng.
The ALTMEMMULT IP core ke ts'ebetso e lumellanang e hlokang oache. AlTMEMMULT IP ea mantlha e kenya lisebelisoa tse ngatafatsang tse nang le phallo e nyane haholo le latency e ka khonehang bakeng sa sete e fanoeng ea li-parameter le litlhaloso.
Setšoantšo se latelang se bonts'a likou tsa mantlha tsa ALTMEMMULT IP.

Setšoantšo sa 21. ALTMEMMULT Ports

TLHOKOMELISO

data_in[] sload_data coeff_in[]

sephetho[] sephetho_e sebetsang_e phethiloe

sload_coeff

oache ea sclr
inst

Lintlha Tse Amanang le Litaba leqepheng la 71

9.1. Likarolo
ALTMEMMULT IP core e fana ka likarolo tse latelang: · E theha li-multiplier tse thehiloeng mohopolong feela ka li-block tsa memori tse fumanehang ho
Intel FPGAs · E ts'ehetsa bophara ba data ba li-bits tse 1 · E ts'ehetsa sebopeho sa boemeli ba data se saennoeng le se sa saennoang

ISO 9001:2015 E Ngolisitsoe

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05
* E boloka li-multiples constants ka har'a memori ea phihlello e sa reroang (RAM)
· E fana ka khetho ea ho khetha mofuta oa block ea RAM
· E ts'ehetsa likou tsa ho kenya tse hlakileng le tse laolang mojaro
9.2. Verilog HDL Prototype
Mohlala o latelang oa Verilog HDL o fumaneha ho Moralo oa Verilog File (.v) altera_mf.v ho eda synthesis directory.
module altmemmult #( paramethara coeff_representation = “HO SAIWE”, paramethara coefficient0 = “HA E SEBELE”, paramethara_representation = “SIGNED”, paramethara target_device_family = “ha e so sebelisoe”, paramethara max_clock_cycles_per_result = 1, paramethara_to_thibelo = 1, paramethara_to_thibelo =1, paramethara_to_thibelo total_latency = 1, parameter width_c = 1, parameter width_d = 1, parameter width_r = 1, parameter width_s = 1, parameter lpm_type = "altmemmult", paramethara lpm_hint = "e sa sebelisoe") ( oache ea terata e kentsoeng, terata e kenang [bophara_c-0: 1]coeff_in, input wire [width_d-0:1] data_in, output wire load_e phethilwe, output wire [width_r-0:1] sephetho, output wire result_valid, input wire sclr, input wire [width_s-0:1] sel, input wire sload_coeff, input wire sload_data)/* synthesis syn_black_box=XNUMX */; endmodule
9.3. Phatlalatso ea Karolo ea VHDL
Phatlalatso ea karolo ea VHDL e fumaneha ho Moralo oa VHDL File (.vhd) altera_mf_components.vhd ho librariesvhdlaltera_mf directory.
component altmemmult generic (coeff_representation: string := "SIGNED"; coefficient0: string := "SA SEBESWE"; data_representation: string := "SIGNED"; target_device_family: string := "sa sebelisoe"; max_clock_cycles_per_result:_phello ea nako := 1; ram_block_type: khoele := “AUTO”; kakaretso_latency: tlhaho; bophara_c: tlhaho; bophara_d: tlhaho; bophara_r: tlhaho; bophara_s: tlhaho: = 1; lpm_hint: khoele := “UNUSED”; lpm_type: khoele:= "altmemmult"); port ( clock: in std_logic; coeff_in: in std_logic_vector (width_c-1 downto 1) := (ba bang => '0'); data_in: in std_logic_vector (width_d-0 downto 1);

Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi 58

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9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

load_done:out std_logic; sephetho: tsoa std_logic_vector(width_r-1 downto 0); result_valid:out std_logic; sclr: in std_logic := '0'; sel: in std_logic_vector(width_s-1 downto 0) := (ba bang => '0'); sload_coeff:in std_logic := '0'; sload_data:in std_logic := '0'); karolo ea ho qetela;

9.4. Maemakepe

Litafole tse latelang li thathamisa likou tsa ho kenya le tse hlahisoang bakeng sa motheo oa IP oa ALTMEMMULT.

Letlapa la 37. ALTMEMMULT Li-ports tsa ho kenya

Lebitso la Port

Ho hlokahala

Tlhaloso

oache

Kenyelletso ea oache ho morekisi.

coeff_in[]

Che

Coefficient input port bakeng sa se atisang. Boholo ba sebaka sa ho kenya se ipapisitse le boleng ba paramethara ea WIDTH_C.

data_in[]

Boemakepe ba ho kenya data ho se atisang. Boholo ba sebaka sa ho kenya se ipapisitse le boleng ba paramethara ea WIDTH_D.

sclr

Che

Keno e hlakileng ea synchronous. Haeba e sa sebelisoe, boleng ba kamehla bo holimo.

rekisa[]

Che

Khetho e tsitsitseng ea coefficient. Boholo ba sebaka sa ho kenya se ipapisitse le WIDTH_S

boleng ba paramethara.

sload_coeff

Che

Boema-kepe ba ho kenya ka khokahanyo ea mojaro. E nkela sebaka sa boleng ba coefficient ea hajoale ka boleng bo boletsoeng ho coeff_in input.

sload_data

Che

Boema-kepe ba ho kenya data e tsamaisanang. Letshwao le hlakisang tshebetso e ntjha ya katiso le ho hlakola tshebetso efe kapa efe e teng ya katiso. Haeba paramethara ea MAX_CLOCK_CYCLES_PER_RESULT e na le boleng ba 1, sebaka sa sload_data se kentsoeng se hlokomolohuoa.

Letlapa la 38. ALTMEMMULT Li-ports tsa Output

Lebitso la Port

Ho hlokahala

Tlhaloso

sephetho[]

Multiplier output port. Boholo ba sebaka sa ho kenya se ipapisitse le boleng ba paramethara ea WIDTH_R.

sephetho_e nepahetse

E bontša ha tlhahiso e le sephetho se nepahetseng sa katiso e felletseng. Haeba MAX_CLOCK_CYCLES_PER_RESULT parameter e na le boleng ba 1, result_valid output port ha e sebelisoe.

load_etsa

Che

E bontša ha coefficient e ncha e qetile ho kenya. Letšoao la load_done le bolela ha coefficient e ncha e qetile ho kenya. Ntle le haeba lets'oao la load_done le phahame, ha ho boleng bo bong ba coefficient bo ka kenngoa mohopolong.

9.5. di-parameter

Tafole e latelang e thathamisa liparamente tsa mantlha tsa ALTMEMMULT IP.

Lethathamo la 39.
WIDTH_D WIDTH_C

Litekanyetso tsa ALTMEMMULT
Lebitso la Parameter

Mofuta o Hlokehang

Tlhaloso

Kakaretso E

E totobatsa bophara ba sebaka sa data_in[].

Kakaretso E

E totobatsa bophara ba kou ea coeff_in[]. e tsoela pele…

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Intel FPGA Integer Arithmetic IP Cores Tataiso ea Mosebelisi 59

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

Lebitso la Parametha WIDTH_R WIDTH

Litokomane / Lisebelisoa

Intel FPGA Integer Arithmetic IP Cores [pdf] Bukana ea Mosebelisi
FPGA Integer Arithmetic IP Cores, Integer Arithmetic IP Cores, Arithmetic IP Cores, IP Cores

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