F Tile Serial Lite IV Intel FPGA IP User Guide

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1 F Tile Serial Lite IV Intel FPGA IP

2 Litokomane / Lisebelisoa

2.1 Litšupiso

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F Tile Serial Lite IV Intel FPGA IP

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F-Tile Serial Lite IV Intel® FPGA IP User Guide
E ntlafalitsoe bakeng sa Intel® Quartus® Prime Design Suite: 22.1 IP Version: 5.0.0

Online Version Romella Maikutlo

UG-20324

ID: 683074 Version: 2022.04.28

Litaba
Litaba
1. Mabapi le F-Tile Serial Lite IV Intel® FPGA IP User Guide ………………………………………….. 4
2. F-Tile Serial Lite IV Intel FPGA IP Overview…………………………………………………………………. 6 2.1. Tlhahisoleseding ka Phatlalatso……………………………………………………………………………………..7 2.2. Likarolo tse Tšehetsoeng……………………………………………………………………………………….. 7 2.3. IP Version Support Level………………………………………………………………………………..8 2.4. Tšehetso ea Kereiti ea Lebelo la Sesebelisoa…………………………………………………………………………..8 2.5. Tšebeliso ea Lisebelisuoa le Nako ea ho Paka. Bandwidth Efficiency…………………………………………………………………………………………………………………………………………. 9
3. Ho Qala 11 3.1. Ho kenya le ho Fana ka Lilaesense tsa Intel FPGA IP Cores………………………………………………………… 11 3.1.1. Intel FPGA IP Evaluation Mode ………………………………………………………………. 11 3.2. Ho Hlalosa Litlhophiso le Likhetho tsa IP…………………………………………………………… 14 3.3. E hlahisitsoe File Sebopeho……………………………………………………………………………………… 14 3.4. Ho etsisa Intel FPGA IP Cores…………………………………………………………………………… 16 3.4.1. Ho Etsisa le ho Tiisa Moralo…………………………………………………….. 17 3.5. Ho kopanya IP Cores ho Lisebelisoa tse ling tsa EDA……………………………………………………………. 17 3.6. Ho Kopanya Moralo o Feletseng……………………………………………………………………………..18
4. Tlhaloso ea Mosebetsi……………………………………………………………………………………….. 19 4.1. TX Datapath…………………………………………………………………………………………..20 4.1.1. Adapter ea TX MAC…………………………………………………………………………….. 21 4.1.2. Kenyelletso ea Lentsoe la Taolo (CW) ……………………………………………………………………… 23 4.1.3. TX CRC……………………………………………………………………………………………28 4.1.4. TX MII Encoder……………………………………………………………………………….29 4.1.5. TX PCS le PMA…………………………………………………………………………….. 30 4.2. RX Datapath………………………………………………………………………………………………. 30 4.2.1. RX PCS le PMA………………………………………………………………………….. 31 4.2.2. RX MII Decoder……………………………………………………………………………………… 31 4.2.3. RX CRC……………………………………………………………………………………….. 31 4.2.4. RX Deskew…………………………………………………………………………………….32 4.2.5. Ho tlosoa ha RX CW…………………………………………………………………………………35 4.3. F-Tile Serial Lite IV Intel FPGA IP Clock Architecture……………………………………………. 36 4.4. Seta Botjha le ho Qala Khokahano…………………………………………………………………………..37 4.4.1. TX Reset le Tatelano ea ho Qala………………………………………………… 38 4.4.2. RX Reset le Tatelano ea ho Qala……………………………………………………. 39 4.5. Khokahano Rate le Bandwidth Eccessive Calculation …………………………………………………….. 40
5. Liparamente…………………………………………………………………………………………………………………………………………………………………. 42
6. F-Tile Serial Lite IV Intel FPGA IP Interface Signals……………………………………………….. 44 6.1. Lipontšo tsa Oache…………………………………………………………………………………………….44 6.2. Seta Matshwao botjha……………………………………………………………………………………………… 44 6.3. Matshwao a MAC………………………………………………………………………………………….. 45 6.4. Matshwao a Phethahatso Botjha a Transceiver……………………………………………………………………… PMA Lipontšo………………………………………………………………………………………….. 48

F-Tile Serial Lite IV Intel® FPGA IP User Guide 2

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Litaba
7. Ho rala ka F-Tile Serial Lite IV Intel FPGA IP…………………………………………………… 51 7.1. Hlophisa Litaelo……………………………………………………………………………………….. 51 7.2. Litaelo tsa ho Sebelisa Liphoso……………………………………………………………………………..51
8. F-Tile Serial Lite IV Intel FPGA IP User Guide Archives ……………………………………………. 52 9. Document Revision History for the F-Tile Serial Lite IV Intel FPGA IP User Guide ………53

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F-Tile Serial Lite IV Intel® FPGA IP User Guide 3

683074 | 2022.04.28 Romella Maikutlo

1. Mabapi le F-Tile Serial Lite IV Intel® FPGA IP User Guide

Tokomane ena e hlalosa likarolo tsa IP, tlhaloso ea meralo, mehato ea ho hlahisa, le tataiso ea ho qapa F-Tile Serial Lite IV Intel® FPGA IP ho sebelisa li-transceivers tsa F-tile ho lisebelisoa tsa Intel Agilex TM.

Bamameli ba Reriloeng

Tokomane ena e reretsoe basebelisi ba latelang:
· Baqapi ba meralo ea meralo ho etsa khetho ea IP nakong ea mohato oa moralo oa moralo oa sistimi
· Baqapi ba li-Hardware ha ba kopanya IP ho moralo oa bona oa boemo ba sistimi
· Lienjineri tsa netefatso nakong ea ketsiso ea boemo ba sistimi le mekhahlelo ea netefatso ea lisebelisoa

Litokomane Tse Amanang

Tafole e latelang e thathamisa litokomane tse ling tsa litšupiso tse amanang le F-Tile Serial Lite IV Intel FPGA IP.

Lethathamo la 1.

Litokomane Tse Amanang

Referense

F-Tile Serial Lite IV Intel FPGA IP Design Example Bukana ea Mosebelisi

Leqephe la Lintlha tsa Sesebelisoa sa Intel Agilex

Tlhaloso
Tokomane ena e fana ka tlhahiso, litataiso tsa ts'ebeliso, le tlhaloso e sebetsang ea F-Tile Serial Lite IV Intel FPGA IP design ex.ampka lisebelisoa tsa Intel Agilex.
Tokomane ena e hlalosa litšobotsi tsa motlakase, litšoaneleho tsa ho fetola, litlhaloso tsa tlhophiso, le nako ea lisebelisoa tsa Intel Agilex.

Lethathamo la 2.
CW RS-FEC PMA TX RX PAM4 NRZ

Acronyms le Glossary Acronym List
Kgutsufatso

Katoloso ea Taolo ea Lentsoe Reed-Solomon Forward Phoso Tokiso ea 'mele e Medium Attachment Transmitter Pulse-Amplitude Modulation 4-Level Ho se khutlele ho lefela

e tsoela pele…

Intel Corporation. Litokelo tsohle li sirelelitsoe. Intel, logo ea Intel, le matšoao a mang a Intel ke matšoao a khoebo a Intel Corporation kapa lithuso tsa eona. Intel e tiisa ts'ebetso ea FPGA ea eona le lihlahisoa tsa semiconductor ho latela litlhaloso tsa hajoale ho latela waranti e tloaelehileng ea Intel, empa e na le tokelo ea ho etsa liphetoho ho lihlahisoa le lits'ebeletso life kapa life ka nako efe kapa efe ntle le tsebiso. Intel ha e nke boikarabello kapa boikarabello bo hlahang ka lebaka la kopo kapa ts'ebeliso ea tlhahisoleseling efe kapa efe, sehlahisoa, kapa ts'ebeletso e hlalositsoeng mona ntle le ha ho lumellane ka ho hlaka ka lengolo ke Intel. Bareki ba Intel ba eletsoa ho fumana mofuta oa morao-rao oa litlhaloso tsa sesebelisoa pele ba itšetleha ka tlhahisoleseling efe kapa efe e phatlalalitsoeng le pele ba kenya liodara tsa lihlahisoa kapa lits'ebeletso. *Mabitso a mang le mabitso a mang a ka nkoa e le thepa ea ba bang.

ISO 9001:2015 E Ngolisitsoe

1. Mabapi le F-Tile Serial Lite IV Intel® FPGA IP User Guide 683074 | 2022.04.28

PCS MII XGMII

Kgutsufatso

Katoloso ea Physical Coding Interface ea Sublayer Media Independent 10 Gigabit Media Independent Interface

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F-Tile Serial Lite IV Intel® FPGA IP User Guide 5

683074 | 2022.04.28 Romella Maikutlo

2. F-Tile Serial Lite IV Intel FPGA IP Overview

Setšoantšo sa 1.

F-Tile Serial Lite IV Intel FPGA IP e loketse puisano ea data ea bandwidth e phahameng bakeng sa lisebelisoa tsa chip-to-chip, board-to-board, le backplane applications.

F-Tile Serial Lite IV Intel FPGA IP e kenyelletsa taolo ea phihlello ea mecha ea litaba (MAC), sesebelisoa sa khouto sa 'mele (PCS), le li-block tsa media tsa 'mele (PMA). IP e ts'ehetsa lebelo la phetisetso ea data ho fihla ho 56 Gbps ka lane le palo e kholo ea litselana tse 'ne tsa PAM4 kapa 28 Gbps ka tsela e nang le boholo ba litselana tsa 16 NRZ. IP ena e fana ka bandwidth e phahameng, liforeimi tse tlase tse holimo, palo e tlase ea I / O, 'me e ts'ehetsa scalability e phahameng lipalong tsa litselana le lebelo. IP ena e boetse e lokisoa habonolo ka ts'ehetso ea mefuta e mengata ea litefiso tsa data ka mokhoa oa Ethernet PCS oa F-tile transceiver.

IP ena e tšehetsa mekhoa e 'meli ea phetisetso:
· Mokhoa oa mantlha - Ena ke mokhoa o hloekileng oa ho phallela moo data e romelloang ntle le pakete ea ho qala, potoloho e se nang letho, le pheletso ea pakete ho eketsa bandwidth. IP e nka data ea pele e nepahetseng e le qalo ea ho phatloha.
· Mokhoa o felletseng-Ona ke mokhoa oa phetisetso ea lipakete. Ka mokhoa ona, IP e romela ho phatloha le potoloho ea sync qalong le qetellong ea pakete e le li-delimiters.

F-Tile Serial Lite IV High Level Block Diagram

Avalon Streaming Interface TX

F-Tile Serial Lite IV Intel FPGA IP
MAC TX
TX USRIF_CTRL

64*n lanes bits (NRZ mode)/ 2*n lanes bits (PAM4 mode)

TX MAC

Adapter KENYA

MII ENCODE

Li-PC tsa tloaelo

TX PCS

TX MII

EMIB ENCODE SCRAMBLER FEC

TX PMA

n Lanes Bits (PAM4 mode)/ n Lanes Bits (NRZ mode)
TX Serial Interface

Avalon Streaming Interface RX
64*n lanes bits (NRZ mode)/ 2*n lanes bits (PAM4 mode)

RX PCS

CW RMV

DESEKE

MII

& TEMOHISANA DECODE

RX MII

EMIB

DECODE BLOCK SYNC & FEC DESCRAMBLER

RX PMA

CSR

2n Lanes Bits (PAM4 mode)/ n Lanes Bits (NRZ mode) RX Serial Interface
Config ea Sehokelo sa Memory-Mapped ea Avalon

Tšōmo

Maikutlo a bonolo

Maikutlo a thata

ISO 9001:2015 E Ngolisitsoe

2. F-Tile Serial Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

O ka hlahisa F-Tile Serial Lite IV Intel FPGA IP design exampLes ho ithuta haholoanyane ka likarolo tsa IP. Sheba F-Tile Serial Lite IV Intel FPGA IP Design Example Bukana ea Mosebelisi.
Lintlha Tse Amanang · Tlhaloso ea Mosebetsi leqepheng la 19 · F-Tile Serial Lite IV Intel FPGA IP Design Example Bukana ea Mosebelisi

2.1. Tlhahisoleseding ea Phallo

Liphetolelo tsa Intel FPGA IP li tsamaisana le mefuta ea software ea Intel Quartus® Prime Design Suite ho fihlela v19.1. Ho qala ka Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP e na le leano le lecha la phetolelo.

Nomoro ea Intel FPGA IP (XYZ) e ka fetoha ka mofuta o mong le o mong oa software ea Intel Quartus Prime. Phetoho ho:

· X e bontša phetoho e kholo ea IP. Haeba u nchafatsa software ea Intel Quartus Prime, u tlameha ho nchafatsa IP.
· Y e bonts'a IP e kenyelletsa likarolo tse ncha. Nchafatsa IP ea hau ho kenyelletsa likarolo tsena tse ncha.
· Z e bonts'a IP e kenyelletsa liphetoho tse nyane. Hlahisa IP ea hau bocha ho kenyelletsa liphetoho tsena.

Lethathamo la 3.

F-Tile Serial Lite IV Intel FPGA IP Release Information

Ntho ea IP Version ea Intel Quartus Prime Version Letsatsi la ho Lokolla Khoutu ea ho Odara

5.0.0 22.1 2022.04.28 IP-SLITE4F

Tlhaloso

2.2. Likarolo tse tšehelitsoeng
Tafole e latelang e thathamisa likarolo tse fumanehang ho F-Tile Serial Lite IV Intel FPGA IP:

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F-Tile Serial Lite IV Intel® FPGA IP User Guide 7

2. F-Tile Serial Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

Lethathamo la 4.

F-Tile Serial Lite IV Intel FPGA IP Features

Sebopeho

Tlhaloso

Phetiso ea Lintlha

· Bakeng sa PAM4 mode:
- FHT e ts'ehetsa feela 56.1, 58, le 116 Gbps ka tsela e nang le boholo ba litsela tse 4.
- FGT e ts'ehetsa ho fihla ho 58 Gbps ka tsela e 'ngoe e nang le litselana tse 12.
Sheba Lethathamo la 18 leqepheng la 42 bakeng sa lintlha tse ling mabapi le litefiso tsa data tsa transceiver tse tšehetsoeng bakeng sa mokhoa oa PAM4.
· Bakeng sa mokhoa oa NRZ:
- FHT e ts'ehetsa 28.05 le 58 Gbps feela ka tsela e nang le litselana tse 4 tse ngata.
- FGT e ts'ehetsa ho fihla ho 28.05 Gbps ka tsela e 'ngoe e nang le litselana tse 16.
Sheba Lethathamo la 18 leqepheng la 42 bakeng sa lintlha tse ling mabapi le litefiso tsa data tsa transceiver tse tšehetsoeng bakeng sa mokhoa oa NRZ.
· E ts'ehetsa mekhoa e tsoelang pele ea ho phallela (Basic) kapa pakete (E Feletseng).
· E tšehetsa lipakete tse tlase tsa foreimi.
· E ts'ehetsa phetiso ea granularity ea byte bakeng sa boholo bo bong le bo bong ba ho phatloha.
· E ts'ehetsa ho lokisoa ha tsela e qalisoang ke mosebelisi kapa ea othomathike.
· E ts'ehetsa nako ea ho lokisoa ha lenaneo.

PCS

· E sebelisa logic e thata ea IP e hokahanang le li-transceivers tsa Intel Agilex F-tile bakeng sa phokotso ea lisebelisoa tse bonolo.
· E tšehetsa PAM4 modulation mode bakeng sa 100GBASE-KP4 litlhaloso. RS-FEC e lula e sebetsa ka mokhoa ona oa modulation.
· E ts'ehetsa NRZ ka mokhoa oa boikhethelo oa ho feto-fetoha ha RS-FEC.
· E ts'ehetsa 64b/66b encoding decoding.

Ho Fumana Phoso le ho Tšoara

· E ts'ehetsa ho hlahloba phoso ea CRC litseleng tsa data tsa TX le RX. · E tšehetsa ho hlahloba phoso ea sehokelo sa RX. · E tšehetsa ho lemoha liphoso tsa RX PCS.

Li-interface

· E ts'ehetsa phetisetso e felletseng ea lipakete tsa duplex ka lihokelo tse ikemetseng.
· E sebelisa khokahano ea ntlha-to-point ho lisebelisoa tse ngata tsa FPGA tse nang le latency e tlase ea phetisetso.
· E ts'ehetsa litaelo tse hlalosoang ke basebelisi.

2.3. IP Version Support Level

Software ea Intel Quartus Prime le tšehetso ea sesebelisoa sa Intel FPGA bakeng sa F-Tile Serial Lite IV Intel FPGA IP e tjena:

Lethathamo la 5.

IP Version le Boemo ba Tšehetso

Intel Quartus Prime 22.1

Sesebelisoa sa li-transceivers tsa Intel Agilex F-tile

IP Version Simulation Compilation Hardware Design

5.0.0

2.4. Sesebediswa Speed Grade Support
F-Tile Serial Lite IV Intel FPGA IP e tšehetsa limaraka tse latelang tsa lebelo bakeng sa lisebelisoa tsa Intel Agilex F-tile: · Kereiti ea lebelo la Transceiver: -1, -2, le -3 · Kereiti ea lebelo la Core: -1, -2, le - 3

F-Tile Serial Lite IV Intel® FPGA IP User Guide 8

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2. F-Tile Serial Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

Lintlha Tse Amanang
Intel Agilex Device Data Sheet Lintlha tse ling mabapi le sekhahla sa data se tšehetsoeng ho li-transceivers tsa Intel Agilex F-tile.

2.5. Tšebeliso ea Mehloli le Latency

Lisebelisoa le latency ea F-Tile Serial Lite IV Intel FPGA IP li fumanoe ho Intel Quartus Prime Pro Edition software version 22.1.

Lethathamo la 6.

Intel Agilex F-Tile Serial Lite IV Intel FPGA IP Resource Utilization
Tekanyo ea latency e ipapisitse le latency ea ho khutla ho tloha ho TX core input ho ea ho RX core output.

Mofuta oa Transceiver

Mofuta o fapaneng

Palo ea Mokhoa oa Lanes oa Boitsebiso RS-FEC ALM

Latency (TX core clock cycle)

FGT

28.05 Gbps NRZ 16

Batho ba Holofetseng ba 21,691 65

Ba holofetseng ka ho Feletseng 22,135 65

Motheo E nolofaditswe 21,915 189

E Felletse 22,452 189

58 Gbps PAM4 12

Motheo E nolofaditswe 28,206 146

E Felletse 30,360 146

FHT

58 Gbps NRZ

Motheo E nolofaditswe 15,793 146

E Felletse 16,624 146

58 Gbps PAM4 4

Motheo E nolofaditswe 15,771 154

E Felletse 16,611 154

116 Gbps PAM4 4

Motheo E nolofaditswe 21,605 128

E Felletse 23,148 128

2.6. Katleho ea Bandwidth

Lethathamo la 7.

Katleho ea Bandwidth

Mefuta e fapaneng ea Transceiver mode

PAM4

Mokhoa oa ho phallela RS-FEC

E Matlafalitsoe ka Botlalo

Basic Nobled

Sekhahla sa biti ea serial ho Gbps (RAW_RATE)
Boholo ba phetisetso ka palo ea lentsoe (BURST_SIZE) (1)
Nako ea ho tsamaisana nakong ea oache (SRL4_ALIGN_PERIOD)

56.0 2,048 4,096

56.0 4,194,304 4,096

Litlhophiso

NRZ

E tletse

E holofetse

E lumelletsoe

28.0

2,048

4,096

Batho ba nang le Bokooa ba 28.0

E lumelletsoe 28.0

4,194,304

4,096

4,096 e tsoetse pele…

(1) The BURST_SIZE for Basic mode e atamela ka ho sa feleng, ka hona ho sebelisoa palo e kholo.

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F-Tile Serial Lite IV Intel® FPGA IP User Guide 9

2. F-Tile Serial Lite IV Intel FPGA IP Overview 683074 | 2022.04.28

Mefuta e fapaneng

Litlhophiso

64/66b encode

0.96969697 0.96969697 0.96969697 0.96969697 0.96969697 0.96969697

Kaholimo ho boholo ba ho phatloha ka palo ea lentsoe (BURST_SIZE_OVHD)

2 (2)

0 (3)

2 (2)

0 (3)

Nako ea ho tsamaisa lesupa 81,915 ka nako ea oache (ALIGN_MARKER_PERIOD)

81,915

81,916

Bophara ba lesupa ho 5

potoloho ea oache

(ALIGN_MARKER_WIDTH)

Matla a bandwidth (4)

0.96821788 0.96916433 0.96827698 0.96822967 0.96922348 0.96917616

Sekhahla se sebetsang (Gbps) (5)

54.2202012 54.27320236 27.11175544 27.11043076 27.13825744 27.13693248

Boholo ba nako ea oache ea mosebelisi (MHz) (6)

423.59532225 424.00939437 423.62117875 423.6004806 424.0352725 424.01457

Related Information Link Rate le Bandwidth Effective Calculation leqepheng la 40

(2) Boemong bo felletseng, boholo ba BURST_SIZE_OVHD bo kenyelletsa START/END Mantsoe a Taolo a phehiloeng ho khokahanyo ea data.
(3) Bakeng sa Boemo ba mantlha, BURST_SIZE_OVHD ke 0 hobane ha ho START/END nakong ea ho phallela.
(4) Sheba Sekhahla sa Khokahano le Palo ea Katleho ea Bandwidth bakeng sa lipalo tse sebetsang hantle tsa bandwidth.
(5) Sheba Sekhahla sa Khokahano le Palo ea Bokhoni ba Bandwidth bakeng sa lipalo tse sebetsang hantle.
(6) Sheba Sekhahla sa Khokahano le Palo ea Bokhoni ba Bandwidth bakeng sa palo e phahameng ka ho fetesisa ea mosebelisi oa oache.

F-Tile Serial Lite IV Intel® FPGA IP User Guide 10

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683074 | 2022.04.28 Romella Maikutlo

3. Ho Qala

3.1. Ho kenya le ho fana ka laesense ea Intel FPGA IP Cores

Sesebelisoa sa Intel Quartus Prime software se kenyelletsa laeborari ea Intel FPGA IP. Laeborari ena e fana ka li-cores tse ngata tsa bohlokoa tsa IP bakeng sa tšebeliso ea hau ea tlhahiso ntle le tlhoko ea laesense e eketsehileng. Li-cores tse ling tsa Intel FPGA IP li hloka ho rekoa laesense e arohaneng bakeng sa ts'ebeliso ea tlhahiso. Intel FPGA IP Evaluation Mode e u lumella ho lekola li-cores tsena tse ngolisitsoeng ka molao tsa Intel FPGA ka papiso le hardware, pele u etsa qeto ea ho reka laesense e felletseng ea tlhahiso ea IP. U hloka feela ho reka laesense e felletseng ea tlhahiso bakeng sa li-cores tsa Intel IP tse ngolisitsoeng ka molao ka mor'a hore u qete tlhahlobo ea hardware 'me u se u loketse ho sebelisa IP tlhahiso.

Software ea Intel Quartus Prime e kenya li-cores tsa IP libakeng tse latelang ka boiketsetso:

Setšoantšo sa 2.

Mokhoa oa ho kenya IP Core
intelFPGA(_pro) quartus - E na le Intel Quartus Prime software ip - E na le laeborari ea Intel FPGA IP le li-cores tsa IP tsa motho oa boraro - E na le khoutu ea mohloli oa laeborari ea Intel FPGA IP - E na le mohloli oa IP oa Intel FPGA files

Lethathamo la 8.

Libaka tsa ho kenya IP Core

Sebaka

Software

:intelFPGA_proquartusipaltera

Khatiso ea Intel Quartus Prime Pro

:/intelFPGA_pro/quartus/ip/altera Intel Quartus Prime Pro Edition

Platform Windows* Linux*

Hlokomela:

Intel Quartus Prime software ha e tšehetse libaka tse tseleng ea ho kenya.

3.1.1. Intel FPGA IP Evaluation Mode
Mokhoa oa mahala oa Intel FPGA IP Evaluation Mode o u lumella ho lekola li-cores tsa Intel FPGA IP tse ngolisitsoeng ka molao ka papiso le lisebelisoa pele u reka. Intel FPGA IP Evaluation Mode e ts'ehetsa litlhahlobo tse latelang ntle le laesense e eketsehileng:
· Etsisa boits'oaro ba Intel FPGA IP e nang le lengolo la motheo tsamaisong ea hau. · Netefatsa tšebetso, boholo, le lebelo la mantlha la IP kapele le ha bonolo. · Hlahisa mananeo a sesebelisoa sa nako e lekanyelitsoeng files bakeng sa meralo e kenyelletsang li-cores tsa IP. · Rulahanya sesebelisoa ka IP ea hau ea mantlha 'me u netefatse moralo oa hau ho Hardware.

ISO 9001:2015 E Ngolisitsoe

3. Ho Qala
683074 | 2022.04.28
Intel FPGA IP Evaluation Mode e tšehetsa mekhoa e latelang ea ts'ebetso:
· Tethered-E lumella ho tsamaisa moralo o nang le laesense ea Intel FPGA IP ka nako e sa lekanyetsoang ka khokahano lipakeng tsa boto ea hau le komporo e amohelang. Mokhoa o kopantsoeng o hloka sehlopha sa liteko tse kopaneng tsa liteko (JTAG) cable e hokahantsoeng lipakeng tsa JTAG boto ea hau le komporo e amohelang, e sebelisang Intel Quartus Prime Programmer nakong ea tlhahlobo ea lisebelisoa. Lenaneo le hloka feela ts'ebetso e fokolang ea software ea Intel Quartus Prime, 'me ha e hloke laesense ea Intel Quartus Prime. K'homphieutha e amohelang e laola nako ea tlhahlobo ka ho romela lets'oao la nako le nako ho sesebelisoa ka mochini oa JTAG boemakepe. Haeba li-cores tsohle tsa IP tse nang le laesense li le molemong oa ts'ehetso ea moralo, nako ea tlhahlobo e tsoela pele ho fihlela tlhahlobo efe kapa efe ea IP e fela. Haeba li-cores tsohle tsa IP li tšehetsa nako ea tlhahlobo e sa lekanyetsoang, sesebelisoa ha se felloe ke nako.
· E sa sebetsaneng-E lumella ho tsamaisa moralo o nang le IP e nang le lengolo la nakoana. IP core e khutlela mokhoeng o sa thijoang haeba sesebelisoa se ikarola ho komporo e amohelang e sebelisang software ea Intel Quartus Prime. IP core e boetse e khutlela mokhoeng o sa tsitsang haeba leha e le efe e 'ngoe e nang le laesense ea IP ea mantlha moralong e sa tšehetse mokhoa oa tethered.
Ha nako ea tlhahlobo e fela bakeng sa Intel FPGA IP efe kapa efe e ngolisitsoeng ka molao moralong, moralo o emisa ho sebetsa. Li-cores tsohle tsa IP tse sebelisang Intel FPGA IP Evaluation Mode li tsoa ka nako e le 'ngoe ha motheo ofe kapa ofe oa IP nakong ea moralo o felile. Ha nako ea tlhahlobo e felile, o tlameha ho hlophisa sesebelisoa sa FPGA bocha pele o tsoela pele ho netefatsa hardware. Ho holisa tšebeliso ea mantlha ea IP bakeng sa tlhahiso, reka laesense e felletseng ea tlhahiso ea mantlha ea IP.
O tlameha ho reka laesense mme o hlahise senotlolo se felletseng sa laesense pele o ka hlahisa lenaneo le sa thibetsoeng la sesebelisoa file. Nakong ea Intel FPGA IP Evaluation Mode, Compiler e hlahisa feela lenaneo le lekanyelitsoeng la sesebelisoa file ( _time_limited.sof) e felloang ke nako ka nako e lekantsoeng.

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Setšoantšo sa 3.

Intel FPGA IP Evaluation Mode Phalow
Kenya Intel Quartus Prime Software ka Intel FPGA IP Library

Parameterize 'me u Kenyeletse Intel FPGA IP Core e nang le License

Netefatsa IP ho Simulator e Tšehetsoeng

Kopanya Moralo ho Intel Quartus Prime Software

Hlahisa Lenaneo la Nako e Lekanyelitsoeng la Sesebelisoa File

Lenaneo la Sesebelisoa sa Intel FPGA le ho netefatsa Ts'ebetso ho Boto
Ha ho na IP e Loketse ho Sebelisa Tlhahiso?
E, Reka Tlhahiso e Feletseng
IP License

Hlokomela:

Kenyelletsa IP e nang le License ho Lihlahisoa tsa Khoebo
Sheba tataiso ea mantlha ea IP bakeng sa mehato ea parameterization le lintlha tsa ts'ebetsong.
Intel e fana ka li-cores tsa IP ka setulo se le seng, kamehla. Tefiso ea laesense e kenyelletsa tlhokomelo le tšehetso ea selemo sa pele. U tlameha ho nchafatsa konteraka ea tlhokomelo ho fumana lintlafatso, litšitiso, le tšehetso ea tekheniki ho feta selemo sa pele. O tlameha ho reka laesense e felletseng ea tlhahiso ea Intel FPGA IP cores e hlokang laesense ea tlhahiso, pele o hlahisa mananeo files eo u ka e sebelisang ka nako e se nang moeli. Nakong ea Intel FPGA IP Evaluation Mode, Compiler e hlahisa feela lenaneo le lekanyelitsoeng la sesebelisoa file ( _time_limited.sof) e felloang ke nako ka nako e lekantsoeng. Ho fumana linotlolo tsa laesense ea hau ea tlhahiso, etela Setsi sa Lilaesense sa Intel FPGA Self-Service Self-Service Center.
Litumellano tsa License tsa Software tsa Intel FPGA li laola ho kengoa le ho sebelisoa ha li-cores tse nang le laesense tsa IP, software ea moralo oa Intel Quartus Prime, le li-cores tsohle tse se nang laesense tsa IP.

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Lintlha tse Amanang · Setsi sa Tšehetso sa Lilaesense tsa Intel FPGA · Selelekela ho Intel FPGA Software Installation and Licensing
3.2. E totobatsa IP Parameters le Options
IP paramethara e u lumella ho hlophisa phapano ea hau ea IP kapele. Sebelisa mehato e latelang ho hlakisa likhetho tsa IP le liparamente ho software ea Intel Quartus Prime Pro Edition.
1. Haeba ha o so na projeke ea Intel Quartus Prime Pro Edition eo ho eona o ka kopanyang F-Tile Serial Lite IV Intel FPGA IP ea hau, u tlameha ho e etsa. a. Ho Intel Quartus Prime Pro Edition, tobetsa File Wizard e Ncha ea Morero ho theha projeke e ncha ea Quartus Prime, kapa File Open Project ho bula morero o teng oa Quartus Prime. Wizate e o kopa hore o hlalose sesebediswa. b. Hlalosa lelapa la sesebelisoa Intel Agilex 'me u khethe sehlahisoa sa F-tile se finyellang litlhoko tsa lebelo la IP. c. Tobetsa Qetella.
2. Ho IP Catalogue, fumana 'me u khethe F-Tile Serial Lite IV Intel FPGA IP. Ho hlaha fensetere e ncha ea IP Variation.
3. Hlalosa lebitso la boemo bo holimo bakeng sa phapano ea hau e ncha ea IP. Mohlophisi oa paramethara o boloka litlhophiso tsa phapang ea IP ho a file bitsetsoe .ip.
4. Tobetsa OK. Mohlophisi oa parameter oa hlaha. 5. Hlalosa li-parameter bakeng sa phapano ea hau ea IP. Sheba karolo ea Parameter bakeng sa
lintlha tse mabapi le F-Tile Serial Lite IV Intel FPGA IP parameters. 6. Ka boikhethelo, ho hlahisa testbench ea ketsiso kapa pokello le moralo oa lisebelisoa
example, latela ditaelo tse ho Moetso Example Bukana ea Mosebelisi. 7. Tobetsa Hlahisa HDL. Lebokose la puisano la Moloko lea hlaha. 8. Hlalosa tlhahiso file ho hlahisa likhetho, ebe o tobetsa Hlahisa. Phapang ea IP
files hlahisa ho latela litlhaloso tsa hau. 9. Tobetsa Qetella. Mohlophisi oa parameter o eketsa boemo bo holimo .ip file ho ea hajoale
morero ka tsela e iketsang. Haeba u khothalletsoa ho kenya .ip ka letsoho file ho morero, tobetsa Project Add/Tlosa Files ho Morero ho eketsa file. 10. Ka mor'a ho hlahisa le ho kenya letsoho phapanong ea hau ea IP, etsa likabelo tse nepahetseng tsa phini ho hokela likou le ho beha liparamente tse loketseng tsa mohlala oa RTL.
Lintlha tse amanang le tsona leqepheng la 42
3.3. E hlahisitsoe File Sebopeho
Software ea Intel Quartus Prime Pro Edition e hlahisa tlhahiso e latelang ea IP file sebopeho.
Bakeng sa boitsebiso bo mabapi le file sebopeho sa moralo example, bua ka F-Tile Serial Lite IV Intel FPGA IP Design Example Bukana ea Mosebelisi.

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Setšoantšo sa 4. F-Tile Serial Lite IV Intel FPGA IP E hlahisitsoe Files
.ip - IP kopanyo file

Phapang ea IP files

_ Phapang ea IP files

example_design

.cmp - phatlalatso ea karolo ea VHDL file _bb.v – Verilog HDL black box EDA synthesis file _inst.v le .vhd – Samplitempele tsa instantiation .xml- tlaleho ea XML file

Example sebaka bakeng sa moralo oa hau oa mantlha oa IP oa khaleample files. Sebaka sa kamehla ke mohlalaample_design, empa o khothalletsoa ho bolela tsela e fapaneng.

.qgsimc - E thathamisa liparamente tsa papiso ho ts'ehetsa ntlafatso e ntseng e eketseha .qgsynthc - E thathamisa liparamente tsa synthesis ho ts'ehetsa ntlafatso e ntseng e eketseha

.qip – E thathamisa IP synthesis files

Tlaleho ea tlhahiso ea _generation.rpt- IP

.sopcinfo- Khokahanyo ea lisebelisoa tsa software file .html- Data ya kgokelo le memori ya mmapa

.csv - Mosebetsi oa Pin file

.spd - E kopanya mongolo oa papiso ea motho ka mong

SIM Ketsiso files

Synthesis ea IP files

.v Ketsiso ea boemo bo holimo file

.v Phatlalatso ea IP ea boemo bo holimo file

Mengolo ea simulator

Lilaebrari tsa subcore

synth
Subcore synthesis files

sim
Ketsiso ea Subcore files

Lethathamo la 9.

F-Tile Serial Lite IV Intel FPGA IP E hlahisitsoe Files

File Lebitso

Tlhaloso

.ip

Sistimi ea Moqapi oa Sethala kapa phapano ea IP ea boemo bo holimo file. ke lebitso leo u fanang ka lona IP ho fapana.

.cmp

Phatlalatso ea Karolo ea VHDL (.cmp) file ke mongolo file e nang le litlhaloso tsa lehae tsa generic le port tseo u ka li sebelisang moetsong oa VHDL files.

html

Tlaleho e nang le tlhahisoleseding ea khokahanyo, 'mapa oa memori o bontšang aterese ea lekhoba le leng le le leng mabapi le monghali e mong le e mong eo e amanang le eona, le likabelo tsa parameter.

_moloko.rpt

Lenane la tlhahiso ea IP kapa Platform Designer file. Kakaretso ea melaetsa nakong ea tlhahiso ea IP.

.qgsimc

E thathamisa liparamente tsa ketsiso ho ts'ehetsa ntlafatso e ntseng e eketseha.

qgsynthc

E thathamisa liparamente tsa synthesis ho ts'ehetsa ntlafatso e ntseng e eketseha.

.qip

E na le lintlha tsohle tse hlokahalang mabapi le karolo ea IP ho kopanya le ho bokella karolo ea IP ho software ea Intel Quartus Prime.
e tsoela pele…

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File Lebitso .sopcinfo
.csv .spd _bb.v _inst.v kapa _inst.vhd .regmap
.svd
.v kapa .vhd mentor/ synopsy/vcs/ synopsy/vcsmx/ xcelium/ submodules/ /

Tlhaloso
E hlalosa likhokahano le likarolo tsa likarolo tsa IP ho sistimi ea Moqapi oa Platform. O ka bapisa litaba tsa eona ho fumana litlhoko ha o nts'etsapele lisebelisoa tsa software bakeng sa likarolo tsa IP. Lisebelisoa tse tlase tse kang ketane ea lisebelisoa tsa Nios® II li sebelisa sena file. The .sopcinfo file le tsamaiso.h file e hlahisoang bakeng sa ketane ea lisebelisoa tsa Nios II e kenyelletsa lintlha tsa 'mapa oa aterese bakeng sa lekhoba le leng le le leng le amanang le mong'a e mong le e mong ea kenang lekhoba. Beng ba fapaneng ba ka ba le 'mapa o fapaneng oa aterese ho fihlella karolo e itseng ea makhoba.
E na le leseli mabapi le boemo ba ntlafatso ea karolo ea IP.
Kenyelletso e hlokahalang file bakeng sa ip-make-simscript ho hlahisa mongolo oa papiso bakeng sa li-simulator tse tšehetsoeng. The .spd file e na le lenane la files e hlahisoang bakeng sa papiso, hammoho le tlhahisoleseling mabapi le mehopolo eo u ka e qalang.
U ka sebelisa Verilog black-box (_bb.v) file joalo ka phatlalatso ea mojule e se nang letho bakeng sa ho sebelisoa joalo ka lebokose le letšo.
HDL mohlalaample instantiation template. U ka kopitsa le ho beha litaba tsa sena file ho HDL ea hau file ho kenya letsoho ho feto-fetoha ha IP.
Haeba IP e na le tlhahisoleseling, .regmap file hlahisa. The .regmap file e hlalosa tlhaiso-leseling ea 'mapa oa master le makhoba interfaces. Sena file e tlatsana le .sopcinfo file ka ho fana ka tlhaiso-leseling e batsi mabapi le sistimi. Sena se nolofalletsa pontšo ea register views le lipalo-palo tseo motho a ka li khethang ho System Console.
E lumella hard processor system (HPS) System Debug lisebelisoa ho view limmapa tse ngolisoang tsa peripherals tse hokahaneng le HPS tsamaisong ea Moqapi oa Platform. Nakong ea ho kopanya, .svd files bakeng sa li-interface tsa makhoba tse bonahalang ho System Console masters li bolokiloe ho .sof file karolong ea ho lokisa liphoso. System Console e bala karolo ena, eo Moqapi oa Platform a ka e botsang bakeng sa tlhaiso-leseling ea 'mapa. Bakeng sa makhoba a tsamaiso, Moqapi oa Platform a ka fumana li-registas ka mabitso.
HDL filetse tiisang submodule e 'ngoe le e 'ngoe kapa IP ea ngoana bakeng sa ho kopanya kapa ho etsisa.
E na le sengoloa sa ModelSim*/QuestaSim* msim_setup.tcl ho seta le ho etsa ketsiso.
E na le shell script vcs_setup.sh ho seta le ho tsamaisa papiso ea VCS*. E na le mongolo oa khetla vcsmx_setup.sh le synopsys_sim.setup file ho theha le ho tsamaisa papiso ea VCS MX.
E na le mongolo oa khetla xcelium_setup.sh le litlhophiso tse ling files ho theha le ho tsamaisa ketsiso ea Xcelium*.
E na le HDL files bakeng sa li-submodule tsa IP.
Bakeng sa bukana e 'ngoe le e' ngoe e hlahisitsoeng ea IP ea ngoana, Moqapi oa Platform o hlahisa li-synth/ le sim/ sub-directory.

3.4. Ho etsisa Intel FPGA IP Cores
Software ea Intel Quartus Prime e ts'ehetsa IP core RTL simulation ho li-simulator tse khethehileng tsa EDA. Ho hlahisa IP ka boikhethelo ho etsa papiso files, ho kenyelletsa le mohlala o sebetsang oa ketsiso, testbench efe kapa efe (kapa example design), le lingoliloeng tse ikhethileng tsa morekisi bakeng sa motheo o mong le o mong oa IP. U ka sebelisa mohlala o sebetsang oa ketsiso le testbench efe kapa efe kapa example moralo bakeng sa ketsiso. Tlhahiso ea tlhahiso ea IP e kanna ea kenyelletsa mangolo a ho bokella le ho tsamaisa testbench efe kapa efe. Lingoliloeng li thathamisa mefuta eohle kapa lilaebrari tseo u li hlokang ho etsisa IP ea hau ea mantlha.

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Intel Quartus Prime software e fana ka kopanyo le li-simulator tse ngata 'me e ts'ehetsa phallo e mengata ea ketsiso, ho kenyeletsoa phallo ea hau e ngotsoeng le e tloaelehileng ea papiso. Ho sa tsotellehe hore na u khetha phallo efe, ketsiso ea mantlha ea IP e kenyelletsa mehato e latelang:
1. Hlahisa IP HDL, testbench (kapa example design), le sengoloa sa ho seta sa simulator files.
2. Hlophisa tikoloho ea hau ea simulator le mengolo efe kapa efe ea papiso.
3. Kopanya lilaebrari tsa mohlala oa papiso.
4. Mathisa simulator ea hau.

3.4.1. Ho Etsisa le ho Tiisa Moralo

Ka mokhoa o ikhethileng, mohlophisi oa paramethara o hlahisa mangolo a ikhethileng a simulator a nang le litaelo tsa ho bokella, ho qaqisa le ho etsisa mefuta ea Intel FPGA IP le laeborari ea mohlala oa papiso. files. U ka kopitsa litaelo ho mongolo oa hau oa simulation testbench, kapa u li hlophise files ho eketsa litaelo tsa ho bokella, ho hlalosa, le ho etsisa moralo oa hau le testbench.

Letlapa la 10. Intel FPGA IP Core Simulation Scripts

Moetsisi

File Directory

ModelSim

_sim/motataisi

QuestaSim

VCS

_sim/synopsy/vcs

Tlhaloso: VCS MX

_sim/synopsy/vcsmx

Xcelium

_sim/xcelium

Script msim_setup.tcl (7)
vcs_setup.sh vcsmx_setup.sh synopsys_sim.setup xcelium_setup.sh

3.5. Ho kopanya IP Cores ho Lisebelisoa tse ling tsa EDA
Ka boikhethelo, sebelisa sesebelisoa se seng se tšehelitsoeng sa EDA ho kopanya moralo o kenyelletsang Intel FPGA IP cores. Ha o hlahisa IP core synthesis files bakeng sa ho sebelisoa le lisebelisoa tsa mokha oa boraro oa EDA, o ka theha sebaka le lenane la likhakanyo tsa nako. Ho thusa ho etsa tlhahiso, laeta Etsa likhakanyo tsa nako le lisebelisoa bakeng sa lisebelisoa tsa motsoako oa EDA ha u khetha IP ea hau.
Sebaka le lenane la likhakanyo tsa nako le hlalosa khokahano ea mantlha ea IP le boqapi, empa ha le kenyelletse lintlha tse mabapi le ts'ebetso ea 'nete. Lintlha tsena li thusa lisebelisoa tse ling tsa mokha oa boraro ho fana ka tlaleho hamolemo le likhakanyo tsa nako. Ntle le moo, lisebelisoa tsa ho kopanya li ka sebelisa tlhaiso-leseling ea nako ho fihlela lintlafatso tse tsamaisoang ke nako le ho ntlafatsa boleng ba liphetho.
Software ea Intel Quartus Prime e hlahisa li _syn.v lenane la marang-rang file ka sebopeho sa Verilog HDL, ho sa tsotelehe tlhahiso file sebopeho seo u se boletseng. Haeba u sebelisa netlist ena bakeng sa ho kopanya, u tlameha ho kenyelletsa IP core wrapper file .v kapa .vhd morerong oa hau oa Intel Quartus Prime.

(7) Haeba ha ua theha khetho ea sesebelisoa sa EDA- e u nolofalletsang ho qala li-simulator tsa EDA tsa mokha oa boraro ho tsoa ho Intel Quartus Prime software - tsamaisa mongolo ona ho ModelSim kapa QuestaSim simulator Tcl console (eseng ho Intel Quartus Prime software. Tcl console) ho qoba liphoso leha e le life.

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3.6. Ho Kopanya Moralo o Felletseng
U ka sebelisa taelo ea Start Compilation ho menu ea Processing ho software ea Intel Quartus Prime Pro Edition ho bokella moralo oa hau.

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4. Tlhaloso ea Ts'ebetso

Setšoantšo sa 5.

F-Tile Serial Lite IV Intel FPGA IP e na le MAC le Ethernet PCS. MAC e buisana le PCS e tloaelehileng ka li-interface tsa MII.

IP e tšehetsa mekhoa e 'meli ea modulation:
· PAM4–E fana ka palo e 1 ho isa ho 12 ea litselana bakeng sa khetho. IP e lula e fana ka liteishene tse peli tsa PCS bakeng sa lane ka 'ngoe ho PAM4 modulation mode.
· NRZ–E fana ka palo ea litsela tse 1 ho isa ho tse 16 bakeng sa khetho.

Mokhoa o mong le o mong oa modulation o tšehetsa mekhoa e 'meli ea data:
· Mokhoa oa mantlha - Ena ke mokhoa o hloekileng oa ho phallela moo data e romelloang ntle le pakete ea ho qala, potoloho e se nang letho, le pheletso ea pakete ho eketsa bandwidth. IP e nka data ea pele e nepahetseng e le qalo ea ho phatloha.

Phetisetso ea Lintlha tsa Mokhoa oa Motheo tx_core_clkout tx_avs_ready

tx_avs_valid tx_avs_data rx_core_clkout rx_avs_ready

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_valid rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

ISO 9001:2015 E Ngolisitsoe

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Setšoantšo sa 6.

· Mokhoa o felletseng-Ena ke phetiso ea data ea mokhoa oa pakete. Ka mokhoa ona, IP e romela ho phatloha le potoloho ea sync qalong le qetellong ea pakete e le li-delimiters.

Phetisetso ea data ea Mokhoa o Felletseng tx_core_clkout

tx_avs_ready tx_avs_valid tx_avs_startofpacket tx_avs_endofpacket
tx_avs_data rx_core_clkout rx_avs_ready rx_avs_valid rx_avs_startofpacket rx_avs_endofpacket

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

Lintlha Tse Li amanang · F-Tile Serial Lite IV Intel FPGA IP Overview leqepheng la 6 · F-Tile Serial Lite IV Intel FPGA IP Design Example Bukana ea Mosebelisi

4.1. TX Datapath
Datapath ea TX e na le likarolo tse latelang: · MAC adapter · Laola thibelo ea ho kenya mantsoe · CRC · MII encoder · PCS block · PMA block

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Setšoantšo sa 7. TX Datapath

Ho tsoa ho mosebelisi logic

TX MAC

Avalon Streaming Interface

Adapter ea MAC

Laola ho Kena ha Mantswe

CRC

MII Encoder

MII Interface Custom PCS
PCS le PMA

TX Serial Interface ho lisebelisoa tse ling tsa FPGA

4.1.1. Adapter ea TX MAC
Adapter ea TX MAC e laola phetisetso ea data ho logic ea mosebelisi e sebelisa sebopeho sa phallo sa Avalon®. Thibelo ena e tšehetsa phetiso ea tlhahisoleseling e hlalositsoeng ke basebelisi le taolo ea phallo.

Ho fetisa Boitsebiso bo hlalositsoeng ke basebelisi

Ka mokhoa o felletseng, IP e fana ka lets'oao la tx_is_usr_cmd leo u ka le sebelisang ho qala potoloho ea tlhahisoleseling e hlalositsoeng ke basebelisi joalo ka phetisetso ea XOFF/XON ho mohopolo oa mosebelisi. U ka qala potoloho ea phetisetso ea tlhahisoleseling e hlalositsoeng ke basebelisi ka ho tiisa lets'oao lena le ho fetisa tlhahisoleseling ka tx_avs_data hammoho le tiisetso ea matšoao a tx_avs_startofpacket le tx_avs_valid. Joale block e tlosa tx_avs_ready bakeng sa lipotoloho tse peli.

Hlokomela:

Karolo ea tlhaiso-leseling e hlalositsoeng ke mosebelisi e fumaneha feela ka Mokhoa o felletseng.

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Setšoantšo sa 8.

Taolo ea Phallo

Ho na le maemo ao TX MAC e sa itokisetsang ho fumana data ho tsoa ho logic ea mosebelisi joalo ka nakong ea ts'ebetso ea ho hokahanya bocha kapa ha ho se na data e fumanehang bakeng sa phetisetso ho tsoa ho mohopolo oa mosebelisi. Ho qoba tahlehelo ea data ka lebaka la maemo ana, IP e sebelisa letšoao la tx_avs_ready ho laola phallo ea data ho tsoa ho logic ea mosebedisi. IP e hlakisa lets'oao ha maemo a latelang a etsahala:
· Ha tx_avs_startofpacket e tiisitsoe, tx_avs_ready e tlosoa bakeng sa saekele e le 'ngoe ea oache.
· Ha tx_avs_endofpacket e tiisitsoe, tx_avs_ready e tlosoa bakeng sa saekele e le 'ngoe ea oache.
· Ha CWs efe kapa efe e tsamaisanang e boleloa tx_avs_ready e hloekisoa bakeng sa li-wache tse peli.
· Ha RS-FEC alignment marker kenyang e etsahala ho PCS ea tloaelo segokanyimmediamentsi sa sebolokigolo, tx_avs_ready e desserated bakeng sa lipotoloho tse 'nè oache.
* Lipotoloho tse ling le tse ling tse 17 tsa Ethernet tsa mantlha ka mokhoa oa modulation oa PAM4 le lipotoloho tsohle tse 33 tsa Ethernet tsa mantlha ka mokhoa oa modulation oa NRZ. The tx_avs_ready e felloa ke matla bakeng sa seketsoana sa oache e le 'ngoe.
· Ha mosebedisi logic deassserts tx_avs_valid nakong ha ho phetiso ya data.

Litšoantšo tse latelang tsa nako ke mohlalaamples ea adaptara ea TX MAC e sebelisang tx_avs_ready bakeng sa taolo ea phallo ea data.

Taolo ea Phallo e nang le tx_avs_valid Dessertion le START/END Li-CW tse Kopantsoeng

tx_core_clkout

tx_avs_valid tx_avs_data

D1 D2 D3

Li-dessert tse sebetsang

EA-D5 D6

tx_avs_ready tx_avs_startofpacket

Li-teassets tse se li loketse bakeng sa lipotoloho tse peli ho kenya END-STRT CW

tx_avs_endofpacket

data ea usrif

D1 D2 D3

CW_data

DN QETELA STRT D0 D1 D2 D3 TŠELA D4

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Setšoantšo sa 9.

Taolo ea Phallo ka Kenyeletso ea Lesupa la Alignment
tx_core_clkout tx_avs_valid

tx_avs_data tx_avs_ready

DN-5 DN-4 DN-3 DN-2 DN-1

DN+1

01234

tx_avs_startofpacket tx_avs_endofpacket

data ea CW_data CRC_data MII_data

DN-1 DN DN DN DN DN DN DN DN+1 DN-1 DN DN DN DN DN +1 DN DN

ke_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

EA-1-DN

DN+1

i_sl_tx_mii_c[7:0]

0x0

ke_sl_tx_mii_am

01234

i_sl_tx_mii_am_pre3

01234

Setšoantšo sa 10.

Taolo ea Phallo e nang le START/END CWs tse Pakaneng li Tsamaellana le Kenyeletso ea Lesupa la Alignment

tx_core_clkout tx_avs_valid

tx_avs_data

DN-5 DN-4 DN-3 DN-2 DN-1

tx_avs_ready

012 345 6

tx_avs_startofpacket

tx_avs_endofpacket

data ea usrif

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

CW_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

CRC_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

MII_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

ke_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

EA-1-DN

QETELA STRT D0

i_sl_tx_mii_c[7:0]

0x0

i_sl_tx_mii_am ke_sl_tx_mii_am_pre3

01234

4.1.2. Laola Lentsoe (CW) Kenyeletso
F-Tile Serial Lite IV Intel FPGA IP e aha li-CW ho ipapisitse le matšoao a kenyellelitsoeng ho tsoa mohopolong oa mosebelisi. Li-CW li bonts'a li-delimiters tsa pakete, tlhahisoleseling ea boemo ba phetisetso kapa data ea mosebelisi ho block ea PCS mme li nkiloe ho likhoutu tsa taolo tsa XGMII.
Tafole e latelang e bonts'a tlhaloso ea li-CW tse tšehetsoeng:

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Lethathamo la 11.
QETELA TEKANE

Tlhaloso ea Li-CW tse Tšehetsoeng

Palo ea Mantsoe (lentsoe le le leng

= likotoana tse 64)

EMPTY_CYC

IDLE

Che

DATA

Ka sehlopha

Tlhaloso
Ho qala ha data delimiter. Qetello ea sekhao sa data. Laola lentsoe (CW) bakeng sa ho tsamaisana le RX. Potoloho e se nang letho phetisong ea data. IDLE (ntle le sehlopha). Lekhetho.

Lethathamo la 12. Tlhaloso ea Tšimo ea CW
Sebaka sa RSVD num_valid_bytes_eob
EMPTY eop sop seop ikamahanya le CRC32 usr

Tlhaloso
Sebaka se bolokiloeng. E ka sebelisoa bakeng sa katoloso e tlang. E hokahane le 0.
Palo ea li-byte tse sebetsang lentsoeng la ho qetela (64-bit). Ena ke boleng ba 3bit. · 3'b000: 8 byte · 3'b001: 1 byte · 3'b010: 2 byte · 3'b011: 3 byte · 3'b100: 4 byte · 3'b101: 5 byte · 3'b110: 6 byte · 3'b111: 7 li-byte
Palo ea mantsoe a sa sebetseng qetellong ea ho phatloha.
E bonts'a sebopeho sa phallo ea RX Avalon ho fana ka lets'oao la ho qetela la pakete.
E bonts'a sebopeho sa phallo ea RX Avalon ho fana ka lets'oao la ho qala pakete.
E bonts'a sebopeho sa phallo ea RX Avalon ho tiisa qalo ea pakete le pheletso ea pakete ka potoloho e tšoanang.
Sheba tumellano ea RX.
Litekanyetso tsa CRC tse khomphuthang.
E bontša hore lentsoe la taolo (CW) le na le boitsebiso bo hlalositsoeng ke mosebedisi.

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4.1.2.1. Ho qala ho phatloha ha CW

Setšoantšo sa 11. Ho qala ha CW Format

QALA

63:56

RSVD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16

sop usr align=0 seop

15:8

mocha

7:0

'hFB(QALA)

taolo 7:0

Lethathamo la 13.

Ka mokhoa o felletseng, o ka kenya START CW ka ho tiisa lets'oao la tx_avs_startofpacket. Ha o tiisa feela lets'oao la tx_avs_startofpacket, sop bit e setiloe. Ha o fana ka matšoao a mabeli a tx_avs_startofpacket le tx_avs_endofpacket, seop bit e setiloe.

QALA CW Maemo a Tšimo
Tšimo sep/seop
mosebelisi (8)
ikamahanya

Boleng

Ho latela tx_is_usr_cmd lets'oao:

1: Ha tx_is_usr_cmd = 1

0: Ha tx_is_usr_cmd = 0

Boemong ba Motheo, MAC e romela START CW ka mor'a hore reset e felisoe. Haeba ho se na data, MAC e lula e romella EMPTY_CYC e tsamaisanang le END le START CWs ho fihlela o qala ho romella lintlha.

4.1.2.2. Qetello ea ho phatloha ha CW

Setšoantšo sa 12. Qetello ea ho phatloha ha CW Format

QETA

63:56

' hFD

55:48

CRC32[31:24]

47:40

CRC32[23:16]

data 39:32 31:24

CRC32[15:8] CRC32[7:0]

23:16 eop=1 RSVD RSVD RSVD

RSVD

15:8

RSVD

HLOKA

7:0

RSVD

nomoro_valid_bytes_eob

taolo

7:0

(8) Sena se tšehetsoa feela ka mokhoa o feletseng.
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Lethathamo la 14.

MAC e kenya END CW ha tx_avs_endofpacket e boleloa. END CW e na le palo ea li-byte tse nepahetseng lentsoeng la ho qetela la data le lintlha tsa CRC.

Boleng ba CRC ke sephetho sa 32-bit CRC bakeng sa data e lipakeng tsa START CW le lentsoe la data pele ho END CW.

Tafole e latelang e bonts'a boleng ba masimo ho END CW.

QETELA Maemo a Tšimo a CW
Sebaka sa sebaka sa CRC32 num_valid_bytes_eob

Boleng 1
CRC32 boleng ba khomphutha. Nomoro ea li-byte tse nepahetseng lentsoeng la ho qetela la data.

4.1.2.3. Ho tsamaisana le CW

Setšoantšo sa 13. Ho tsamaisana ho kopantsoe le CW Format

ALIGN CW e kopane le START/END

64+8bits XGMII Interface

QALA

63:56

RSVD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16 eop=0 sop=0 usr=0 amahanya=1 seop=0

15:8

RSVD

7:0

' hFB

taolo 7:0

64+8bits XGMII Interface

QETA

63:56

' hFD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

taolo 7:0

ALIGN CW ke CW e tsamaisanang le START/END kapa END/START CWs. O ka kenya ALIGN e parakaneng CW ka ho tiisa lets'oao la tx_link_reinit, ho seta k'haontara ea Period ea Alignment, kapa ho qala ho seta bocha. Ha ALIGN paired CW e kentsoe, lebala la align le behiloe ho 1 ho qala sebaka sa ho tsamaisana le moamoheli ho lekola khokahano ea data litseleng tsohle.

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Lethathamo la 15.

LOKISA Maemo a Tšimo a CW
Hlophisa sebaka
eop sop usr seop

Boleng 1 0 0 0 0

4.1.2.4. CW e se nang letho

Setšoantšo sa 14. Sebopeho sa CW se se nang letho

EMPTY_CYC Kopana le END/START

64+8bits XGMII Interface

QETA

63:56

' hFD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

taolo 7:0

64+8bits XGMII Interface

QALA

63:56

RSVD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16

sop=0 usr=0 amahanya=0 seop=0

15:8

RSVD

7:0

' hFB

taolo 7:0

Lethathamo la 16.

Ha o tlosa tx_avs_valid bakeng sa li-wache tse peli nakong ea ho phatloha, MAC e kenya EMPTY_CYC CW e tsamaisanang le END/START CWs. U ka sebelisa CW ena ha ho se na data e fumanehang bakeng sa phetiso ea nakoana.

Ha o tlosa tx_avs_valid bakeng sa sekhetlo se le seng, IP deassserts tx_avs_valid bakeng sa nako e habeli ea tx_avs_valid deassertion ho hlahisa para ea END/START CWs.

EMPTY_CYC CW Maemo a Tšimo
Hlophisa sebaka
eop

Boleng 0 0

e tsoela pele…

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Field sop usr seop

Boleng 0 0 0

4.1.2.5. CW e sa sebetse

Setšoantšo sa 15. Sebopeho sa CW se sa sebetseng

IDLE CW

63:56

'h07

55:48

'h07

47:40

'h07

data

39:32 31:24

'h07'h07

23:16

'h07

15:8

'h07

7:0

'h07

taolo 7:0

MAC e kenya IDLE CW ha ho se na phetiso. Nakong ena, lets'oao la tx_avs_valid le tlase.
U ka sebelisa IDLE CW ha phetisetso e phatlohileng e phethiloe kapa phetisetso e le boemong bo sa sebetseng.

4.1.2.6. Lentsoe la data

Lentsoe la data ke moputso oa pakete. Li-bits tsa taolo tsa XGMII kaofela li behiloe ho 0 ka sebopeho sa mantsoe a data.

Setšoantšo sa 16. Data Word Format

64+8 bits XGMII Interface

LENTSOE LETSATSI

63:56

data ea basebelisi 7

55:48

data ea basebelisi 6

47:40

data ea basebelisi 5

data

39:32 31:24

Lintlha tsa mosebelisi 4 data ea mosebelisi 3

23:16

data ea basebelisi 2

15:8

data ea basebelisi 1

7:0

data ea basebelisi 0

taolo 7:0

4.1.3. TX CRC
U ka nolofalletsa TX CRC thibela u sebelisa Enable CRC parameter ho IP Parameter Editor. Karolo ena e tšehetsoa ka mekhoa ea Motheo le e Feletseng.

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MAC e eketsa boleng ba CRC ho END CW ka ho tiisa lets'oao la tx_avs_endofpacket. Ka mokhoa oa BASIC, ke ALIGN CW feela e pakiloeng le END CW e nang le sebaka se nepahetseng sa CRC.
TX CRC block block e hokahana le TX Control Word Insertion le TX MII Encode block. Thibelo ea TX CRC e kopanya boleng ba CRC bakeng sa data ea 64-bit ea potoloho e le 'ngoe ho tloha ho START CW ho ea ho END CW.
U ka tiisa lets'oao la crc_error_inject ho senya data ka boomo ka tsela e itseng ho theha liphoso tsa CRC.

4.1.4. TX MII Encoder

TX MII encoder e sebetsana le phetisetso ea pakete ho tloha ho MAC ho ea ho TX PCS.

Setšoantšo se latelang se bontša mokhoa oa data ka bese ea 8-bit MII ka mokhoa oa ho feto-fetoha oa PAM4. START le END CW li hlaha hang litseleng tse ling le tse ling tse peli tsa MII.

Setšoantšo sa 17. PAM4 Modulation Mode MII Data Pattern Pattern

CYCLE 1

CYCLE 2

CYCLE 3

CYCLE 4

CYCLE 5

SOP_CW

DATA_1

DATA_9 DATA_17

IDLE

DATA_DUMMY SOP_CW
DATA_DUMMY

DATA_2 DATA_3 DATA_4

DATA_10 DATA_11 DATA_12

DATA_18 DATA_19 DATA_20

EOP_CW IDLE
EOP_CW

SOP_CW

DATA_5 DATA_13 DATA_21

IDLE

DATA_DUMMY DATA_6 DATA_14 DATA_22 EOP_CW

SOP_CW DATA_DUMMY

DATA_7 DATA_8

DATA_15 DATA_16

DATA_23 DATA_24

IDLE EOP_CW

Setšoantšo se latelang se bonts'a mokhoa oa data ho bese ea 8-bit MII ka mokhoa oa modulation oa NRZ. START le END CW li hlaha litseleng tsohle tsa MII.

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Setšoantšo sa 18. NRZ Modulation Mode MII Data Pattern

CYCLE 1

CYCLE 2

CYCLE 3

SOP_CW

DATA_1

DATA_9

SOP_CW

DATA_2 DATA_10

SOP_CW SOP_CW

DATA_3 DATA_4

DATA_11 DATA_12

SOP_CW

DATA_5 DATA_13

SOP_CW

DATA_6 DATA_14

SOP_CW

DATA_7 DATA_15

SOP_CW

DATA_8 DATA_16

CYCLE 4 DATA_17 DATA_18 DATA_19 DATA_20 DATA_21 DATA_22 DATA_23 DATA_24

CYCLE 5 EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW

4.1.5. TX PCS le PMA
F-Tile Serial Lite IV Intel FPGA IP e hlophisa transceiver ea F-tile ho mokhoa oa Ethernet PCS.

4.2. Lethathamo la lintlha tsa RX
RX datapath e na le likarolo tse latelang: · PMA block · PCS block · MII decoder · CRC · Deskew block · Laola thibelo ea ho tlosa Lentsoe.

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Setšoantšo sa 19. RX Datapath

Ho logic ea basebelisi Avalon Streaming Interface
RX MAC
Laola ho Tlosa Lentsoe
Deskew

CRC

Sesebelisoa sa MII

MII Interface Custom PCS
PCS le PMA

RX Serial Interface Ho tsoa ho lisebelisoa tse ling tsa FPGA
4.2.1. RX PCS le PMA
F-Tile Serial Lite IV Intel FPGA IP e lokisa transceiver ea F-tile ho mokhoa oa Ethernet PCS.
4.2.2. RX MII Decoder
Sebaka sena se supa hore na data e kenang e na le mantsoe a taolo le matšoao a ho tsamaisana. The RX MII decoder e hlahisa data ka sebopeho sa 1-bit e sebetsang, 1-bit marker indicator, 1bit control indicator, le 64-bit data lane ka 'ngoe.
4.2.3. RX CRC
U ka nolofalletsa TX CRC thibela u sebelisa Enable CRC parameter ho IP Parameter Editor. Karolo ena e tšehetsoa ka mekhoa ea Motheo le e Feletseng. RX CRC block block e hokahana le RX Control Word Removal le RX MII Decoder blocks. IP e fana ka letšoao la rx_crc_error ha phoso ea CRC e etsahala.

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IP e hlakola rx_crc_error ha ho phatloha ho hong le ho hong ho hocha. Ke tlhahiso ho logic ea mosebelisi bakeng sa ho sebetsana le liphoso tsa mosebelisi.
4.2.4. RX Deskew
The RX deskew block e lemoha matšoao a ho tsamaisana bakeng sa tsela e 'ngoe le e' ngoe ebe e hokahanya data pele e e romella ho thibela ho tlosoa ha RX CW.
U ka khetha ho lumella setsi sa IP hore se tsamaisane le data bakeng sa lane ka 'ngoe ka bo eona ha phoso ea ho tsamaisana e etsahala ka ho beha parameter ea Enable Auto Alignment ho IP parameter Editor. Haeba o tima tšobotsi ea ho ikamahanya le maemo, IP core e fana ka letšoao la rx_error ho bontša phoso ea ho tsamaisana. U tlameha ho tiisa rx_link_reinit ho qala ts'ebetso ea ho tsamaisana ha tsela ha phoso e etsahala.
Deskew ea RX e lemoha matšoao a ho tsamaisana ho latela mochini oa mmuso. Setšoantšo se latelang se bonts'a linaha tse ho RX deskew block.

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Setšoantšo sa 20.

RX Deskew Lane Alignment State Machine e nang le Auto Alignment e Nobled Flow Chart
Qala

IDLE

Khutlisa = 1 e, che

Li-PC tsohle

che

litselana li lokile?

ho joalo

LETELA

Matšoao ohle a sync No
e fumanwe?
ho joalo
TLALI

che
ee, Timeout?

ho joalo
E lahlehetsoe ke ho tsamaisana?
ha ho Pheletso

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Setšoantšo sa 21.

RX Deskew Lane Alignment State Machine e nang le Auto Alignment Disabled Flow Flow Chate
Qala

IDLE

Khutlisa = 1 e, che

Li-PC tsohle

che

litselana li lokile?

ho joalo

ho joalo
rx_link_reinit =1
ha ho PHOSO

che e, Timeout?

LETELA
che Lits'oants'o tsohle tsa sync
e fumanwe?
ee HLOKOMELA

ho joalo
E lahlehetsoe ke ho tsamaisana?
che
QETA
1. Ts'ebetso ea ho tsamaisana e qala ka boemo ba IDLE. Boloko bo fallela sebakeng sa WAIT ha litsela tsohle tsa PCS li se li lokile 'me rx_link_reinit e tlositsoe.
2. Boemong ba WAIT, block e hlahloba matšoao ohle a fumanoeng a tiisitsoe ka har'a potoloho e tšoanang. Haeba boemo bona e le 'nete, boloko e ea sebakeng sa ALIGNED.
3. Ha boloko bo le boemong ba TSOHLE, e bontša hore litselana li hlophisitsoe. Boemong bona, block e ntse e tsoela pele ho beha leihlo tselana ea ho tsamaisana le ho hlahloba hore na matšoao ohle a teng nakong ea potoloho e tšoanang. Haeba bonyane lesupa le le leng le le sieo potolohong e ts'oanang 'me parameter ea Enable Auto Alignment e setiloe, block e ea ho

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Naha ea IDLE ho qala hape ts'ebetso ea ho hokahanya. Haeba Enable Auto Alignment e sa hlophisoa 'me bonyane lesupa le le leng le le sieo ka nako e ts'oanang, block e ea sebakeng sa ERROR 'me e emetse hore mosebelisi a fane ka lets'oao la rx_link_reinit ho qala ts'ebetso ea ho lokisa tsela.

Setšoantšo sa 22. Tokiso ea Lane e nang le Enable Auto Alignment E nolofalitsoe rx_core_clk

rx_link_up

rx_link_reinit

le_tsohle_matshwao

Naha ea Deskew

ALGNED

IDLE

LETELA

ALGNED

AUTO_ALIGN = 1

Setšoantšo sa 23. Tokiso ea Lane ka Enable Auto Alignment Disabled rx_core_clk

rx_link_up

rx_link_reinit

le_tsohle_matshwao

Naha ea Deskew

ALGNED

PHOSO

IDLE

LETELA

ALGNED

AUTO_ALIGN = 0
4.2.5. Ho tlosoa ha RX CW
Sebaka sena se khetholla li-CW mme se romela data ho logic ea mosebedisi ho sebelisa sebopeho sa Avalon sa ho phallela ka mor'a ho tlosoa ha CWs.
Ha ho se na data e nepahetseng e fumanehang, block ea ho tlosa ea RX CW e hlahisa lets'oao la rx_avs_valid.
Ka mokhoa o FULL, haeba mochine oa mosebedisi o behiloe, thibela sena se tiisa letšoao la rx_is_usr_cmd 'me data ea potoloho ea oache ea pele e sebelisoa e le tlhahisoleseding kapa taelo e hlalositsoeng ke mosebedisi.
Ha rx_avs_ready deassserts le rx_avs_valid asserts, block ea ho tlosa ea RX CW e hlahisa boemo ba phoso mohopolong oa mosebelisi.
Matshwao a phallang a Avalon a amanang le boloko bona a tjena: · rx_avs_startofpacket · rx_avs_endofpacket · rx_avs_channel · rx_avs_empty · rx_avs_data

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· rx_avs_valid
· rx_num_valid_bytes_eob
· rx_is_usr_cmd (e fumaneha feela ka Mokhoa o felletseng)
4.3. F-Tile Serial Lite IV Intel FPGA IP Clock Architecture
F-Tile Serial Lite IV Intel FPGA IP e na le lisebelisoa tsa lioache tse 'ne tse hlahisang lioache ho li-blocks tse fapaneng: · Transceiver reference clock (xcvr_ref_clk)
li-chips kapa li-oscillator tse hlahisang lioache tsa TX MAC, RX MAC, le TX le RX custom PCS blocks. Sheba li-Parameters bakeng sa mefuta e tšehetsoeng ea maqhubu. · TX core clock (tx_core_clk)-Oache ena e nkiloe ho transceiver PLL e sebelisetsoa TX MAC. Oache ena hape ke oache e hlahisoang ho tsoa ho transceiver ea F-tile ho hokela mohopolong oa mosebelisi oa TX. · RX core clock (rx_core_clk) -Oache ena e tsoa ho transceiver PLL e sebelisetsoa RX deskew FIFO le RX MAC. Oache ena hape ke oache e tsoang ho transceiver ea F-tile ho hokela mohopolong oa mosebelisi oa RX. · Oache bakeng sa sebopeho sa transceiver reconfiguration (reconfig_clk) -oache e kenang ho tsoa lipotolohong tsa oache tse kantle kapa li-oscillator tse hlahisang lioache tsa sebopeho sa F-tile transceiver reconfiguration ho TX le RX datapaths. Maqhubu a oache ke 100 ho isa ho 162 MHz.
Setšoantšo se latelang sa block se bontša F-Tile Serial Lite IV Intel FPGA IP oache libaka le likhokahano ka har'a IP.

F-Tile Serial Lite IV Intel® FPGA IP User Guide 36

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Setšoantšo sa 24.

F-Tile Serial Lite IV Intel FPGA IP Clock Architecture

Oscillator

FPGA1
F-Tile Serial Lite IV Intel FPGA IP Transceiver Reconfiguration Interface Clock
(reconfig_clk)

tx_core_clkout (hokela ho mohopolo oa mosebelisi)

tx_core_clk= clk_pll_div64[mid_ch]

FPGA2

F-Tile Serial Lite IV Intel FPGA IP

Transceiver Reconfiguration Interface Clock

(reconfig_clk)

Oscillator

rx_core_clk= clk_pll_div64[mid_ch]

rx_core_clkout (hokela ho mohopolo oa mosebelisi)

clk_pll_div64[mid_ch] clk_pll_div64[n-1:0]

Avalon Streaming Interface TX Data
TX MAC

serial_link[n-1:0]

Deskew

FIFO

Avalon Streaming Interface RX Data RX MAC

Lintlha tsa Avalon Streaming Interface RX
RX MAC

Deskew FIFO

rx_core_clkout (hokela ho mohopolo oa mosebelisi)

rx_core_clk= clk_pll_div64[mid_ch]

Li-PC tsa tloaelo

serial_link[n-1:0]

TX MAC

Avalon Streaming Interface TX Data

tx_core_clk= clk_pll_div64[mid_ch]

tx_core_clkout (hokela ho mohopolo oa mosebelisi)

Transceiver Ref Clock (xcvr_ref_clk)
Transceiver Ref Clock (xcvr_ref_clk)

Oscillator*

Tšōmo

Sesebelisoa sa FPGA
TX core clock domain
RX core clock domain
Sesebediswa sa kantle Matshwao a data

4.4. Seta bocha 'me u qale ho hokahanya
MAC, F-tile Hard IP, le li-blocks tsa ho hlophisa bocha li na le matšoao a fapaneng a ho seta bocha: · TX le RX MAC blocks li sebelisa tx_core_rst_n le rx_core_rst_n matšoao a reset. · tx_pcs_fec_phy_reset_n le rx_pcs_fec_phy_reset_n reset signals drive
setaolo se bonolo sa reset ho seta botjha F-tile Hard IP. · Reconfiguration block e sebelisa lets'oao la reconfig_reset reset.

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Setšoantšo sa 25. Reset Architecture
Avalon Streaming Interface TX Data
MAC
Avalon Streaming SYNC Interface RX Data

FPGA F-tile Serial Lite IV Intel FPGA IP

tx_mii rx_mii
phy_ehip_ready phy_rx_pcs_ready

F-tile IP e thata

TX Serial Data RX Serial Data

tx_core_rstn rx_core_rstn tx_pcs_fec_phy_reset_n rx_pcs_fec_phy_reset_n reconfig_reset

Seta lintlha hape
Tlhahisoleseding e Amanang · Hlakola Tataiso leqepheng la 51 · F-Tile Serial Lite IV Intel FPGA IP Design Example Bukana ea Mosebelisi
4.4.1. TX Reset le Tatelano ea ho Qala
Tatelano ya ho seta botjha ya TX bakeng sa F-Tile Serial Lite IV Intel FPGA IP e tjena: 1. Assert tx_pcs_fec_phy_reset_n, tx_core_rst_n, and reconfig_reset
ka nako e ts'oanang ho seta botjha F-tile hard IP, MAC, le li-block tsa tlhophiso. Lokolla tx_pcs_fec_phy_reset_n le reconfiguration reset ka mor'a ho emela tx_reset_ack ho etsa bonnete ba hore li-blocks li tsosolositsoe hantle. 2. IP joale e tiisa hore phy_tx_lanes_stable, tx_pll_locked, le phy_ehip_ready matšoao ka mor'a hore tx_pcs_fec_phy_reset_n reset e lokolloe, ho bontša hore TX PHY e se e loketse ho fetisoa. 3. Li-dessert tsa tx_core_rst_n ka mor'a hore letšoao la phy_ehip_ready le phahame. 4. IP e qala ho fetisetsa litlhaku tsa IDLE ho sebopeho sa MII hang ha MAC e felile. Ha ho na tlhoko ea ho tsamaisana le TX lane le skewing hobane litselana tsohle li sebelisa oache e le 'ngoe. 5. Ha o ntse o fetisetsa litlhaku tsa IDLE, MAC e tiisa letšoao la tx_link_up. 6. Joale MAC e qala ho fetisa ALIGN e tsamaisanang le START/END kapa END/START CW ka nako e itseng ho qala mokhoa oa ho lokisa tsela ea moamoheli ea hoketsoeng.

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Setšoantšo sa 26.

TX Reset le ho Qala Nako Sets'oants'o sa Nako
reconfig_sl_clk

reconfig_clk

tx_core_rst_n

tx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

tx_reset_ack

tx_pll _ notletsoe

phy_tx_lanes_stable

phy_ehip_ready

tx_li nk_up

7
5 6 8

4.4.2. RX Reset le Tatelano ea ho Qala
Tatelano ea reset ea RX bakeng sa F-Tile Serial Lite IV Intel FPGA IP e tjena:
1. Assert rx_pcs_fec_phy_reset_n, rx_core_rst_n, le reconfig_reset ka nako e le 'ngoe ho tsosolosa F-tile hard IP, MAC, le li-blocks tsa ho tsosolosa. Release rx_pcs_fec_phy_reset_n le reconfiguration reset ka mor'a ho emela rx_reset_ack ho etsa bonnete ba hore li-blocks li hlophisitsoe hantle.
2. IP ebe e tiisa phy_rx_pcs_ready signal ka mor'a hore tloaelo ea PCS e lokolloe, ho bontša hore RX PHY e se e loketse ho fetisoa.
3. Li-dessert tsa rx_core_rst_n ka mor'a hore letšoao la phy_rx_pcs_ready le phahame.
4. IP e qala mokhoa oa ho lokisa tsela ka mor'a hore ho seta bocha RX MAC e lokolloe le ha e fumana ALIGN e kopantsoeng le START/END kapa END/START CW.
5. Sebaka sa RX deskew block se tiisa hore rx_link_up signal hang ha ho lokisoa ha litsela tsohle ho phethiloe.
6. IP ebe e tiisa rx_link_up letšoao ho logic ea mosebedisi ho bontša hore sehokelo sa RX se se se loketse ho qala kamohelo ea data.

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Setšoantšo sa 27. Sets'oants'o sa RX le ho Qala Nako ea ho Qala
reconfig_sl_clk

reconfig_clk

rx_core_rst_n

rx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

rx_reset_ack

rx_cdr_lock

rx_block_lock

rx_pcs_ready

rx_link_up

3 3 3 2

4 5 5

6 7

4.5. Khokahano Rate le Bandwidth Effective Calculation

Palo ea katleho ea F-Tile Serial Lite IV Intel FPGA IP bandwidth e tjena ka tlase:

Bandwidth e sebetsang hantle = raw_rate * 64/66 * (burst_size – burst_size_ovhd)/burst_size * [align_marker_period / (align_marker_period + align_marker_width)] * [(srl4_align_period – 2) / srl4_align_period

Lethathamo la 17. Bandwidth Effective Variables Tlhaloso

E fetohang

Tlhaloso

raw_rate burst_size

Ena ke sekhahla sa biti se fihletsoeng ke sehokelo sa serial. raw_rate = SERVES bophara * transceiver clock frequency Example: raw_rate = 64 * 402.812500 Gbps = 25.78 Gbps
Boleng ba boholo ba ho phatloha. Ho bala karolelano ea katleho ea bandwidth, sebelisa boleng bo tloaelehileng ba boholo ba ho phatloha. Bakeng sa sekhahla se phahameng, sebelisa boholo ba boholo ba ho phatloha.

burst_size_ovhd

Thepa ea boholo bo phatlohileng.
Ha e le ka botlalo, boleng ba burst_size_ovhd bo bua ka START le END li-CW tse palaneng.
Maemong a Mantlha, ha ho burst_size_ovhd hobane ha ho START le END li-CW tse palaneng.

lekanya_letshwao_nako

Boleng ba nako eo ho kengoang lesupa la ho tsamaisana. Boleng ke potoloho ea oache ea 81920 bakeng sa ho bokella le 1280 bakeng sa papiso e potlakileng. Boleng bona bo fumanoa ho PCS hard logic.

align_marker_width srl4_align_period

Palo ea lipotoloho tsa oache moo lesupa le nepahetseng le behiloeng holimo.
Palo ea lipotoloho tsa oache lipakeng tsa matšoao a mabeli a tolamiso. U ka beha boleng bona u sebelisa parameter ea nako ea Alignment ho IP Parameter Editor.

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Lipalo tsa sekhahla sa lihokelo li tjena ka tlase: Sekhahla se sebetsang = katleho ea bandwidth * raw_rate O ka fumana boholo ba maqhubu a oache ea mosebelisi ka equation e latelang. Palo e phahameng ka ho fetisisa ea palo ea lioache ea mosebedisi e nka ho phalla ha data ho tsoelang pele 'me ha ho na potoloho ea IDLE e hlahang mohopolong oa mosebedisi. Sekhahla sena se bohlokoa ha ho etsoa moralo oa mosebelisi FIFO ho qoba ho tlala ha FIFO. Boholo ba maqhubu a oache = sekhahla se sebetsang / 64

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5. di-parameter

Letlapa la 18. F-Tile Serial Lite IV Intel FPGA IP Parameter Tlhaloso

Paramethara

Boleng

Ea kamehla

Tlhaloso

Kakaretso Design Options

PMA modulation mofuta

· PAM4 · NRZ

PAM4

Khetha mokhoa oa ho feto-fetoha oa PCS.

Mofuta oa PMA

· FHT · FGT

FGT

E khetha mofuta oa transceiver.

Lebelo la lintlha tsa PMA

· Bakeng sa PAM4 mode:
- Mofuta oa transceiver oa FGT: 20 Gbps 58 Gbps
- Mofuta oa transceiver oa FHT: 56.1 Gbps, 58 Gbps, 116 Gbps
· Bakeng sa mokhoa oa NRZ:
- Mofuta oa transceiver oa FGT: 10 Gbps 28.05 Gbps
- Mofuta oa transceiver oa FHT: 28.05 Gbps, 58 Gbps

56.1 (FGT/FHT PAM4)
28.05 Gbps (FGT/FHT NRZ)

E totobatsa sekhahla se sebetsang sa data ho tlhahiso ea transceiver e kenyelletsang phetiso le litaba tse ling. Theko e baloa ke IP ka ho pota-pota sebaka se le 1 sa decimal ho yuniti ea Gbps.

Mokhoa oa PMA

· Duplex · Tx · Rx

Duplex

Bakeng sa mofuta oa transceiver oa FHT, tataiso e tšehetsoeng ke duplex feela. Bakeng sa mofuta oa transceiver oa FGT, tataiso e tšehetsoeng ke Duplex, Tx, le Rx.

Palo ea PMA

· Bakeng sa PAM4 mode:

litselana

- 1 ho isa ho 12

· Bakeng sa mokhoa oa NRZ:

- 1 ho isa ho 16

Khetha palo ea litsela. Bakeng sa moralo o bonolo, palo e tšehelitsoeng ea litselana ke 1.

PLL maqhubu a oache

· Bakeng sa mofuta oa transceiver oa FHT: 156.25 MHz
· Bakeng sa mofuta oa transceiver oa FGT: 27.5 MHz 379.84375 MHz, ho itšetlehile ka sekhahla sa data sa transceiver se khethiloeng.

· Bakeng sa mofuta oa transceiver oa FHT: 156.25 MHz
· Bakeng sa mofuta oa transceiver oa FGT: 165 MHz

E totobatsa khafetsa oache ea litšupiso ea transceiver.

Sistimi ea PLL

—

sesupa-tshupanako

makhetlo a mangata

170 MHz

E fumaneha feela bakeng sa mofuta oa transceiver oa FHT. E totobatsa oache ea referense ea System PLL 'me e tla sebelisoa e le kenyelletso ea F-Tile Reference le System PLL Clocks Intel FPGA IP ho hlahisa oache ea System PLL.

Khafetsa ea sistimi ea PLL
Nako ea ho tsamaisana

— 128 65536

Numella RS-FEC

Thusa

876.5625 MHz 128 Ntsha

E totobatsa maqhubu a oache ea System PLL.
E totobatsa nako ea lesupa la ho tsamaisana. Theko e tlameha ho ba x2. Bulela ho nolofalletsa karolo ea RS-FEC.
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Paramethara

Boleng

Ea kamehla

Tlhaloso

Thibela

Bakeng sa PAM4 PCS modulation mode, RS-FEC e lula e sebetsa.

Mosebelisi

Mokhoa oa ho phallela

· FALL · MOTHEO

E tletse

Khetha phallo ea data bakeng sa IP.

E feletseng: Mokhoa ona o romela potoloho ea ho qala-pakete le qetello ea pakete ka har'a foreimi.

Motheo: Ena ke mokhoa o hloekileng oa ho phallela moo data e romelloang ntle le ho qala-pakete, e se nang letho, le ho qetela-ea-pakete ho eketsa bandwidth.

Lumella CRC

Numella ho thibela

Thibela

Bulela ho lumella ho lemoha le ho lokisa liphoso tsa CRC.

Dumella ho tsamaisana ha otho

Numella ho thibela

Thibela

Bulela ho kenya tšebetsong mokhoa oa ho itlhophisa oa tsela.

Numella sebaka sa ho lokisa bothata

Numella ho thibela

Thibela

Ha ON, F-Tile Serial Lite IV Intel FPGA IP e kenyelletsa Endpoint e kentsoeng ea Debug e hokahanang ka hare le sebopeho sa mohopolo oa Avalon. IP e ka etsa liteko tse itseng le ho lokisa liphoso ka JTAG ho sebelisa System Console. Boleng ba kamehla bo Koetsoe.

Simplex Merging (Sebopeho sena sa paramethara se fumaneha feela ha u khetha moralo oa FGT o habeli.)

RSFEC e nolofalitsoe ho Serial Lite IV Simplex IP e behiloeng seteisheneng se tšoanang sa FGT.

Numella ho thibela

Thibela

Bulela khetho ena haeba o hloka motsoako oa tlhophiso o nang le RS-FEC e lumelletsoeng le e holofalitsoeng bakeng sa F-Tile Serial Lite IV Intel FPGA IP ka moralo o habeli o bonolo bakeng sa mokhoa oa transceiver oa NRZ, moo TX le RX li behiloeng ho FGT e tšoanang. likanale.

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6. F-Tile Serial Lite IV Intel FPGA IP Interface Signals

6.1. Lipontšo Tsa Oache

Lethathamo la 19. Lipontšo tsa Oache

Lebitso

Tsela e Bophara

Tlhaloso

tx_core_clkout

Oache ea mantlha ea Output TX bakeng sa sebopeho sa TX se tloaelehileng sa PCS, TX MAC le lintlha tsa mosebelisi ho

mokhoa oa TX.

Oache ena e hlahisoa ho tsoa ho "PCS" block.

rx_core_clkout

Oache ea mantlha ea RX bakeng sa sebopeho sa RX se tloaelehileng sa PCS, RX deskew FIFO, RX MAC

le lintlha tsa mosebelisi ho datapath ea RX.

Oache ena e hlahisoa ho tsoa ho "PCS" block.

xcvr_ref_clk
reconfig_clk reconfig_sl_clk

Kena oache ea litšupiso ea Transceiver.

Ha mofuta oa transceiver o setetsoe ho FGT, hokela oache ena ho lets'oao la tlhahiso (out_refclk_fgt_0) ea F-Tile Reference le System PLL Clocks Intel FPGA IP. Ha mofuta oa transceiver o setetsoe ho FHT, hokela

oache ena ho letšoao la tlhahiso (out_fht_cmmpll_clk_0) ea F-Tile Reference le System PLL Clocks Intel FPGA IP.

Sheba li-Parameters bakeng sa mefuta e tšehetsoeng ea maqhubu.

Oache e Kenyang bakeng sa sebopeho sa transceiver bocha.

Maqhubu a oache ke 100 ho isa ho 162 MHz.

Hokela lets'oao lena la oache ho li-circuits tsa oache tse kantle kapa li-oscillator.

Oache e Kenyang bakeng sa sebopeho sa transceiver bocha.

Maqhubu a oache ke 100 ho isa ho 162 MHz.

Hokela lets'oao lena la oache ho li-circuits tsa oache tse kantle kapa li-oscillator.

out_systempll_clk_ 1

Kenyeletso

Sisteme PLL oache.
Hokela oache ena ho lets'oao la tlhahiso (out_systempll_clk_0) ea F-Tile Reference le System PLL Clocks Intel FPGA IP.

Lintlha tse amanang le tsona leqepheng la 42

6.2. Seta Lipontšo bocha

Letlapa la 20. Hlahisa Lipontšo

Lebitso

Tsela e Bophara

tx_core_rst_n

Kenyeletso

Clock Domain Asynchronous

rx_core_rst_n

Kenyeletso

Asynchronous

tx_pcs_fec_phy_reset_n 1

Kenyeletso

Asynchronous

Tlhaloso

Lets'oao la ho seta botjha e sebetsang-tlase. E tsosolosa F-Tile Serial Lite IV TX MAC.

Lets'oao la ho seta botjha e sebetsang-tlase. E tsosolosa F-Tile Serial Lite IV RX MAC.

Lets'oao la ho seta botjha e sebetsang-tlase.

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Lebitso

Width Direction Clock Domain

Tlhaloso

E seta bocha F-Tile Serial Lite IV TX tloaelo PCS.

rx_pcs_fec_phy_reset_n 1

Kenyeletso

Asynchronous

Lets'oao la ho seta botjha e sebetsang-tlase. E seta bocha F-Tile Serial Lite IV RX tloaelo PCS.

reconfig_reset

Kenyeletso

reconfig_clk Letšoao le sebetsang-le phahameng la reset.

E seta botjha "block" ea "mapped" ea Avalon memory-mapped interface.

reconfig_sl_reset

Kenya reconfig_sl_clk Letšoao la ho seta botjha ka mafolofolo.

E seta botjha "block" ea "mapped" ea Avalon memory-mapped interface.

6.3. Lipontšo tsa MAC

Lethathamo la 21.

Lipontšo tsa TX MAC
Tafoleng ena, N e emela palo ea litselana tse behiloeng ho IP parameter editor.

Lebitso

Bophara

Direction Clock Domain

Tlhaloso

tx_avs_ready

Output tx_core_clkout Letshwao la phallo la Avalon.

Ha e tiisa, e bontša hore TX MAC e se e loketse ho amohela data.

tx_avs_data

· (64*N)*2 (PAM4 mode)
· 64*N (NRZ mode)

Kenyeletso

tx_core_clkout Letšoao la ho phallela la Avalon. Lintlha tsa TX.

tx_avs_channel

Kenya tx_core_clkout lets'oao la ho phallela la Avalon.

Nomoro ea mocha bakeng sa data e fetisoang nakong ea ha joale.

Letšoao lena ha le fumanehe ka mokhoa oa Motheo.

tx_avs_valid

Kenya tx_core_clkout lets'oao la ho phallela la Avalon.

Ha e tiisetsoa, e bontša hore lets'oao la data la TX le nepahetse.

tx_avs_startofpacket

Kenya tx_core_clkout lets'oao la ho phallela la Avalon.

Ha e tiisetsoa, e bontša ho qala ha pakete ea data ea TX.

Iketsetse sekhechana sa oache e le 'ngoe feela bakeng sa pakete ka 'ngoe.

Letšoao lena ha le fumanehe ka mokhoa oa Motheo.

tx_avs_endofpacket

Kenya tx_core_clkout lets'oao la ho phallela la Avalon.

Ha e tiisitsoe, e bontša pheletso ea pakete ea data ea TX.

Iketsetse sekhechana sa oache e le 'ngoe feela bakeng sa pakete ka 'ngoe.

Letšoao lena ha le fumanehe ka mokhoa oa Motheo.

tx_avs_letho

Kenya tx_core_clkout lets'oao la ho phallela la Avalon.

E bontša palo ea mantsoe a sa sebetseng nakong ea ho phatloha ho hoholo ha data ea TX.

Letšoao lena ha le fumanehe ka mokhoa oa Motheo.

tx_num_valid_bytes_eob

Kenyeletso

tx_core_clkout

E bontša palo ea li-byte tse nepahetseng lentsoeng la ho qetela la ho phatloha ha ho qetela. Letšoao lena ha le fumanehe ka mokhoa oa Motheo.
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Lebitso tx_is_usr_cmd
tx_link_up tx_link_reinit
crc_error_inject tx_error

Ka bophara 1
1 1
N 5

Direction Clock Domain

Tlhaloso

Kenyeletso

tx_core_clkout

Ha ho netefatsoa, lets'oao lena le qala potoloho ea tlhaiso-leseling e hlalositsoeng ke mosebelisi.
Kenya lets'oao lena ka nako e ts'oanang le polelo ea tx_startofpacket.
Letšoao lena ha le fumanehe ka mokhoa oa Motheo.

Output tx_core_clkout Ha e tiisitsoe, e bontša hore khokahanyo ea data ea TX e se e loketse phetiso ea data.

Sephetho

tx_core_clkout

Ha ho tiisoa, lets'oao lena le qala ho hokahanya litselana hape.
Kenya lets'oao lena bakeng sa oache e le 'ngoe ho etsa hore MAC e romele ALIGN CW.

Kenyeletso

tx_core_clkout Ha e tiisetsoa, MAC e kenya phoso ea CRC32 litseleng tse khethiloeng.

Output tx_core_clkout Ha e sebelisoe.

Setšoantšo se latelang sa nako se bontša example ea phetiso ea data ea TX ea mantsoe a 10 ho tsoa mohopolong oa basebelisi ho pholletsa le litselana tse 10 tsa TX.

Setšoantšo sa 28.

Setšoantšo sa Nako ea Phetiso ea Lintlha tsa TX
tx_core_clkout

tx_avs_valid

tx_avs_ready

tx_avs_startofpackets

tx_avs_endofpackets

tx_avs_data

0,1..,19 10,11…19 …… N-10..

0,1,2,…, 9

… N-10..

Tsela ea 0

……………

STRT 0 10

N-10 QETELA STRT 0

Tsela ea 1

……………

STRT 1 11

N-9 QETELA STRT 1

N-10 QETELA IDLE IDLE N-9 FEELA IDLE IDLE

Tsela ea 9

……………

STRT 9 19

N-1 QETELA STRT 9

N-1 QETELA SEBELE

Lethathamo la 22.

Lipontšo tsa RX MAC
Tafoleng ena, N e emela palo ea litselana tse behiloeng ho IP parameter editor.

Lebitso

Bophara

Direction Clock Domain

Tlhaloso

rx_avs_ready

Kenya rx_core_clkout Letšoao la ho phallela la Avalon.

Ha e tiisetsoa, e bontša hore mohopolo oa mosebelisi o ikemiselitse ho amohela data.

rx_avs_data

(64*N)*2 (PAM4 mode)
64*N (mokgwa wa NRZ)

Sephetho

rx_core_clkout Letšoao la ho phallela la Avalon. Lintlha tsa RX.

rx_avs_channel

Output rx_core_clkout Letshwao la phallo la Avalon.

Nomoro ea mocha bakeng sa data

e amohetsoeng ka potoloho ea hona joale.

Letšoao lena ha le fumanehe ka mokhoa oa Motheo.

rx_avs_valid

Output rx_core_clkout Letshwao la phallo la Avalon.

e tsoela pele…

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Lebitso

Bophara

Direction Clock Domain

Tlhaloso

Ha e tiisetsoa, e bontša hore lets'oao la data la RX le nepahetse.

rx_avs_startofpacket

Output rx_core_clkout Letshwao la phallo la Avalon.

Ha e tiisetsoa, e bontša ho qala ha pakete ea data ea RX.

Iketsetse sekhechana sa oache e le 'ngoe feela bakeng sa pakete ka 'ngoe.

Letšoao lena ha le fumanehe ka mokhoa oa Motheo.

rx_avs_endofpacket

Output rx_core_clkout Letshwao la phallo la Avalon.

Ha e tiisitsoe, e bontša pheletso ea pakete ea data ea RX.

Iketsetse sekhechana sa oache e le 'ngoe feela bakeng sa pakete ka 'ngoe.

Letšoao lena ha le fumanehe ka mokhoa oa Motheo.

rx_avs_letho

Output rx_core_clkout Letshwao la phallo la Avalon.

E bontša palo ea mantsoe a sa sebetseng nakong ea ho phatloha ho hoholo ha data ea RX.

Letšoao lena ha le fumanehe ka mokhoa oa Motheo.

rx_num_valid_bytes_eob

Sephetho

rx_core_clkout E bontša palo ea li-byte tse nepahetseng lentsoeng la ho qetela la ho phatloha ha ho qetela.
Letšoao lena ha le fumanehe ka mokhoa oa Motheo.

rx_is_usr_cmd

Output rx_core_clkout Ha ho boleloa, lets'oao lena le qala mosebelisi-

sedikadikwe sa tlhahisoleseding.

Kenya lets'oao lena ka nako e ts'oanang le polelo ea tx_startofpacket.

Letšoao lena ha le fumanehe ka mokhoa oa Motheo.

rx_link_up

Output rx_core_clkout Ha e tiisitsoe, e bontša sehokelo sa data sa RX

e loketse ho amohela data.

rx_link_reinit

Input rx_core_clkout Ha e tiisetsoa, lets'oao lena le qala litselana

peakanyo bocha.

Haeba o tima Enable Auto Alignment, etsa lets'oao lena bakeng sa saekele e le 'ngoe ho etsa hore MAC e lokise litselana hape. Haeba Enable Auto Alignment e setiloe, MAC e lokisa litsela ka bo eona.

Se ke oa fana ka lets'oao lena ha Enable Auto Alignment e setiloe.

rx_phoso

(N*2*2)+3 (PAM4 mode)
(N*2)*3 (Mokhoa oa NRZ)

Sephetho

rx_core_clkout

Ha e tiisitsoe, e bontša hore maemo a phoso a etsahala ho datapath ea RX.
· [(N*2+2):N+3] = E bontša phoso ea PCS bakeng sa tsela e itseng.
· [N+2] = E bontsha phoso ya tolamiso. Ntlafatsa hape ho tsamaisana ha tsela haeba karoloana ena e tiisitsoe.
· [N+1]= E bontša hore data e fetisetsoa ho mosebelisi ha logic ea mosebelisi e sa itokisetsa.
· [N] = E bontša tahlehelo ea ho tsamaisana.
· [(N-1):0] = E bontša hore data e na le phoso ea CRC.

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6.4. Transceiver Reconfiguration Signals

Lethathamo la 23.

PCS Reconfiguration Lipontšo
Tafoleng ena, N e emela palo ea litselana tse behiloeng ho IP parameter editor.

Lebitso

Bophara

Direction Clock Domain

Tlhaloso

reconfig_sl_read

Kenya taelo ea ho bala reconfig_sl_ PCS

clk

lipontšo.

reconfig_sl_write

Kenya reconfig_sl_ PCS reconfiguration ngola

clk

matshwao a taelo.

reconfig_sl_aterese

14 likotoana + clogb2N

Kenyeletso

reconfig_sl_ clk

E totobatsa aterese ea khokahanyo ea memori ea PCS ea Avalon tseleng e khethiloeng.
Tsela e 'ngoe le e' ngoe e na le li-bits tse 14 'me likotoana tse ka holimo li bua ka lane offset.
Example, bakeng sa moralo oa 4-lane NRZ/PAM4, e nang le reconfig_sl_address[13:0] e buang ka boleng ba aterese:
· reconfig_sl_address[15:1 4] beha ho 00 = aterese ea lane 0.
· reconfig_sl_address[15:1 4] beha ho 01 = aterese ea lane 1.
· reconfig_sl_address[15:1 4] beha ho 10 = aterese ea lane 2.
· reconfig_sl_address[15:1 4] beha ho 11 = aterese ea lane 3.

reconfig_sl_readdata

Output reconfig_sl_ E totobatsa lintlha tsa ntlafatso ea PCS

clk

ho baloa ke potoloho e itokisitseng ka a

tsela e khethiloeng.

reconfig_sl_waitrequest

Output reconfig_sl_ E emela tokiso ea PCS

clk

Sehokelo sa Avalon memory-mapped

lets'oao le thibang tseleng e khethiloeng.

reconfig_sl_writedata

Input reconfig_sl_ E Hlalosa lintlha tsa ntlafatso ea PCS

clk

ho ngoloa saekeleng ea ho ngola ka a

tsela e khethiloeng.

reconfig_sl_readdata_vali

Sephetho

reconfig_sl_ E hlakisa tokiso ea PCS hape

clk

data e fumanoeng e sebetsa sebakeng se khethiloeng

lane.

Lethathamo la 24.

F-Tile Hard IP Reconfiguration Lipontšo
Tafoleng ena, N e emela palo ea litselana tse behiloeng ho IP parameter editor.

Lebitso

Bophara

Direction Clock Domain

Tlhaloso

reconfig_bala

Kenya reconfig_clk PMA reconfiguration bala

matshwao a taelo.

reconfig_write

Kenya reconfig_clk PMA reconfiguration ngola

matshwao a taelo.

reconfig_aterese

18 likotoana + clog2bN

Kenyeletso

reconfig_clk

E totobatsa aterese ea sebopeho sa mohopolo oa PMA Avalon tseleng e khethiloeng.
e tsoela pele…

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Lebitso
reconfig_readdata reconfig_waitrequest reconfig_writedata reconfig_readdatavalid

Bophara
32 1 32 1

Direction Clock Domain

Tlhaloso

Mekhoeng ea bobeli ea PAM4 ad NRZ, tsela e 'ngoe le e' ngoe e na le li-bits tse 18 'me tse setseng tse ka holimo li bua ka tsela ea ho fokotsa tsela.
Example, bakeng sa moralo oa litsela tse 4:
· reconfig_address[19:18] beha ho 00 = aterese ea lane 0.
· reconfig_address[19:18] beha ho 01 = aterese ea lane 1.
· reconfig_address[19:18] beha ho 10 = aterese ea lane 2.
· reconfig_address[19:18] beha ho 11 = aterese ea lane 3.

Sephetho

reconfig_clk E Hlalosa data ea PMA e lokelang ho baloa ka potoloho e itokiselitseng tseleng e khethiloeng.

Sephetho

reconfig_clk E emetse PMA Avalon e kentsoeng mohopolong oa lets'oao la ho emisa tseleng e khethiloeng.

Kenyeletso

reconfig_clk E hlalosa lintlha tsa PMA tse lokelang ho ngoloa ka potoloho ea ho ngola ka tsela e khethiloeng.

Sephetho

reconfig_clk E Hlalosa hore data ea PMA e amohetsoeng e nepahetse ka tsela e khethiloeng.

6.5. Lipontšo tsa PMA

Lethathamo la 25.

Lipontšo tsa PMA
Tafoleng ena, N e emela palo ea litselana tse behiloeng ho IP parameter editor.

Lebitso

Bophara

Direction Clock Domain

Tlhaloso

phy_tx_lanes_stable

N*2 (PAM4 mode)
N (Mokhoa oa NRZ)

Sephetho

Asynchronous Ha e tiisitsoe, e bontša hore datapath ea TX e se e loketse ho romela data.

tx_pll_ notletsoe

N*2 (PAM4 mode)
N (Mokhoa oa NRZ)

Sephetho

Asynchronous Ha e tiisitsoe, e bontša hore TX PLL e fihletse boemo ba senotlolo.

phy_ehip_ready

N*2 (PAM4 mode)
N (Mokhoa oa NRZ)

Sephetho

Asynchronous

Ha e tiisetsoa, e bontša hore PCS e tloaelehileng e qetile ho qala ka hare 'me e loketse ho fetisoa.
Letšoao lena le tiisa ka mor'a hore tx_pcs_fec_phy_reset_n le tx_pcs_fec_phy_reset_nare e hlajoe.

tx_serial_data

Output TX serial clock TX serial pins.

rx_serial_data

Kenya RX serial clock RX serial pins.

phy_rx_block_lock

N*2 (PAM4 mode)
N (Mokhoa oa NRZ)

Sephetho

Asynchronous Ha e tiisitsoe, e bontša hore tokiso ea 66b block e phethiloe bakeng sa litselana.

rx_cdr_lock

N*2 (PAM4 mode)

Sephetho

Asynchronous

Ha e tiisitsoe, e bontša hore lioache tse fumanoeng li notletsoe data.
e tsoela pele…

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Bolela phy_rx_pcs_ready phy_rx_hi_ber

Bophara

Direction Clock Domain

Tlhaloso

N (Mokhoa oa NRZ)

N*2 (PAM4 mode)
N (Mokhoa oa NRZ)

Sephetho

Asynchronous

Ha e tiisetsoa, e bontša hore litselana tsa RX tsa mocha oa Ethernet o tsamaellanang li hokahane ka botlalo 'me li loketse ho amohela data.

N*2 (PAM4 mode)
N (Mokhoa oa NRZ)

Sephetho

Asynchronous

Ha e tiisetsoa, e bontša hore RX PCS ea mocha o lumellanang oa Ethernet o boemong ba HI BER.

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7. Ho theha ka F-Tile Serial Lite IV Intel FPGA IP

7.1. Seta Litaelo bocha
Latela litataiso tsena tsa ho seta bocha ho kenya tšebetsong boemo ba sistimi ea hau bocha.
Kopanya tx_pcs_fec_phy_reset_n le rx_pcs_fec_phy_reset_n matshwao mmoho boemong ba sistimi e le ho seta TX le RX PCS ka nako e le 'ngoe.
· Assert tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, tx_core_rst_n, rx_core_rst_n, le reconfig_reset matšoao ka nako e le 'ngoe. Sheba ho Reset and Link Initialization bakeng sa tlhaiso-leseling e batsi mabapi le ho seta bocha ha IP le tatelano ea ho qala.
· Tšoara tx_pcs_fec_phy_reset_n, le rx_pcs_fec_phy_reset_n matšoao a tlaase, 'me reconfig_reset signal e phahameng' me u emele tx_reset_ack le rx_reset_ack ho tsosolosa F-tile ka thata IP le li-blocks tsa reconfiguration.
· Ho fihlella khokahano e potlakileng lipakeng tsa lisebelisoa tsa FPGA, seta bocha li-IP tse hokahaneng tsa F-Tile Serial Lite IV Intel FPGA ka nako e le 'ngoe. Sheba F-Tile Serial Lite IV Intel FPGA IP Design Example Bukana ea Mosebelisi bakeng sa tlhaiso-leseling mabapi le ho beha leihlo sehokelo sa IP TX le RX u sebelisa bukana ea lisebelisoa.
Lintlha Tse Amanang
· Seta bocha le ho qala khokahano leqepheng la 37
· F-Tile Serial Lite IV Intel FPGA IP Design Example Bukana ea Mosebelisi

7.2. Litaelo tsa ho Sebelisa Liphoso

Tafole e latelang e thathamisa litataiso tsa ho sebetsana le liphoso bakeng sa maemo a phoso a ka hlahang ka moralo oa F-Tile Serial Lite IV Intel FPGA IP.

Lethathamo la 26. Maemo a Phoso le Tataiso ea ho Tšoara

Boemo ba Phoso
Tsela e le 'ngoe kapa ho feta ha e khone ho theha puisano ka mor'a nako e behiloeng.

Tataiso
Kenya ts'ebetsong mokhoa oa ho qeta nako ho tsosolosa sehokelo boemong ba kopo.

Tsela e lahleheloang ke puisano ka mor'a hore puisano e thehoe.
Lane e lahleheloa ke puisano nakong ea ts'ebetso ea deskew.

Sena se ka etsahala kamora kapa nakong ea mekhahlelo ea phetiso ea data. Kenya ts'ebetsong tlhahlobo ea tahlehelo ea lihokelo boemong ba ts'ebeliso ebe o seta sehokelo bocha.
Kenya ts'ebetso ea ho tsosolosa lihokelo bakeng sa tsela e fosahetseng. U tlameha ho netefatsa hore tsela ea boto ha e fete 320 UI.

Tsela ea tahlehelo ka mor'a hore litsela tsohle li lokisoe.

Sena se ka etsahala ka mor'a kapa nakong ea mekhahlelo ea phetiso ea data. Kenya ts'ebetsong mokhoa oa ho lemoha tahlehelo boemong ba kopo ho qala bocha mokhoa oa ho lokisa tsela.

ISO 9001:2015 E Ngolisitsoe

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8. F-Tile Serial Lite IV Intel FPGA IP User Guide Archives

Liphetolelo tsa IP li tšoana le mefuta ea software ea Intel Quartus Prime Design Suite ho fihla ho v19.1. Ho tsoa ho Intel Quartus Prime Design Suite software version 19.2 kapa hamorao, li-cores tsa IP li na le morero o mocha oa phetolelo ea IP.

Haeba mofuta oa IP core o sa thathamisoa, ho sebetsa tataiso ea mosebelisi bakeng sa mofuta o fetileng oa IP.

Intel Quartus Prime Version
21.3

Mofuta oa IP Core 3.0.0

Tataiso ea mosebelisi F-Tile Serial Lite IV Intel® FPGA IP User Guide

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9. Nalane ea Phetoho ea Litokomane bakeng sa F-Tile Serial Lite IV Intel FPGA IP User Guide

Phetolelo ea Tokomane 2022.04.28
2021.11.16 2021.10.22 2021.08.18

Intel Quartus Prime Version
22.1
21.3 21.3 21.2

IP Version 5.0.0
3.0.0 3.0.0 2.0.0

Liphetoho
· Tafole e Nchafalitsoeng: F-Tile Serial Lite IV Intel FPGA IP Features - Tlhaloso e ntlafalitsoeng ea Phetisetso ea Lintlha ka tšehetso e eketsehileng ea FHT transceiver rate: 58G NRZ, 58G PAM4, le 116G PAM4
· Tafole e Nchafalitsoeng: F-Tile Serial Lite IV Intel FPGA IP Parameter Description — E kentsoe paramethara e ncha · Sisteme PLL frequency frequency · Noble debug endpoint — E ntlafalitse boleng ba PMA data rate — Naming e nchafalitsoeng ea parametha hore e tsamaisane le GUI.
· E ntlafalitse tlhaloso ea phetisetso ea data ho Lethathamo: F-Tile Serial Lite IV Intel FPGA IP Features.
· Lebitso la tafole le fetoletsoeng hape ho F-Tile Serial Lite IV Intel FPGA IP Parameter Tlhaloso karolong ea Parameters bakeng sa ho hlaka.
· Tafole e Nchafalitsoeng: Litekanyetso tsa IP: - E kentse paramethara e ncha–RSFEC e lumelletsoeng ho tse ling tsa Serial Lite IV Simplex IP tse behiloeng seteisheneng se tšoanang sa FGT. - E ntlafalitse boleng ba kamehla bakeng sa maqhubu a oache ea referense ea Transceiver.
Tokollo ea pele.

ISO 9001:2015 E Ngolisitsoe

Litokomane / Lisebelisoa

	Intel F Tile Serial Lite IV Intel FPGA IP [pdf] Bukana ea Mosebelisi F Tile Serial Lite IV Intel FPGA IP, F Tile Serial Lite IV, Intel FPGA IP
	Intel F-Tile Serial Lite IV Intel FPGA IP [pdf] Bukana ea Mosebelisi F-Tile Serial Lite IV Intel FPGA IP, Serial Lite IV Intel FPGA IP, Lite IV Intel FPGA IP, IV Intel FPGA IP, FPGA IP, IP

Litšupiso

Bukana ea Mosebelisi

F Tile Serial Lite IV Intel FPGA IP

Litokomane / Lisebelisoa

Litšupiso

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