VISHAY IRFD120 Power MOSFET Owner's Manual

Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The 4 pin DIP package is a low cost machine-insertab le case style which can be stacked in multiple combinations on standard 0.1″ pin centers. The dual drain serves as a thermal link to the mounting surface for power dissipation levels up to 1 W.

ORDERING INFORMATION
Package	HVMDIP
Lead (Pb)-free	IRFD120PbF

ABSOLUTE MAXIMUM RATINGS (T_A = 25 °C, unless otherwise noted)
PARAMETER			SYMBOL	LIMIT	UNIT
Drain-source voltage			VDS	100	V
Gate-source voltage			VGS	± 20
Continuous drain current	V_GS at 10 V	T_A = 25 °C	I_D	1.3	A
		T_A = 100 °C		0.94
Pulsed drain current ^a			IDM	10
Linear derating factor				0.0083	W/°C
Single pulse avalanche energy ^b			EAS	100	mJ
Repetitive avalanche current ^a			IAR	1.3	A
Repetitive avalanche energy ^a			EAR	0.13	mJ
Maximum power dissipation	T_A = 25 °C		P_D	1.3	W
Peak diode recovery dV/dt ^c			dV/dt	5.5	V/ns
Operating junction and storage temperature range			TJ, Tstg	-55 to +175	°C
Soldering recommendations (peak temperature)	For 10 s			300^d

Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 25 V, starting TJ = 25 °C, L = 22 mH, Rg = 25 Ω, IAS = 2.6 A (see fig. 12)
c. ISD ≤ 9.2 A, dI/dt ≤ 110 A/μs, VDD ≤ VDS, TJ ≤ 175 °C
d. 1.6 mm from case

THERMAL RESISTANCE RATINGS
PARAMETER	SYMBOL	TYP.	MAX.	UNIT
Maximum Junction-to-Ambient	RthJA	–	120	°C/W

SPECIFICATIONS (T_J = 25 °C, unless otherwise noted)
PARAMETER	SYMBOL	TEST CONDITIONS		MIN.	TYP.	MAX.	UNIT
Static
Drain-Source Breakdown Voltage	VDS	V_GS = 0 V, I_D = 250 μA		100	–	–	V
V_DS Temperature Coefficient	DV_DS/T_J	Reference to 25 °C, I_D = 1 mA		–	0.13	–	V/°C
Gate-Source Threshold Voltage	VGS(th)	V_DS = V_GS, I_D = 250 μA		2.0	–	4.0	V
Gate-Source Leakage	IGSS	V_GS = ± 20 V		–	–	± 100	nA
Zero Gate Voltage Drain Current	IDSS	V_DS = 100 V, V_GS = 0 V		–	–	25	μA
Zero Gate Voltage Drain Current	IDSS	V_DS = 80 V, V_GS = 0 V, T_J = 150 °C		–	–	250	μA
Drain-Source On-State Resistance	RDS(on)	V_GS = 10 V	I_D = 0.78 A^b	–	–	0.27	W
Forward Transconductance	gfs	V_DS = 50 V, I_D = 0.78 A^b		0.80	–	–	S
Dynamic
Input Capacitance	Ciss	V_GS = 0 V V_DS = 25 V f = 1.0 MHz, see fig. 5		–	360	–	pF
Output Capacitance	Coss			–	150	–
Reverse Transfer Capacitance	Crss			–	34	–
Total Gate Charge	Q_g	V_GS = 10 V	I_D = 9.2 A, V_DS = 80 V see fig. 6 and 13^b	–	–	16	nC
Gate-Source Charge	Qgs			–	–	4.4
Gate-Drain Charge	Qgd			–	–	7.7
Turn-On Delay Time	td(on)	V_DD = 50 V, I_D = 9.2 A R_g = 18 W, R_D = 5.2 W, see fig. 10^b		–	6.8	–	ns
Rise Time	t_r			–	27	–
Turn-Off Delay Time	td(off)			–	18	–
Fall Time	t_f			–	17	–
Internal Drain Inductance	L_D	Between lead, 6 mm (0.25″) from package and center of die contact		–	4.0	–	nH
Internal Source Inductance	L_S			–	6.0	–	nH
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current	I_S	MOSFET symbol showing the integral reverse p – n junction diode		–	–	1.3	A
Pulsed Diode Forward Current^a	ISM			–	–	10	A
Body Diode Voltage	VSD	T_J = 25 °C, I_S = 1.3 A, V_GS = 0 V^b		–	–	2.5	V
Body Diode Reverse Recovery Time	trr	T_J = 25 °C, I_F = 9.2 A, dI/dt = 100 A/μs^b		–	130	260	ns
Body Diode Reverse Recovery Charge	Qrr	T_J = 25 °C, I_F = 9.2 A, dI/dt = 100 A/μs^b		–	0.65	1.3	μC
Forward Turn-On Time	ton	Intrinsic turn-on time is negligible (turn-on is dominated by L_S and L_D)

Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %

TYPICAL CHARACTERISTICS

(25 °C, unless otherwise noted)

Peak Diode Recovery dV/dt Test Circuit

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91128.

HVM DIP

(High voltage)

	INCHES		MILLIMETERS
DIM.	MIN.	MAX.	MIN.	MAX.
A	0.310	0.330	7.87	8.38
E	0.300	0.425	7.62	10.79
L	0.270	0.290	6.86	7.36
ECN: X10-0386-Rev. B, 06-Sep-10 DWG: 5974

Note

Package length does not include mold flash, protrusions or gate burrs. Package width does not include interplead flash or protrusions.

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