MICROCHIP Sinc3 Filter
Product Information
- Specifications
- Core Version: Sinc3 Filter v4.3
- Supported Device Families: PolarFire MPF300T
- Device Utilization:
- Resources: LUTs 157, DFF 218
- Performance: 200 MHz
- Features
- The Sinc3 Filter is a low-pass filter that removes high-frequency components above the cutoff frequency while preserving frequencies below it. It implements three stages of integration and differentiation at a decimated clock.
- Supported Tool Flow
- The Sinc3 Filter core comes with encrypted RTL code for instantiation with SmartDesign. Simulation, Synthesis, and Layout are done using Libero software. Licensing requires purchasing the encrypted RTL separately.
- Device Utilization and Performance
- The Sinc3 Filter utilizes 157 LUTs, and 218 DFFs, and operates at a performance of 200 MHz on the PolarFire MPF300T device.
- Functional Description
- The Sinc3 Filter hardware implementation involves three stages of integration and differentiation for low-pass filtering.
- Sinc3 Filter Parameters and Interface Signals
- Configuration Settings
- Users can configure the cutoff frequency and other filter parameters for the Sinc3 Filter.
- Input and Output Signals
- The Sinc3 Filter accepts input signals for filtering and provides filtered output signals based on the configured parameters.
- Product Usage Instructions
- Configure the cutoff frequency and other filter settings as needed.
- Apply input signals to the Sinc3 Filter for processing.
- Retrieve the filtered output signals for further analysis or processing.
FAQs
- Q: What is the ideal delay for the Sinc3 Filter?
- A: An ideal Sinc3 Filter requires an infinite delay, but a practical implementation involves three stages of integration and differentiation at a decimated clock.
- Q: What tool flow is recommended for working with the Sinc3 Filter?
- A: The Sinc3 Filter core is designed to be used with Libero software for simulation, synthesis, and layout. The encrypted RTL code facilitates instantiation with SmartDesign.
Introduction
The Sinc3 Filter is a low-pass filter that removes all high-frequency components above the cutoff frequency without affecting the frequencies below the cutoff frequency. An ideal Sinc3 Filter requires an infinite delay. A practical Sinc3 Filter has three stages of integration and three stages of differentiation at a decimated clock.
Summary
| Core Version | This document applies to Sinc3 Filter v4.3. |
| Supported Device | • PolarFire® SoC |
| Families | • PolarFire |
| • RTG4™ | |
| • IGLOO® 2 | |
| • SmartFusion® 2 | |
| Supported Tool Flow | Requires Libero® SoC v11.8 or later releases. |
| Licensing | Complete encrypted RTL code is provided for the core, enabling the core to be instantiated with SmartDesign. Simulation, Synthesis, and Layout are performed with Libero software. Sinc3 Filter is licensed with encrypted RTL that must be purchased separately. For more information, see Sinc3 Filter. |
Features
Sinc3 Filter has the following key features:
- Demodulate data from a Delta-Sigma modulator, which is widely used in delta-sigma-type Analog-to-Digital Converter (ADC)
- Convert the serial bitstream from ADC to parallel data
Implementation of IP Core in Libero Design Suite
- IP core must be installed to the IP Catalog of the Libero® System-on-Chip (SoC) software.
- This is installed automatically through the IP Catalog update function in the Libero SoC software, or the IP core is manually downloaded from the catalogue.
- Once the IP core is installed in the Libero SoC software IP Catalog, the core is configured, generated, and instantiated within the SmartDesign tool for inclusion in the Libero project list.
Device Utilization and Performance
Table 1. Sinc3 Filter Utilization
| Device Details | Resources | Performance (MHz) | RAMs | Math Blocks | Chip Globals | |||
| Family | Device | LUTs | DFF | LSRAM | μSRAM | |||
| PolarFire® SoC | MPFS250T | 157 | 218 | 200 | 0 | 0 | 0 | 0 |
| PolarFire | MPF300T | 157 | 218 | 200 | 0 | 0 | 0 | 0 |
| SmartFusion® 2 | M2S150 | 157 | 218 | 200 | 0 | 0 | 0 | 0 |
Important:
- The data in this table is captured using typical synthesis and layout settings. CDR reference clock source was set to Dedicated with other configurator values unchanged.
- The clock is constrained to 200 MHz while running the timing analysis to achieve the performance numbers.
Functional Description
- This section describes the implementation details of the Sinc3 Filter.
- The following figure shows the system-level block diagram of the Sinc3 Filter.
Figure 1-1. System-Level Block Diagram of Sinc3 Filter
Hardware Implementation of Sinc3 Filter
- The following figure shows the hardware implementation of the Sinc3 Filter.
Figure 1-2. Hardware Implementation of Sinc3 Filter
The clk_adc_i signal is the modulator clock from the ADC to the Sinc3 Filter. The filter implements three sequential integrations at the rate of clk_adc_i. A decimated clock is generated internally based on configuration parameters as shown in the following equation. The output of the third integrator is differentiated serially three times concerning the decimated clock to generate the output.
Sinc3 Filter Parameters and Interface Signals
- This section discusses the parameters in the Sinc3 Filter GUI configurator and I/O signals.
Configuration Settings
- The following table lists the description of the configuration parameters used in the hardware implementation of Sinc3 Filter.
- These are generic parameters and are varied as per the requirement of the application.
Table 2-1. Configuration Parameters
| Signal Name | Description |
| g_STD_IO_WIDTH | Width of the input and output signals |
| g_DECIMATION_FACTOR | Division factor used to generate the decimated clock from the system clock input |
| g_BIPOLAR | Select 0, if ADC is unipolar Select 1 if ADC is bipolar |
| g_NEGATE_OUTPUT | Select 0 if the data at the data_o port must be negated Select 1 if the data at the data_o port must be passed through |
Input and Output Signals
The following table lists the input and output ports of the Sinc3 Filter.
Table 2-2. Inputs and Outputs of Sinc3 Filter
| Signal Name | Direction | Description |
| reset_i | Input | Active low asynchronous reset signal to design |
| clk_adc_i | Input | Modulator clock coming from ADC |
| data_adc_i | Input | Data bitstream from the modulator in ADC |
| reg_rst_i | Input | When 1, reset all the registers. When 0, the filter is normally operated. |
| clk_dec_o | Output | Decimated clock output. This is the same clock used for a differentiator. The output of the filter updates at the rising edge of this output. This signal is not generated when res_rst_i is high. |
| data_o | Output | Filtered data output |
Timing Diagrams
- This section discusses the Sinc3 Filter timing diagram.
- The following figure shows the timing diagram of the Sinc3 Filter.
Figure 3-1. Sinc3 Filter Timing Diagram
Testbench
- A unified testbench is used to verify and test the Sinc3 Filter called user testbench.
- Testbench is provided to check the functionality of the Sinc3 Filter IP.
Simulation
The following steps describe how to simulate the core using the testbench:
- Open the Libero SoC application, click the Catalog tab, expand Solutions-MotorControl, double-click Sinc3 Filter, and then click OK. The documentation associated with the IP is listed under Documentation.
- Important: If you do not see the Catalog tab, navigate to View > Windows menu and click Catalog to make it visible.
- Figure 4-1. Sinc3 Filter IP Core in Libero SoC Catalog
- On the Stimulus Hierarchy tab, select the testbench (sin3_filter_tb.v), right-click and then click Simulate Pre-Synth Design > Open Interactively.
- Important: If you do not see the Stimulus Hierarchy tab, navigate to View > Windows menu and click Stimulus Hierarchy to make it visible.
- Figure 4-2. Simulating Pre-Synthesis Design
- ModelSim opens with the testbench file, as shown in the following figure.
- Figure 4-3. ModelSim Simulation Window
- Important: If the simulation is interrupted due to the runtime limit specified in the.do file, use the run -all command to complete the simulation.
Revision History
The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.
Table 5-1. Revision History
| Revision | Date | Description |
| A | 03/2023 | The following is the list of changes in revision A of the document:
• Migrated the document to the Microchip template. • Updated the document number to DS00004938A from 50200733. • Added 3. Timing Diagrams. • Added 4. Testbench. |
| 3.0 | — | The following list of changes are made in revision 3.0 of the document.
• Block Diagram of Sinc3 Filter is edited to replace the input signal hold_i with reg_rst_i. • Inputs and Outputs of the Sinc3 Filter are edited to replace the input signal hold_i with reg_rst_i and its description. |
| 2.0 | — | The following list of changes are made in revision 2.0 of the document.
• The Configuration Parameters table was updated to add the configuration parameters g_BIPOLAR and g_NEGATE_OUTPUT and their descriptions. • A new equation to calculate the equivalent resolution of the Sinc3 Filter output concerning the decimation factor is added in Hardware Implementation. • Block Diagram of Sinc3 Filter was edited to add the input signal hold_i. • Inputs and Outputs of the Sinc3 Filter table were edited to add the input signal, hold_i and its description. |
| 1.0 | 09/2016 | Revision 1.0 was the first publication of this document. |
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Documents / Resources
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MICROCHIP Sinc3 Filter [pdf] User Guide Sinc3 Filter, Sinc3, Filter |