MICROCHIP AN5454 Video Streaming with SDR Using Polar Fire
Introduction (Ask a Question)
This application note describes the implementation of Software Defined Radio on PolarFire® using an AD9371 radio transceiver, a dual camera sensor, and an HDMI monitor. The demo illustrates the transmission of live video wirelessly from a transmitter to a receiver setup and displays the received video on an HDMI monitor. This solution is developed on Microchip’s PolarFire Video kit, which features an MPF300TS PolarFire FPGA. A Software-Defined Radio (SDR) is a versatile technology used across numerous communication systems due to its adaptive capabilities. Unlike traditional radios, which rely on fixed hardware, SDRs leverage software for signal processing and management. A well-designed SDR typically comprises various fixed components, such as an antenna, front-end RF hardware, and an Analog-to-Digital Converter (ADC) or a Digital-to-Analog Converter (DAC).
The video is captured with the camera sensor at the transmitter end. The captured data undergoes various image processing techniques such as adaptive brightness and image enhancement. Following this, the data is compressed using JPEG and then transmitted to the SDR Tx. When the RF signal is received, it is demodulated by another SDR or compatible receiver to extract the original video data. This data is encoded and then decoded with a JPEG Decoder. The receiver transfers the video data to a monitor using a High Definition Multimedia Interface (HDMI) connection. HDMI is a widely used interface that provides high-quality digital video and audio.
The demo demonstrates the following features:
- Supports wireless transmission of video between two hardware setups
- Supports configuration of AD9371 RF board using Mi-V soft processor on FPGA device
- JPEG compression of live video captured from MIPI CSI2 camera with HD resolution
- Transmission of compressed video through SDR
- Display the received video on the Rx setup over HDMI
- Provides HD resolution video transfer with 19.2 Mbps speed
- Provides carrier frequency and phase offset correction using preamble-based auto-correlation method
- Supports FEC encoding to correct data transmission errors
- Supports Custom Packetization and Depacketization method
The PolarFire Video kit enables prototyping of Video and Imaging solutions with support for the following interfaces:
- MPFS300T PolarFire Video Kit device
- MIPI CSI-2 interface
- Dual Sony Camera
- FPGA Mezzanine Card (FMC) connector
- LPDDR4, and DDR4 memories
- HDMI, camera, and other interfaces
For more information about the PolarFire Video kit, see the PolarFire FPGA Video and Imaging Kit with MPF300T Device.
Demo Requirements
The following table lists the hardware and software requirements for running the demo.
Table 1-1. Demo Requirements
| Requirement | Description |
| Hardware and Accessories | |
| PolarFire® Video Kit | MPF300-VIDEO-KIT-NS
kit Contents: • PolarFire Video and Imaging Board with MPF300T-1FCG1152E Device • Dual Camera Sensor board – VIDEO-DC-DUALCAM • HDMI cable • 12V power pack/AC adapter • USB 2.0 A male to mini-B type Two Two-for-two board demo and one-for-one board demo |
| Image Sensor module | LI-IMX334-MIPI-MICRO v1.0 |
| SMA cable | Male to male
Required to provide the reference clock from the clock generator to AD9528 on the AD9371 FMC card. |
| Clock Source | Required to provide 30.72 MHz frequency for the reference clock to AD9371 |
| AD9371 | Analog Devices Radio Frequency (RF) board for transceiver functionality and digital signal processing function
Two Two-for-two board demo and one-for-one board demo |
| Host PC | A host PC with a USB port
Two Two-for-two board demo and one-for-one board demo |
| HDMI Monitor | To display the processed resultant video data for an HD resolution (1280 x 720) |
| Omnidirectional antenna | Two antennas are required for transmitting or receiving the radio signal
• One for transmitting • One for receiving |
| Utility Software | |
| FlashPro Express v2023.1 | To program the .job file on the PolarFire FPGA device |
| Programming job file | mpf_an5454_v2024p2_df.job |
Demo Prerequisites (Ask a Question)
Before you start the demo, ensure that the following components are in place:
- Download the demo design files from the following link: AN5454: Video Streaming with SDR using PolarFire and AD9371.
- The programming job file is placed at
- <$download_folder>\mpf_an5454_v2024p2_df\Programming_File.
Demo Design (Ask a Question)
The Libero® design contains both the transmitter (Tx) path and the receiver (Rx) path. The communication with the analog radio chip, AD9371, happens through JESD204B. As the design has both transmitter and receiver paths, the demo is operated in the following two modes:
- Two boards communication
- Same board communication
Two Boards Communication Setup (Ask a Question)
The setup for the two boards’ communication, requires the following equipment:
- Two PolarFire FPGA video kits
- Two AD9371 FMC cards
- Two clock generators
- One camera sensor
- One HDMI monitor
For more instructions on setting up the demo, see Setting up the Demo section. The camera captures data, which is then transmitted through the MIPI interfaces and compressed using JPEG encoding. The encoded data undergoes processing within the Image Signal Processing (ISP) blocks. After this, the data is sent to the SDR transmitter, where it is segmented into packets of a predefined size and wirelessly transmitted. At the receiving end, the SDR receiver captures the transmitted data, decodes it with a JPEG Decoder, and finally sends the video data to the HDMI monitor. The following figure shows the two-board communication setup.
Figure 3-1. Two Boards Communication
Same Board Communication Setup (Ask a Question)
The setup for the same board communication requires the following equipment:
- One PolarFire FPGA video kit
- One AD9371 FMC card
- One clock generator
- One camera sensor
- One HDMI monitor
The camera sensor captures video data which is then processed by the PolarFire FPGA. The FPGA device processes the video data and prepares it for transmission. The AD9371 FMC card modulates the processed video data and transmits it over the air through a radio frequency signal. At the receiving end, the same FMC card demodulates the incoming RF signal to retrieve the video data. Subsequently, the PolarFire FPGA processes this data and outputs it to an HDMI monitor, enabling the end-user to view the transmitted video content. The following figure shows the same board communication setup.
Figure 3-2. Same Board Communication
Transmitter (Ask a Question)
The following figure depicts the process flow of an SDR transmitter. A camera sensor initially captures video data, which undergoes refinement through ISP techniques such as Bayer interpolation, Gamma correction, image enhancement, and auto exposure. The data is then converted from RGB to YCbCr format. This processed data is compressed using a JPEG Encoder and then aligned through a FIFO buffer to ensure synchronization with the packetization process. The packetization involves the addition of headers, identification, access codes, and a CRC for error checking. The data is serialized into bits and further protected by Forward Error Correction (FEC) to enable error detection and correction at the receiver’s end.
Figure 3-3. Process Flow of a Transmitter
The FEC-encoded data is digitally modulated into I/Q symbols using QPSK at the physical layer, which includes a preamble and pilot symbols to adjust for frequency and phase discrepancies. To conform to emission regulations and reduce interference, thereby enhancing the signal-to-noise ratio, a Raised-Cosine filter is used for spectrum shaping. Subsequently, the refined I/Q baseband signals are transmitted through the high-speed JESD interface to the AD9371, where they are combined with the high-frequency RF signal. The resultant message signal is then broadcasted wirelessly through an antenna.
Receiver (Ask a Question)
An SDR receiver captures data through an antenna and subsequently processes it using the AD9371 RF chip. This chip demodulates the signal and then transmits it to an FPGA in I/Q format using the JESD protocol. To reduce noise, a matched filter is applied. Automatic Gain Control (AGC) is crucial for maintaining consistent signal levels to ensure accurate decoding.
The following figure shows the process flow of an anDR receiver.
Figure 3-4. Process Flow of a Receiver
The I/Q samples are oversampled by a factor of 8 and then filtered. Auto-correlation is used on the oversampled data to find the right timing for sampling the preamble and packet symbols, with multiple auto-correlation instances staggered by one clock cycle. Any frequency and phase offsets identified by auto-correlation are corrected by adjusting the I/Q values.
The Physical Layer (PHY) encompasses the procedures leading up to the acquisition of clean In-phase/Quadrature (I/Q) values, which symbolize the transmitted data and are essential for demodulation and data bit extraction. To correct bit errors resulting from channel distortion, a Viterbi decoder is used, which yields one corrected bit for every two bits demodulated.
The data undergoes a transformation from bits to bytes through a Serial-In-Parallel-Out (SIPO) converter, with packet header access codes ensuring correct alignment. The depacketization module then authenticates the data by comparing it to the receiver’s ID and conducts error checking using CRC. Upon successful ID match, the data is queued in a FIFO buffer. Subsequently, it is decoded with a JPEG decoder, converted from YCbCr to RGB format, and transmitted to an HDMI monitor using the HDMI protocol, resulting in the display of the captured video.
Clocking Structure (Ask a Question)
The PF_CCC generates the 50 MHz fabric clocks from the REF_CLK generated by PF_XCVR_REF_CLK. The onboard 156.25 MHz clock is the reference clock for the XCVR, which further provides the operating clock of 153.6 MHz for the TX_Path and RX_Path blocks. The onboard 148.5 MHz onboard oscillator provides a reference clock to generate clocks used in the video pipeline.
The following figure shows the clocking structure of the design.
Reset Structure (Ask a Question)
The INIT_MONITOR IP asserts the following signals:
- FABRIC_RESET_N: Asserted after the initialization of the fabric, whereas FABRIC_POR_N is used to reset the MSS.
- DEVICE_INIT_DONE: Asserted after the initialization of the PolarFire SoC device.
- EXTERNAL RESET: Asserted when the user wants to reset the design, externally.
The following figure shows the reset structure of the design.
Figure 3-6. Reset Structure
Resource Utilization (Ask a Question)
The following figure shows the summary of resource utilization and performance data.
Figure 3-7. Resource Utilization and Performance
Ports (Ask a Question)
The following table lists the ports of the demo design.
Table 3-1. Input and Output Ports
| Port Name | Direction | Description |
| SDR Ports | ||
| RESET_SW_N_I | Input | Resethe t the switch for the Design |
| REF_CLK_PAD_N | Input | XCVR Reference clock 156.25 MHz |
| REF_CLK_PAD_P | ||
| DAC_SYNC_N | Input | Sync signal from AD9371 |
| DAC_SYNC_P | ||
| LANE0_RXD_N | Input | Transceiver lanes connected to AD9371 |
| LANE0_RXD_P | ||
| LANE1_RXD_N | ||
| LANE1_RXD_P | ||
| PADN | Input | SYSREF signal from AD9371 FMC card |
| PADP | ||
| ADC_SYNC_N | — | Sync signal to AD9371 |
| ADC_SYNC_P | ||
| LANE0_TXD_N | Output | Transceiver lanes connected to AD9371 |
| LANE0_TXD_P | ||
| LANE1_TXD_N | ||
| LANE1_TXD_P | ||
| MSS Peripheral Ports | ||
| SPI_SDI | Input | SPI data input |
| TCK | Input | CoreJTAG pin |
| TDI | Input | CoreJTAG pin |
| TMS | Input | CoreJTAG pin |
| ………..continued | ||
| Port Name | Direction | Description |
| TRSTB | Input | CoreJTAG pin |
| GPIO_11_IN | Input | Connected to AD9371 |
| GPIO_10_IN | Input | Connected to AD9371 |
| SPI_SCLK | Output | SPI clock |
| SPI_SDO | Output | SPI data out |
| SPI_SS1 | Output | SPI chip select |
| TDO | Output | CoreJTAG pin |
| CAM1_SCL | Output | Camera control pins |
| CAM1_SDA | Output | Camera control pins |
| GPIO_OUT | Output | GPIO[4-9] → Connected to AD9371 |
| CAM1_EN | Output | Camera enable pin |
| Video Pipeline Ports | ||
| CAM1_RX_CLK_N | Input | Input pads to receive the reference clock for the camera sensor module |
| CAM1_RX_CLK_P | ||
| CAM1_RXD_N[3:0] | Input | Input pads to receive the live video from the camera sensor module. These pads are assigned to the Bank 7 I/Os. |
| CAM1_RXD_P[3:0] | ||
| HDMI_REF_CLK_PAD_N | Input | Input pads to receive the reference clock for the HDMI XCVR |
| HDMI_REF_CLK_PAD_P | ||
| REF_CLK_0 | Input | Reference clock for the video pipeline CCC |
| CAMERA_CLK | Output | Camera clock |
| HDMI_LANE0_TXD_N | Output | HDMI XCVR lanes |
| HDMI_LANE0_TXD_P | ||
| HDMI_LANE1_TXD_N | ||
| HDMI_LANE1_TXD_P | ||
| HDMI_LANE2_TXD_N | ||
| HDMI_LANE2_TXD_P | ||
| HDMI_LANE3_TXD_N | ||
| HDMI_LANE3_TXD_P | ||
| ………..continued | ||
| Port Name | Direction | Description |
| ACT_N | Output | DDR ports |
| BG | ||
| CAS_N | ||
| CK0_N | ||
| CK0 | ||
| CKE | ||
| CS_N | ||
| ODT | ||
| RAS_N | ||
| RESET_N | ||
| SHIELD0 | ||
| SHIELD1 | ||
| SHIELD2 | ||
| SHIELD3 | ||
| WE_N | ||
| A[13:0] | ||
| BA[1:0] | ||
| DM_N[3:0] | ||
| DQS_N[3:0] | ||
| DQ[31:0] | ||
Setting Up the Demo (Ask a Question)
The demonstration involves the following steps:
- Setting up the Hardware
- Same Board Communication
- Two Boards Communication
- Programming the Device
Setting Up the Hardware (Ask a Question)
After generating the bitstream, the PolarFire device is programmed on the Video kit. Ensure that the jumper settings on the Video kit board are the same as listed in the following table.
Table 4-1. Jumper Settings for Video Kit
| Jumper | Default Position | Functionality |
| J15 | Open | SPI Slave and Master mode selection. By default, SPI master is selected. |
| J17 | Open | 100K PD for TRSTn. By default, 1K PD is connected |
| J19 | Pin 1 and 2 | Default: XCVR_VREF is connected to GND |
| J28 | Pin 1 and 2 | Default: Programming through the FTDI |
| J24 | Pin 2 and 4 | Default: VDDAUX4 voltage is set to 3V3 |
| J25 | Pin 5 and 6 | Default: Bank4 voltage is set to 1V8 |
| J36 | Pin 1 and 2 | Default: Board power up through the SW4 |
| SW6 | OFF | Default: 700 MHz carrier frequency is selected |
| SW6 | ON | User DIP switch |
| SW4 | OFF | Power ON/OFF switch |
| J20 | 12V Input | 12V input to the board |
The following figure shows the board setup for the mentioned jumper settings.
Figure 4-1. PolarFire Video Kit Jumper Settings
- Connect the camera sensor to J5 on the PolarFire Video kit.
- Connect the AD9371 to the J14 FMC connector.
- Connect the signal generator by setting it to 30.72 MHz and 1.8 Vpp to the J401 of the AD9371.
- Connect one omnidirectional antenna to the J305 (TX1 SMA connector) and the other antenna to the J200 (RX1 SMA connector) of AD9371.
- Connect the HDMI cable to the J1 (HDMI 2.0 Tx port) of the PolarFire Video kit.
- Connect the host PC to the PolarFire Video kit through J12 using a USB Mini cable.
- Connect the power supply cable to J20 of the PolarFire Video kit.
- Power up the HDMI monitor.
- Power up the PolarFire Video kit using the SW4 slide switch.
Two Boards Communication (Ask a Question)
To set up two boards communication, perform the following steps:
- Connect the camera sensor to J5 on the PolarFire Video kit, which is a transmitter.
- Connect the AD9371 to the J14 FMC connector on both PolarFire Video kits.
- Connect the signal generator by setting it to 30.72 MHz and 1.8 Vpp to the J401 of the AD9371.
- Connect one omnidirectional antenna to J305 (TX1 SMA connector) of the Transmitter AD9371 and the other antenna to J200 (RX1 SMA connector) of the Receiver AD9371.
- Connect the HDMI cable to the J1 (HDMI 2.0 Tx port) of the PolarFire Video kit of the receiver.
- Connect the host PC to the two PolarFire Video kits through J12 using a USB Mini cable.
- Connect the power supply cable to J20 on two PolarFire Video kits.
- Power up the HDMI monitor.
- Power up the PolarFire Video kit using the SW4 slide switch.
Programming the Device (Ask a Question)
This section describes how to program the PolarFire FPGA Video kit with the .job file using FlashPro Express. To program the device, perform the following steps:
The mpf_an5454_v2024p2_df.job file is available at <download_folder\mpf_an5454_v2024p2_jb.
- Connect a micro USB to J12 from the host PC and start the FlashPro Express software from its installation.
- To create a new job project, select New or navigate to the Project menu and select New Job Project from FlashPro Express Job.
- In the New Job Project, from the FlashPro Express Job dialog box, enter the following values:
- Programming job file: Click Browse, navigate to the location where the .job file is located, and select the file. The default location is: <$download_folder>\mpf_an5454_v2024p2_df\Programming_Job.
- FlashPro Express job project location: Click Browse and navigate to the location where you want to save the project.
- Click OK. The required programming file is selected and ready to be programmed into the device.
- The FlashPro Express window appears as shown in the following figure. Confirm that a programmer number (for example, 79DE6C53) appears in the Programmer field. If it does not, then confirm the board connections and click Refresh/Rescan Programmers. Figure 4-2. Programming the Device
- Click RUN. When the device is programmed successfully, a RUN PASSED status is displayed asshown in the following figure. Figure 4-3. FlashPro Express—RUN PASSED
- Close FlashPro Express or in the Project tab, click Exit.
- Power cycle the board using SW5.
SoftConsole
The SoftConsole project, included with the Libero design, uses the APIs for AD9371 and AD9528 from Analog Devices, which are used to initialize and configure the clock generator AD9528. The RF transceiver AD9371, which has a built-in Arm® processor, runs calibration and other power-uppsequences required to initialize AD9371. The Arm binary byte file required for the built-in Arm processor is loaded by the Soft Mi-V processor in the FPGA power-up sequence, which indeed communicates with AD9371 and AD9528 through the Serial Peripheral Interface (SPI). The Mi-V processor reads the status of AD9528 and AD9371 through SPI during initialization and displays the status on the UART terminal.
\The following listed messages are displayed on the Receive Data window:
- SPI AD9371: Before initiating SPI communication between the Mi-V processor and the AD9371 (including AD9528), the process is visible on the screen following the proper initialization of the UART. If the message is not displayed or if random data is displayed on the GUI, then check the UART baudrate value in the GUI.
- Camera Initialised Successfully: The Mi-V processor utilizes the CoreI2C to configure the camera’s registers. Upon successful initialization of the camera, a confirmation message is displayed.
- PLL Locked: The Mi-V processor monitors the CLKPLLL bit and displays a message indicating whether the CLKPLL is locked. If the CLKPLL is not locked, a “PLL not locked” message is displayed.
- Multi-Chip Sync Successful: After performing Multi-Chip Sync, the Mi-V processor verifies if the Multi-Chip Sync was successful. If successful, a success message is displayed; otherwise, “Multi-Chip Sync Failed” is displayed.
- AD9371 Arm Version 4.0.6: After loading an Arm binary byte file, the Mi-V processor reads the version of the loaded binary. This message is displayed if the binary byte array is loaded properly and the version is read back. If it is not loaded properly, an arbitrary number is displayed.
- (CLK, RX, TX, SNIFFER) PLLs Locked: The displayed message indicates that the Mi-V processor is performing a check on the PLLs for the CLK, RX, TX, and sniffer. If not locked, it displays the message “(CLK, RX, TX, SNIFFER) PLLs not locked” along with the PLL lock status. For more information about PLL status bits, see the UG992 AD9371 user guide for Analog Devices.
- Calibrations Completed Successfully: The Mi-V processor queries the calibration status of AD9371. This message is displayed if the Arm processor (in the AD9371) completes calibrations. Otherwise, this message is not displayed.
- Successfully Initialised AD9371: This final message is displayed when AD9371 is initialized and configured correctly. If AD9371 is not configured correctly or fails to initialize, the message “Initialization Failed, Status = XXXX” is displayed, along with the status bits (indicated as XXXX). The status bits are used to debug failures during initialization.
Running the Demo
To run the demo, perform the following steps:
- After programming the PolarFire FPGA Video kit, connect AD9371 to the FMC connector.
- Connect the SMA cable to the clock generator output and J401 on the AD9371. This acts as the reference clock for the FMC card.
- Connect the antennas to the appropriate transmitter and receiver of the FMC card, depending on the type of demo being used.
- For the demonstration on the two boards, connect one antenna to J305 (Tx1) of the first demo kit and connect the second antenna to J200 (Rx1) of the second demo kit, as shown in the following figure.
Figure 6-1. Video Kit Demo Setup using Two Boards
- For the demonstration on the same board, connect one antenna to the J305 (Tx1) and the second antenna to the J200 (Rx1) of the same board, as shown in the following figure.
Figure 6-2. Video Kit Demo Setup using the Same Board
Changing the Tx and Rx Frequency
The SDR demo runs with four different Local Oscillator (LO) frequencies. To modify the LO frequency, use the DIP switch SW6. Ensure to configure the same frequency on both the transmit and receive sides. In the two-board demonstration, the distance between the antennas is determined by the configured frequency. The following table lists the available LO frequencies.
Table 6-1. Frequency Settings
| Switch [2:1] | LO Frequency |
| ON: ON | 700 MHz |
| ON: OFF | 1200 MHz |
| OFF: ON | 2400 MHz |
| OFF: OFF | 5800 MHz |
Important: EnsureA toggle SW2 after changing the LO Frequency.
Running the Demo on Two Boards (Ask a Question)
To run the demo on the two boards, perform the following steps:
- After programming the bit files, launch any port terminal application such as TeraTerm as shown in the following figure.
Figure 6-3. TeraTerm Connection
- Select the appropriate serial port (COM41 is the appropriate port for this demo setup, select accordingly for the user’s setup).
- Select the baud rate or speed as 460800 for the respective COM port, as shown in the following figure.
Figure 6-4. Setting the Serial Port and Baud Rate
- After completing the preceding steps, power cycle the board and wait for the following message “Successfully Initialized AD9371”.
- Repeat the same steps for the second setup as well.
- Once the receiver setup is ready, connect the HDMI monitor to the J1 to see the video output as shown in the following figure.
Figure 6-5. Video Output
Running the Demo on the Same Board (Ask a Question)
To run the demo on the same board, perform the following steps:
- After programming the bit files, launch any port terminal application such as TeraTerm as shown in the following figure. Figure 6-6. TeraTerm Connection
- Select the appropriate serial port (COM41 is the appropriate port for this demo setup, select accordingly for the user’s setup).
- Select the baud rate or speed as 460800 for the respective COM port, as shown in the following figure.
Figure 6-7. Setting the Serial Port and Baud Rate
- After completing the preceding steps, power cycle the board and wait for the following message “Successfully Initialised AD9371”.
- Connect the HDMI monitor to the J1 of the PolarFire Video kit to display video on the monitor.
Revision History
The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication.
Table 7-1. Revision History
| Revision | Date | Description |
| B | 12/2024 | Updated the .job file path throughout the document. |
| A | 07/2024 | Initial release |
Microchip FPGA Support
- Microchip FPGA products group backs its products with various support services, including Customer Service, Customer Technical Support Center, a website, and worldwide sales offices. Customers are suggested to visit Microchip online resources before contacting support as it is very likely that their queries have been already answered.
- Contact the Technical Support Center through the website at www.microchip.com/support. Mention the FPGA Device Part number, select the appropriate case category, and upload design files while creating a technical support case.
- Contact Customer Service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization.
- From North America, call 800.262.1060
- From the rest of the world, call 650.318.4460
- Fax, from anywhere in the world, 650.318.8044
Microchip Information
Trademarks
- The “Microchip” name and logo, the “M” logo, and other names, logos, and brands are registered and unregistered trademarks of Microchip Technology Incorporated or its affiliates and/or subsidiaries in the United States and/or other countries (“Microchip.
- Trademarks”). Information regarding Microchip Trademarks can be found at https://www.microchip.com/en-us/about/legal-information/microchip-trademarks.
- ISBN: 979-8-3371-0304-4
Legal Notice
This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information
in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at www.microchip.com/en-us/support/design-help/client-support-services.
THIS INFORMATION IS PROVIDED BY MICROCHIP “AS IS”. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP’S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE NUMBER OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION.
Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify, and hold harmless Microchip from any any damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip products:
- Microchip products meet the specifications contained in their particular Microchip Data Sheet.
- Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions.
- Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip products are strictly prohibited and may violate the Digital Millennium Copyright Act.
- Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products.
Documents / Resources
 |
MICROCHIP AN5454 Video Streaming with SDR Using Polar Fire [pdf] Instructions AN5454 Video Streaming with SDR Using Polar Fire, AN5454, Video Streaming with SDR Using Polar Fire, SDR Using Polar Fire, Using Polar Fire, Polar Fire |