UG0644 DDR AXI Arbiter
Product Information
Iyo DDR AXI Arbiter chinhu chehardware chinopa a
64-bit AXI master interface kune iyo DDR-SDRAM pane-chip controllers.
Inowanzo shandiswa mumavhidhiyo maapplication ekubhafa uye
kugadzirisa kwevhidhiyo pixel data. Chigadzirwa chemushandisi bhuku chinopa
ruzivo rwakadzama uye mirairo pamusoro pekushandiswa kwehardware,
simulation, uye kushandisa zviwanikwa.
Hardware Implementation
Iyo DDR AXI Arbiter yakagadzirirwa kusangana neDDR-SDRAM
pa-chip controllers. Inopa 64-bit AXI master interface
iyo inogonesa kugadzirisa nekukurumidza kwevhidhiyo pixel data. Mushandisi wechigadzirwa
bhuku rinopa tsananguro yedhizaini yeDDR AXI
Arbiter uye kushandiswa kwayo kwehardware.
Simulation
Chigadzirwa chemushandisi bhuku rinopa mirairo yekutevedzera iyo
DDR AXI Arbiter uchishandisa MSS SmartDesign uye Testbench maturusi. Izvi
zvishandiso zvinogonesa mushandisi kusimbisa kurongeka kwedhizaini uye
chengetedza kushanda kwakakodzera kwechikamu chehardware.
Resource Utilization
Iyo DDR AXI Arbiter inoshandisa zviwanikwa zvehurongwa senge logic
maseru, memory blocks, uye routing zviwanikwa. Mushandisi wechigadzirwa
bhuku rinopa yakadzama sosi yekushandisa mushumo iyo
inotsanangura zvinodikanwa zvezviwanikwa zveDDR AXI Arbiter. Izvi
ruzivo runogona kushandiswa kuve nechokwadi chekuti chikamu chehardware chinogona
kuitwa mukati meiyo iripo system zviwanikwa.
Mirayiridzo Yekushandiswa Kwechigadzirwa
Mirayiridzo inotevera inopa nhungamiro yekuti ungashandisa sei
DDR AXI Arbiter:
Danho 1: Hardware Implementation
Shandisa iyo DDR AXI Arbiter hardware chikamu kune interface
neDDR-SDRAM pa-chip controllers. Tevera magadzirirwo
tsananguro yakapihwa muchigadzirwa chemushandisi bhuku kuti ive nechokwadi
kushandiswa kwechikamu chehardware.
Danho 2: Simulation
Tevedzera iyo DDR AXI Arbiter dhizaini uchishandisa MSS SmartDesign uye
Testbench zvishandiso. Tevera mirairo inopihwa muchigadzirwa
bhuku remushandisi kusimbisa kurongeka kwedhizaini uye kuve nechokwadi
kushanda zvakanaka kwechikamu chehardware.
Danho rechitatu: Resource Utilization
Review mushumo wekushandisa zviwanikwa wakapihwa muchigadzirwa
bhuku remushandisi kuona izvo zvekushandisa zvinodiwa zveDDR AXI
Arbiter. Ita shuwa kuti chikamu chehardware chinogona kuitwa
mukati meiyo iripo system zviwanikwa.
Nekutevera mirairo iyi, unogona kushandisa zvinobudirira iyo DDR
AXI Arbiter hardware chikamu chevhidhiyo pixel data buffering uye
kugadzirisa mumavhidhiyo maapplication.
UG0644 User Guide
DDR AXI Arbiter
Kukadzi 2018
DDR AXI Arbiter
Zviri mukati
1 Revision History ………………………………………………………………………………………………………………….. 1
1.1 Ongororo 5.0 …………………………………………………………………………………………………………………………………………………………………………. 1 1.2 Ongororo 4.0 ………………………………………………………………………………………………………………………………………………………………………………… 1 1.3 Kudzokorora 3.0 1 Ongororo 1.4 …………………………………………………………………………………………………………………………………………………………………………………. 2.0 1 Ongororo 1.5 ……………………………………………………………………………………………………………………………………………………………………………………. 1.0
2 Nhanganyaya …………………………………………………………………………………………………………………….. 2 3 Hardware Kuitwa …………………………………………………………………………………………………
3.1 Tsanangudzo yeMagadzirirwo ……………………………………………………………………………………………………………………… …………………………………………………………………………………………………………….. 3 3.2 Configuration Parameters ……… ………………………………………………………………………………………………. 5 3.3 Madhayagiramu eNguva …………………………………………………………………………………………………………………. 13 3.4 Testbench ……………………………………………………………………………………………………………………….. 14
3.5.1 Simulating MSS SmartDesign ………………………………………………………………………………………………………. 25 3.5.2 Simulating Testbench …………………………………………………………………………………………………………. 30 3.6 Mashandisirwo Ezviwanikwa …………………………………………………………………………………………………………….. 31
UG0644 Mushandisi Yekudzokorodza 5.0
DDR AXI Arbiter
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Revision History
Nhoroondo yekudzokorora inotsanangura shanduko dzakaitwa mugwaro. Kuchinja kwacho kunorongwa nekudzokorora, kutanga nebhuku razvino uno.
1.1
Kudzokorora 5.0
Mukudzokorora 5.0 yegwaro iri, iyo Resource Utilization chikamu uye Resource Utilisation Report
zvakagadziridzwa. Kuti uwane rumwe ruzivo, ona Resource Utilization (ona peji 31).
1.2
Kudzokorora 4.0
Inotevera ipfupiso yeshanduko mudzokororo 4.0 yegwaro iri.
Yakawedzera testbench gadziriso paramita mutafura. Kuti uwane rumwe ruzivo, ona Configuration Parameters (ona peji 16) .. Yakawedzerwa ruzivo kutevedzera musimboti uchishandisa testbench. Kuti uwane rumwe ruzivo, ona Testbench (ona peji 16). Yakagadziridza iyo Resource Utilization yeDDR AXI Arbiter kukosha mutafura. Kuti uwane rumwe ruzivo, ona Resource Utilization (ona peji 31).
1.3
Kudzokorora 3.0
Inotevera ipfupiso yeshanduko mudzokororo 3.0 yegwaro iri.
Yakawedzera 8-bit ruzivo rwekunyora chiteshi 1 uye 2. Kuti uwane rumwe ruzivo, ona Tsanangudzo Yekugadzira (ona peji 3). Yakagadziridzwa Testbench chikamu. Kuti uwane rumwe ruzivo, ona Testbench (ona peji 16).
1.4
Kudzokorora 2.0
Mukudzokorora 2.0 yegwaro iri, manhamba nematafura mune zvakagadziridzwa muchikamu cheTestbench.
Kuti uwane rumwe ruzivo, ona Testbench (ona peji 16).
1.5
Kudzokorora 1.0
Revision 1.0 yaive yekutanga kuburitswa kwegwaro iri
UG0644 Mushandisi Yekudzokorodza 5.0
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DDR AXI Arbiter
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Nhanganyaya
Memories chikamu chakakosha cheiyo chero yakajairwa vhidhiyo uye mifananidzo yekushandisa. Iwo anoshandiswa kubhafa vhidhiyo pixel data. Imwe yakajairika buffering example inoratidzira furemu buffers umo iyo yakazara vhidhiyo pixel data yefuremu inovharirwa mundangariro.
Dual data rate (DDR) -synchronous DRAM (SDRAM) ndeimwe yendangariro dzinowanzoshandiswa mumavhidhiyo maapplication ekubhafa. SDRAM inoshandiswa nekuda kwekumhanya kwayo iyo inodiwa kukurumidza kugadzirisa mumavhidhiyo masisitimu.
Mufananidzo unotevera unoratidza example yedhiyabhorosi-level dhizaini yeDDR-SDRAM ndangariro inopindirana nevhidhiyo application.
Mufananidzo 1 · DDR-SDRAM Memory Interfacing
MuMicrosemi SmartFusion®2 System-on-Chip (SoC), kune maviri pa-chip DDR controllers ane 64-bit advanced extensible interface (AXI) uye 32-bit yepamusoro-yepamusoro-inoshanda bhazi (AHB) yevaranda inopindirana yakananga kumunda inorongwa. gedhi array (FPGA) jira. Iyo AXI kana AHB master interface inodiwa kuti uverenge nekunyora iyo DDR-SDRAM ndangariro yakatarisana kune iyo-chip DDR controllers.
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DDR AXI Arbiter
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Hardware Implementation
3.1
Dhizaini Dhizaini
Iyo DDR AXI Arbiter inopa 64-bit AXI master interface kune iyo DDR-SDRAM pa-chip controllers ye.
SmartFusion2 zvishandiso. Iyo DDR AXI Arbiter ine mana ekuverenga chiteshi uye maviri ekunyora chiteshi akananga kune
user logic. Iyo block inopindirana pakati peaya mana ekuverenga chiteshi kuti ipe mukana kune iyo AXI kuverenga
chiteshi nenzira yakatenderedza-robin. Chero bedzi chiteshi chekuverenga 1 master chikumbiro chekuverenga chiri pamusoro, iyo AXI
verenga chiteshi chakagoverwa kwairi. Verenga chiteshi 1 yakagadzika kubuda data upamhi hwe24-bit. Verenga zviteshi 2, 3,
uye 4 inogona kugadzirwa se8-bit, 24-bit, kana 32-bit data kubuda upamhi. Izvi zvinosarudzwa nepasi rose
configuration parameter.
Iyo block zvakare inopokana pakati peaya maviri ekunyora chiteshi kupa mukana kune iyo AXI yekunyora chiteshi nenzira inotenderera-robin. Zvose zvinyorwa zvekunyora zvine zvakakosha zvakaenzana. Nyora chiteshi 1 uye 2 inogona kugadzirwa se8-bit, 24-bit, kana 32-bit yekupinda data upamhi.
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DDR AXI Arbiter
Nhamba inotevera inoratidza yepamusoro-pini-kunze dhayagiramu yeDDR AXI Arbiter. Mufananidzo 2 · Top-Level Block Diagram yeDDR AXI Arbiter Block
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DDR AXI Arbiter
Iyi inotevera nhamba inoratidza iyo yepamusoro-level block dhizaini yehurongwa ine DDR AXI Arbiter block yakaiswa muSmartFusion2 mudziyo. Mufananidzo 3 · System-Level Block Diagram yeDDR AXI Arbiter paSmartFusion2 Device
3.2
Zvinopinza uye Zvinobuda
Iyi tafura inotevera inonyora ekuisa uye kubuda madoko eDDR AXI Arbiter.
Tafura 1 · Kupinza uye Kubuda Ports yeDDR AXI Arbiter
Zita rechiratidzo RESET_N_I
Direction Input
Upamhi
SYS_CLOCK_I BUFF_READ_CLOCK_I
Input Input
rd_req_1_i rd_ack_o
Input Kubuda
rd_done_1_o start_read_addr_1_i
Output Inzwa Zvinotaurwa
bytes_to_read_1_i
Input
vhidhiyo_rdata_1_o
Output
[(g_AXI_AWIDTH-1):0] [(g_RD_CHANNEL1_AXI_BUFF_ AWIDTH + 3) – 1 : 0] [(g_RD_CHANNEL1_VIDEO_DATA_WIDTH1):0]Tsanangudzo
Active yakaderera asynchronous reset chiratidzo kugadzira
System wachi
Nyora chiteshi chemukati buffer yekuverenga wachi, inofanira kupetwa kaviri SYS_CLOCK_I frequency
Verenga chikumbiro kubva kuna Master 1
Arbiter kubvuma kuverenga chikumbiro kubva kuna Master 1
Verenga kupedzisa kuna Master 1
DDR kero kubva panofanira kutangirwa kuverenga chiteshi 1
Mabhayiti anoverengerwa kubva pakuverenga chiteshi 1
Vhidhiyo data kubuda kubva kuverenga chiteshi 1
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DDR AXI Arbiter
Zita rechiratidzo rdata_valid_1_o rd_req_2_i rd_ack_2_o
rd_done_2_o start_read_addr_2_i
bytes_to_read_2_i
vhidhiyo_rdata_2_o
rdata_valid_2_o rd_req_3_i rd_ack_3_o
rd_done_3_o start_read_addr_3_i
bytes_to_read_3_i
vhidhiyo_rdata_3_o
rdata_valid_3_o rd_req_4_i rd_ack_4_o
rd_done_4_o start_read_addr_4_i
bytes_to_read_4_i
vhidhiyo_rdata_4_o
rdata_valid_4_o wr_req_1_i wr_ack_1_o
wr_done_1_o start_write_addr_1_i
bytes_to_write_1_i
vhidhiyo_wdata_1_i
wdata_valid_1_i wr_req_2_i
Direction Output Output
Output Inzwa Zvinotaurwa
Input
Output
Output Input Output
Output Inzwa Zvinotaurwa
Input
Output
Output Input Output
Output Inzwa Zvinotaurwa
Input
Output
Output Input Output
Output Inzwa Zvinotaurwa
Input
Input
Input Input
Upamhi
[(g_AXI_AWIDTH-1):0] [(g_RD_CHANNEL2_AXI_BUFF_AWIDTH + 3) – 1 : 0] [(g_RD_CHANNEL2_VIDEO_DATA_WIDTH1):0] [(g_AXI_AWIDTH-1):0ID_CHANNA_3):3] ) – 1 : 0] [(g_RD_CHANNEL3_VIDEO_DATA_WIDTH1 ):0] [(g_AXI_AWIDTH-1):0] [(g_RD_CHANNEL4_AXI_BUFF_AWIDTH + 3) – 1 : 0] [(g_RD_CHANNEL4_VIDEO_DATA_WIDTH1):0] [(g_AXI_AWIDTH_CHANNEL_FFNID_1) TH + 0) - 1: 3 ] [(g_WR_CHANNEL1_VIDEO_DATA_WIDTH0):1]
Tsanangudzo Verenga data inoshanda kubva kuchiteshi chekuverenga 1 Verenga chikumbiro kubva kuna Master 2 Arbiter kubvuma kuverenga chikumbiro kubva kuna Master 2 Verenga kupedzisa kuna Master 2 DDR kero kubva panofanira kutangirwa yekuverenga chiteshi 2 Bytes kuti iverengwe kubva kuverenga chiteshi 2 Vhidhiyo data. zvabuda kubva kuchiteshi chekuverenga 2 Verenga data inoshanda kubva kugedhi yekuverenga 2 Verenga chikumbiro kubva kuna Master 3 Arbiter kubvuma kuverenga chikumbiro kubva kuna Master 3 Verenga kupedzisa kuna Master 3 DDR kero kubva panofanira kutangirwa kuverenga chiteshi 3 Bytes kuti iverengwe kubva pakuverenga chiteshi 3 Vhidhiyo data kubuda kubva kuverenga chiteshi 3 Verenga data inoshanda kubva pakuverenga chiteshi 3 Verenga chikumbiro kubva kuna Master 4 Arbiter kubvuma kuti uverenge chikumbiro kubva kuna Master 4 Verenga kupedzisa kuna Master 4 DDR kero kubva panofanira kutangirwa kuverenga chiteshi 4 Bytes kuve. verenga kubva pakuverenga chiteshi 4 Vhidhiyo data yakabuda kubva pakuverenga chiteshi 4 Verenga data inoshanda kubva pakuverenga chiteshi 4 Nyora chikumbiro kubva kuna Master 1 Arbiter kubvuma kunyora chikumbiro kubva kuna Master 1 Nyora kupedzisa kuna Master 1 DDR kero iyo kunyora kunofanira kuitika kubva pakunyora chiteshi 1 Mabhaiti anozonyorwa kubva pakunyora chiteshi 1 Vhidhiyo data Input yekunyora chiteshi 1
Nyora data inoshanda pakunyora chiteshi 1 Nyora chikumbiro kubva kuna Master 1
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DDR AXI Arbiter
Zita rechiratidzo wr_ack_2_o
Direction Output
wr_done_2_o start_write_addr_2_i
Output Inzwa Zvinotaurwa
bytes_to_write_2_i
Input
vhidhiyo_wdata_2_i
Input
wdata_valid_2_i AXI I/F masiginecha Verenga Kero Channel m_arid_o
Input Kubuda
m_araddr_o
Output
m_arlen_o
Output
m_arsize_o m_arburst_o
Output Output
m_arlock_o
Output
m_arcache_o
Output
m_arprot_o
Output
Upamhi
[(g_AXI_AWIDTH-1):0] [(g_WR_CHANNEL2_AXI_BUFF_AWIDTH + 3) – 1 : 0] [(g_WR_CHANNEL2_VIDEO_DATA_WIDTH1):0]
Tsanangudzo Arbiter kubvuma kunyora chikumbiro kubva kuna Master 2 Nyora kupedzisa kuna Master 2 DDR kero iyo kunyora kunofanira kuitika kubva pakunyora chiteshi 2 Bytes kunyorwa kubva pakunyora chiteshi 2 Vhidhiyo data Input yekunyora chiteshi 2
Nyora data inoshanda kunyora chiteshi 2
Verenga kero ID. Identification tag yeboka rekero yekuverenga yezviratidzo.
Verenga kero. Inopa kero yekutanga yekuverenga burst transaction. Chete kero yekutanga yekuputika inopiwa.
Kuputika kureba. Inopa iyo chaiyo nhamba yekutamiswa mukuputika. Ruzivo urwu runotara nhamba yekufambiswa kwedata kwakabatana nekero
Kuputika saizi. Saizi yekuchinjisa yega yega mukuputika
Burst type. Yakabatana neruzivo rwehukuru, inodonongodza kuti kero yekuchinjisa yega yega mukati mekuputika inoverengerwa sei.
Yakagadziriswa ku2'b01 à Inowedzera kero yakaputika
Kiya mhando. Inopa rumwe ruzivo nezve maatomu maitiro ekutamisa.
Yakagadziriswa ku2'b00 kune Yakajairika Access
Cache type. Inopa rumwe ruzivo nezve cacheable maitiro ekutamisa.
Yakagadziriswa ku4'b0000 kune Isiri-cacheable uye isiri-bufferable
Kudzivirirwa mhando. Inopa ruzivo rwekudzivirira chikamu chekutengeserana.
Yakagadziriswa ku3'b000 kune Yakajairika, yakachengeteka kuwana data
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DDR AXI Arbiter
Zita rechiratidzo m_arvalid_o
Direction Output
Upamhi
m_ready_i
Input
Verenga Data Channel
m_rid_i
Input
[3:0]m_rdata_i m_rresp_i
m_rlast_i m_rvalid_i
Input Input
[(g_AXI_DWIDTH-1):0] [1:0]Input Input
m_ready_o
Output
Nyora Kero Channel
m_awid_o
Output
m_awaddr_o
Output
[3:0] [(g_AXI_AWIDTH-1):0]UG0644 Mushandisi Yekudzokorodza 5.0
Tsanangudzo Verenga kero inoshanda.
Kana HIGH, kero yekuverenga uye yekudzora ruzivo inoshanda uye inoramba yakakwira kusvika kero yekubvuma chiratidzo, m_arready, yakakwira.
`1' = Kero uye kudzora ruzivo runoshanda
`0' = Kero uye kudzora ruzivo haruna kushanda. Verenga kero yagadzirira. Muranda akagadzirira kugamuchira kero uye anosanganisirwa masaini ekudzora:
1 = muranda akagadzirira
0 = muranda asina kugadzirira.
Verenga ID tag. ID tag yeboka rekuverenga data rezviratidzo. Iyo m_rid kukosha inogadzirwa neMuranda uye inofanirwa kuenderana nem_arid kukosha kwekuverenga kutengeserana kwairi kupindura. Verenga data. Verenga mhinduro.
Mamiriro ekuendeswa kwekuverenga. Mhinduro dzinotenderwa ndedze OK, EXOKAY, SLVERR, uye DECERR. Verenga pakupedzisira.
Kuchinjisa kwekupedzisira mukuverenga kwakaputika. Verenga ichokwadi. Inodiwa yekuverenga data iripo uye kutumira kwekuverenga kunogona kupedzisa:
1 = verenga data iripo
0 = kuverenga data haisipo. Verenga wakagadzirira. Tenzi anogona kugamuchira iyo yekuverenga data uye mhinduro ruzivo:
1= tenzi vakagadzirira
0 = tenzi haana kugadzirira.
Nyora kero ID. Identification tag yekero yekunyora boka rezviratidzo. Nyora kero. Inopa kero yekutanga kutamisa mune yekunyora kuputika transaction. Iwo anobatanidzwa ekudzora masaini anoshandiswa kuona maadero ezvasara kutamiswa mukuputika.
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DDR AXI Arbiter
Zita rechiratidzo m_awlen_o
Direction Output
Upamhi [3:0]
m_awsize_o
Output
[2:0]m_awburst_o
Output
[1:0]m_awlock_o
Output
[1:0]m_awcache_o
Output
[3:0]m_awprot_o
Output
[2:0]m_awvalid_o
Output
Tsanangudzo
Kuputika kureba. Inopa iyo chaiyo nhamba yekutamiswa mukuputika. Ruzivo urwu runotara nhamba yekufambiswa kwedata kwakabatana nekero.
Kuputika saizi. Saizi yekuchinjisa yega yega mukuputika. Byte lane strobes inoratidza chaizvo kuti ndedzipi nzira dzekuvandudza.
Yakagadziriswa ku 3'b011 kusvika 8 bytes pakutumira data kana 64-bit kutamiswa
Burst type. Yakabatana neruzivo rwehukuru, inodonongodza kuti kero yekuchinjisa yega yega mukati mekuputika inoverengerwa sei.
Yakagadziriswa ku2'b01 à Inowedzera kero yakaputika
Kiya mhando. Inopa rumwe ruzivo nezve maatomu maitiro ekutamisa.
Yakagadziriswa ku2'b00 kune Yakajairika Access
Cache type. Inoratidza iyo inobatika, inochengeteka, kunyora-kuburikidza, kunyora-shure, uye kugovera hunhu hwekutengeserana.
Yakagadziriswa ku4'b0000 kune Isiri-cacheable uye isiri-bufferable
Kudzivirirwa mhando. Inotaridza yakajairika, rombo, kana chengetedzo nhanho yekutengeserana uye kana kutengeserana kuri kuwana data kana kuwana yekuraira.
Yakagadziriswa ku3'b000 kune Yakajairika, yakachengeteka kuwana data
Nyora kero inoshanda. Inoratidza iyo kero yekunyora inoshanda uye kutonga
ruzivo rwuripo:
1 = kero uye kudzora ruzivo rwuripo
0 = kero uye ruzivo rwekutonga harisipo. Kero uye ruzivo rwekutonga zvinoramba zvakadzikama kusvika kero yekubvuma chiratidzo, m_awready, yaenda HIGH.
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DDR AXI Arbiter
Zita rechiratidzo m_awready_i
Direction Input
Upamhi
Nyora Data Channel
m_wid_o
Output
[3:0]m_wdata_o m_wstrb_o
Output Output
[(g_AXI_DWIDTH-1):0]AXI_DWDITH parameter[7:0]
m_wlast_o m_wvalid_o
Output Output
m_wready_i
Input
Nyora Response Channel Signals
m_bid_i
Input
[3:0]m_bresp_i m_bvalid_i
Input
[1:0]Input
m_bready_o
Output
Tsanangudzo Nyora kero yakagadzirira. Zvinoratidza kuti muranda akagadzirira kugamuchira kero uye anosanganisirwa masaini ekudzora:
1 = muranda akagadzirira
0 = muranda asina kugadzirira.
Nyora ID tag. ID tag yekunyora data transfer. Iko m_wid kukosha inofanira kufanana nem_awid kukosha kwekunyora kwekutengeserana. Nyora data
Nyora strobes. Ichi chiratidzo chinoratidza kuti ndedzipi nzira dzekugadzirisa mundangariro. Pane imwe yekunyora strobe kune ese masere mabhiti ekunyora data bhasi Nyora pekupedzisira. Kuchinjisa kwekupedzisira mukuputika kwekunyora. Nyora zvinoshanda. Yakakodzera kunyora data uye strobes zviripo:
1 = nyora data uye strobes iripo
0 = nyora data uye strobes haisipo. Nyora wakagadzirira. Muranda anogona kugamuchira iyo data yekunyora: 1 = muranda akagadzirira
0 = muranda asina kugadzirira.
Mhinduro ID. The identification tag yemhinduro yekunyora. Iko m_bid kukosha kunofanirwa kuenderana nem_awid kukosha kwekunyora kutengeserana uko muranda ari kupindura. Nyora mhinduro. Mamiriro ekunyora kutengeserana. Mhinduro dzinotenderwa ndeidzi OKAY, EXOKAY, SLVERR, uye DECERR. Nyora mhinduro inoshanda. Mhinduro yekunyora iripo iripo:
1 = nyora mhinduro iripo
0 = nyora mhinduro haisipo. Mhinduro yakagadzirira. Master anogona kugamuchira ruzivo rwemhinduro.
1 = tenzi akagadzirira
0 = tenzi haana kugadzirira.
Iyi inotevera nhamba inoratidza yemukati block dhizaini yeDDR AXI arbiter.
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DDR AXI Arbiter
Iyi inotevera nhamba inoratidza yemukati block dhizaini yeDDR AXI arbiter. Mufananidzo 4 · Internal Block Diagram yeDDR AXI Arbiter
Imwe neimwe chiteshi chekuverenga inokonzereswa kana ikawana chiratidzo chepamusoro chekuisa pane kuverenga_req_(x)_i yekuisa. Zvadaro
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Imwe neimwe chiteshi chekuverenga inokonzereswa kana ikawana chiratidzo chepamusoro chekuisa pane kuverenga_req_(x)_i yekuisa. Zvadaro sampLes iyo yekutanga AXI kero uye mabyte ekuverenga mapimendi ayo ari kupinza kubva kune ekunze tenzi. Iyo chiteshi inobvuma nyanzvi yekunze nekuchinja read_ack_(x)_o. Iyo chiteshi inobata zvinopinza uye inogadzira inodiwa AXI kutengeserana kuverenga iyo data kubva kuDDR-SDRAM. Iyo data yakaverengerwa mu64-bit AXI fomati inochengetwa mumukati buffer. Mushure mekunge iyo data inodiwa yaverengwa uye yakachengetwa mukati memukati buffer, iyo un-packer module inogoneswa. Iyo un-packer module inoburitsa yega yega 64-bit izwi mune inobuda data bit kureba kunodiwa kune iyo chaiyo chiteshi che ex.ample kana chiteshi chakagadziriswa se 32-bit yakabuda data upamhi, rimwe nerimwe 64-bit izwi rinotumirwa seaviri 32-bit inobuda data mazwi. Kune chiteshi 1 inova 24-bit chiteshi, iyo un-packer inoburitsa yega yega 64-bit izwi mune 24-bit data inobuda. Sezvo 64 isiri kuwanda kwemakumi maviri nemana, iyo un-packer yekuverenga chiteshi 24 inosanganisa boka remashoko matatu 1-bit kuti igadzire sere 64-bit data mazwi. Izvi zvinoisa chisungo pakuverenga chiteshi 24 kuti data byte yakakumbirwa natenzi wekunze inofanira kupatsanurwa ne1. Verenga chiteshi 8, 2, uye 3 inogona kugadziridzwa se4-bit, 8bit, uye 24-bit data upamhi, iyo zvakatemwa ne g_RD_CHANNEL(X) _VIDEO_DATA_WIDTH yepasirese gadziriso parameter. Kana ivo vakagadziriswa se32-bit, iyo yataurwa pamusoro inomanikidza ichashanda kune yega yega zvakare. Asi kana vakagadzirirwa se24-bit kana 8-bit, hapana chinomanikidzika sekuti 32 inowandisa 64 uye 32. Muzviitiko izvi, izwi rimwe nerimwe re 8-bit rinobudiswa mumashoko maviri e data 64-bit kana masere 32. -bit data mazwi.
Verenga Chiteshi 1 chinoburitsa 64-bit data mazwi akaverengwa kubva muDDR-SDRAM kuenda ku24-bit inobuda data mazwi mumabhechi e48 64-bit mazwi, ndipo pese panowanikwa mazwi makumi mana nemasere nemakumi matanhatu nenhatu mune yemukati buffer yekuverenga chiteshi 48, iyo un-packer inotanga kuiburitsa kuti ipe 64-bit data yakabuda. Kana iyo yakakumbirwa data byte kuverenga isingasviki 1 24-bit mazwi, iyo un-packer inogoneswa chete mushure mekunge data rakazara raverengwa kubva muDDR-SDRAM. Mumatanho matatu asara ekuverenga, iyo un-packer anotanga kutumira kuverenga data chete mushure mekunge nhamba yakazara yakakumbirwa yemabheti yaverengwa kubva kuDDR-SDRAM.
Kana chiteshi chekuverenga chakagadzirirwa 24-bit kubuda kwehupamhi, kero yekutanga kuverenga inofanira kuenderana ne24-bytes muganhu. Izvi zvinodikanwa kugutsa chisungo chekuti un-packer anoburitsa boka remashoko matatu 64-bit kuti abudise sere 24-bit mazwi ekubuda.
Yese machaneti ekuverenga anoburitsa iyo yakaverengwa yakaitwa goho kune yekunze tenzi mushure mekunge mabheti akakumbirwa atumirwa kuna tenzi wekunze.
Panyaya yekunyora chiteshi, tenzi wekunze anofanirwa kuisa iyo data inodiwa kune chaiyo chiteshi. Iyo yekunyora chiteshi inotora iyo data yekupinda uye inoaisa mu 64-bit mazwi uye inoachengeta mudura remukati. Mushure mekunge iyo data inodiwa yachengetwa, tenzi wekunze anofanira kupa chikumbiro chekunyora pamwe nekero yekutanga uye mabhayiti ekunyora. On sampnemazwi aya, nzira yekunyora inobvuma tenzi wekunze. Mushure meizvi, chiteshi chinoburitsa iyo AXI inonyora kutengeserana kunyora iyo yakachengetwa data muDDR-SDRAM. Yese nzira dzekunyora dzinoburitsa kunyorwa kwakaitwa kuburitsa kuna tenzi wekunze kana mabheti akakumbirwa anyorwa muDDR-SDRAM. Mushure mekunge chikumbiro chekunyora chapihwa kune chero chiteshi chekunyora, data nyowani haifanire kunyorwa mugwara rekunyora, kudzamara kutengeserana kwazvino kwaratidzwa nekusimbisa wr_done_(x)_o
Nyora machanera 1 uye 2 anogona kugadziridzwa se8-bit, 24-bit, uye 32-bit data wide, izvo zvinotsanangurwa neg_WR_CHANNEL(X)_VIDEO_DATA_WIDTH global configuration parameter. Kana akagadziridzwa se24bit, saka mabhayiti achanyorwa anofanira kunge akawanda sere sezvo mutakuri wemukati anorongedza sere 24-bit data mazwi kuti abudise matatu 64-bit data mazwi. Asi kana vakagadziridzwa se8-bit kana 32-bit, hapana chinomanikidza chakadaro.
Kune 32-bit chiteshi, mashoma maviri 32-bit mazwi anofanira kuverengwa. Kune 8-bit chiteshi, mashoma 8-bit mazwi anoda kuverengerwa, nekuti hapana padding inopihwa nearbiter module. Mune ese machanera ekuverenga nekunyora, kudzika kwemukati mabuffers akawanda echiratidziro chakatwasuka upamhi. Iyo yemukati buffer kudzika inoverengerwa sezvizvi:
g_RD_CHANNEL(X)_HORIZONTAL_RESOLUTION* g_RD_CHANNEL(X)_VIDEO_DATA_WIDTH * g_RD_CHANNEL(X)_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Kupi, X = Nhamba yechiteshi
Iyo yemukati buffer hupamhi inotarwa neAXI data bhazi hupamhi kureva, gadziriso parameter
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Iyo yemukati buffer upamhi inotarwa neAXI data bhazi hupamhi kureva, configuration parameter g_AXI_DWIDTH.
Iyo AXI kuverenga nekunyora kutengeserana kunoitwa zvinoenderana neiyo ARM AMBA AXI yakatarwa. Saizi yekutengeserana kwega yega yekufambisa data inogadziriswa ku64-bit. Iyo block inogadzira AXI kutengeserana kweyakagadziriswa kuputika kureba kwe16 beats. Iyo block zvakare inotarisa kana chero kuputika kumwe kunoyambuka AXI kero muganhu we4 KByte. Kana kuputika kumwe kwakayambuka muganho we4 KByte, kuputika kunopatsanurwa kuita 2 kuputika pamuganhu we4 KByte.
3.3
Configuration Parameters
Tafura inotevera inonyora zvigadziriso zvimiro zvinoshandiswa mukushandiswa kwehardware yeDDR AXI Arbiter. Aya ndiwo generic paramita uye anogona kusiana zvichienderana nezvinodiwa zvekushandisa.
Tafura 2 · Configuration Parameters
Zita g_AXI_AWIDTH g_AXI_DWIDTH g_RD_CHANNEL1_AXI_BUFF_AWIDTH
g_RD_CHANNEL2_AXI_BUFF_AWIDTH
g_RD_CHANNEL3_AXI_BUFF_AWIDTH
g_RD_CHANNEL4_AXI_BUFF_AWIDTH
g_WR_CHANNEL1_AXI_BUFF_AWIDTH
g_WR_CHANNEL2_AXI_BUFF_AWIDTH
g_RD_CHANNEL1_HORIZONTAL_RESOLUTION g_RD_CHANNEL2_HORIZONTAL_RESOLUTION g_RD_CHANNEL3_HORIZONTAL_RESOLUTION g_RD_CHANNEL4_HORIZONTAL_RESOLUTION g_WR_CHANNEL1_HORIZONTAL_RESOLUTION g_RD_CHANNEL2_HORIZONTAL_RESOLUTION g_WR_CHANNEL1_HORIZONTAL_RESOLUTION_ RD_CHANNEL2_VIDEO_DATA_WIDTH g_RD_CHANNEL3_VIDEO_DATA_WIDTH g_RD_CHANNEL4_VIDEO_DATA_WIDTH g_RD_CHANNEL1_VIDEO_DATA_WIDTH g_WR_CHANNEL2_VIDEO_DATA_WIDTH g_WR_CHANNELD_CHANNELD_BUDTH_G_WR_CHANNELD_CHANNEL1 AGE
Tsanangudzo
AXI kero yehupamhi hwebhazi
AXI data bhazi upamhi
Kero yehupamhi hwebhazi yekuverenga Channel 1 yemukati buffer, inochengeta iyo AXI yekuverenga data.
Kero yehupamhi hwebhazi yekuverenga Channel 2 yemukati buffer, inochengeta iyo AXI yekuverenga data.
Kero yehupamhi hwebhazi yekuverenga Channel 3 yemukati buffer, inochengeta iyo AXI yekuverenga data.
Kero yehupamhi hwebhazi yekuverenga Channel 4 yemukati buffer, inochengeta iyo AXI yekuverenga data.
Kero bhazi upamhi hwekunyora Channel 1 yemukati buffer, iyo inochengeta iyo AXI kunyora data.
Kero bhazi upamhi hwekunyora Channel 2 yemukati buffer, iyo inochengeta iyo AXI kunyora data.
Vhidhiyo inoratidzira yakachinjika resolution yekuverenga Channel 1
Vhidhiyo inoratidzira yakachinjika resolution yekuverenga Channel 2
Vhidhiyo inoratidzira yakachinjika resolution yekuverenga Channel 3
Vhidhiyo inoratidzira yakachinjika resolution yekuverenga Channel 4
Vhidhiyo inoratidzira yakachinjika resolution yekunyora Channel 1
Vhidhiyo inoratidzira yakachinjika resolution yekunyora Channel 2
Verenga Channel 1 vhidhiyo inobuda bit wide
Verenga Channel 2 vhidhiyo inobuda bit wide
Verenga Channel 3 vhidhiyo inobuda bit wide
Verenga Channel 4 vhidhiyo inobuda bit wide
Nyora Channel 1 vhidhiyo Input bit width.
Nyora Channel 2 vhidhiyo Input bit width.
Hudzamu hwemukati buffer yekuverenga Channel 1 maererano nehuwandu hwekuratidzira mitsara yakachinjika. Kudzika kwebhafa ndiko g_RD_CHANNEL1_HORIZONTAL_RESOLUTION * g_RD_CHANNEL1_VIDEO_DATA_WIDTH * g_RD_CHANNEL1_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
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3.4
Zita g_RD_CHANNEL2_BUFFER_LINE_STORAGE g_RD_CHANNEL3_BUFFER_LINE_STORAGE g_RD_CHANNEL4_BUFFER_LINE_STORAGE g_WR_CHANNEL1_BUFFER_LINE_STORAGE g_WR_CHANNEL2_BUFFER_LINE_STORAGE
Tsanangudzo
Hudzamu hwemukati buffer yekuverenga Channel 2 maererano nehuwandu hwekuratidzira mitsara yakachinjika. Kudzika kwebhafa ndiko g_RD_CHANNEL2_HORIZONTAL_RESOLUTION * g_RD_CHANNEL2_VIDEO_DATA_WIDTH * g_RD_CHANNEL2_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Hudzamu hwemukati buffer yekuverenga Channel 3 maererano nehuwandu hwekuratidzira mitsara yakachinjika. Kudzika kwebhafa ndiko g_RD_CHANNEL3_HORIZONTAL_RESOLUTION * g_RD_CHANNEL3_VIDEO_DATA_WIDTH * g_RD_CHANNEL3_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Hudzamu hwemukati buffer yekuverenga Channel 4 maererano nehuwandu hwekuratidzira mitsara yakachinjika. Kudzika kwebhafa ndiko g_RD_CHANNEL4_HORIZONTAL_RESOLUTION * g_RD_CHANNEL4_VIDEO_DATA_WIDTH * g_RD_CHANNEL4_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Hudzamu hwemukati buffer yekunyora Channel 1 maererano nehuwandu hwekuratidzira mitsara yakachinjika. Kudzika kwebhafa ndiko g_WR_CHANNEL1_HORIZONTAL_RESOLUTION * g_WR_CHANNEL1_VIDEO_DATA_WIDTH * g_WR_CHANNEL1_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Hudzamu hwemukati buffer yekunyora Channel 2 maererano nehuwandu hwekuratidzira mitsara yakachinjika. Kudzika kwebhafa ndiko g_WR_CHANNEL2_HORIZONTAL_RESOLUTION * g_WR_CHANNEL2_VIDEO_DATA_WIDTH * g_WR_CHANNEL2_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Madhiyamu enguva
Iyi inotevera nhamba inoratidza kubatana kwekuverenga nekunyora chikumbiro chekumisikidza, kutanga kero yendangariro, mabhayiti ekuverenga kana kunyora mameseji kubva kune ekunze tenzi, kuverenga kana kunyora kubvuma, uye kuverenga kana kunyora kupedzisa zvinopihwa nearbiter.
Mufananidzo 5 · Dhiagiramu Yenguva yeZviratidzo Zvinoshandiswa Mukunyora / Kuverenga kuburikidza neAXI Interface
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Iyi inotevera nhamba inoratidza kubatana pakati pekunyora data kupinza kubva kune yekunze tenzi pamwe neiyo data yekuisa inoshanda kune ese maviri ekunyora chiteshi. Mufananidzo 6 · Dhiagiramu Yenguva Yekunyora muKuchengeta Kwemukati
Mufananidzo unotevera unoratidza kubatana pakati pekuverengwa kwedata kunobuda kuna tenzi wekunze pamwe chete nekubuda kwedata kunoshanda kune ese akaverengerwa machannel 2, 3, uye 4. Mufananidzo 7 · Nguva yedhiyagiramu yeData Yakagamuchirwa kuburikidza neDDR AXI Arbiter yeKuverenga Channels 2, 3. ,uye 4
Mufananidzo unotevera unoratidza kubatana kuri pakati pezvakaverengwa data kubva kuChannel 1 yaverengwa apo g_RD_CHANNEL 1_HORIZONTAL_RESOLUTION yakakura kudarika 128 (pano = 256). Mufananidzo 8 · Dhiagiramu Yenguva yeData Yakagamuchirwa kuburikidza neDDR AXI Arbiter Read Channel 1 (inopfuura 128 bytes)
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Mufananidzo unotevera unoratidza kubatana kuri pakati pezvakaverengwa data rakabuda paChannel 1 apo g_RD_CHANNEL 1_HORIZONTAL_RESOLUTION iri pasi kana kuenzana ne128 (panyaya iyi = 64). Mufananidzo 9 · Dhiagiramu Yenguva yeData Yakagamuchirwa kuburikidza neDDR AXI Arbiter Read Channel 1 (isingasviki kana yakaenzana ne128 bytes)
3.5
Testbench
Testbench inopihwa kutarisa kushanda kweDDR Arbiter core. Tafura inotevera inonyora ma parameter anogona kugadzirwa zvinoenderana nekushandisa.
Tafura 3 · Testbench Configuration Parameters
Zita IMAGE_1_FILE_NAME IMAGE_2_FILE_NAME g_DATA_WIDTH WIDTH HEIGHT
Tsanangudzo Input file zita remufananidzo uchanyorwa nekunyora chiteshi 1 Input file zita remufananidzo kuti rinyorwe nekunyora chiteshi 2 Vhidhiyo data yakafara yekuverenga kana kunyora chiteshi Kugadziriswa kwechifananidzo kunyorwa uye kuverengerwa nekunyora uye kuverenga chiteshi Kugadziriswa kwechifananidzo kunyorwa nekuverengwa nekunyora uye kuverenga. channels
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Matanho anotevera anotsanangura mashandisiro anoita testbench kutevedzera musimboti kuburikidza neLibero SoC. 1. Mufafitera reDesign Flow, tinya kurudyi Gadzira SmartDesign wobva wadzvanya Run kuti ugadzire SmartDesign.
Mufananidzo 10 · Gadzira SmartDesign
2. Isa zita rekugadzirwa kutsva se video_dma muGadzira Itsva SmartDesign dialog box uye tinya OK. A SmartDesign inogadzirwa, uye canvas inoratidzwa kurudyi kweDesign Flow pane.
Mufananidzo 11 · Kutumidza SmartDesign
3. Muhwindo reCatalog, wedzera Solutions-Vhidhiyo uye dhonza-uye-donhedza SF2 DDR Memory Arbiter muSmartDesign canvas.
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Mufananidzo 12 · DDR Memory Arbiter muLibero SoC Catalog
Iyo DDR Memory Arbiter Core inoratidzwa, sezvinoratidzwa mumufananidzo unotevera. Dzvanya kaviri pakati kuti ugadzirise arbiter kana zvichidikanwa.
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Mufananidzo 13 · DDR Memory Arbiter Core muSmartDesign Canvas
4. Sarudza zvese zviteshi zvepakati uye tinya-kurudyi wobva wadzvanya Promote to Top Level, sezvakaratidzwa mu
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4. Sarudza zvese zviteshi zvepakati uye tinya-kurudyi uye wobva wadzvanya Kurudzira Kumusoro Wepamusoro, sezvakaratidzwa mumufananidzo unotevera. Mufananidzo 14 · Kurudzira kuPamusoro Level Option
Ita shuwa yekusimudzira madoko ese kusvika padanho repamusoro usati wadzvanya iyo gadzira chikamu icon mubhara rekushandisa.
5. Dzvanya chiratidzo cheGadzira Chikamu muSmartDesign toolbar, sezvinoratidzwa mumufananidzo unotevera.
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5. Dzvanya chiratidzo cheGadzira Chikamu muSmartDesign toolbar, sezvinoratidzwa mumufananidzo unotevera. Iyo SmartDesign chikamu chinogadzirwa. Mufananidzo 15 · Gadzira Chikamu
6. Enda ku View > Windows > Files. The Files dialog box inoratidzwa. 7. Tinya-kurudyi folda yekutevedzera uye tinya Import Files, sezvinoratidzwa mumufananidzo unotevera.
Mufananidzo 16 · Import File
8. Kupinza mufananidzo kukurudzira file, fambisa uye unza imwe yeinotevera files uye tinya Open.
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8. Kupinza mufananidzo kukurudzira file, fambisa uye unza imwe yeinotevera files uye tinya Open. a. A sample RGB_in.txt file inopihwa ne testbench munzira inotevera:
..Project_namecomponentMicrosemiSolutionCore ddr_memory_arbiter 2.0.0Stimulus
Kupinza kunze sample test bhenji rekuisa mufananidzo, tarisa kune iyo sample testbench yekuisa mufananidzo file, wobva wadzvanya Vhura, sezvinoratidzwa pamufananidzo unotevera. Mufananidzo 17 · Input Image File Selection
b. Kuti utore kunze mufananidzo wakasiyana, tarisa kune folda ine mufananidzo waunoda file, wobva wadzvanya Open. Mufananidzo wakatengwa kunze kwenyika file yakanyorwa pasi pekufananidza dhairekitori, sezvinoratidzwa mumufananidzo unotevera. Mufananidzo 18 · Input Image File muSimulation Directory
9. Kupinza iyo ddr BFM files. Piri files izvo zvakaenzana ne
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9. Kupinza iyo ddr BFM files. Piri files ayo akaenzana neDDR BFM — ddr3.v uye ddr3_parameters.v anopiwa testbench panzira inotevera: ..Project_namecomponentMicrosemiSolutionCoreddr_memory_arbiter 2.0.0Stimulus. Tinya-kurudyi folda yekusimudzira uye sarudza Import Files sarudzo, wobva wasarudza BFM yambotaurwa files. Iyo yakatorwa kunze kwenyika DDR BFM files akanyorwa pasi pekukurudzira, sezvinoratidzwa mumufananidzo unotevera. Mufananidzo 19 · Inotengeswa kunze kwenyika File
10. Enda ku File > Import > Zvimwe. The Import Files dialog box inoratidzwa. Mufananidzo 20 · Import Testbench File
11. Isai testbench uye chikamu cheMSS files (top_tb.cxf, mss_top_sb_MSS.cxf, mss_top.cxf, uye mss
..Project_namecomponentMicrosemiSolutionCoreddr_memory_arbiter 2.0.0Stimulus
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Mufananidzo 21 · Import Testbench uye MSS Chikamu Files
Mufananidzo 22 · top_tb Yakagadzirwa
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3.5.1
Kutevedzera MSS SmartDesign
Mirayiridzo inotevera inotsanangura maitiro ekutevedzera MSS SmartDesign:
1. Dzvanya iyo Dhizaini Hierarchy tab uye sarudza Chikamu kubva pane show yekudonha-pasi runyorwa. Iyo yakaunzwa kunze MSS SmartDesign inoratidzwa.
2. Tinya-kurudyi mss_top pasi peBasa wodzvanya Vhura Chikamu, sezvakaratidzwa mumufananidzo unotevera. Iyo mss_top_sb_0 chikamu chinoratidzwa.
Mufananidzo 23 · Vhura Chikamu
3. Tinya-kurudyi chikamu mss_top_sb_0 wobva wadzvanya Gadzirisa, sezvinoratidzwa mumufananidzo unotevera.
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3. Tinya-kurudyi chikamu mss_top_sb_0 wobva wadzvanya Gadzirisa, sezvinoratidzwa mumufananidzo unotevera. Mufananidzo 24 · Gadzira Chikamu
Iwindo reMSS Configuration rinoratidzwa, sezvinoratidzwa mumufananidzo unotevera. Mufananidzo 25 · MSS Configuration Window
4. Dzvanya Next kuburikidza nematabo ose ekugadzirisa, sezvinoratidzwa mumufananidzo unotevera.
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4. Dzvanya Next kuburikidza nematabo ose ekugadzirisa, sezvinoratidzwa mumufananidzo unotevera. Mufananidzo 26 · Configuration Tabs
Iyo MSS inogadziriswa mushure meInterrupts tab yagadziriswa. Nhamba inotevera inoratidza kufambira mberi kweMSS Configuration. Mufananidzo 27 · MSS Configuration Window After Configuration
5. Dzvanya Next mushure mekugadzirisa kwapera. Iyo Memory Mepu hwindo inoratidzwa, sezvakaratidzwa mumufananidzo unotevera.
Mufananidzo 28 · Memory Mepu
6. Dzvanya Finish.
7. Dzvanya Gadzira Chikamu kubva kuSmartDesign toolbar kuti ugadzire MSS, sezvinoratidzwa mu
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7. Dzvanya Gadzira Chikamu kubva kuSmartDesign toolbar kuti ubudise MSS, sezvinoratidzwa mumufananidzo unotevera. Mufananidzo 29 · Gadzira Chikamu
8. Muhwindo reDesign Hierarchy, tinya-kurudyi mss_top pasi peBasa uye tinya Set As Root, sezvinoratidzwa mumufananidzo unotevera. Mufananidzo 30 · Isa MSS seMudzi
9. MuDzaini Inoyerera hwindo, wedzera Verify Pre-synthesized Design pasi peGadzira Dhizaini, tinya-kurudyi
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9. Mufafitera reDesign Flow, wedzera Verify Pre-synthesized Design pasi peGadzira Dhizaini, tinya-kurudyi Simulate uye baya Vhura Interactively. Inotevedzera iyo MSS. Mufananidzo 31 · Tevedzera iyo Pre-synthesized Design
10. Tinya Kwete kana meseji yekuzivisa inoratidzwa kubatanidza Testbench stimulus neMSS. 11. Vhara hwindo reModelsim mushure mokunge kuenzanisa kwapera.
Mufananidzo 32 · Window yekufananidza
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3.5.2
Simulating Testbench
Mirayiridzo inotevera inotsanangura maitiro ekutevedzera testbench:
1. Sarudza top_tb SmartDesign Testbench wobva wadzvanya Gadzira Chikamu kubva kuSmartDesign toolbar kuti ubudise testbench, sezvinoratidzwa pamufananidzo unotevera.
Mufananidzo 33 · Kugadzira Chikamu
2. Muhwindo reStimulus Hierarchy, tinya-kurudyi top_tb (top_tb.v) testbench file wobva wadzvanya Set as active stimulus. Iyo yekurudziro inobatiswa yetop_tb testbench file.
3. Muhwindo reStimulus Hierarchy, tinya-kurudyi top_tb (
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DDR AXI Arbiter
3. Muhwindo reStimulus Hierarchy, tinya-kurudyi top_tb (top_tb.v) testbench file uye tinya Vhura Interactively kubva Simulate Pre-Synth Dhizaini. Izvi zvinotevedzera musimboti wefuremu imwe chete. Mufananidzo 34 · Simulating Pre-Synthesis Design
4. Kana simulation ichikanganiswa nekuda kweiyo runtime muganhu muDO file, shandisa run -all command kupedzisa simulation. Mushure mekunge simulation yapera, famba uchienda View > Files > simulation ku view mufananidzo webhenji rekubuda file mune yekufananidza folda.
Kubuda kwesimulation mavara akaenzana nefuremu imwe chete yemufananidzo, anochengetwa muRead_out_rd_ch(x).txt text file zvichienderana nechani yekuverenga yakashandiswa. Izvi zvinogona kushandurwa kuita mufananidzo uye kuenzaniswa nemufananidzo wekutanga.
3.6
Resource Utilization
Iyo DDR Arbiter block inoshandiswa paM2S150T SmartFusion®2 System-on-Chip (SoC) FPGA mu
FC1152 package) uye PolarFire FPGA (MPF300TS_ES - 1FCG1152E package).
Tafura 4 · Resource Utilization yeDDR AXI Arbiter
Resource DFFs 4-inopinza LUTs MACC RAM1Kx18
Kushandisa 2992 4493 0 20
(Kune:
g_RD_CHANNEL(X)_HORIZONTAL_RESOLUTION = 1280
g_RD_CHANNEL(X)_BUFFER_LINE_STORAGE = 1
g_WR_CHANNEL(X)_BUFFER_LINE_STORAGE = 1
g_AXI_DWIDTH = 64
g_RD_CHANNEL(X)_VIDEO_DATA_WIDTH = 24
RAM64x18
g_WR_CHANNEL(X)_VIDEO_DATA_WIDTH = 32) 0
UG0644 Mushandisi Yekudzokorodza 5.0
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DDR AXI Arbiter
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50200644
UG0644 Mushandisi Yekudzokorodza 5.0
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Zvinyorwa / Zvishandiso
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Microchip UG0644 DDR AXI Arbiter [pdf] Bhuku reMushandisi UG0644 DDR AXI Arbiter, UG0644, DDR AXI Arbiter, AXI Arbiter |
