MICROCHIP H.264 4K I-Frame Encoder IP Cores

Nhanganyaya

H.264 chiyero chevhidhiyo chakakurumbira kudzvanya vhidhiyo yedhijitari. Iyo inozivikanwa zvakare seMPEG-4 Part10 kana Yepamberi Vhidhiyo Coding (MPEG-4 AVC). H.264 inoshandisa block-wise maitiro ekudzvanya vhidhiyo apo saizi yebhuroko inotsanangurwa se 16 x 16 uye bhuroko rakadaro rinonzi macro block. Iyo compression standard inotsigira akasiyana profiles inotsanangura chiyero chekumanikidza uye kuoma kwekuita. Vhidhiyo mafuremu ekumanikidzwa anobatwa seI-Frame, P-Frame, uye B-Frame. Iyo I-Frame intra-coded furemu uko kudzvanywa kunoitwa nekushandisa ruzivo rwuri mukati mefuremu. Hapana mamwe mafuremu anodiwa kuti atore iyo I-Frame. A P-Frame inomanikidzwa nekushandisa shanduko maererano neyakatangira furemu inogona kuve I-Frame kana P-Frame. Kutsikirirwa kweB-Frame kunoitwa nekushandisa shanduko yekufamba neruremekedzo kune ese ekutanga furemu uye inouya furemu. Iyo I-Frame compression process ine ina stages-Intra kufanotaura, Integer shanduko, Quantization, uye Entropy encoding. H.264 inotsigira marudzi maviri eencoding—Context Adaptive Variable Length Coding (CAVLC) uye Context Adaptive Binary Arithmetic Coding (CABAC). Iyo yazvino vhezheni yeIP inoshandisa Baseline profile uye inoshandisa CAVLC ye entropy encoding. Zvakare, iyo IP inotsigira encoding yeI-Frames chete kusvika ku4K resolution.

Features

H.264 I-Frame Encoder inotsigira chinhu chakakosha chinotevera:

• Inoshandisa Kudzvanya paYCbCr 420 Vhidhiyo Format
• Tinotarisira Kupinza muYCbCr 422 Vhidhiyo Format
• Inotsigira 8 mabhiti eChimwe Chinhu (Y, Cb, uye Cr)
• Inotsigira ITU-T H.264 Annex B Inopindirana neNAL byte Stream Output
• Standalone Operation, CPU, kana processor Rubatsiro Haidiwe
• Mushandisi Configurable Hunhu Factor QP Panguva Yekumhanya Nguva
• Kuverenga paChiyero che 1 pixel per Clock
• Inotsigira Kudzvanya kusvika Kugadziriswa kwe4K (3840 × 2160) 60 fps
• Minimal Latency (252 μs yeHD yakazara kana mitsetse gumi neminomwe yakachinjika)
• Inotsigira 2 uye 4 zvimedu

Mhuri Dzakatsigirwa
H.264 4K I-Frame Encoder inotsigira mhuri dzinotevera:

• PolarFire® SoC FPGA
• PolarFire FPGA

Hardware Implementation

Nhamba inotevera inoratidza H.264 4K I-Frame Encoder IP block diagram.
Mufananidzo 1-1. H.264 4K I-Frame Encoder IP Block Diagram

Zvinopinza uye Zvinobuda
Tafura inotevera inoronga zviteshi zvekupinza uye zvinobuda zveH.264 4K I-Frame Encoder IP.
Tafura 1-1. Zvekupinda nezvinobuda zveH.264 4K I-Frame Encoder IP

Zita rechiratidzo	Direction	Upamhi	Tsanangudzo
RESET_N	Input	1	Active-low Asynchronous reset chiratidzo kune dhizaini.
PIX_CLK_I	Input	1	wachi yekuisa iyo mapixels anouya ari sampakatungamirirwa.
DDR_CLK_I	Input	1	Wachi kubva kuDDR memory controller.
HRES_I	Input	16	Horizontal resolution yemufananidzo wekupinda. Inofanira kuva yakawanda ye16.
VRES_I	Input	16	Kugadziriswa kwemufananidzo wekupinda. Inofanira kuva yakawanda ye16.
QP_I	Input	6	Quality factor yeH.264 quantization. Ukoshi hunotangira pa 0 kusvika pa 51 apo 0 inomiririra hukuru hwepamusoro nekutsikirira kwakadzikira uye 51 inomiririra kudzvanya kwepamusoro.
DATA0_O	Output	16	H.264 Slice0 yakavharwa data yakabuda ine NAL unit, Slice header, SPS, PPS, uye encoded data ye macro blocks.
DATA_VALID0_O	Output	1	Chiratidzo chinoratidza Slice0 data yakavharwa inoshanda.
DATA1_O	Output	16	H.264 Slice1 yakavharwa data yakabuda ine Slice header, uye encoded data yemacro blocks.
DATA_VALID1_O	Output	1	Chiratidzo chinoratidza Slice1 data yakavharwa inoshanda.
DATA2_O	Output	16	H.264 Slice2 yakavharwa data yakabuda ine Slice header, uye encoded data yemacro blocks.
DATA_VALID2_O	Output	1	Chiratidzo chinoratidza Slice2 data yakavharwa inoshanda.

………..enderera mberi
Zita rechiratidzo	Direction	Upamhi	Tsanangudzo
DATA3_O	Output	16	H.264 Slice3 yakavharwa data yakabuda ine Slice header, uye encoded data yemacro blocks.
DATA_VALID3_O	Output	1	Chiratidzo chinoratidza Slice3 data yakavharwa inoshanda.
DDR_LINE_GAP_I	Input	16	Mutsetse mukaha pakati pemitsetse yemifananidzo yakachinjika muDDR memory.
FRAME_START_ADDR_I	Input	7/8	DDR furemu buffer kero. 7 bits kana iyo gap inogadzirirwa 32 MB. 8 bits kana iyo gap yefuremu inogadzirirwa 16 MB.
FRAME_END_O	Output	1	Kupera kweH.264 bit stream kune furemu.
Verenga Channel 0 Arbiter Interface Ports
RDATA0_I	Input	Input data wide	Verenga data kubva kune arbiter
RVALID0_I	Input	1	Verenga data inoshanda kubva kune arbiter
ARREADY0_I	Input	1	Arbiter kubvuma
BUSER0_I	Input	1	Verenga kupedza
ARADDR0_O	Output	32	DDR kero kubva panofanira kutanga kuverenga
ARVALID0_O	Output	1	Verenga chikumbiro kune arbiter
ARSIZE0_O	Output	8	Verenga kuputika saizi
Verenga Channel 1 Arbiter Interface Ports
RDATA1_I	Input	Input data wide	Verenga data kubva kune arbiter
RVALID1_I	Input	1	Verenga data inoshanda kubva kune arbiter
ARREADY1_I	Input	1	Arbiter kubvuma
BUSER1_I	Input	1	Verenga kupedza
ARADDR1_O	Output	32	DDR kero kubva panofanira kutanga kuverenga
ARVALID1_O	Output	1	Verenga chikumbiro kune arbiter
ARSIZE1_O	Output	8	Verenga kuputika saizi
Verenga Channel 2 Arbiter Interface Ports
RDATA2_I	Input	Input data wide	Verenga data kubva kune arbiter
RVALID2_I	Input	1	Verenga data inoshanda kubva kune arbiter
ARREADY2_I	Input	1	Arbiter kubvuma
BUSER2_I	Input	1	Verenga kupedza
ARADDR2_O	Output	32	DDR kero kubva panofanira kutanga kuverenga
ARVALID2_O	Output	1	Verenga chikumbiro kune arbiter
ARSIZE2_O	Output	8	Verenga kuputika saizi
Verenga Channel 3 Arbiter Interface Ports
RDATA3_I	Input	Input data wide	Verenga data kubva kune arbiter
RVALID3_I	Input	1	Verenga data inoshanda kubva kune arbiter

………..enderera mberi
Zita rechiratidzo	Direction	Upamhi	Tsanangudzo
ARREADY3_I	Input	1	Arbiter kubvuma
BUSER3_I	Input	1	Verenga kupedza
ARADDR3_O	Output	32	DDR kero kubva panofanira kutanga kuverenga
ARVALID3_O	Output	1	Verenga chikumbiro kune arbiter
ARSIZE3_O	Output	8	Verenga kuputika saizi

Configuration Parameters
Tafura inotevera inoronga tsananguro yezvakajairwa zvigadziriso parameters anoshandiswa mukuitwa kwehardware yeH.264 4K I-Frame Encoder, iyo inogona kusiyanisa zvichienderana nezvinodiwa zvekushandisa.
Tafura 1-2. H.264 4K I-Frame Encoder Configuration Parameters

Zita	Tsanangudzo
16x16_DC_INTRA_PREDICTION	Sarudzo yekugonesa iyo 16 x 16 intra dc kufanotaura pamwe ne4 x 4 intra dc kufanotaura.
NUM_SLICES	Sarudza zvidimbu zviviri kutsigira 2K pamakumi matatu fps. Sarudza zvidimbu zvina kutsigira 4K pa30 fps.
DDR_AXI_DATA_WIDTH	Sarudza iyo DATA hupamhi hwekuverenga chiteshi, iyo inofanirwa kuve yakabatana nevhidhiyo arbiter IP.
FRAME_GAP	Sarudza furemu buffer size. Kune 4K sarudza 32 MB.

IP Configurator
Nhamba inotevera inoratidza H.264 4K I-Frame Encoder IP configurator.

Mufananidzo 1-2. IP Configuration

Hardware Implementation of H.264 4K I-Frame Encoder IP
Iyo H.264 4K I-Frame Encoder IP inokamura furemu yega yega kuita 2/4 zvidimbu nemaencodes uchishandisa encoder yechidimbu. Iyo DDR yekuverenga logic inotarisira iyo furemu data muDDR ndangariro seYCbCr 422 fomati. Mutsetse wemutsetse uri pakati pemutsara wese wakachinjika wefuremu muDDR ndangariro unofanirwa kutsanangurwa kuburikidza neDDR_LINE_GAP_I yekuisa. IP inoshandisa 422 mafomati sekuisa uye inoshandisa compression mu420 mafomati. Iyo Slice0 inobuda zvakare ine SPS uye PPS musoro. Zvese zvimedu bit stream zvinopihwa zvakasiyana. Zvose zvimedu bit stream kubatanidza pamwe chete inova yekupedzisira H.264 bit stream. Nhamba inotevera inoratidza H.264 4K I-Frame encoder IP block diagram.
Mufananidzo 1-3. H.264 4K I-Frame Encoder IP Block Diagram

Mufananidzo unotevera unoratidza dhayagiramu encoder block.

Mufananidzo 1-4. Slice Encoder Block Diagram

Dhizaini Tsananguro Slice Encoder
Ichi chikamu chinotsanangura akasiyana emukati mamodule eiyo slice encoder.
16 x 16 Matrix Framer
Iyi module inogadzira 16 x 16 macro blocks yeY chikamu maererano neH.264 tsanangudzo. Mabhafa emutsetse anoshandiswa kuchengeta mitsara gumi nematanhatu yakachinjika yemufananidzo wekupinza, uye 16 x 16 matrix inogadzirwa pachishandiswa mashift register.
8 x 8 Matrix Framer
Iyi module inogadzira 8 x 8 macro blocks echikamu cheC sekuenderana neH.264 mafomati mazana mana nemakumi maviri. Mabhafa emutsetse anoshandiswa kuchengeta mitsetse misere yakachinjika yemufananidzo wekupinza, uye 420 x 8 matrix inogadzirwa pachishandiswa mashift register. Kubva pa8 x 16 matrix, iyo Cb neCr zvikamu zvakapatsanurwa kugadzira imwe neimwe 8 x 16 matrix.
4 x 4 Matrix Framer
Iyo integer shanduko, quantization, uye CAVLC encoding inoshanda pane 4 x 4 sub-block mukati me macroblock. Iyo 4 x 4 matrix framer inogadzira 4 x 4 sub-block kubva pa16 x 16 kana 8 x 8 macroblock. Iyi jenareta yematrix inotenderera nepakati pese-zvivharo zvemacroblock isati yaenda kune inotevera macroblock.
Intra Prediction
H.264 inoshandisa dzakasiyana-siyana intra-prediction modes kuderedza ruzivo mu 4 x 4 block. Iyo intra-prediction block muIP inoshandisa chete 4 x 4 kana 16 x 16 DC kufanotaura. 16 x 16 inoshandiswa kuQP tsika dzinopfuura 35 kana 16 x 16 intra-DC kufanotaura kuchigoneswa muIP configurator. Chikamu cheDC chinoverengerwa kubva kumusoro chiri padyo uye chasara 4 x 4 kana 16 x 16 zvidhinha.
Integer Shanduko
H.264 inoshandisa integer discrete cosine shanduko panogoverwa macoefficients pane integer transform matrix uye quantization matrix zvekuti hapana kuwanda kana kupatsanurwa mukushandurwa kweinhamba. Nhamba inoshandura stage inoshandisa shanduko uchishandisa shift uye kuwedzera mashandiro.
Quantization
Iyo quantization inowanza imwe neimwe inobuda yeakazara shanduko ine predetermined quantization kukosha kunotsanangurwa neQP mushandisi wekuisa kukosha. Nhamba ye QP kukosha inobva ku0 kusvika 51. Chero kukosha kudarika 51 ndiko clamped kusvika 51. Yakaderera QP kukosha inoreva kudzvanya kwakaderera uye mhando yepamusoro uye zvakasiyana.
CAVLC
H.264 inoshandisa marudzi maviri eentropy encoding—Context Adaptive Variable Length Coding (CAVLC) uye Context Adaptive Binary Arithmetic Coding (CABAC). Iyo IP inoshandisa CAVLC yekukodha iyo quantized inobuda.
Musoro jenareta
Iyo yemusoro jenareta block inogadzira iyo block misoro, zvimedu misoro, Sequence Parameter Set (SPS), Mufananidzo Parameter Set (PPS), uye Network Abstraction Layer (NAL) unit zvichienderana nemuenzaniso wevhidhiyo furemu.
H.264 Stream Jenareta
H.264 stream generator block inosanganisa CAVLC inobuda pamwe chete nemusoro kuti igadzire encoded inobuda maererano neH.264 standard format.

 

Testbench

Testbench inopiwa kutarisa kushanda kweH.264 4K I-Frame Encoder IP.
Simulation
Iyo simulation inoshandisa 432 x 240 mufananidzo muYCbCr422 fomati inomiririrwa nembiri. files, imwe neimwe yeY uye C sekuisa uye inogadzira H.264 ine 4 zvimedu file fomati ine mafuremu maviri.
Matanho anotevera anotsanangura maitiro ekutevedzera musimboti uchishandisa testbench:

1. Enda kuLibero® SoC Catalog > View > Windows > Catalog, uye wobva wawedzera Solutions-Vhidhiyo. Baya kaviri H264_4K_Iframe_Encoder, wobva wadzvanya OK. H264_4K_Iframe-Encoder IP inoonekwa pane SmartDesign canvas.
   Mufananidzo 2-1. H.264 4K I-Frame Encoder IP Core muLibero® SoC Catalog
2. Enda kune Files tab uye sarudza simulation> Ngenisa Files.
   Mufananidzo 2-2. Import Files
3. Ngenisa kunze H264_sim_data_in_y.txt, H264_sim_data_in_c.txt, uye H264_refOut.txt files kubva munzira inotevera: ..\ \ chikamu\Microsemi\SolutionCore\ H264_4K_Iframe_Encoder\ \Stimulus.
4. Kupinza zvakasiyana file, tsvaga folda ine zvinodiwa file, wobva wadzvanya Open. The imported file yakanyorwa pasi pekufananidza, ona mufananidzo unotevera.
   Mufananidzo 2-3. Kubva kunze kwenyika Files
5. Enda kune Dhizaini Hierarchy tebhu uye tinya kurudyi paH264_4K_Iframe_Enc_C0 uye sarudza Set SeMudzi. Mufananidzo 2-4. Set SeMudzi
6. Enda kune Stimulus Hierarchy tab uye sarudza H264_4K_Iframe_Encoder_tb (H264_4K_Iframe_Encoder_tb. v) > Simulate Pre-Synth Design > Vhura Interactively. IP inofananidzwa nemafuremu maviri. Mufananidzo 2-5. Simulating Pre-Synthesis Dhizaini
7. ModelSim inotanga ne testbench file sezvinoratidzwa mumufananidzo unotevera.

Mufananidzo 2-6. ModelSim Simulation Window

Zvakakosha: Kana simulation ikavhiringwa nekuda kwemuganho wenguva yekumhanya unotsanangurwa mu.do file, shandisa run -all command kupedzisa simulation.

License

• H.264 4K I-Frame Encoder IP inopihwa chete mufomu yakavharidzirwa pasi perezinesi.
• Encrypted RTL source code irezinesi rakakiiwa, rinofanira kutengwa zvakasiyana. Iwe unogona kuita simulation, synthesis, dhizaini, uye kuronga iyo Field Programmable Gate Array (FPGA) silicon uchishandisa Libero dhizaini suite.
• Rezinesi rekuongorora rinopihwa mahara kuti utarise maficha eH.264 Encoder. Rezinesi rekuongorora rinopera mushure mekushandiswa kweawa pane Hardware.

Installation Instructions

• Iyo yakakosha inofanirwa kuiswa muLibero SoC software. Inoitwa otomatiki kuburikidza neCatalog yekuvandudza basa mukati
• Libero SoC software, kana CPZ file inogona kuwedzerwa nemaoko uchishandisa iyo Add Core catalogue chimiro. Panguva iyo CPZ file yakaiswa muLibero, iyo musimboti inogona kugadzirwa, kugadzirwa, uye nekumisikidzwa mukati meSmartDesign kuti ibatanidzwe muLibero purojekiti.
• Kuti uwane mamwe mirairo yekumisikidza kwepakati, kupihwa rezinesi, uye kushandiswa zvakajairika, ona Libero SoC Online Rubatsiro.

Tafura inotevera inoronga mashandisirwo ezviwanikwa zve asample H.264 4K I-Frame Encoder IP dhizaini yakagadzirirwa PolarFire FPGA (MPF300TS-1FCG1152I pasuru) uye inogadzira data yakamanikidzwa nekushandisa 4:2:2 s.ampnguva yedata rekuisa.
Tafura 5-1. Resource Utilization yeH.264 4K I-Frame Encoder IP

Element	4 Zvimedu	2 Zvimedu
4LUTs	73588	37017
DFFs	67543	33839
LSRAM	592	296
µSRAM	84	42
Math Blocks	89	45
Interface 4-inopinza LUTs	25524	12780
Interface DFFs	25524	12780

Revision History

Tafura yenhoroondo yekudzokorora inotsanangura shanduko dzakaitwa mugwaro. Kuchinja kwacho kunorongwa nekudzokorora, kutanga nebhuku razvino uno.
Tafura 6-1. Revision History

Kudzokorora	Date	Tsanangudzo
A	01/2023	Kutanga Kusunungurwa.

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Trademarks
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Zvinyorwa / Zvishandiso

MICROCHIP H.264 4K I-Frame Encoder IP Cores [pdf] Bhuku reMushandisi H.264 4K I-Frame Encoder IP Cores, H.264 4K, I-Frame Encoder IP Cores, Encoder IP Cores, IP Cores

References

• User Manual