F Tile Serial Lite IV Intel FPGA IP User Guide

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1 F Tile Serial Lite IV Intel FPGA IP

2 Zvinyorwa / Zvishandiso

2.1 References

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F Tile Serial Lite IV Intel FPGA IP

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F-Tile Serial Lite IV Intel® FPGA IP User Guide
Yakagadziridzwa yeIntel® Quartus® Prime Design Suite: 22.1 IP Version: 5.0.0

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UG-20324

ID: 683074 Version: 2022.04.28

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1. Nezve F-Tile Serial Lite IV Intel® FPGA IP User Guide………………………………………….. 4
2. F-Tile Serial Lite IV Intel FPGA IP Overview………………………………………………………………. 6 2.1. Ruzivo Rwakabudiswa…………………………………………………………………………………..7 2.2. Zvinotsigirwa ………………………………………………………………………………….. 7 2.3. IP Version Support Level……………………………………………………………………………..8 2.4. Rutsigiro rweDevice Yegiredhi………………………………………………………………………..8 2.5. Resource Utilization and Latency ………………………………………………………………………… Bandwidth Efficiency ………………………………………………………………………………………. 9
3. Kutanga …………………………………………………………………………………………………. 11 3.1. Kuisa uye Kupa Rezinesi Intel FPGA IP Cores………………………………………………………… 11 3.1.1. Intel FPGA IP Evaluation Mode……………………………………………………………. 11 3.2. Kudoma IP Parameters uye Sarudzo………………………………………………………… 14 3.3. Yakagadzirwa File Chimiro………………………………………………………………………………… 14 3.4. Kutevedzera Intel FPGA IP Cores…………………………………………………………………………… Kutevedzera uye Kuona Magadzirirwo…………………………………………………….. 16 3.4.1. Kubatanidza IP Cores mune Zvimwe Zvishandiso zveEDA…………………………………………………………. 17 3.5. Kunyora Iyo Yakazara Dhizaini…………………………………………………………………………..17
4. Tsanangudzo Yemashandiro…………………………………………………………………………………….. 19 4.1. TX Datapath………………………………………………………………………………………..20 4.1.1. TX MAC Adapter…………………………………………………………………………….. 21 4.1.2. Kupinza Izwi (CW) Insertion ………………………………………………………………… TX CRC…………………………………………………………………………………………23 4.1.3. TX MII Encoder……………………………………………………………………………….28 4.1.4. TX PCS uye PMA………………………………………………………………………….. 29 4.1.5. RX Datapath……………………………………………………………………………………………. 30 4.2. RX PCS uye PMA………………………………………………………………………….. 30 4.2.1. RX MII Decoder………………………………………………………………………………… 31 4.2.2. RX CRC…………………………………………………………………………………….. 31 4.2.3. RX Deskew………………………………………………………………………………….31 4.2.4. RX CW Removal………………………………………………………………………………… F-Tile Serial Lite IV Intel FPGA IP Clock Architecture……………………………………………. 32 4.2.5. Reset uye Link Initialization ………………………………………………………………………..35 4.3. TX Reset uye Initialization Sequence……………………………………………………. 36 4.4. RX Reset uye Initialization Sequence……………………………………………………. 37 4.4.1. Link Rate uye Bandwidth Efficiency Calculation ………………………………………………….. 38
5. Parameters………………………………………………………………………………………………………… 42
6. F-Tile Serial Lite IV Intel FPGA IP Interface Signals…………………………………………….. 44 6.1. Chiratidzo chewachi………………………………………………………………………………………….44 6.2. Reset Signals…………………………………………………………………………………………… 44 6.3. MAC Signals………………………………………………………………………………………….. 45 6.4. Transceiver Reconfiguration Signals…………………………………………………………………… 48 6.5. PMA Signals………………………………………………………………………………………….. 49

F-Tile Serial Lite IV Intel® FPGA IP User Guide 2

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7. Kugadzira neF-Tile Serial Lite IV Intel FPGA IP…………………………………………………… 51 7.1. Reset Guidelines…………………………………………………………………………………….. 51 7.2. Zvikanganiso Pakubata Mazano……………………………………………………………………………..51
8. F-Tile Serial Lite IV Intel FPGA IP User Guide Archives……………………………………………. 52 9. Document Revision History yeF-Tile Serial Lite IV Intel FPGA IP User Guide ………53

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1. Nezve F-Tile Serial Lite IV Intel® FPGA IP User Guide

Ichi chinyorwa chinotsanangura IP maficha, tsananguro yezvivakwa, matanho ekugadzira, uye nhungamiro yekugadzira iyo F-Tile Serial Lite IV Intel® FPGA IP uchishandisa iyo F-tile transceivers muIntel Agilex TM zvishandiso.

Vateereri Vanotarisirwa

Gwaro iri rakaitirwa vashandisi vanotevera:
· Dhizaini madhizaini ekuita IP sarudzo panguva yegadziriro-level dhizaini yekuronga chikamu
· Vagadziri ve Hardware kana vachibatanidza iyo IP mune yavo system-level dhizaini
· Validation mainjiniya panguva yesystem-level simulation uye hardware yekusimbisa zvikamu

Related Documents

Reference

F-Tile seri Lite IV Intel FPGA IP Dhizaini Example User Guide

Intel Agilex Device Data Sheet

Tsanangudzo
Ichi chinyorwa chinopa chizvarwa, nhungamiro yekushandisa, uye tsananguro inoshanda yeF-Tile Serial Lite IV Intel FPGA IP dhizaini ex.ampzvishoma muIntel Agilex zvishandiso.
Ichi chinyorwa chinotsanangura maitiro emagetsi, kushandura maitiro, zvigadziriso zvekugadzirisa, uye nguva yeIntel Agilex madivayiri.

Tafura 2.
CW RS-FEC PMA TX RX PAM4 NRZ

Acronyms uye Glossary Acronym List
Acronym

Kuwedzera Kudzora Izwi Reed-Soromoni Pamberi Chikanganiso Kugadzirisa Muviri Wepakati Attachment Transmitter Receiver Pulse-Amplitude Modulation 4-Level Kusadzokera-kuna-zero

akaenderera…

Intel Corporation. Kodzero dzese dzakachengetwa. Intel, iyo Intel logo, uye mamwe maIntel mamaki zviratidzo zveIntel Corporation kana vatsigiri vayo. Intel inobvumidza kuita kwayo FPGA uye semiconductor zvigadzirwa kune zvazvino zvirevo zvinoenderana neIntel's standard waranti, asi inochengetera kodzero yekuita shanduko kune chero zvigadzirwa nemasevhisi chero nguva pasina chiziviso. Intel haitore mutoro kana mutoro unobva mukushandisa kana kushandiswa kwechero ruzivo, chigadzirwa, kana sevhisi inotsanangurwa pano kunze kwekunge yakabvumiranwa nekunyora neIntel. Vatengi veIntel vanorairwa kuti vawane yazvino vhezheni yezvakatemwa zvemudziyo vasati vavimba nechero ruzivo rwakaburitswa uye vasati vaisa maodha ezvigadzirwa kana masevhisi. *Mamwe mazita nemhando zvinogona kunzi ndezvevamwe.

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1. Nezve F-Tile Serial Lite IV Intel® FPGA IP User Guide 683074 | 2022.04.28

PCS MII XGMII

Acronym

Kuwedzera Kwemuviri Coding Sublayer Media Yakazvimiririra Chiratidziro 10 Gigabit Media Yakazvimirira Chiratidziro

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2. F-Tile Serial Lite IV Intel FPGA IP Overview

Mufananidzo 1.

F-Tile Serial Lite IV Intel FPGA IP inokodzera yakakwira bandwidth data kutaurirana kune chip-to-chip, bhodhi-ku-bhodhi, uye backplane application.

Iyo F-Tile Serial Lite IV Intel FPGA IP inosanganisa midhiya yekuwana kutonga (MAC), yemuviri coding sublayer (PCS), uye yemuviri midhiya yekunamatira (PMA) zvidhinha. IP inotsigira kukurumidza kwekufambisa data kunosvika 56 Gbps pamugwagwa une huwandu hunopfuura ina PAM4 nzira kana 28 Gbps pamugwagwa une huwandu hwe16 NRZ nzira. Iyi IP inopa yakakwira bandwidth, yakaderera pamusoro pemafuremu, yakaderera I/O kuverenga, uye inotsigira yakakwirira scalability munhamba mbiri dzenzira nekumhanya. Iyi IP zvakare inogadziriswa zvakare nyore nerutsigiro rwehuwandu hwehuwandu hwe data neEthernet PCS modhi yeF-tile transceiver.

Iyi IP inotsigira nzira mbiri dzekutumira:
· Basic modhi-Iyi ndiyo yakachena yekutepfenyura modhi iyo data inotumirwa pasina yekutanga-packet, isina chinhu kutenderera, uye kupera-kwe-packet kuwedzera bandwidth. Iyo IP inotora yekutanga data data sekutanga kwekuputika.
· Yakazara modhi-Iyi imodhi yekufambisa yepakiti. Mune iyi modhi, iyo IP inotumira kuputika uye kutenderera kutenderera pakutanga uye kumagumo kwepaketi se delimiters.

F-Tile Serial Lite IV Yakakwirira Level Block Dhiagiramu

Avalon Streaming Interface TX

F-Tile seri Lite IV Intel FPGA IP
MAC TX
TX USRIF_CTRL

64 * n lanes bits (NRZ mode) / 2 * n nzira bits (PAM4 mode)

TX MAC

Adapter INSERT

MII ENCODE

Custom PCS

TX PCS

TX MII

EMIB ENCODE SCRAMBLER FEC

TX PMA

n Lanes Bits (PAM4 mode)/ n Lanes Bits (NRZ mode)
TX Serial Interface

Avalon Streaming Interface RX
64 * n lanes bits (NRZ mode) / 2 * n nzira bits (PAM4 mode)

RX PCS

CW RMV

DESKEW

MII

& ALIGN DECODE

RX MII

EMIB

DECODE BLOCK SYNC & FEC DESCRAMBLER

RX PMA

CSR

2n Lanes Bits (PAM4 modhi)/ n Lanes Bits (NRZ modhi) RX Serial Interface
Avalon Memory-Mapped Interface Register Config

Legend

Soft logic

Hard logic

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Unogona kugadzira F-Tile seri Lite IV Intel FPGA IP dhizaini examples kudzidza zvakawanda nezve IP maficha. Tarisa kune F-Tile seri Lite IV Intel FPGA IP Dhizaini Example User Guide.
Ruzivo rwunoenderana · Ruzivo Rwekuita pane peji 19 · F-Tile seri Lite IV Intel FPGA IP Dhizaini Example User Guide

2.1. Kuburitsa Ruzivo

Intel FPGA IP shanduro dzinoenderana neIntel Quartus® Prime Design Suite software shanduro kusvika v19.1. Kutanga muIntel Quartus Prime Design Suite software vhezheni 19.2, Intel FPGA IP ine chirongwa chitsva chekushandura.

Iyo Intel FPGA IP vhezheni (XYZ) nhamba inogona kuchinja neimwe Intel Quartus Prime software shanduro. Shanduko mu:

X inoratidza kudzokororwa kukuru kweIP. Kana iwe ukagadzirisa iyo Intel Quartus Prime software, iwe unofanirwa kuvandudza iyo IP.
Y inoratidza iyo IP inosanganisira zvinhu zvitsva. Gadzirisa IP yako kuti ubatanidze zvinhu zvitsva izvi.
Z inoratidza kuti IP inosanganisira shanduko diki. Gadzirisa IP yako kuti ubatanidze shanduko idzi.

Tafura 3.

F-Tile Serial Lite IV Intel FPGA IP Release Information

Item IP Shanduro Intel Quartus Prime Version Release Date Kuodha Code

5.0.0 22.1 2022.04.28 IP-SLITE4F

Tsanangudzo

2.2. Inotsigirwa Zvimiro
Iri tafura rinotevera rinoratidza zvinhu zviripo muF-Tile Serial Lite IV Intel FPGA IP:

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Tafura 4.

F-Tile seri Lite IV Intel FPGA IP Zvimiro

Feature

Tsanangudzo

Data Transfer

YePAM4 modhi:
- FHT inotsigira chete 56.1, 58, uye 116 Gbps pamugwagwa une huwandu hwe4 nzira.
- FGT inotsigira anosvika makumi mashanu nesere Gbps panzira ine huwandu hunosvika gumi nemaviri.
Tarisa Tafura 18 papeji 42 kuti uwane rumwe ruzivo nezve inotsigirwa transceiver data rates yePAM4 modhi.
YeNRZ modhi:
- FHT inotsigira chete 28.05 uye 58 Gbps pamugwagwa une huwandu hwe4 nzira.
- FGT iri kutsigira inosvika 28.05 Gbps pamugwagwa une huwandu hwegumi nematanhatu.
Tarisa Tafura 18 papeji 42 kuti uwane rumwe ruzivo nezve inotsigirwa transceiver data rates yeNRZ mode.
· Inotsigira kuenderera kutenderera (Basic) kana packet (Yakazara) modes.
· Inotsigira yakaderera pamusoro furemu mapaketi.
· Inotsigira byte granularity kutamiswa kwese kuputika saizi.
· Inotsigira mushandisi-yekutanga kana otomatiki nzira kurongeka.
· Inotsigira programmable alignment nguva.

PCS

· Inoshandisa yakaoma IP logic inosangana neIntel Agilex F-tile transceivers yekudzikisa zvinyoro zvinyoro.
Inotsigira PAM4 modulation mode ye100GBASE-KP4 yakatarwa. RS-FEC inogara ichigoneswa mune iyi modulation mode.
· Inotsigira NRZ ine sarudzo yeRS-FEC modulation mode.
· Inotsigira 64b/66b encoding decoding.

Kuona kukanganisa uye Kubata

· Inotsigira CRC kukanganisa kutarisa paTX uye RX data nzira. · Inotsigira RX yekubatanidza kukanganisa kutarisa. · Inotsigira RX PCS kuona kukanganisa.

Interfaces

· Inotsigira chete yakazara duplex packet kutumira ine yakazvimirira ma link.
· Inoshandisa point-to-point yekubatanidza kune akawanda FPGA zvishandiso zvine yakaderera kutamisa latency.
· Inotsigira mirairo yakatsanangurwa nemushandisi.

2.3. IP Version Support Level

Iyo Intel Quartus Prime software uye Intel FPGA mudziyo tsigiro yeF-Tile Serial Lite IV Intel FPGA IP yakaita seiyi:

Tafura 5.

IP Version uye Chikamu chekutsigira

Intel Quartus Prime 22.1

Chishandiso Intel Agilex F-tile transceivers

IP Version Simulation Compilation Hardware Dhizaini

5.0.0

2.4. Mudziyo Wekumhanyisa Giredhi Tsigiro
Iyo F-Tile Serial Lite IV Intel FPGA IP inotsigira anotevera kumhanya mamakisi eIntel Agilex F-tile zvishandiso: · Transceiver kumhanya giredhi: -1, -2, uye -3 · Core kumhanya giredhi: -1, -2, uye - 3

F-Tile Serial Lite IV Intel® FPGA IP User Guide 8

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Related Information
Intel Agilex Device Data Sheet Rumwe ruzivo nezve inotsigirwa data chiyero muIntel Agilex F-tile transceivers.

2.5. Resource Utilization uye Latency

Izvo zviwanikwa uye latency yeF-Tile Serial Lite IV Intel FPGA IP yakawanikwa kubva kuIntel Quartus Prime Pro Edition software shanduro 22.1.

Tafura 6.

Intel Agilex F-Tile seri Lite IV Intel FPGA IP Resource Utilization
Iyo latency kuyerwa kwakavakirwa pakutenderera rwendo latency kubva kuTX musimboti wekuisa kune RX musimboti kubuda.

Transceiver Type

Variant

Nhamba yeData Lanes Mode RS-FEC ALM

Latency (TX musimboti wachi kutenderera)

FGT

28.05 Gbps NRZ 16

Basic Disabled 21,691 65

Vakaremara zvizere 22,135 65

Basic Inogoneswa 21,915 189

Yakazara Inogoneswa 22,452 189

58 Gbps PAM4 12

Basic Inogoneswa 28,206 146

Yakazara Inogoneswa 30,360 146

FHT

58 Gbps NRZ

Basic Inogoneswa 15,793 146

Yakazara Inogoneswa 16,624 146

58 Gbps PAM4 4

Basic Inogoneswa 15,771 154

Yakazara Inogoneswa 16,611 154

116 Gbps PAM4 4

Basic Inogoneswa 21,605 128

Yakazara Inogoneswa 23,148 128

2.6. Bandwidth Efficiency

Tafura 7.

Bandwidth Efficiency

Variables Transceiver mode

PAM4

Kuyerera maitiro RS-FEC

Yakazara Inogoneswa

Basic Enabled

Serial interface bit rate muGbps (RAW_RATE)
Saizi yekupfupikisa yekuchinjisa muhuwandu hwezwi (BURST_SIZE) (1)
Nguva yekuenzanisa mukutenderera kwewachi (SRL4_ALIGN_PERIOD)

56.0 2,048 4,096

56.0 4,194,304 4,096

Settings

NRZ

Full

Yakaremara

Yagoneswa

28.0

2,048

4,096

Basic Yakaremara 28.0

Yakagoneswa 28.0

4,194,304

4,096

4,096 vakaenderera…

(1) Iyo BURST_SIZE yeBasic modhi inosvika kusingagumi, saka nhamba huru inoshandiswa.

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Variables

Settings

64/66b encode

0.96969697 0.96969697 0.96969697 0.96969697 0.96969697 0.96969697

Pamusoro pehukuru hwekuputika muhuwandu hwezwi (BURST_SIZE_OVHD)

2 (2)

0 (3)

2 (2)

0 (3)

Kurongeka kwechiratidzo 81,915 muwachi kutenderera (ALIGN_MARKER_PERIOD)

81,915

81,916

Alignment marker wide in 5

wachi kutenderera

(ALIGN_MARKER_WIDTH)

Bandwidth kunyatsoshanda (4)

0.96821788 0.96916433 0.96827698 0.96822967 0.96922348 0.96917616

Kushanda mwero (Gbps) (5)

54.2202012 54.27320236 27.11175544 27.11043076 27.13825744 27.13693248

Yakanyanya mushandisi wachi frequency (MHz) (6)

423.59532225 424.00939437 423.62117875 423.6004806 424.0352725 424.01457

Related Information Link Rate uye Bandwidth Efficiency Calculation pane peji 40

(2) MuModhi Yakazara, saizi yeBURST_SIZE_OVHD inosanganisirwa neSTART/END Kudzora Mazwi akapetwa mune data stream.
(3) PaBasic modhi, BURST_SIZE_OVHD iri 0 nekuti hapana START/END panguva yekushambadzira.
(4) Tarisa kune Link Rate uye Bandwidth Efficiency Calculation ye bandwidth kunyatsoita kuverenga.
(5) Tarisa kune Link Rate uye Bandwidth Efficiency Calculation kuti ibudirire chiyero kuverenga.
(6) Tarisa kune Link Rate uye Bandwidth Efficiency Calculation kune yakanyanya mushandisi wachi frequency kuverenga.

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3. Kutanga

3.1. Kuisa uye Rezinesi Intel FPGA IP Cores

Iyo Intel Quartus Prime software yekumisikidza inosanganisira iyo Intel FPGA IP raibhurari. Raibhurari iyi inopa akawanda anobatsira IP cores ekushandisa kwako kugadzira pasina kudiwa kweimwe rezinesi. Mamwe Intel FPGA IP cores inoda kutengwa kwerezinesi rakasiyana rekushandisa kugadzira. Iyo Intel FPGA IP Evaluation Mode inobvumidza iwe kuti uongorore aya ane rezinesi Intel FPGA IP cores mukuenzanisa uye hardware, usati wafunga kutenga yakazara yekugadzira IP yepakati rezinesi. Iwe unongoda kutenga rezinesi rekugadzira rakazara rezinesi reIntel IP cores mushure mekunge wapedza kuyedza hardware uye wagadzirira kushandisa IP mukugadzira.

Iyo Intel Quartus Prime software inoisa IP cores munzvimbo dzinotevera nekusarudzika:

Mufananidzo 2.

IP Core Kuisa Nzira
intelFPGA (_pro) quartus - Iine Intel Quartus Prime software ip - Iine Intel FPGA IP raibhurari uye yechitatu-bato IP cores altera - Iine Intel FPGA IP raibhurari sosi kodhi -Ine iyo Intel FPGA IP sosi files

Tafura 8.

IP Core Kuisa Nzvimbo

Nzvimbo

Software

:intelFPGA_proquartusipaltera

Intel Quartus Prime Pro Edition

:/intelFPGA_pro/quartus/ip/altera Intel Quartus Prime Pro Edition

Platform Windows* Linux*

Cherechedza:

Iyo Intel Quartus Prime software haitsigire nzvimbo munzira yekuisa.

3.1.1. Intel FPGA IP Evaluation Mode
Iyo yemahara Intel FPGA IP Evaluation Mode inobvumidza iwe kuti uongorore ine rezinesi Intel FPGA IP cores mukuenzanisa uye hardware usati watenga. Intel FPGA IP Evaluation Mode inotsigira inotevera ongororo pasina imwe rezinesi:
· Tevedzera maitiro eane rezinesi Intel FPGA IP musimboti mune yako system. · Simbisa mashandiro, saizi, uye kumhanya kweiyo IP musimboti nekukurumidza uye nyore. · Gadzira nguva-inogumira mudziyo kuronga files yezvigadziriso zvinosanganisira IP cores. · Ronga mudziyo une IP yako musimboti uye simbisa dhizaini yako muhardware.

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3. Kutanga
683074 | 2022.04.28
Intel FPGA IP Evaluation Mode inotsigira anotevera maitiro ekushanda:
· Tethered-Inobvumira kumhanyisa dhizaini ine rezinesi Intel FPGA IP zvachose ine chinongedzo pakati pebhodhi rako nekombuta inotambira. Tethered mode inoda serial yakabatana bvunzo chiito boka (JTAG) tambo yakabatana pakati peJTAG chiteshi pabhodhi rako uye komputa inotambira, iri kumhanyisa Intel Quartus Prime Programmer kwenguva yenguva yekuongorora Hardware. Iyo Programmer inongoda kuisirwa kushoma kweIntel Quartus Prime software, uye haidi Intel Quartus Prime rezinesi. Iyo komputa inotambira inodzora nguva yekuongorora nekutumira chiratidzo che periodic kune mudziyo kuburikidza neJTAG port. Kana ese ane marezinesi eIP cores mudhizaini inotsigira tethered modhi, nguva yekuongorora inomhanya kusvika chero IP musimboti wongororo yapera. Kana ese eIP cores achitsigira isina muganho yekuongorora nguva, chishandiso hachipere-nguva.
· Isina kuvharwa-Inobvumira kumhanyisa dhizaini ine IP ine rezinesi kwenguva shoma. Iyo IP musimboti inodzokera kune isina kuvharwa modhi kana mudziyo ukadzima kubva pakombuta inotambira ichimhanyisa Intel Quartus Prime software. Iyo IP musimboti inodzokera kune isina untethered modhi kana chero imwe marezinesi IP musimboti mudhizaini isingatsigire tethered mode.
Kana nguva yekuongorora yapera kune chero ine rezinesi Intel FPGA IP mudhizaini, dhizaini inomira kushanda. Yese IP cores inoshandisa Intel FPGA IP Evaluation Mode nguva yekubuda panguva imwe chete kana chero IP musimboti mukugadzira nguva kunze. Kana nguva yekuongorora yapera, unofanira kuronga zvakare FPGA mudziyo usati waenderera mberi nekuongorora kwehardware. Kuti uwedzere kushandiswa kweiyo IP musimboti wekugadzira, tenga yakazara rezinesi rekugadzira reiyo IP musimboti.
Iwe unofanirwa kutenga rezinesi uye kugadzira yakazara rezenisi rezenisi kiyi usati wagadzira isina kurambidzwa dhizaini hurongwa file. Munguva yeIntel FPGA IP Evaluation Mode, iyo Compiler inongogadzira chete-inogumira nguva yedhizaini hurongwa file ( _time_limited.sof) inopera panguva yakatarwa.

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Mufananidzo 3.

Intel FPGA IP Evaluation Mode Flow
Isa iyo Intel Quartus Prime Software ine Intel FPGA IP Library

Parameterize uye Instantiate ine Rezinesi Intel FPGA IP Core

Simbisa iyo IP mune Inotsigirwa Simulator

Nyora Dhizaini muIntel Quartus Prime Software

Gadzira Yenguva-Yakaganhurwa Chishandiso Chirongwa File

Ronga iyo Intel FPGA Chishandiso uye Simbisa Kushanda paBhodhi
Hapana IP Yakagadzirira Kushandiswa Kwekugadzira?
Hongu Tenga Kugadzirwa Kwakazara
IP License

Cherechedza:

Sanganisira IP ine Rezinesi mune Zvekutengesa Zvigadzirwa
Tarisa kune yega yega IP musimboti mushandisi gwara rematanho eparameterization uye ruzivo rwekuita.
Intel marezinesi IP cores pane-se-seat, nekusingaperi. Mari yerezinesi inosanganisira kugadzirisa kwegore rekutanga uye rutsigiro. Iwe unofanirwa kuvandudza kondirakiti yekuchengetedza kuti ugamuchire zvigadziriso, gadziriso dzebug, uye rutsigiro rwehunyanzvi kupfuura gore rekutanga. Iwe unofanirwa kutenga rezinesi rakazara rekugadzira reIntel FPGA IP cores inoda rezinesi rekugadzira, usati wagadzira hurongwa files kuti iwe unogona kushandisa kwenguva isina muganho. Munguva yeIntel FPGA IP Evaluation Mode, iyo Compiler inongogadzira chete-inogumira nguva yedhizaini hurongwa file ( _time_limited.sof) inopera panguva yakatarwa. Kuti uwane makiyi ako erezinesi rekugadzira, shanyira iyo Intel FPGA Self-Service Licensing Center.
Iyo Intel FPGA Software License Zvibvumirano zvinotonga kuisirwa uye kushandiswa kwerezinesi IP cores, iyo Intel Quartus Prime dhizaini software, uye ese asina kunyoreswa IP cores.

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Ruzivo rwunoenderana · Intel FPGA Rezinesi Rekutsigira Center · Nhanganyaya kuIntel FPGA Kuisirwa Software uye Rezinesi
3.2. Kutsanangura iyo IP Parameters uye Sarudzo
Iyo IP parameter mupepeti inokutendera iwe kukurumidza kugadzirisa yako tsika IP kusiyanisa. Shandisa matanho anotevera kutsanangura IP sarudzo uye paramita muIntel Quartus Prime Pro Edition software.
1. Kana iwe usati uine Intel Quartus Prime Pro Edition chirongwa umo kubatanidza yako F-Tile Serial Lite IV Intel FPGA IP, unofanira kugadzira imwe. a. MuIntel Quartus Prime Pro Edition, tinya File New Project Wizard kugadzira itsva Quartus Prime project, kana File Vhura Project kuvhura iripo Quartus Prime project. Iyo wizard inokukurudzira kuti utaure mudziyo. b. Taura iyo mhuri yemudziyo Intel Agilex uye sarudza yekugadzira F-tile mudziyo unosangana nekumhanyisa giredhi zvinodiwa zveIP. c. Dzvanya Finish.
2. Mune IP Catalog, tsvaga uye sarudza F-Tile Serial Lite IV Intel FPGA IP. The New IP Variation hwindo rinoonekwa.
3. Nyora zita repamusoro-soro kune yako itsva tsika IP kusiyana. Iyo parameter mupepeti inochengetedza iyo IP kusiyanisa marongero mune a file zita .ip.
4. Dzvanya OK. Iyo parameter editor inooneka. 5. Tsanangura maparameter e IP yako kusiyana. Tarisa kune iyo Parameter chikamu che
ruzivo nezve F-Tile Serial Lite IV Intel FPGA IP paramita. 6. Optionally, kugadzira simulation testbench kana compilation uye hardware dhizaini
example, tevera mirairo iri muDesign Example User Guide. 7. Dzvanya Gadzira HDL. The Generation dialog box inoonekwa. 8. Taura zvakabuda file chizvarwa sarudzo, wobva wadzvanya Gadzira. Iyo IP musiyano
files gadzira zvinoenderana nezvaunoda. 9. Dzvanya Finish. Iyo parameter editor inowedzera yepamusoro-level .ip file kune yazvino
chirongwa otomatiki. Kana ukakumbirwa kuti uwedzere nemaoko .ip file kupurojekiti, tinya Project Wedzera/Bvisa Files muProjekti yekuwedzera iyo file. 10. Mushure mekugadzira uye nekumisikidza IP yako shanduko, ita akakodzera pini migove yekubatanidza madoko uye kuseta chero yakakodzera per-chiitiko RTL paramita.
Inoenderana Ruzivo Paramita pane peji 42
3.3. Yakagadzirwa File Chimiro
Iyo Intel Quartus Prime Pro Edition software inogadzira inotevera IP inobuda file chimiro.
Kuti uwane ruzivo nezve file chimiro chekugadzira example, tarisa kune F-Tile Serial Lite IV Intel FPGA IP Dhizaini Example User Guide.

F-Tile Serial Lite IV Intel® FPGA IP User Guide 14

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Mufananidzo 4. F-Tile Serial Lite IV Intel FPGA IP Yakagadzirwa Files
.ip - IP kubatanidzwa file

IP kuchinja files

_ IP kuchinja files

example_design

.cmp – VHDL component declaration file _bb.v - Verilog HDL bhokisi dema EDA synthesis file _inst.v uye .vhd – Sampuye instantiation templates .xml- XML report file

Exampnzvimbo ye IP yako musimboti dhizaini example files. Nzvimbo yakasarudzika ndeye example_design, asi unokurudzirwa kutsanangura imwe nzira.

.qgsimc - Inonyora mifanidzo yekuenzanisa kutsigira kuwedzera patsva .qgsynthc - Inonyora synthesis parameters kutsigira kuwedzera patsva

.qip – Lists IP synthesis files

_generation.rpt- IP generation report

.sopcinfo- Software tool-chain integration file .html- Connection uye memory mepu data

.csv – Pini basa file

.spd - Inosanganisa zvinyorwa zvekufananidzira

Sim Simulation files

synth IP synthesis files

.v Top-level simulation file

.v Top-level IP synthesis file

Simulator zvinyorwa

Subcore library

synth
Subcore synthesis files

sim
Subcore Simulation files

Tafura 9.

F-Tile seri Lite IV Intel FPGA IP Yakagadzirwa Files

File Zita

Tsanangudzo

.ip

Iyo Platform Dhizaini system kana yepamusoro-level IP musiyano file. ndiro zita raunopa yako IP musiyano.

.cmp

The VHDL Component Declaration (.cmp) file chinyorwa file iyo ine yemuno generic uye chiteshi tsananguro dzaunogona kushandisa muVHDL dhizaini files.

.html

Chirevo chine ruzivo rwekubatanidza, mepu yendangariro inoratidza kero yemuranda wega wega neruremekedzo kune yega tenzi kwayakabatanidzwa, uye parameter migove.

_generation.rpt

IP kana Platform Dhizaini yechizvarwa log file. Pfupiso yemameseji panguva yeIP chizvarwa.

.qgsimc

Inonyora masimulation paramita kutsigira kuwedzera patsva.

.qgsynthc

Inonyora synthesis parameters kutsigira kuwedzera patsva.

.qip

Iine ruzivo rwese rwunodiwa nezve IP chikamu chekubatanidza uye kuunganidza iyo IP chikamu muIntel Quartus Prime software.
akaenderera…

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File Zita .sopcinfo
.csv .spd _bb.v _inst.v kana _inst.vhd .regmap
.svd
.v kana .vhd mentor/ synopsy/vcs/ synopsy/vcsmx/ xcelium/ submodules/ /

Tsanangudzo
Inotsanangura zvinongedzo uye IP chikamu parameterizations mune yako Platform Dhizaini system. Iwe unogona kupenengura zvirimo kuti uwane zvinodiwa kana iwe uchigadzira madhiraivha esoftware ezvikamu zveIP. Maturusi ekudzika akadai seNios® II chishandiso cheni shandisa izvi file. The .sopcinfo file uye hurongwa.h file inogadzirwa yeNios II chishandiso cheni inosanganisira kero mepu ruzivo rwemuranda wega wega hama kuna tenzi wega anowana muranda. Vatenzi vakasiyana vanogona kuve nemepu yekero yakasiyana yekuwana chimwe chikamu chevaranda.
Iine ruzivo rwekusimudzira mamiriro echikamu cheIP.
Inodiwa kuiswa file ye ip-make-simscript kugadzira zvinyorwa zvekunyepedzera zvemasimulator anotsigirwa. The .spd file ine runyorwa rwe files inogadzirwa yekufananidza, pamwe neruzivo nezve ndangariro dzaunogona kutanga.
Unogona kushandisa Verilog dema-bhokisi (_bb.v) file sechinhu chisina chinhu chiziviso chekushandisa sebhokisi dema.
HDL example instantiation template. Unogona kukopa nekunamira zviri mukati meizvi file muHDL yako file kusimbisa IP kusiyanisa.
Kana IP iine ruzivo rwekunyoresa, .regmap file zvinogadzira. The .regmap file inotsanangura ruzivo rwemepu yekunyoresa tenzi uye muranda interfaces. Izvi file inozadzisa .sopcinfo file nekupa ruzivo rwakadzama rwerejista nezve system. Izvi zvinogonesa rejista kuratidza views uye mushandisi customizable manhamba muSystem Console.
Inobvumira zvakaoma processor system (HPS) System Debug maturusi kuti view mamepu ekurejisa emaperipheral akabatana neHPS muPlatform Designer system. Panguva yekubatanidza, iyo .svd files for muranda interfaces anooneka kuSystem Console masters anochengetwa mu.sof file muchikamu chekugadzirisa. System Console inoverenga chikamu ichi, icho Platform Dhizaini inogona kubvunza ruzivo rwemepu yekunyoresa. Kune nhapwa dzehurongwa, Platform Designer inogona kuwana marejista nemazita.
HDL files inosimbisa imwe neimwe submodule kana yemwana IP ye synthesis kana simulation.
Ine ModelSim*/QuestaSim* script msim_setup.tcl yekumisikidza uye kuita simulation.
Ine shell script vcs_setup.sh yekumisikidza nekumhanyisa VCS* simulation. Ine shell script vcsmx_setup.sh uye synopsys_sim.setup file kumisikidza uye kumhanya VCS MX simulation.
Iine shell script xcelium_setup.sh uye kumwe kuseta files kumisikidza uye kumhanya Xcelium * simulation.
Iine HDL files ye IP submodules.
Kune yega yega yakagadzirwa yemwana IP dhairekitori, Platform Dhizaini inogadzira synth/ uye sim/ sub-dhairekitori.

3.4. Kutevedzera Intel FPGA IP Cores
Iyo Intel Quartus Prime software inotsigira IP musimboti RTL simulation mune chaiyo EDA simulators. IP chizvarwa nesarudzo inogadzira simulation files, kusanganisira iyo inoshanda simulation modhi, chero testbench (kana example dhizaini), uye mutengesi-chaiwo simulator yekuseta zvinyorwa zvega rega IP musimboti. Iwe unogona kushandisa iyo inoshanda simulation modhi uye chero testbench kana example dhizaini yekufananidza. IP chizvarwa chinobuda chinogonawo kusanganisira zvinyorwa kuunganidza uye kumhanya chero testbench. Iwo manyoro anonyora ese mamodheru kana maraibhurari aunoda kutevedzera yako IP musimboti.

F-Tile Serial Lite IV Intel® FPGA IP User Guide 16

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Iyo Intel Quartus Prime software inopa kubatanidzwa neakawanda simulators uye inotsigira akawanda simulation kuyerera, kusanganisira yako yakanyorwa uye tsika simulation inoyerera. Chero kuyerera kwaunosarudza, IP musimboti simulation inosanganisira anotevera matanho:
1. Gadzira IP HDL, testbench (kana example dhizaini), uye simulator yekuseta script files.
2. Gadzirisa yako simulator nharaunda uye chero simulation zvinyorwa.
3. Unganidza maraibhurari emuenzaniso wokutevedzera.
4. Mhanya simulator yako.

3.4.1. Kutevedzera uye Kusimbisa Dhizaini

Nekusagadzika, iyo parameter mupepeti inogadzira simulator-chaiwo zvinyorwa zvine mirairo yekuunganidza, kutsanangura, uye kutevedzera Intel FPGA IP modhi uye yekunyepedzera modhi raibhurari. files. Unogona kukopa mirairo mune yako simulation testbench script, kana kugadzirisa izvi files yekuwedzera mirairo yekunyora, kujekesa, uye kutevedzera dhizaini yako uye testbench.

Tafura 10. Intel FPGA IP Core Simulation Scripts

Simulator

File Directory

ModelSim

_sim/mentor

ChechiCas

VCS

_sim/synopsy/vcs

VCS MX

_sim/synopsy/vcsmx

Xcelium

_sim/xcelium

Script msim_setup.tcl (7)
vcs_setup.sh vcsmx_setup.sh synopsys_sim.setup xcelium_setup.sh

3.5. Synthesizing IP Cores mune Zvimwe EDA Zvishandiso
Sarudzo, shandisa imwe inotsigirwa EDA chishandiso kugadzira dhizaini inosanganisira Intel FPGA IP cores. Paunogadzira iyo IP core synthesis files yekushandisa neyechitatu-bato EDA synthesis maturusi, unogona kugadzira nzvimbo uye nguva yekufungidzira netlist. Kuti ugone kugonesa chizvarwa, batidza Gadzira nguva uye fungidziro yezvishandiso kune yechitatu-bato EDA synthesis maturusi paunenge uchigadzirisa yako IP musiyano.
Iyo nharaunda uye fungidziro yenguva netlist inotsanangura iyo IP musimboti yekubatanidza uye dhizaini, asi haisanganisire ruzivo nezve mashandiro echokwadi. Ruzivo urwu runogonesa mamwe echitatu-bato synthesis maturusi kuti aite zvirinani kurondedzera nzvimbo uye nguva yekufungidzira. Uye zvakare, maturusi ekubatanidza anogona kushandisa ruzivo rwenguva kuti awane optimization inofambiswa nenguva uye kugadzirisa mhando yemhedzisiro.
Iyo Intel Quartus Prime software inogadzira iyo _syn.v netlist file muVerilog HDL fomati, zvisinei nezvakabuda file fomati yaunotsanangura. Kana iwe ukashandisa iyi netlist yekubatanidza, iwe unofanirwa kusanganisira iyo IP musimboti wrapper file .v kana .vhd muIntel Quartus Prime project.

(7) Kana usina kumisa EDA chishandiso sarudzo- iyo inoita kuti iwe utange yechitatu-bato EDA simulators kubva kuIntel Quartus Prime software-mhanyisa chinyorwa ichi muModelSim kana QuestaSim simulator Tcl console (kwete muIntel Quartus Prime software. Tcl console) kudzivirira chero zvikanganiso.

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3.6. Kunyora Iyo Yakazara Dhizaini
Iwe unogona kushandisa iyo Kutanga Kuunganidza kuraira pane iyo Kugadzirisa menyu muIntel Quartus Prime Pro Edition software kuunganidza dhizaini yako.

F-Tile Serial Lite IV Intel® FPGA IP User Guide 18

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4. Tsanangudzo Inoshanda

Mufananidzo 5.

F-Tile Serial Lite IV Intel FPGA IP ine MAC uye Ethernet PCS. Iyo MAC inotaurirana neyakajairwa PCS kuburikidza neMII interfaces.

Iyo IP inotsigira maviri modulation modes:
PAM4–Inopa 1 kusvika gumi nembiri nhamba yenzira dzekusarudza. Iyo IP inogara ichisimbisa maviri PCS chiteshi kune imwe neimwe nzira muPAM12 modulation mode.
· NRZ–Inopa 1 kusvika gumi nematanhatu nhamba dzenzira dzekusarudza.

Imwe neimwe modulation mode inotsigira maviri data modes:
· Basic modhi-Iyi ndiyo yakachena yekutepfenyura modhi iyo data inotumirwa pasina yekutanga-packet, isina chinhu kutenderera, uye kupera-kwe-packet kuwedzera bandwidth. Iyo IP inotora yekutanga data data sekutanga kwekuputika.

Basic Mode Data Transfer tx_core_clkout tx_avs_ready

tx_avs_valid tx_avs_data rx_core_clkout rx_avs_ready

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_valid rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

ISO 9001:2015 Yakanyoreswa

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Mufananidzo 6.

· Yakazara modhi-Iyi ndiyo packet modhi yekufambisa data. Mune iyi modhi, iyo IP inotumira kuputika uye kutenderera kutenderera pakutanga uye kumagumo kwepaketi se delimiters.

Yakazara Modhi Yekuchinjisa Dhata tx_core_clkout

tx_avs_ready tx_avs_valid tx_avs_startofpacket tx_avs_endofpacket
tx_avs_data rx_core_clkout rx_avs_ready rx_avs_valid rx_avs_startofpacket rx_avs_endofpacket

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

Ruzivo Rwakabatana · F-Tile Serial Lite IV Intel FPGA IP Overview iri papeji 6 · F-Tile Serial Lite IV Intel FPGA IP Dhizaini Example User Guide

4.1. TX Datapath
Iyo TX datapath ine zvinhu zvinotevera: · MAC adapta · Kudzora izwi rekuisa block · CRC · MII encoder · PCS block · PMA block

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Mufananidzo 7. TX Datapath

Kubva mushandisi logic

TX MAC

Avalon Streaming Interface

MAC Adapter

Dzora Kupinza Shoko

CRC

MII Encoder

MII Interface Custom PCS
PCS uye PMA

TX Serial Interface Kune Imwe FPGA Chishandiso

4.1.1. TX MAC Adapter
Iyo TX MAC adapta inodzora kuendesa data kune mushandisi mantiki uchishandisa iyo Avalon® yekushambadzira interface. Ichi chivharo chinotsigira kufambisa-kutsanangurwa kweruzivo rwemushandisi uye kuyerera kwekutonga.

Kutamisa Mushandisi-yakatsanangurwa Ruzivo

Mune Yakazara modhi, iyo IP inopa tx_is_usr_cmd siginecha yaunogona kushandisa kutanga-yakatsanangurwa ruzivo kutenderera senge XOFF/XON kutapurirana kune mushandisi logic. Iwe unogona kutanga iyo inotsanangurwa nemushandisi ruzivo rwekufambisa kutenderera nekusimbisa chiratidzo ichi uye kuendesa ruzivo uchishandisa tx_avs_data pamwe nekutaura kwetx_avs_startofpacket uye tx_avs_valid masaini. Iyo block inozobvisa iyo tx_avs_yakagadzirira mavhiri maviri.

Cherechedza:

Iyo mushandisi-inotsanangurwa ruzivo ruzivo inowanikwa chete mune Yakazara mode.

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Mufananidzo 8.

Kudzora Kuyerera

Pane mamiriro ezvinhu apo iyo TX MAC haina kugadzirira kugamuchira data kubva kumushandisi logic senge panguva yekubatanidza re-alignment process kana pasina data iripo yekutapurirana kubva kumushandisi logic. Kuti udzivise kurasikirwa kwedata nekuda kwemamiriro ezvinhu aya, IP inoshandisa tx_avs_ready siginecha kudzora kuyerera kwe data kubva kumushandisi logic. Iyo IP inobvisa chiratidzo kana zvinotevera zvikaitika:
· Kana tx_avs_startofpacket ichinzi, tx_avs_ready inodhindwa kwewachi imwe chete.
· Kana tx_avs_endofpacket ichinzi, tx_avs_ready inodhindwa kwewachi imwe chete.
· Kana chero maCWs akapetwa achinzi tx_avs_ready inodhindwa kwemawachi maviri.
· Kana RS-FEC alignment marker kuiswa kunoitika pacustomer PCS interface, tx_avs_ready inodhindwa kwemawachi mana.
* Yese gumi nematanhatu Ethernet core wachi kutenderera muPAM17 modulation modulation uye yega makumi matatu nematatu Ethernet core wachi kutenderera muNRZ modulation mode. Iyo tx_avs_ready inodhindwa kwewachi imwe chete.
· Kana mushandisi logic dhiasserts tx_avs_valid panguva isina kutapurirana data.

Aya madhayagiramu enguva anotevera ndeekareampzvishoma zveTX MAC adapta uchishandisa tx_avs_ready yedata flow control.

Kudzora Kuyerera ne tx_avs_valid Deassertion uye START/END Akabatanidzwa CWs

tx_core_clkout

tx_avs_valid tx_avs_data

D1 D2 D3

Madhiziwiti anoshanda

D5 D6

tx_avs_ready tx_avs_startofpacket

Yakagadzirira siginecha madhizaini maviri ekutenderera kuisa END-STRT CW

tx_avs_endofpacket

usrif_data

D1 D2 D3

CW_data

DN END STRT D0 D1 D2 D3 EMPTY D4

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Mufananidzo 9.

Kudzora Kuyerera neAlignment Marker Insertion
tx_core_clkout tx_avs_valid

tx_avs_data tx_avs_ready

DN-5 DN-4 DN-3 DN-2 DN-1

DN+1

01234

tx_avs_startofpacket tx_avs_endofpacket

usrif_data CW_data CRC_data MII_data

DN-1 DN DN DN DN DN DN DN DN DN+1 DN-1 DN DN DN DN DN DN +1 DN-1 DN DN DN DN DN DN

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

DN-1

DN+1

i_sl_tx_mii_c[7:0]

0x0

i_sl_tx_mii_am

01234

i_sl_tx_mii_am_pre3

01234

Mufananidzo 10.

Kudzora Kuyerera ne START/END Paired CWs Inopindirana neAlignment Marker Insertion

tx_core_clkout tx_avs_valid

tx_avs_data

DN-5 DN-4 DN-3 DN-2 DN-1

tx_avs_ready

012 345 6

tx_avs_startofpacket

tx_avs_endofpacket

usrif_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

CW_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

CRC_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

MII_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

DN-1

PENDA STRT D0

i_sl_tx_mii_c[7:0]

0x0

i_sl_tx_mii_am i_sl_tx_mii_am_pre3

01234

4.1.2. Kudzora Izwi (CW) Insertion
Iyo F-Tile Serial Lite IV Intel FPGA IP inovaka maCWs zvichienderana nemasaini ekuisa kubva kumushandisi pfungwa. Iwo maCW anoratidza packet delimiters, ruzivo rwemamiriro ekufambisa kana data remushandisi kuPCS block uye anotorwa kubva kuXGMII control codes.
Tafura inotevera inoratidza tsananguro yemaCW anotsigirwa:

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Tafura 11.
TANGA KUENDERERA

Tsanangudzo yeCWs Inotsigirwa

Nhamba yeMazwi (1 izwi

= 64 bits)

Ehe

EMPTY_CYC

Ehe

IDLE

Aihwa

DATA

Ehe

In-band

Tsanangudzo
Kutanga kwedata delimiter. Kupera kwedata delimiter. Dzora izwi (CW) rekugadzirisa RX. Empty cycle mukuendesa data. IDLE (kunze kwebhendi). Payload.

Tafura 12. CW Munda Tsanangudzo
Munda RSVD nhamba_valid_bytes_eob
EMPTY eop sop seop align CRC32 usr

Tsanangudzo
Reserved field. Inogona kushandiswa kuwedzera mune ramangwana. Yakasungirirwa ku0.
Nhamba yemabhaiti anoshanda muzwi rekupedzisira (64-bit). Uku ndiko kukosha kwe3bit. · 3'b000: 8 bytes · 3'b001: 1 byte · 3'b010: 2 bytes · 3'b011: 3 bytes · 3'b100: 4 bytes · 3'b101: 5 byte · 3'b110: 6 bytes · 3'b111: 7 bytes
Nhamba yemazwi asina basa pakupera kwekuputika.
Inoratidza iyo RX Avalon yekushambadzira interface yekusimbisa chiratidzo chekuguma-kwe-packet.
Inoratidza iyo RX Avalon yekushambadzira interface yekusimbisa yekutanga-ye-packet chiratidzo.
Inoratidza iyo RX Avalon yekushambadzira interface yekusimbisa yekutanga-ye-packet uye kuguma-kwe-packet mukutenderera kumwechete.
Tarisa RX kurongeka.
Iko kukosha kwekombuta CRC.
Inoratidza kuti izwi rekutonga (CW) rine ruzivo rwakatsanangurwa nemushandisi.

F-Tile Serial Lite IV Intel® FPGA IP User Guide 24

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4.1.2.1. Kutanga-kwe-kuputika CW

Mufananidzo 11. Kutanga-kwe-kuputika kweCW Format

START

63:56

RSVD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16

sop usr align=0 seop

15:8

channel

7:0

'hFB(START)

kudzora 7:0

Tafura 13.

Mune Full mode, unogona kuisa START CW nekusimbisa tx_avs_startofpacket siginecha. Paunongotaura chete tx_avs_startofpacket siginecha, iyo sop bit inoiswa. Paunosimbisa zvese tx_avs_startofpacket uye tx_avs_endofpacket masiginecha, iyo seop bit inoiswa.

KUTANGA CW Munda Hukoshi
Munda sop/seop
usr (8)
align

Value

Zvichienderana ne tx_is_usr_cmd chiratidzo:

1: Kana tx_is_usr_cmd = 1

0: Kana tx_is_usr_cmd = 0

MuBasic modhi, iyo MAC inotumira START CW mushure mekunge kuseta kwabviswa. Kana pasina data iripo, MAC inoramba ichitumira EMPTY_CYC yakabatana neEND uye START CWs kusvika watanga kutumira data.

4.1.2.2. Kupera-kwe-kuputika CW

Mufananidzo 12. Kupera-kwe-kuputika kweCW Format

END

63:56

'hFD

55:48

CRC32[31:24]

47:40

CRC32[23:16]

data 39:32 31:24

CRC32[15:8] CRC32[7:0]

23:16 eop=1 RSVD RSVD RSVD

RSVD

15:8

RSVD

EMPTY

7:0

RSVD

nhamba_valid_bytes_eob

control

7:0

(8) Izvi zvinotsigirwa chete mu Full mode.
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Tafura 14.

Iyo MAC inoisa iyo END CW kana tx_avs_endofpacket ichinzi. Iyo END CW ine huwandu hwemabhaiti anoshanda pazwi rekupedzisira data uye ruzivo rweCRC.

CRC kukosha ndeye 32-bit CRC mhinduro yedata iri pakati pe START CW neshoko redata pamberi pe END CW.

Tafura inotevera inoratidza kukosha kweminda muEND CW.

END CW Munda Wakoshi
Munda eop CRC32 nhamba_valid_bytes_eob

Kukosha 1
CRC32 computed value. Nhamba yemabhaiti echokwadi pazwi rekupedzisira data.

4.1.2.3. Alignment Paired CW

Mufananidzo 13. Kurongeka Paired CW Format

ALIGN CW Paya ne START/END

64+8bits XGMII Interface

START

63:56

RSVD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16 eop=0 sop=0 usr=0 align=1 seop=0

15:8

RSVD

7:0

'hFB

kudzora 7:0

64+8bits XGMII Interface

END

63:56

'hFD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

kudzora 7:0

Iyo ALIGN CW ndeye CW yakapetwa ine START/END kana END/START CWs. Iwe unogona kuisa iyo ALIGN yapetwa CW nekusimbisa tx_link_reinit siginecha, kuseta iyo Alignment Period counter, kana kutanga kuseta patsva. Kana iyo ALIGN paired CW ikaiswa, iyo align munda inoiswa kune 1 kuti itange iyo inogamuchira yekumisikidza block kutarisa kurongeka kwedata mumigwagwa yese.

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Tafura 15.

ALIGN CW Munda Wakakosha
Kurongedza
eop sop usr seop

Kukosha 1 0 0 0 0

4.1.2.4. Empty-cycle CW

Mufananidzo 14. Empty-cycle CW Format

EMPTY_CYC Peya neEND/START

64+8bits XGMII Interface

END

63:56

'hFD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

kudzora 7:0

64+8bits XGMII Interface

START

63:56

RSVD

55:48

RSVD

47:40

RSVD

data

39:32 31:24

RSVD RSVD

23:16

sop=0 usr=0 align=0 seop=0

15:8

RSVD

7:0

'hFB

kudzora 7:0

Tafura 16.

Paunobvisa tx_avs_valid kwemawachi maviri panguva yekuputika, MAC inoisa EMPTY_CYC CW yakapetwa neEND/START CWs. Unogona kushandisa iyi CW kana pasina data iripo yekutapurirana kwechinguvana.

Paunobvisa tx_avs_valid kwechikamu chimwe chete, IP desserts tx_avs_valid kwekaviri nguva ye tx_avs_valid deassertion kugadzira peya yeEND/START CWs.

EMPTY_CYC CW Field Values
Kurongedza
eop

Kukosha 0 0

akaenderera…

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Munda sop usr seop

Kukosha 0 0 0

4.1.2.5. Idle CW

Mufananidzo 15. Idle CW Format

IDLE CW

63:56

'h07

55:48

'h07

47:40

'h07

data

39:32 31:24

'h07'h07

23:16

'h07

15:8

'h07

7:0

'h07

kudzora 7:0

Iyo MAC inoisa iyo IDLE CW kana pasina kutapurirana. Munguva iyi, tx_avs_valid chiratidzo chakaderera.
Iwe unogona kushandisa iyo IDLE CW kana kuputika kwekufambisa kwapera kana kutapurirana kuri munzvimbo isina basa.

4.1.2.6. Data Word

Izwi re data ndiro mubhadharo wepaketi. Iyo XGMII yekudzora mabhiti ese akaiswa ku0 mune data izwi fomati.

Mufananidzo 16. Data Word Format

64+8 bits XGMII Interface

DATA WORD

63:56

data yemushandisi 7

55:48

data yemushandisi 6

47:40

data yemushandisi 5

data

39:32 31:24

data remushandisi 4 data remushandisi 3

23:16

data yemushandisi 2

15:8

data yemushandisi 1

7:0

data yemushandisi 0

kudzora 7:0

4.1.3. TX CRC
Iwe unogona kugonesa iyo TX CRC block uchishandisa iyo Gonesa CRC paramende muIP Parameter Mharidzo. Iyi ficha inotsigirwa mune ese maBasic uye Full modes.

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Iyo MAC inowedzera kukosha kweCRC kuEND CW nekusimbisa tx_avs_endofpacket siginecha. Mune iyo BASIC modhi, iyo ALIGN CW chete yakapetwa neEND CW ine inoshanda CRC ndima.
Iyo TX CRC block inopindirana neTX Control Word Insertion uye TX MII Encode block. Iyo TX CRC block inokokorodza kukosha kweCRC ye64-bit kukosha pa-cycle data kubva paSTART CW kusvika paEND CW.
Iwe unogona kutaura iyo crc_error_inject siginecha yekukanganisa nemaune data mune yakatarwa nzira kugadzira CRC zvikanganiso.

4.1.4. TX MII Encoder

Iyo TX MII encoder inobata kutakura kwepaketi kubva kuMAC kuenda kuTX PCS.

Nhamba inotevera inoratidza iyo data patani pa8-bit MII bhazi muPAM4 modulation mode. Iyo START uye END CW inooneka kamwe mumigwagwa miviri yeMII.

Mufananidzo 17. PAM4 Modulation Mode MII Data Pattern

CYCLE 1

CYCLE 2

CYCLE 3

CYCLE 4

CYCLE 5

SOP_CW

DATA_1

DATA_9 DATA_17

IDLE

DATA_DUMMY SOP_CW
DATA_DUMMY

DATA_2 DATA_3 DATA_4

DATA_10 DATA_11 DATA_12

DATA_18 DATA_19 DATA_20

EOP_CW IDLE
EOP_CW

SOP_CW

DATA_5 DATA_13 DATA_21

IDLE

DATA_DUMMY DATA_6 DATA_14 DATA_22 EOP_CW

SOP_CW DATA_DUMMY

DATA_7 DATA_8

DATA_15 DATA_16

DATA_23 DATA_24

IDLE EOP_CW

Nhamba inotevera inoratidza iyo data patani pa8-bit MII bhazi muNRZ modulation mode. Iyo START uye END CW inoonekwa munzira dzese dzeMII.

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Mufananidzo 18. NRZ Modulation Mode MII Data Pattern

CYCLE 1

CYCLE 2

CYCLE 3

SOP_CW

DATA_1

DATA_9

SOP_CW

DATA_2 DATA_10

SOP_CW SOP_CW

DATA_3 DATA_4

DATA_11 DATA_12

SOP_CW

DATA_5 DATA_13

SOP_CW

DATA_6 DATA_14

SOP_CW

DATA_7 DATA_15

SOP_CW

DATA_8 DATA_16

CYCLE 4 DATA_17 DATA_18 DATA_19 DATA_20 DATA_21 DATA_22 DATA_23 DATA_24

CYCLE 5 EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW

4.1.5. TX PCS uye PMA
Iyo F-Tile Serial Lite IV Intel FPGA IP inogadzirisa iyo F-tile transceiver kune Ethernet PCS modhi.

4.2. RX Datapath
Iyo RX datapath ine zvinhu zvinotevera: · PMA block · PCS block · MII decoder · CRC · Deskew block · Kudzora Shoko rekubvisa block

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Mufananidzo 19. RX Datapath

Kune mushandisi logic Avalon Streaming Interface
RX MAC
Dzora Kubvisa Shoko
Deskew

CRC

MII Decoder

MII Interface Custom PCS
PCS uye PMA

RX Serial Interface Kubva kune Imwe FPGA Chishandiso
4.2.1. RX PCS uye PMA
Iyo F-Tile Serial Lite IV Intel FPGA IP inogadzirisa F-tile transceiver kune Ethernet PCS maitiro.
4.2.2. RX MII Decoder
Iri bhuroka rinoratidza kana dhata rinouya riine izwi rekudzora uye nekumisikidza mamaki. Iyo RX MII decoder inoburitsa data iri muchimiro che1-bit inoshanda, 1-bit marker chiratidzo, 1bit control chiratidzo, uye 64-bit data panzira.
4.2.3. RX CRC
Iwe unogona kugonesa iyo TX CRC block uchishandisa iyo Gonesa CRC paramende muIP Parameter Mharidzo. Iyi ficha inotsigirwa mune ese maBasic uye Full modes. Iyo RX CRC block inopindirana neRX Kudzora Shoko Kubvisa uye RX MII Decoder mabhuroko. Iyo IP inotaura rx_crc_error chiratidzo kana CRC kukanganisa.

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Iyo IP inobvisa iyo rx_crc_error pakuputika kwega kwega. Icho chinobuda kune mushandisi logic yemushandisi logic kukanganisa kubata.
4.2.4. RX Deskew
Iyo RX deskew block inoona mamaki ekumisikidza kune yega yega nzira uye inogadzirisa zvakare iyo data isati yatumira kune iyo RX CW yekubvisa block.
Iwe unogona kusarudza kurega iyo IP musimboti kuti ienzanise iyo data kune yega nzira otomatiki kana kukanganisa kwekugadzirisa kukaitika nekuisa iyo Inogonesa Auto Alignment parameter muIP parameter Mharidzo. Kana iwe ukadzima iyo otomatiki yekumisikidza ficha, iyo IP musimboti inotaura rx_error chiratidzo kuratidza kukanganisa kwekugadzirisa. Iwe unofanirwa kutaura rx_link_reinit kuti utange nzira yekumisikidza nzira kana kukanganisa kwenzira kukaitika.
Iyo RX deskew inoona mamaki ekumisikidza akavakirwa pamushini wehurumende. Dhiagiramu inotevera inoratidza nyika muRX deskew block.

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Mufananidzo 20.

RX Deskew Lane Alignment State Machine ine Auto Alignment Inogonesa Flow Chart
Tanga

IDLE

Reset = 1 hongu kwete

Yese maPC

Aihwa

nzira dzakagadzirira?

Ehe

WAIT

Yese mamakisi ekubatanidza kwete
waonekwa?
Ehe
ALIGN

Aihwa
hongu Timeout?

Ehe
Warasika kurongeka?
no End

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Mufananidzo 21.

RX Deskew Lane Alignment State Machine ine Auto Alignment Yakaremara Flow Chart
Tanga

IDLE

Reset = 1 hongu kwete

Yese maPC

Aihwa

nzira dzakagadzirira?

Ehe

Ehe
rx_link_reinit =1
hapana ERROR

kwete hongu Timeout?

WAIT
kwete All sync markers
waonekwa?
hongu ALIGN

Ehe
Warasika kurongeka?
Aihwa
End
1. Kurongeka kwekugadzirisa kunotanga neIDLE state. Iyo block inoenda ku WAIT state kana nzira dzese dzePCS dzagadzirira uye rx_link_reinit yabviswa.
2. Mu WAIT mamiriro, bhuroka rinotarisa zvese zvakaonekwa mamaki anosimbiswa mukati meiyo kutenderera kumwechete. Kana mamiriro aya ari echokwadi, bhuroka rinoenda kune ARIGNED state.
3. Kana chivharo chiri mu ALIGNED state, chinoratidza kuti mikoto yakarongeka. Mune ino mamiriro, iyo block inoenderera nekutarisa kurongeka kwenzira uye kutarisa kana ese mamaki aripo mukati mekutenderera kumwechete. Kana chinenge chicherechedzo chisipo mukutenderera kumwechete uye iyo Inogonesa Auto Alignment parameter yaiswa, block inoenda kune

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IDLE nyika kuti itangezve maitiro ekugadzirisa. Kana Gonesa Auto Alignment isina kusetwa uye kana chicherechedzo chimwechete chisipo mukutenderera kumwechete, block inoenda kuERROR state uye inomirira kuti mushandisi pfungwa ataure rx_link_reinit siginecha kuti atange nzira yekumisikidza nzira.

Mufananidzo 22. Kurongeka kweMukoto neInogonesa Kurongeka Kwemotokari Inogoneswa rx_core_clk

rx_link_up

rx_link_reinit

uye_zvose_zvicherechedzo

Deskew State

ALGNED

IDLE

WAIT

ALGNED

AUTO_ALIGN = 1

Mufananidzo 23. Kurongekazve kweNzira neInogonesa Kurongedza Otomatiki Yakaremara rx_core_clk

rx_link_up

rx_link_reinit

uye_zvose_zvicherechedzo

Deskew State

ALGNED

ERROR

IDLE

WAIT

ALGNED

AUTO_ALIGN = 0
4.2.5. RX CW Kubviswa
Iyi block inogadzirisa maCW uye inotumira data kumushandisi wekushandisa uchishandisa iyo Avalon yekushambadzira interface mushure mekubviswa kweCWs.
Kana pasina data iripo, iyo RX CW yekubvisa block desserts iyo rx_avs_valid chiratidzo.
Mune FULL mode, kana mushandisi bhiti akaiswa, iyi block inomiririra rx_is_usr_cmd chiratidzo uye data iri mukutanga wachi kutenderera rinoshandiswa seruzivo-rakatsanangurwa nemushandisi kana kuraira.
Kana rx_avs_ready deasserts uye rx_avs_valid zvirevo, iyo RX CW yekubvisa block inoburitsa mamiriro ekukanganisa kune mushandisi logic.
Masaini eAvalon ekutepfenyura ane chekuita neblock iri anotevera: · rx_avs_startofpacket · rx_avs_endofpacket · rx_avs_channel · rx_avs_empty · rx_avs_data

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· rx_avs_valid
· rx_num_valid_bytes_eob
· rx_is_usr_cmd (inowanikwa chete mu Full mode)
4.3. F-Tile seri Lite IV Intel FPGA IP Clock Architecture
Iyo F-Tile Serial Lite IV Intel FPGA IP ine wachi ina yekupinza iyo inogadzira wachi kune akasiyana mabhuroko: · Transceiver referensi wachi (xcvr_ref_clk) -Kupinza wachi kubva kunze wachi.
machipisi kana oscillator anogadzira wachi dzeTX MAC, RX MAC, uye TX uye RX tsika PCS mabhuroko. Tarisa kuParameters kune inotsigirwa frequency renji. · TX core clock (tx_core_clk)-Iyi wachi inotorwa kubva kune transceiver PLL inoshandiswa paTX MAC. Wachi iyi zvakare inoburitsa wachi kubva kuF-tile transceiver yekubatanidza kune TX mushandisi mantiki. RX core clock (rx_core_clk) -Iyi wachi inotorwa kubva kune transceiver PLL inoshandiswa RX deskew FIFO uye RX MAC. Wachi iyi zvakare inoburitsa wachi kubva kuF-tile transceiver yekubatanidza kune RX mushandisi logic. · Wachi yetransceiver reconfiguration interface (reconfig_clk) -wachi yekupinda kubva kunze kwewachi maseketi kana oscillator iyo inogadzira wachi dzeF-tile transceiver reconfiguration interface mune zvese TX neRX datapaths. Wachi frequency ndeye 100 kusvika 162 MHz.
Iyi inotevera block dhizaini inoratidza F-Tile Serial Lite IV Intel FPGA IP wachi madomasi uye zvinongedzo mukati meIP.

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Mufananidzo 24.

F-Tile seri Lite IV Intel FPGA IP Clock Architecture

Oscillator

FPGA1
F-Tile Serial Lite IV Intel FPGA IP Transceiver Reconfiguration Interface Clock
(reconfig_clk)

tx_core_clkout (batanidza kune mushandisi logic)

tx_core_clk= clk_pll_div64[pakati_ch]

FPGA2

F-Tile seri Lite IV Intel FPGA IP

Transceiver Reconfiguration Interface Clock

(reconfig_clk)

Oscillator

rx_core_clk= clk_pll_div64[pakati_ch]

rx_core_clkout (batanidza kune mushandisi logic)

clk_pll_div64[mid_ch] clk_pll_div64[n-1:0]

Avalon Streaming Interface TX Data
TX MAC

serial_link[n-1:0]

Deskew

FIFO

Avalon Streaming Interface RX Data RX MAC

Avalon Streaming Interface RX Data
RX MAC

Deskew FIFO

rx_core_clkout (batanidza kune mushandisi logic)

rx_core_clk= clk_pll_div64[pakati_ch]

Custom PCS

serial_link[n-1:0]

TX MAC

Avalon Streaming Interface TX Data

tx_core_clk= clk_pll_div64[pakati_ch]

tx_core_clkout (batanidza kune mushandisi logic)

Transceiver Ref Clock (xcvr_ref_clk)
Transceiver Ref Clock (xcvr_ref_clk)

Oscillator*

Legend

FPGA mudziyo
TX musimboti wachi domain
RX musimboti wachi domain
Transceiver referensi wachi domain Yekunze mudziyo Zviratidzo zvedata

4.4. Reset uye Link Initialization
Iyo MAC, F-tile Yakaoma IP, uye mabhuroki ekugadzirisa zvakare ane akasiyana masaini ekuisa patsva: · TX uye RX MAC mabhuroko anoshandisa tx_core_rst_n uye rx_core_rst_n reset masaini. · tx_pcs_fec_phy_reset_n uye rx_pcs_fec_phy_reset_n reset zviratidzo drive
iyo yakapfava reset controller yekumisikidza zvakare F-tile Hard IP. · Reconfiguration block inoshandisa reconfig_reset reset chiratidzo.

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Mufananidzo 25. Reset Architecture
Avalon Streaming Interface TX Data
MAC
Avalon Streaming SYNC Interface RX Data

FPGA F-tile Seri Lite IV Intel FPGA IP

tx_mii rx_mii
phy_ehip_ready phy_rx_pcs_ready

F-tile Yakaoma IP

TX Serial Data RX Serial Data

tx_core_rstn rx_core_rstn tx_pcs_fec_phy_reset_n rx_pcs_fec_phy_reset_n reconfig_reset

Dzorerazve Logic
Ruzivo rwunoenderana · Reset Mazano ari papeji 51 · F-Tile Serial Lite IV Intel FPGA IP Design Example User Guide
4.4.1. TX Reset uye Initialization Sequence
Iyo TX reset sequence yeF-Tile Serial Lite IV Intel FPGA IP ndeiyi inotevera: 1. Assert tx_pcs_fec_phy_reset_n, tx_core_rst_n, uye reconfig_reset
panguva imwe chete kuseta zvakare F-tile yakaoma IP, MAC, uye zvidhinha zvekugadzirisa. Sunungura tx_pcs_fec_phy_reset_n uye reconfiguration reset mushure mekumirira tx_reset_ack kuti ive nechokwadi chekuti mabhuroki aiswa patsva. 2. IP inobva yati phy_tx_lanes_stable, tx_pll_locked, uye phy_ehip_ready zviratidzo mushure mokunge tx_pcs_fec_phy_reset_n reset yasunungurwa, kuratidza kuti TX PHY yakagadzirira kutapurika. 3. Chiratidzo che tx_core_rst_n dhiasserts mushure mokunge phy_ehip_ready chiratidzo ichikwira. 4. IP inotanga kutumira mavara eIDLE paMII interface kana MAC yapera. Iko hakuna chinodiwa kuti TX kurongeka uye skewing nekuti nzira dzese dzinoshandisa wachi imwechete. 5. Paunenge uchitumira mavara eIDLE, MAC inosimbisa tx_link_up chiratidzo. 6. MAC inobva yatanga kutumira ALIGN yakapetwa ne START/END kana END/START CW panguva yakatarwa kuti itange nzira yekuenzanisa nzira yeinogamuchira yakabatana.

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Mufananidzo 26.

TX Reset uye Kutanga Nguva Yenguva Dhiagiramu
reconfig_sl_clk

reconfig_clk

tx_core_rst_n

tx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

tx_reset_ack

tx_pll _yakavharwa

phy_tx_lanes_stable

phy_ehip_ready

tx_li nk_up

7
5 6 8

4.4.2. RX Reset uye Initialization Sequence
Iyo RX reset sequence yeF-Tile Serial Lite IV Intel FPGA IP yakaita seinotevera:
1. Assert rx_pcs_fec_phy_reset_n, rx_core_rst_n, uye reconfig_reset panguva imwe chete kugadzirisa F-tile yakaoma IP, MAC, uye reconfiguration blocks. Sunungura rx_pcs_fec_phy_reset_n uye reconfiguration reset mushure mekumirira rx_reset_ack kuti ive nechokwadi chekuti mabhuroki akaiswa patsva.
2. IP inobva yati phy_rx_pcs_ready chiratidzo mushure mokunge tsika PCS reset yasunungurwa, kuratidza RX PHY yakagadzirira kutapurika.
3. Chiratidzo che rx_core_rst_n dhiasserts mushure me phy_rx_pcs_ready chiratidzo chinoenda kumusoro.
4. IP inotanga nzira yekugadzirisa nzira mushure mekunge RX MAC reset yasunungurwa uye pakugamuchira ALIGN yapetwa START/END kana END/START CW.
5. Iyo RX deskew block inosimbisa iyo rx_link_up chiratidzo kana kurongeka kwenzira dzese kwapera.
6. IP inobva yataura rx_link_up chiratidzo kumushandisi logic kuratidza kuti RX link yakagadzirira kutanga kugamuchira data.

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Mufananidzo 27. RX Reset uye Initialization Timing Diagram
reconfig_sl_clk

reconfig_clk

rx_core_rst_n

rx_pcs_fec_phy_reset_n 1

reconfig_reset

reconfig_sl_reset

rx_reset_ack

rx_cdr_lock

rx_block_lock

rx_pcs_ready

rx_link_up

3 3 3 2

4 5 5

6 7

4.5. Link Rate uye Bandwidth Efficiency Calculation

Iyo F-Tile Serial Lite IV Intel FPGA IP bandwidth kunyatso calculation iri pazasi:

Bandwidth kunyatsoshanda = raw_rate * 64/66 * (burst_size – burst_size_ovhd)/burst_size * [align_marker_period / (align_marker_period + align_marker_width)] * [(srl4_align_period – 2) / srl4_align_period]

Tafura 17. Bandwidth Efficiency Variables Tsanangudzo

Variable

Tsanangudzo

mbishi_rate burst_size

Iyi ndiyo bit rate inowanikwa neiyo serial interface. raw_rate = SERDES hupamhi * transceiver wachi frequency Example: raw_rate = 64 * 402.812500 Gbps = 25.78 Gbps
Kukosha kwekukura kwekuputika. Kuti uverenge avhareji bandwidth kushanda, shandisa zvakajairika kuputika saizi kukosha. Kuti uwane huwandu hwehuwandu, shandisa huwandu hwehukuru hwakaputika.

burst_size_ovhd

The burst size overhead value.
Mune Full mode, burst_size_ovhd kukosha kuri kureva START uye END maCW akapetwa.
MuBasic mode, hapana burst_size_ovhd nekuti hapana START uye END maCW akabatana.

align_marker_period

Kukosha kwenguva inoiswa chiratidzo chekuenzanisa. Iko kukosha ndeye 81920 wachi kutenderera kwekubatanidza uye 1280 yekukurumidza simulation. Kukosha uku kunowanikwa kubva kuPCS hard logic.

align_marker_width srl4_align_period

Huwandu hwema dhizaini ewachi panokwirirwa chiratidzo chechiratidzo chekuenzanisa.
Huwandu hwekutenderera kwewachi pakati pemaki maviri ekurongeka. Unogona kuseta kukosha uku uchishandisa iyo Alignment Period parameter muIP Parameter Mharidzo.

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Maverengero echiyero chekubatanidza ari pasi apa: Chiyero chinoshanda = bandwidth kunyatsoshanda * raw_rate Unogona kuwana yakanyanya mushandisi wachi frequency neinotevera equation. Iyo yakanyanya mushandisi wachi frequency kuverenga inotora inoenderera data kutenderera uye hapana IDLE kutenderera kunoitika pamushandisi logic. Mwero uyu wakakosha pakugadzira mushandisi mantiki FIFO kudzivirira FIFO kufashukira. Yakanyanya mushandisi wachi frequency = inoshanda mwero / 64

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5. Paramita

Tafura 18. F-Tile Serial Lite IV Intel FPGA IP Parameter Tsanangudzo

Parameter

Value

Default

Tsanangudzo

General Design Options

PMA modulation mhando

PAM4 · NRZ

PAM4

Sarudza PCS modulation mode.

PMA Type

· FHT · FGT

FGT

Inosarudza mhando yetransceiver.

PMA data mutengo

YePAM4 modhi:
- FGT transceiver mhando: 20 Gbps 58 Gbps
- FHT transceiver mhando: 56.1 Gbps, 58 Gbps, 116 Gbps
YeNRZ modhi:
- FGT transceiver mhando: 10 Gbps 28.05 Gbps
- FHT transceiver mhando: 28.05 Gbps, 58 Gbps

56.1 (FGT/FHT PAM4)
28.05 Gbps (FGT/FHT NRZ)

Inotsanangura huwandu hwe data hunoshanda pakubuda kweiyo transceiver inobatanidza kutapurirana uye zvimwe pamusoro. Hukoshi hunoverengerwa neIP nekutenderedza kusvika 1 decimal nzvimbo muGbps unit.

PMA mode

· Duplex · Tx · Rx

Duplex

Kune FHT transceiver mhando, iyo inotsigirwa nzira ndeye duplex chete. Kune FGT transceiver mhando, iyo inotsigirwa nzira ndeye Duplex, Tx, uye Rx.

Nhamba ye PMA

YePAM4 modhi:

nzira

- 1 kusvika ku12

YeNRZ modhi:

- 1 kusvika ku16

Sarudza nhamba yemigwagwa. Kune simplex dhizaini, nhamba inotsigirwa yenzira ndeye 1.

PLL referensi wachi frequency

· YeFHT transceiver mhando: 156.25 MHz
· YeFGT transceiver mhando: 27.5 MHz 379.84375 MHz, zvichienderana neyakasarudzwa transceiver data rate.

· YeFHT transceiver mhando: 156.25 MHz
· YeFGT transceiver mhando: 165 MHz

Inodoma frequency yewachi yetransceiver.

System PLL

—

referensi wachi

frequency

170 MHz

Inowanikwa chete yeFHT transceiver type. Inotsanangura iyo System PLL referensi wachi uye ichashandiswa sekuisa kweF-Tile Reference uye System PLL Mawachi Intel FPGA IP kugadzira iyo System PLL wachi.

System PLL frequency
Nguva yeAlignment

— 128 65536

Gonesa RS-FEC

Enable

876.5625 MHz 128 Gonesa

Inotsanangura iyo System PLL wachi frequency.
Inotsanangura nguva yechiratidzo. Kukosha kunofanira kuva x2. Batidza kugonesa RS-FEC chimiro.
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Parameter

Value

Default

Tsanangudzo

Disable

YePAM4 PCS modulation mode, RS-FEC inogara ichigoneswa.

User Interface

Streaming mode

· ZVAKAZARA · BASIC

Full

Sarudza iyo data inoyerera yeIP.

Yakazara: Iyi modhi inotumira yekutanga-ye-packet uye kupera-kwe-packet kutenderera mukati mefuremu.

Nheyo: Iyi ndiyo nzira yakachena yekufambisa iyo data inotumirwa pasina kutanga-kwe-packet, isina chinhu, uye kupera-kwe-packet kuwedzera bandwidth.

Gonesa CRC

Gonesa Disable

Disable

Batidza kuti CRC ione kukanganisa uye kugadzirisa.

Gonesa kurongeka kwe otomatiki

Gonesa Disable

Disable

Batidza kuti uite otomatiki nzira yekuenzanisa.

Gonesa debug endpoint

Gonesa Disable

Disable

Kana ON, iyo F-Tile Serial Lite IV Intel FPGA IP inosanganisira yakamisikidzwa Debug Endpoint iyo yemukati inobatana neAvalon memory-mapped interface. Iyo IP inogona kuita mimwe miedzo uye kugadzirisa mabasa kuburikidza neJTAG uchishandisa iyo System Console. Default value iri Off.

Simplex Kubatanidza (Iyi paramende inongowanikwa chete kana ukasarudza FGT dual simplex dhizaini.)

RSFEC inogoneswa pane imwe Serial Lite IV Simplex IP yakaiswa pane imwechete FGT chiteshi (s)

Gonesa Disable

Disable

Batidza iyi sarudzo kana iwe uchida musanganiswa wekumisikidza neRS-FEC inogoneswa uye yakaremara yeF-Tile Serial Lite IV Intel FPGA IP mune mbiri simplex dhizaini yeNRZ transceiver mode, uko zvese TX neRX zvakaiswa paFGT imwechete. chiteshi(s).

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6. F-Tile Serial Lite IV Intel FPGA IP Interface Signals

6.1. Clock Signals

Tafura 19. Zviratidzo zvewachi

Zita

Width Direction

Tsanangudzo

tx_core_clkout

Output TX musimboti wachi yeTX tsika PCS interface, TX MAC uye mushandisi mantiki mukati.

iyo TX datapath.

Wachi iyi inogadzirwa kubva kutsika PCS block.

rx_core_clkout

Kuburitsa RX musimboti wachi yeRX tsika PCS interface, RX deskew FIFO, RX MAC

uye mushandisi mantiki muRX datapath.

Wachi iyi inogadzirwa kubva kutsika PCS block.

xcvr_ref_clk
reconfig_clk reconfig_sl_clk

Isa Transceiver referensi wachi.

Kana iyo transceiver mhando yaiswa kuFGT, batanidza wachi iyi kune inobuda chiratidzo (out_refclk_fgt_0) yeF-Tile Reference uye System PLL Clocks Intel FPGA IP. Kana iyo transceiver mhando yakaiswa kuFHT, batanidza

wachi iyi kune inobuda chiratidzo (kunze_fht_cmmpll_clk_0) yeF-Tile Reference uye System PLL Clocks Intel FPGA IP.

Tarisa kuParameters kune inotsigirwa frequency renji.

Input wachi ye transceiver reconfiguration interface.

Wachi frequency ndeye 100 kusvika 162 MHz.

Batanidza iyi wachi yekuisa chiratidzo kune ekunze wachi maseketi kana oscillator.

Input wachi ye transceiver reconfiguration interface.

Wachi frequency ndeye 100 kusvika 162 MHz.

Batanidza iyi wachi yekuisa chiratidzo kune ekunze wachi maseketi kana oscillator.

out_systempll_clk_ 1

Input

System PLL wachi.
Batanidza wachi iyi kune inobuda chiratidzo (out_systempll_clk_0) yeF-Tile Reference uye System PLL Mawachi Intel FPGA IP.

Inoenderana Ruzivo Paramita pane peji 42

6.2. Reset Signals

Tafura 20. Reset Signals

Zita

Width Direction

tx_core_rst_n

Input

Clock Domain Asynchronous

rx_core_rst_n

Input

Asynchronous

tx_pcs_fec_phy_reset_n 1

Input

Asynchronous

Tsanangudzo

Active-low reset chiratidzo. Reset iyo F-Tile Serial Lite IV TX MAC.

Active-low reset chiratidzo. Reset iyo F-Tile Serial Lite IV RX MAC.

Active-low reset chiratidzo.

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Zita

Width Direction Clock Domain

Tsanangudzo

Reset iyo F-Tile Serial Lite IV TX tsika PCS.

rx_pcs_fec_phy_reset_n 1

Input

Asynchronous

Active-low reset chiratidzo. Reset iyo F-Tile Serial Lite IV RX tsika PCS.

reconfig_reset

Input

reconfig_clk Active-yakakwirira reset chiratidzo.

Inogadzirisazve iyo Avalon memory-mapped interface reconfiguration block.

reconfig_sl_reset

Input reconfig_sl_clk Active-high reset chiratidzo.

Inogadzirisazve iyo Avalon memory-mapped interface reconfiguration block.

6.3. MAC Signals

Tafura 21.

TX MAC Signals
Mutafura iyi, N inomiririra huwandu hwenzira dzakaiswa muIP parameter mupepeti.

Zita

Upamhi

Direction Clock Domain

Tsanangudzo

tx_avs_ready

Output tx_core_clkout Avalon yekufambisa chiratidzo.

Kana yasimbiswa, inoratidza kuti TX MAC yakagadzirira kugamuchira data.

tx_avs_data

· (64*N)*2 (PAM4 modhi)
· 64*N (NRZ mode)

Input

tx_core_clkout Avalon yekufambisa chiratidzo. TX data.

tx_avs_channel

Input tx_core_clkout Avalon sigini yekufambisa.

Nhamba yechiteshi che data iri kutamiswa pane yazvino kutenderera.

Iyi siginecha haisi kuwanikwa muBasic mode.

tx_avs_valid

Input tx_core_clkout Avalon sigini yekufambisa.

Kana yakasimbiswa, inoratidza iyo TX data siginecha inoshanda.

tx_avs_startofpacket

Input tx_core_clkout Avalon sigini yekufambisa.

Kana yasimbiswa, inoratidza kutanga kweTX data packet.

Ongorora kungotenderera wachi imwe chete packet yega yega.

Iyi siginecha haisi kuwanikwa muBasic mode.

tx_avs_endofpacket

Input tx_core_clkout Avalon sigini yekufambisa.

Kana yakasimbiswa, inoratidza kupera kweTX data packet.

Ongorora kungotenderera wachi imwe chete packet yega yega.

Iyi siginecha haisi kuwanikwa muBasic mode.

tx_avs_empty

Input tx_core_clkout Avalon sigini yekufambisa.

Inotaridza huwandu hwemazwi asiri echokwadi mukuputika kwekupedzisira kweTX data.

Iyi siginecha haisi kuwanikwa muBasic mode.

tx_num_valid_bytes_eob

Input

tx_core_clkout

Inoratidza huwandu hwemabhaiti anoshanda muzwi rekupedzisira rekupedzisira kuputika. Iyi siginecha haisi kuwanikwa muBasic mode.
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Zita tx_is_usr_cmd
tx_link_up tx_link_reinit
crc_error_inject tx_error

Upamhi 1
1 1
N 5

Direction Clock Domain

Tsanangudzo

Input

tx_core_clkout

Kana yakasimbiswa, chiratidzo ichi chinotangisa mushandisi akatsanangurwa ruzivo kutenderera.
Rongedza chiratidzo ichi panguva imwe chete yewachi se tx_startofpacket assertion.
Iyi siginecha haisi kuwanikwa muBasic mode.

Output tx_core_clkout Kana zvichinzi, zvinoratidza kuti TX data link yagadzirira kutapurirana data.

Output

tx_core_clkout

Kana ikasimbiswa, chiratidzo ichi chinotangisa kurongekazve kwemigwagwa.
Rongedza iyi siginecha yewachi imwe chete kuti iite kuti MAC itumire ALIGN CW.

Input

tx_core_clkout Kana zvichinzi, MAC inobaya CRC32 kukanganisa kune nzira dzakasarudzwa.

Output tx_core_clkout Haina kushandiswa.

Inotevera dhayagiramu yenguva inoratidza example yeTX data kutumirwa kwemazwi gumi kubva mushandisi mantiki kuyambuka gumi TX serial nzira.

Mufananidzo 28.

TX Dhata Yekufambisa Nguva Dhiagiramu
tx_core_clkout

tx_avs_valid

tx_avs_ready

tx_avs_startofpackets

tx_avs_endofpackets

tx_avs_data

0,1..,19 10,11…19 …… N-10..

0,1,2, 9, XNUMX,…, XNUMX

… N-10..

Nzira ye0

……………

STT 0 10

N-10 END 0

Nzira ye1

……………

STT 1 11

N-9 END 1

N-10 KUPEDZA IDLE IDLE N-9 KUPEDZA IDLE IDLE

Nzira ye9

……………

STT 9 19

N-1 END 9

N-1 KUPERA IDLE IDLE

Tafura 22.

RX MAC Zviratidzo
Mutafura iyi, N inomiririra huwandu hwenzira dzakaiswa muIP parameter mupepeti.

Zita

Upamhi

Direction Clock Domain

Tsanangudzo

rx_avs_ready

Input rx_core_clkout Avalon sigini yekufambisa.

Kana yasimbiswa, inoratidza kuti mushandisi pfungwa yakagadzirira kugamuchira data.

rx_avs_data

(64*N)*2 (PAM4 modhi)
64*N (NRZ mode)

Output

rx_core_clkout Avalon yekufambisa chiratidzo. RX data.

rx_avs_channel

Kubuda rx_core_clkout Avalon yekuyerera sigiyoni.

Nhamba yechiteshi che data

yakagamuchirwa pane yazvino kutenderera.

Iyi siginecha haisi kuwanikwa muBasic mode.

rx_avs_valid

Kubuda rx_core_clkout Avalon yekuyerera sigiyoni.

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Zita

Upamhi

Direction Clock Domain

Tsanangudzo

Kana yakasimbiswa, inoratidza iyo RX data siginecha inoshanda.

rx_avs_startofpacket

Kubuda rx_core_clkout Avalon yekuyerera sigiyoni.

Kana yakasimbiswa, inoratidza kutanga kweRX data packet.

Ongorora kungotenderera wachi imwe chete packet yega yega.

Iyi siginecha haisi kuwanikwa muBasic mode.

rx_avs_endofpacket

Kubuda rx_core_clkout Avalon yekuyerera sigiyoni.

Kana yakasimbiswa, inoratidza kupera kweRX data packet.

Ongorora kungotenderera wachi imwe chete packet yega yega.

Iyi siginecha haisi kuwanikwa muBasic mode.

rx_avs_empty

Kubuda rx_core_clkout Avalon yekuyerera sigiyoni.

Inoratidza nhamba yemashoko asina-akakodzera mukuputika kwekupedzisira kweRX data.

Iyi siginecha haisi kuwanikwa muBasic mode.

rx_num_valid_bytes_eob

Output

rx_core_clkout Inoratidza huwandu hwemabhaiti anoshanda muzwi rekupedzisira rekupedzisira kuputika.
Iyi siginecha haisi kuwanikwa muBasic mode.

rx_is_usr_cmd

Output rx_core_clkout Kana zvichinzi, chiratidzo ichi chinotangisa mushandisi-

inotsanangurwa kutenderera kweruzivo.

Rongedza chiratidzo ichi panguva imwe chete yewachi se tx_startofpacket assertion.

Iyi siginecha haisi kuwanikwa muBasic mode.

rx_link_up

Output rx_core_clkout Kana yasimbiswa, inoratidza RX data link

yakagadzirira kugamuchira data.

rx_link_reinit

Input rx_core_clkout Kana zvichinzi, chiratidzo ichi chinotangisa nzira

kugadzirisa zvakare.

Kana iwe ukadzima Gonesa Auto Alignment, simbisa iyi siginecha yewachi imwe kutenderera kukonzeresa iyo MAC kurongedzazve nzira. Kana iyo Inogonesa Auto Alignment yakasetwa, iyo MAC inogadzirisa nzira otomatiki.

Usataure chiratidzo ichi kana Gonesa Auto Alignment yaiswa.

rx_error

(N*2*2)+3 (PAM4 modhi)
(N*2)*3 (NRZ mode)

Output

rx_core_clkout

Kana yakasimbiswa, inoratidza kukanganisa mamiriro anoitika muRX datapath.
· [(N*2+2):N+3] = Inoratidza PCS kukanganisa kune chaiyo nzira.
· [N+2] = Inoratidza kukanganisa kwekugadzirisa. Gadzirisazve kurongeka kwenzira kana chidimbu ichi chichisimbiswa.
· [N+1]= Inoratidza data inotumirwa kune mushandisi logic kana mushandisi logic isati yagadzirira.
· [N] = Inoratidza kurasikirwa kwekugadzirisa.
· [(N-1):0] = Inoratidza data rine CRC kukanganisa.

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6.4. Transceiver Reconfiguration Signals

Tafura 23.

PCS Reconfiguration Signals
Mutafura iyi, N inomiririra huwandu hwenzira dzakaiswa muIP parameter mupepeti.

Zita

Upamhi

Direction Clock Domain

Tsanangudzo

reconfig_sl_read

Input reconfig_sl_ PCS reconfiguration kuverenga command

clk

zviratidzo.

reconfig_sl_write

Input reconfig_sl_ PCS reconfiguration nyora

clk

raira zviratidzo.

reconfig_sl_address

14 bits + clogb2N

Input

reconfig_sl_ clk

Inotsanangura PCS reconfiguration Avalon memory-mapped interface kero munzira yakasarudzwa.
Mukoto wega wega une mabhiti gumi nemana uye mabhiti ekumusoro anoreva nzira yekumisa.
Example, ye4-lane NRZ/PAM4 dhizaini, ine reconfig_sl_address[13:0] inoreva kukosha kwekero:
· reconfig_sl_address[15:1 4] set to 00 = kero yelane 0.
· reconfig_sl_address[15:1 4] set to 01 = kero yelane 1.
· reconfig_sl_address[15:1 4] set to 10 = kero yelane 2.
· reconfig_sl_address[15:1 4] set to 11 = kero yelane 3.

reconfig_sl_readdata

Output reconfig_sl_ Inotsanangura PCS reconfiguration data

clk

kuverengwa neakagadzirira kutenderera mu a

nzira yakasarudzwa.

reconfig_sl_waitrequest

Output reconfig_sl_ Inomiririra PCS reconfiguration

clk

Avalon memory-mapped interface

chiratidzo chinomira munzira yakasarudzwa.

reconfig_sl_writedata

Input reconfig_sl_ Inotsanangura PCS reconfiguration data

clk

kuti dzinyorwe pachinyorwa chekunyora mu a

nzira yakasarudzwa.

reconfig_sl_readdata_vali

Output

reconfig_sl_ Inotsanangura PCS reconfiguration

clk

data yakagamuchirwa inoshanda mune yakasarudzwa

lane.

Tafura 24.

F-Tile Yakaoma IP Reconfiguration Zviratidzo
Mutafura iyi, N inomiririra huwandu hwenzira dzakaiswa muIP parameter mupepeti.

Zita

Upamhi

Direction Clock Domain

Tsanangudzo

reconfig_read

Input reconfig_clk PMA reconfiguration kuverenga

raira zviratidzo.

reconfig_write

Input reconfig_clk PMA reconfiguration nyora

raira zviratidzo.

reconfig_address

18 bits + clog2bN

Input

reconfig_clk

Inotsanangura PMA Avalon memorymapped interface kero munzira yakasarudzwa.
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Zita
reconfig_readdata reconfig_waitrequest reconfig_writedata reconfig_readdatavalid

Upamhi
32 1 32 1

Direction Clock Domain

Tsanangudzo

Mune ese ari maviri PAM4 ad NRZ modhi, nzira yega yega ine gumi nemasere mabhiti uye akasara ekumusoro mabheti anoreva nzira yekumisa.
Example, kune 4-nzira dhizaini:
· reconfig_address[19:18] set to 00 = kero yelane 0.
· reconfig_address[19:18] set to 01 = kero yelane 1.
· reconfig_address[19:18] set to 10 = kero yelane 2.
· reconfig_address[19:18] set to 11 = kero yelane 3.

Output

reconfig_clk Inotsanangura PMA data kuti iverengerwe neyakagadzirira kutenderera munzira yakasarudzwa.

Output

reconfig_clk Inomiririra PMA Avalon memorymapped interface inomira chiratidzo mune yakasarudzwa nzira.

Input

reconfig_clk Inotsanangura PMA data kuti inyorwe pane yekunyora kutenderera munzira yakasarudzwa.

Output

reconfig_clk Inotsanangura PMA reconfiguration yakagamuchirwa data inoshanda munzira yakasarudzwa.

6.5. PMA Signals

Tafura 25.

PMA Signals
Mutafura iyi, N inomiririra huwandu hwenzira dzakaiswa muIP parameter mupepeti.

Zita

Upamhi

Direction Clock Domain

Tsanangudzo

phy_tx_lanes_stable

N*2 (PAM4 modhi)
N (NRZ mode)

Output

Asynchronous Kana yakasimbiswa, inoratidza TX datapath yakagadzirira kutumira data.

tx_pll_locked

N*2 (PAM4 modhi)
N (NRZ mode)

Output

Asynchronous Kana yakasimbiswa, inoratidza kuti TX PLL yawana chimiro chekuvhara.

phy_ehip_ready

N*2 (PAM4 modhi)
N (NRZ mode)

Output

Asynchronous

Kana yasimbiswa, inoratidza kuti tsika PCS yapedza kutanga kwemukati uye yagadzirira kutapurirana.
Chiratidzo ichi chinosimbisa mushure mekunge tx_pcs_fec_phy_reset_n uye tx_pcs_fec_phy_reset_nare yabviswa.

tx_serial_data

Kuburitsa TX seri wachi TX siriiri pini.

rx_serial_data

Input RX serial wachi RX serial pini.

phy_rx_block_lock

N*2 (PAM4 modhi)
N (NRZ mode)

Output

Asynchronous Kana yakasimbiswa, inoratidza kuti iyo 66b block alignment yapera kune nzira.

rx_cdr_lock

N*2 (PAM4 modhi)

Output

Asynchronous

Kana yasimbiswa, inoratidza kuti wachi dzakadzoserwa dzakavharwa kune data.
akaenderera…

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Zita phy_rx_pcs_ready phy_rx_hi_ber

Upamhi

Direction Clock Domain

Tsanangudzo

N (NRZ mode)

N*2 (PAM4 modhi)
N (NRZ mode)

Output

Asynchronous

Kana yakasimbiswa, inoratidza kuti nzira dzeRX dzeEthernet chiteshi dzakanyatsoenderana uye dzakagadzirira kugamuchira data.

N*2 (PAM4 modhi)
N (NRZ mode)

Output

Asynchronous

Kana yasimbiswa, inoratidza kuti RX PCS yeEthernet chiteshi chiri muHI BER state.

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7. Kugadzira neF-Tile Serial Lite IV Intel FPGA IP

7.1. Reset Guidelines
Tevedza aya nhungamiro yekumisikidza yako system-level reset.
· Sunga tx_pcs_fec_phy_reset_n uye rx_pcs_fec_phy_reset_n masiginecha pamwe chete padanho rehurongwa kuitira kuseta zvakare TX neRX PCS panguva imwe chete.
· Assert tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, tx_core_rst_n, rx_core_rst_n, uye reconfig_reset zviratidzo panguva imwe chete. Tarisa kune Reset uye Link Initialization kuti uwane rumwe ruzivo nezve IP reset uye yekutanga kutevedzana.
· Bata tx_pcs_fec_phy_reset_n, uye rx_pcs_fec_phy_reset_n zviratidzo zvakaderera, uye reconfig_reset chiratidzo chakakwirira uye kumirira tx_reset_ack uye rx_reset_ack kuti igadzirise zvakare F-tile yakaoma IP uye mabhuroki ekugadzirisa.
· Kuti uwane nekukurumidza kubatana-kumusoro pakati peFPGA zvishandiso, gadzirisa zvakare yakabatana F-Tile Serial Lite IV Intel FPGA IPs panguva imwe chete. Tarisa kune F-Tile seri Lite IV Intel FPGA IP Dhizaini Example Mushandisi Gaidhi yeruzivo rwekutarisa iyo IP TX uye RX link uchishandisa iyo toolkit.
Related Information
· Gadzirisa uye Batanidza Kutanga pane peji 37
F-Tile seri Lite IV Intel FPGA IP Dhizaini Example User Guide

7.2. Zvikanganiso Pakubata Mirayiridzo

Iri tafura rinotevera rinoratidza kukanganisa kwekubata nhungamiro yemamiriro ekukanganisa anogona kuitika neF-Tile Serial Lite IV Intel FPGA IP dhizaini.

Tafura 26. Kukanganisa Mamiriro uye Mabatiro Mazano

Error Condition
Imwe kana kupfuura nzira haigone kumisa kutaurirana mushure menguva yakatarwa.

Guidelines
Shandisa nguva-yekunze sisitimu yekumisazve chinongedzo padanho rekushandisa.

Mukoto unorasikirwa nekutaurirana mushure mekunge kutaurirana kwagadzirwa.
Mukoto unorasikirwa nekutaurirana panguva yedeskew process.

Izvi zvinogona kuitika mushure kana panguva yekufambisa data. Ita yekuona kurasikirwa kwekubatanidza padanho rekushandisa uye gadzirisazve chinongedzo.
Shandisa link reinitialization maitiro kune yakanganisa nzira. Iwe unofanirwa kuve nechokwadi kuti bhodhi routing haipfuure 320 UI.

Kurongeka kwenzira yekurasika mushure mekunge nzira dzese dzagadziriswa.

Izvi zvinogona kuitika mushure kana panguva yekuchinjisa data. Gadzirisa kurongeka kwenzira yekurasika padanho rekunyorera kuti utangezve nzira yekumisikidza nzira.

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8. F-Tile Serial Lite IV Intel FPGA IP User Guide Archives

IP shanduro dzakafanana neIntel Quartus Prime Design Suite software shanduro kusvika v19.1. Kubva kuIntel Quartus Prime Design Suite software vhezheni 19.2 kana gare gare, IP cores ine itsva IP shanduro chirongwa.

Kana IP core vhezheni isina kunyorwa, gwara remushandisi rekare IP core version rinoshanda.

Intel Quartus Prime Version
21.3

IP Core Version 3.0.0

User Guide F-Tile Serial Lite IV Intel® FPGA IP User Guide

ISO 9001:2015 Yakanyoreswa

683074 | 2022.04.28 Tumira Mhinduro

9. Document Revision History yeF-Tile Serial Lite IV Intel FPGA IP User Guide

Rondedzero Shanduro 2022.04.28
2021.11.16 2021.10.22 2021.08.18

Intel Quartus Prime Version
22.1
21.3 21.3 21.2

IP Shanduro 5.0.0
3.0.0 3.0.0 2.0.0

Kuchinja
· Tafura Yakagadziridzwa: F-Tile Seri Lite IV Intel FPGA IP Zvimiro - Yakagadziridzwa Tsananguro Yekuchinjisa Dhata nekuwedzera FHT transceiver rate rutsigiro: 58G NRZ, 58G PAM4, uye 116G PAM4
· Yakagadziridzwa Tafura: F-Tile Serial Lite IV Intel FPGA IP Parameter Tsananguro - Yakawedzera nyowani parameter · System PLL referensi wachi frequency · Gonesa debug endpoint - Yakagadziridza Mavhesi ePMA data reti - Yakagadziridzwa paramita zita kuti ienderane neGUI.
· Yakagadziridzwa tsananguro yekuchinjisa data muTafura: F-Tile Serial Lite IV Intel FPGA IP Zvimiro.
· Yakatumidzwa zita retafura IP kune F-Tile seri Lite IV Intel FPGA IP Parameter Tsananguro muchikamu cheParameters kuti chijekese.
· Yakagadziridzwa Tafura: IP paramita: - Yakawedzera paramende nyowani-RSFEC inogoneswa pane imwe Serial Lite IV Simplex IP yakaiswa pane imwechete FGT chiteshi. - Yakagadziridza yakasarudzika tsika dzeTransceiver referensi wachi frequency.
Kusunungurwa kwekutanga.

ISO 9001:2015 Yakanyoreswa

Zvinyorwa / Zvishandiso

	Intel F Tile Serial Lite IV Intel FPGA IP [pdf] Bhuku reMushandisi F Tile Serial Lite IV Intel FPGA IP, F Tile Serial Lite IV, Intel FPGA IP
	Intel F-Tile seri Lite IV Intel FPGA IP [pdf] Bhuku reMushandisi F-Tile Serial Lite IV Intel FPGA IP, Serial Lite IV Intel FPGA IP, Lite IV Intel FPGA IP, IV Intel FPGA IP, FPGA IP, IP

References

User Manual

F Tile Serial Lite IV Intel FPGA IP

Zvinyorwa / Zvishandiso

References

Siya mhinduro

Kanzura mhinduro