VHDLwhiz VHDL Resitala UART Su'ega Interface Generator Tusi Taiala
A'oa'o pe fa'apefea ona fa'aoga le VHDL Registers UART Test Interface Generator, o se meafaigaluega mamana a le VHDLwhiz, e fa'atupu ai fa'aoga VHDL fa'apitoa ma fa'amaumauga Python mo le faitau ma le tusiaina o fa'amaumauga o le resitala FPGA e fa'aaoga ai le UART. Su'esu'e le fa'atulagaina o fa'amaumauga ma mea e mana'omia e fa'aoga lelei ai lenei oloa. Atoatoa mo tagata atiaʻe o loʻo sailia ni fofo lelei o suʻega FPGA.