UG0644 DDR AXI Arbiter

Fa'amatalaga o oloa

O le DDR AXI Arbiter o se vaega meafaigaluega e maua ai se
64-bit AXI matai fa'aoga i le DDR-SDRAM i luga o masini masini.
E masani ona faʻaaogaina i ata vitio mo le faʻapipiʻiina ma
fa'agaioiga o fa'amatalaga pika vitio. O lo'o tu'uina mai e le tusi fa'aoga oloa
faʻamatalaga auiliili ma faʻatonuga i le faʻatinoina o meafaigaluega,
fa'ata'ita'iga, ma le fa'aogaina o punaoa.

Fa'atinoga o Meafaigaluega

O le DDR AXI Arbiter ua mamanuina e faʻafesoʻotaʻi ma le DDR-SDRAM
pule i luga o masini. E maua ai le 64-bit AXI matai matai
lea e mafai ai ona fa'agaioiina vave fa'amatalaga pika vitio. Le tagata fa'aoga oloa
tusi lesona e maua ai se faʻamatalaga auiliili o le mamanu o le DDR AXI
Arbiter ma lona fa'atinoina o meafaigaluega.

Fa'ata'oto

O lo'o tu'uina atu i le tusi lesona fa'aoga oloa fa'atonuga i le fa'atusaina o le
DDR AXI Arbiter faʻaaogaina MSS SmartDesign ma Testbench meafaigaluega. O nei
meafaigaluega e mafai ai e le tagata faʻaoga ona faʻamaonia le saʻo o le mamanu ma
fa'amautinoa le fa'agaioiga lelei o le vaega meafaigaluega.

Fa'aaogaina o Punaoa

O le DDR AXI Arbiter e faʻaogaina punaoa faʻapitoa e pei ole faʻatatau
sela, poloka manatua, ma punaoa auala. Le tagata fa'aoga oloa
tusi lesona o loʻo tuʻuina atu ai se faʻamatalaga auiliili o le faʻaaogaina o punaoa lea
o lo'o fa'amatala mai ai mea e mana'omia e le DDR AXI Arbiter. Lenei
faʻamatalaga e mafai ona faʻaogaina e faʻamautinoa ai e mafai e le vaega meafaigaluega
ia fa'atinoina i totonu o puna'oa o lo'o avanoa.

Fa'atonuga o le Fa'aaogaina o Mea

O fa'atonuga o lo'o i lalo e maua ai le ta'iala ile fa'aogaina o le
DDR AXI Arbiter:

Laasaga 1: Fa'atinoga o Meafaigaluega

Fa'atino le DDR AXI Arbiter meafaigaluega meafaigaluega e fa'aoga
faʻatasi ai ma le DDR-SDRAM i luga o masini masini. Mulimuli i le mamanu
fa'amatalaga o lo'o tu'uina atu i totonu o le tusi fa'aoga oloa ina ia mautinoa lelei
fa'atinoina o le vaega o meafaigaluega.

Laasaga 2: Fa'ata'ita'iga

Fa'ata'ita'i le mamanu a le DDR AXI Arbiter e fa'aaoga ai MSS SmartDesign ma
Mea faigaluega Testbench. Mulimuli i faatonuga o loʻo tuʻuina atu i totonu o le oloa
tusi fa'aoga e fa'amaonia ai le sa'o o le mamanu ma fa'amautinoa
galue lelei o le vaega meafaigaluega.

Laasaga 3: Fa'aogaina o Punaoa

Review le lipoti o le fa'aogaina o puna'oa o lo'o tu'uina atu i totonu o le oloa
fa'aoga tusi lesona e fuafua ai punaoa mana'omia o le DDR AXI
Fa'amasino. Ia mautinoa e mafai ona faʻatinoina le vaega o meafaigaluega
i totonu o punaoa o lo'o avanoa.

I le mulimuli i nei faʻatonuga, e mafai ona e faʻaogaina lelei le DDR
AXI Arbiter meafaigaluega meafaigaluega mo ata vitio fa'amaumauga fa'amaumauga ma
fa'agaioiga i ata vitio.

UG0644 Fa'aoga Taiala
DDR AXI Arbiter
Fepuari 2018

DDR AXI Arbiter
Mataupu
1 Talafaasolopito Toe Iloilo ……………………………………………………………………………………………………………………… 1
1.1 Toe Iloiloga 5.0 ……………………………………………………………………………………………………………. 1 1.2 Toe Iloiloga 4.0 ……………………………………………………………………………………………………………. 1 1.3 Toe Iloiloga 3.0 ……………………………………………………………………………………………………………. 1 1.4 Toe Iloiloga 2.0 ……………………………………………………………………………………………………………. 1 1.5 Toe Iloiloga 1.0 ……………………………………………………………………………………………………………. 1
2 Folasaga …………………………………………………………………………………………………………….. 2 3 Meafaigaluega Fa'atinoga ……………………………………………………………………………………… 3
3.1 Fa'amatalaga o Fuafuaga …………………………………………………………………………………………………………… 3 3.2 Ulufale ma Galuega Fa'atino …………………………………………………………………………………………………………….. 5 3.3 Fa'asologa o Parata ……… ………………………………………………………………………………………. 13 3.4 Ata o Taimi ……………………………………………………………………………………………………………. 14 3.5 Su'e Su'ega …………………………………………………………………………………………………………….. 16
3.5.1 Fa'ata'ita'iga MSS SmartDesign ………………………………………………………………………………………………. 25 3.5.2 Fa'ata'ita'iga laulau su'esu'e …………………………………………………………………………………………………………. 30 3.6 Fa'aaogāina Punaoa …………………………………………………………………………………………………………… 31
UG0644 Fa'aoga Taiala Toe Iloiloga 5.0

DDR AXI Arbiter

1

Toe Iloilo Tala'aga

O le tala fa'asolopito o lo'o fa'amatalaina suiga na fa'atinoina i le pepa. O suiga o lo'o lisiina e ala i toe iloiloga, amata i le lomiga aupito lata mai.

1.1

Toe Iloiloga 5.0

I le toe iloiloga 5.0 o lenei pepa, le vaega o le Fa'aogaina o Punaoa ma le Lipoti o le Fa'aaogaina o Punaoa

sa faafou. Mo nisi faamatalaga, tagai i le Fa'aaogaina o Punaoa (tagai itulau 31).

1.2

Toe Iloiloga 4.0

O lo'o i lalo le aotelega o suiga i le toe iloiloga 4.0 o lenei pepa.

Fa'aopoopo le fa'asologa o le fa'ata'ita'iga i le laulau. Mo nisi fa'amatalaga, va'ai Parata Fa'atonu (silasila i le itulau 16). Mo nisi faamatalaga, tagai Testbench (tagai itulau 16). Fa'afou le Fa'aogaina o Punaoa mo DDR AXI Arbiter tau i le laulau. Mo nisi faamatalaga, tagai i le Fa'aaogaina o Punaoa (tagai itulau 31).

1.3

Toe Iloiloga 3.0

O lo'o i lalo le aotelega o suiga i le toe iloiloga 3.0 o lenei pepa.

Fa'aopoopoina fa'amatalaga 8-bit mo le tusiaina o le alalaupapa 1 ma le 2. Mo nisi fa'amatalaga, va'ai Fa'amatalaga Fa'ailoga (silasila i le itulau 3). Fa'afou vaega Testbench. Mo nisi faamatalaga, tagai Testbench (tagai itulau 16).

1.4

Toe Iloiloga 2.0

I le toe iloiloga 2.0 o lenei pepa, o fuainumera ma laulau i totonu na faʻafouina i le Testbench vaega.

Mo nisi faamatalaga, tagai Testbench (tagai itulau 16).

1.5

Toe Iloiloga 1.0

Toefuataiga 1.0 o le lomiga muamua lea o lenei pepa

UG0644 Fa'aoga Taiala Toe Iloiloga 5.0

1

DDR AXI Arbiter

2

Folasaga

O manatuaga o se vaega taua o soʻo se ata masani ma ata faʻataʻitaʻiga. O lo'o fa'aaogaina mo le fa'asaoina o fa'amatalaga pika vitio. Tasi fa'aliga masani fa'atasiample fa'aaliga fa'avaa pa'u lea e fa'amaufa'ailogaina ai fa'amatalaga uma pika vitio mo se fa'avaa i le manatua.

Lua fa'amaumauga fa'amaumauga (DDR)-synchronous DRAM (SDRAM) o se tasi lea o manatuaga masani i fa'aoga vitio mo le fa'apolopolo. E faʻaaogaina le SDRAM ona o lona saoasaoa lea e manaʻomia mo le faʻavaveina o gaioiga i polokalama vitio.

O le ata lea o loʻo faʻaalia mai ai le exampLe o se ata faʻatulagaina o le DDR-SDRAM manatua e fesoʻotaʻi ma le faʻaoga vitio.

Ata 1 · DDR-SDRAM Memory Interfacing

I le Microsemi SmartFusion®2 System-on-Chip (SoC), e lua i luga o le chip DDR controllers ma le 64-bit advanced extensible interface (AXI) ma le 32-bit advanced high-performance bus (AHB) fesoʻotaʻiga pologa agai i le fanua e mafai ona faʻaogaina. fa'ailoga faitotoa (FPGA) ie. E manaʻomia se matai matai AXI poʻo AHB e faitau ma tusi ai le DDR-SDRAM manatua e faʻafesoʻotaʻi i luga ole masini DDR controllers.

UG0644 Fa'aoga Taiala Toe Iloiloga 5.0

2

DDR AXI Arbiter

3

Fa'atinoga o Meafaigaluega

3.1

Mamanu Faamatalaga

O le DDR AXI Arbiter o loʻo tuʻuina atu se 64-bit AXI matai faʻaoga i le DDR-SDRAM i luga o le masini masini

SmartFusion2 masini. O le DDR AXI Arbiter e fa ala faitau ma lua laina tusitusi agai i le

manatu fa'aoga. O le poloka e filifili i le va o alalaupapa faitau e fa e maua ai le avanoa i le AXI faitau

alavai i se faiga lapotopoto. Afai lava e maualuga le talosaga faitau a le matai 1, o le AXI

faitau alalaupapa ua fa'asoa i ai. Faitau le auala 1 o loʻo faʻamautu faʻamatalaga faʻamatalaga o le 24-bit. Faitau ala 2, 3,

ma le 4 e mafai ona faʻatulagaina e pei o le 8-bit, 24-bit, poʻo le 32-bit le lautele o faʻamaumauga. O lenei ua filifilia e le lalolagi

fa'asologa fa'atulagaina.

O le poloka foi e filifili i le va o auala tusitusi e lua e maua ai le avanoa i le AXI tusitusi ala i se faiga lapotopoto. E tutusa uma le fa'amuamua o auala tusitusi. Tusi le ala 1 ma le 2 e mafai ona fa'atulagaina e pei o le 8-bit, 24-bit, po'o le 32-bit le lautele o fa'amatalaga.

UG0644 Fa'aoga Taiala Toe Iloiloga 5.0

3

DDR AXI Arbiter
O le ata o loʻo i lalo o loʻo faʻaalia ai le pito i luga o le pito i luga o le ata o le DDR AXI Arbiter. Ata 2 · Fa'ata'ita'iga Poloka Tulaga Maualuga o le DDR AXI Arbiter Block

UG0644 Fa'aoga Taiala Toe Iloiloga 5.0

4

DDR AXI Arbiter
O le ata o loʻo i lalo o loʻo faʻaalia ai le faʻataʻitaʻiga o poloka pito i luga o se faiga faʻatasi ma le poloka DDR AXI Arbiter ua faʻapipiʻiina i totonu o le masini SmartFusion2. Ata 3 · Fa'asologa o Polokalama Fa'atonu a le DDR AXI Arbiter ile SmartFusion2 Device

3.2

Ulufale ma Galuega Fa'atino
O le laulau o lo'o i lalo o lo'o lisiina ai ports o lo'o tu'uina atu ma fa'aulufale a le DDR AXI Arbiter.

Laulau 1 · Taulaga Fa'aulu ma Fa'aulufale a le DDR AXI Arbiter

Igoa Fa'ailoga RESET_N_I

Fa'asinomaga Ulufale

Lautele

SYS_CLOCK_I BUFF_READ_CLOCK_I

Ulufale Ulufale

rd_req_1_i rd_ack_o

Galuega faatino sao

rd_faia_1_o amata_faitau_addr_1_i

Galuega faatino sao

bytes_to_read_1_i

Ulufale

video_rdata_1_o

Tuuina atu

[(g_AXI_AWIDTH-1):0] [(g_RD_CHANNEL1_AXI_BUFF_ AWIDTH + 3) – 1 : 0] [(g_RD_CHANNEL1_VIDEO_DATA_WIDTH1):0]

Fa'amatalaga
Fa'ailoilo toe setiina maualalo asynchronous i le mamanu
Uati System
Tusi le uati faitau fa'alava i totonu ole alalaupapa, e tatau ona fa'aluaina ole SYS_CLOCK_I fa'atele
Faitau le talosaga mai le Matai 1
Fa'ailoa a le Arbiter e faitau le talosaga mai le Matai 1
Faitau le mae'a i le Matai 1
tuatusi DDR mai le mea e tatau ona amata ai le faitau mo le faitau laina 1
Bytes e tatau ona faitau mai le faitau ala 1
Fa'amatalaga fa'amatalaga vitio mai le ala faitau 1

UG0644 Fa'aoga Taiala Toe Iloiloga 5.0

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DDR AXI Arbiter

Igoa Fa'ailoga rdata_valid_1_o rd_req_2_i rd_ack_2_o
rd_faia_2_o amata_faitau_addr_2_i
bytes_to_read_2_i
video_rdata_2_o
rdata_valid_2_o rd_req_3_i rd_ack_3_o
rd_faia_3_o amata_faitau_addr_3_i
bytes_to_read_3_i
video_rdata_3_o
rdata_valid_3_o rd_req_4_i rd_ack_4_o
rd_faia_4_o amata_faitau_addr_4_i
bytes_to_read_4_i
video_rdata_4_o
rdata_valid_4_o wr_req_1_i wr_ack_1_o
wr_done_1_o start_write_addr_1_i
bytes_to_write_1_i
video_wdata_1_i
wdata_valid_1_i wr_req_2_i

Fa'atonuga Fa'aulufale Fa'aulu
Galuega faatino sao
Ulufale
Tuuina atu
Ulufale Ulufale Ulufale
Galuega faatino sao
Ulufale
Tuuina atu
Ulufale Ulufale Ulufale
Galuega faatino sao
Ulufale
Tuuina atu
Ulufale Ulufale Ulufale
Galuega faatino sao
Ulufale
Ulufale
Ulufale Ulufale

Lautele
[(g_AXI_AWIDTH-1):0] [(g_RD_CHANNEL2_AXI_BUFF_AWIDTH + 3) – 1 : 0] [(g_RD_CHANNEL2_VIDEO_DATA_WIDTH1):0] [(g_AXI_AWIDTH-1):0] [(g_RD_AWIDTH_CHANNEL3_VIDEO_DATA_WIDTH3):1] [(g_RD_AWIDTH-0):3] [(g_RD_AWIDTH_CHANN. g_RD_CHANNEL1_VIDEO_DATA_WIDTH0 ):1] [(g_AXI_AWIDTH-0):4] [(g_RD_CHANNEL3_AXI_BUFF_AWIDTH + 1) – 0 : 4] [(g_RD_CHANNEL1_VIDEO_DATA_WIDTH0):1] [(g_AXI_AWIDTH-0):1] [(g_BUFF_WRIDTH-3):1] [(g_BUFF_WRIDTH-0):1] [(g_BUFF_WRID) 1 ] [(g_WR_CHANNEL0_VIDEO_DATA_WIDTHXNUMX):XNUMX]

Fa'amatalaga Faitau fa'amatalaga fa'amaonia mai le faitau auala 1 Faitau le talosaga mai le Matai 2 Arbiter fa'ailoa e faitau le talosaga mai le Matai 2 Faitau fa'amae'aina ile Master 2 DDR tuatusi mai le mea e tatau ona amata ai le faitau mo le faitau laina 2 Paita e faitau mai le faitau laina 2 Fa'amatalaga vitio galuega faatino mai le ala faitau 2 Faitau fa'amatalaga fa'amaonia mai le ala faitau 2 Faitau le talosaga mai le Matai 3 Arbiter fa'ailoa e faitau le talosaga mai le Matai 3 Faitau fa'amae'aina ile Master 3 DDR tuatusi mai le mea e tatau ona amata ai le faitau mo le faitau ala 3 Bytes e faitau mai le faitau auala 3 Fa'amatalaga fa'amatalaga vitio mai le ala faitau 3 Faitau fa'amatalaga fa'amaonia mai le faitau alalaupapa 3 Faitau le talosaga mai le Matai 4 Arbiter fa'ailoa e faitau le talosaga mai le Matai 4 Faitau fa'amae'aina ile Master 4 DDR tuatusi mai le mea e tatau ona amata ai le faitau mo le faitau laina 4 Bytes e tatau ona maua. faitau mai le ala faitau 4 Fa'amatalaga fa'amatalaga vitio mai le ala faitau 4 Faitau fa'amatalaga fa'amaonia mai le ala faitau 4 Tusi le talosaga mai le Matai 1 Arbiter fa'ailoa e tusi le talosaga mai le Matai 1 Tusi le mae'a i le Master 1 DDR tuatusi e tatau ona tusi mai le ala tusitusi 1 Paita e tusia mai le ala tusitusi 1 Fa'amatalaga Vitio Ulufale e tusi ai le alalaupapa 1
Tusi fa'amaumauga fa'amaonia e tusi ai le ala 1 Tusi le talosaga mai le Matai 1

UG0644 Fa'aoga Taiala Toe Iloiloga 5.0

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DDR AXI Arbiter

Igoa Faailoga wr_ack_2_o

Fa'atonuga

wr_done_2_o start_write_addr_2_i

Galuega faatino sao

bytes_to_write_2_i

Ulufale

video_wdata_2_i

Ulufale

wdata_valid_2_i AXI I/F faailoilo Faitau Tuatusi Alalaupapa m_arid_o

Galuega faatino sao

m_araddr_o

Tuuina atu

m_arlen_o

Tuuina atu

m_arsize_o m_arburst_o

Fa'atosinaga Fa'atino

m_arlock_o

Tuuina atu

m_arcache_o

Tuuina atu

m_arprot_o

Tuuina atu

Lautele
[(g_AXI_AWIDTH-1):0] [(g_WR_CHANNEL2_AXI_BUFF_AWIDTH + 3) – 1 : 0] [(g_WR_CHANNEL2_VIDEO_DATA_WIDTH1):0]

Fa'amatalaga Arbiter fa'ailoa e tusi ai le talosaga mai le Matai 2 Tusi le fa'amae'aina ile Master 2 DDR tuatusi lea e tatau ona tupu mai ai le tusitusi 2 Paita e tusia mai le ala tusitusi 2 Vitio fa'amatalaga Fa'aulu e tusi ai le alalaupapa 2
Tusi fa'amaumauga fa'amaonia e tusi ai le ala 2

[3:0] [(g_AXI_AWIDTH-1):0] [3:0] [2:0] [1:0] [1:0] [3:0] [2:0]

Faitau tuatusi ID. Fa'ailoaga tag mo le vaega faitau tuatusi o faailoilo.
Faitau le tuatusi. Tuuina atu le tuatusi muamua o se fefaʻatauaʻiga faʻasalalau faitau. E na'o le tuatusi amata o le fa'alavelave o lo'o tu'uina mai.
Pa'u umi. Tuuina atu le numera saʻo o fesiitaiga i se pa. O lenei fa'amatalaga e fuafua ai le aofa'i o fa'amatalaga e feso'ota'i ma le tuatusi
Tele pa'u. Tele o fesiitaiga taitasi i le pa
Ituaiga pa. Fa'atasi ma le tele o fa'amatalaga, fa'amatalaga pe fa'apefea ona fa'atatau le tuatusi mo fesiitaiga ta'itasi i totonu o le pa.
Fa'amau i le 2'b01 à Fa'aopoopo le tuatusi malepe
Ituaiga loka. Tuuina atu faʻamatalaga faaopoopo e uiga i uiga atomika o le fesiitaiga.
Fa'amau i le 2'b00 à Normal Access
Ituaiga Cache. Tuuina atu faʻamatalaga faʻaopoopo e uiga i uiga faʻaogaina o le fesiitaiga.
Fa'amau i le 4'b0000 à E le mafai ona fa'aogaina ma e le mafai ona pa'u
Ituaiga puipuiga. E tu'uina atu fa'amatalaga vaega o puipuiga mo le fefa'atauaiga.
Fa'amau i le 3'b000 à masani, fa'amautu fa'amaumauga

UG0644 Fa'aoga Taiala Toe Iloiloga 5.0

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DDR AXI Arbiter
Igoa Faailoga m_arvalid_o

Fa'atonuga

Lautele

m_ua_i

Ulufale

Faitau Fa'amatalaga Fa'amatalaga

m_rid_i

Ulufale

[3:0]

m_rdata_i m_rresp_i
m_rlast_i m_rvalid_i

Ulufale Ulufale

[(g_AXI_DWIDTH-1):0] [1:0]

Ulufale Ulufale

m_sauni_o

Tuuina atu

Tusi le Alalautusi Fa'amatalaga

m_wid_o

Tuuina atu

m_awaddr_o

Tuuina atu

[3:0] [(g_AXI_AWIDTH-1):0]

UG0644 Fa'aoga Taiala Toe Iloiloga 5.0

Fa'amatalaga Faitau tuatusi aoga.
A HIGH, o le tuatusi faitau ma faʻamatalaga faʻatonutonu e aoga ma tumau maualuga seia oʻo ina maualuga le faailoilo, m_arready.
`1′ = tuatusi ma fa'amatalaga fa'atonutonu e aoga
`0′ = tuatusi ma fa'amatalaga fa'atonutonu e le aoga. Faitau le tuatusi ua saunia. Ua sauni le pologa e talia se tuatusi ma fa'ailo fa'atonutonu fa'atasi:
1 = pologa ua sauni
0 = pologa e le'i sauni.
Faitau ID tag. ID tag o le vaega faitau fa'amaumauga o fa'ailoga. O le tau m_rid e gaosia e le Slave ma e tatau ona fetaui ma le tau m_arid o le fefaʻatauaʻiga faitau lea e tali atu ai. Faitau fa'amaumauga. Faitau le tali.
Le tulaga o le fesiitaiga faitau. Tali fa'atagaina o OKAY, EXOKAY, SLVERR, ma DECERR. Faitau mulimuli.
Fa'aliliuga mulimuli i se faitauga faitau. Faitau aoga. O lo'o maua fa'amaumauga mana'omia e faitau ma e mafai ona mae'a le fa'aliliuga faitau:
1 = faitau faʻamatalaga avanoa
0 = faitau fa'amatalaga e le maua. Faitau sauni. E mafai e le Matai ona talia faʻamatalaga faitau ma faʻamatalaga tali:
1= matai sauni
0 = matai e le'i sauni.
Tusi ID tuatusi. Fa'ailoaga tag mo le vaega tusi tuatusi o faailoilo. Tusi le tuatusi. Tuuina atu le tuatusi o le fesiitaiga muamua i se fefaʻatauaʻiga tusitusi pa. O fa'ailo fa'atonutonu feso'ota'i e fa'aoga e iloa ai tuatusi o fa'aliliuga o totoe i le pa.
8

DDR AXI Arbiter
Igoa Faailoga m_awlen_o

Fa'atonuga

Lautele [3:0]

m_awsize_o

Tuuina atu

[2:0]

m_awburst_o

Tuuina atu

[1:0]

m_awlock_o

Tuuina atu

[1:0]

m_awcache_o

Tuuina atu

[3:0]

m_awprot_o

Tuuina atu

[2:0]

m_awvalid_o

Tuuina atu

Fa'amatalaga
Pa'u umi. Tuuina atu le numera saʻo o fesiitaiga i se pa. O lenei fa'amatalaga e fuafua ai le aofa'i o fa'amatalaga e feso'ota'i ma le tuatusi.
Tele pa'u. Tele o fesiitaiga taitasi i le pa. E fa'ailoa sa'o mai e ala pa'i ala e fa'afou.
Fa'amau i le 3'b011 i le 8 paita i le fa'aliliuina o fa'amatalaga po'o le fa'aliliuina o le 64-bit
Ituaiga pa. Fa'atasi ma le tele o fa'amatalaga, fa'amatalaga pe fa'apefea ona fa'atatau le tuatusi mo fesiitaiga ta'itasi i totonu o le pa.
Fa'amau i le 2'b01 à Fa'aopoopo le tuatusi malepe
Ituaiga loka. Tuuina atu faʻamatalaga faaopoopo e uiga i uiga atomika o le fesiitaiga.
Fa'amau i le 2'b00 à Normal Access
Ituaiga Cache. Fa'ailoa mai le fa'apolopolo, fa'apolopolo, tusi-i totonu, tusi-i tua, ma fa'asoa uiga o le fefa'atauaiga.
Fa'amau i le 4'b0000 à E le mafai ona fa'aogaina ma e le mafai ona pa'u
Ituaiga puipuiga. Fa'ailoa mai le tulaga masani, fa'apitoa, po'o le saogalemu o le puipuiga o le fefa'atauaiga ma pe o le fefa'ataua'iga o se fa'amatalaga fa'amatalaga po'o se fa'atonuga.
Fa'amau i le 3'b000 à masani, fa'amautu fa'amaumauga
Tusi le tuatusi aoga. Fa'ailoa mai o le tuatusi tusi aoga ma le pule
o lo'o maua fa'amatalaga:
1 = tuatusi ma fa'amatalaga fa'atonutonu avanoa
0 = tuatusi ma fa'amatalaga fa'atonutonu e le maua. O le tuatusi ma fa'amatalaga fa'atonutonu e tumau pea se'ia o'o i luga ole fa'ailoga ole tuatusi, m_awready, maualuga.

UG0644 Fa'aoga Taiala Toe Iloiloga 5.0

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DDR AXI Arbiter

Igoa Faailoga m_awready_i

Fa'asinomaga Ulufale

Lautele

Tusi Fa'amatalaga Fa'amatalaga

m_wid_o

Tuuina atu

[3:0]

m_wdata_o m_wstrb_o

Fa'atosinaga Fa'atino

[(g_AXI_DWIDTH-1):0] AXI_DWDITH parakalafa
[7:0]

m_wlast_o m_wvalid_o

Fa'atosinaga Fa'atino

m_wready_i

Ulufale

Tusi Fa'ailo Alaala Tali

m_bid_i

Ulufale

[3:0]

m_bresp_i m_bvalid_i

Ulufale

[1:0]

Ulufale

m_bready_o

Tuuina atu

Fa'amatalaga Tusi le tuatusi ua saunia. Fa'ailoa mai ua sauni le pologa e talia se tuatusi ma fa'ailo fa'atonutonu fa'atasi:
1 = pologa ua sauni
0 = pologa e le'i sauni.
Tusi ID tag. ID tag o le fa'aliliuina o fa'amatalaga tusitusia. Ole tau m_wid e tatau ona fetaui ma le tau m_wid o le fefa'atauaiga tusitusi. Tusi fa'amaumauga
Tusi strobes. O le fa'ailoga lea e fa'ailoa mai po'o fea ala paita e fa'afou ile manatua. E tasi le strobe tusitusi mo vaega ta'i valu o le pasi tusi fa'amaumauga Tusi mulimuli. Fa'aliliuga mulimuli i se fa'alavelave tusitusi. Tusi aoga. O lo'o avanoa fa'amaumauga tusitusia ma strobes:
1 = tusi faʻamaumauga ma strobes avanoa
0 = tusi fa'amaumauga ma strobes e le maua. Tusi saunia. E mafai e le pologa ona talia le fa'amaumauga tusitusi: 1 = pologa ua sauni
0 = pologa e le'i sauni.
ID Tali. Le faailoaina tag o le tali tusitusia. O le tau m_bid e tatau ona fetaui ma le tau m_awid o le fefaʻatauaiga tusitusi lea e tali atu ai le pologa. Tusi tali. Tulaga o le fefa'atauaiga tusitusi. O tali fa'atagaina o OKAY, EXOKAY, SLVERR, ma DECERR. Tusi tali sa'o. E avanoa le tali tusitusia sa'o:
1 = tusi tali avanoa
0 = tusi le tali e le maua. Sauni tali. E mafai e le Matai ona talia faʻamatalaga tali.
1 = matai sauni
0 = matai e le'i sauni.

O le ata o loʻo i lalo o loʻo faʻaalia ai le poloka poloka i totonu o le DDR AXI arbiter.

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O le ata o loʻo i lalo o loʻo faʻaalia ai le poloka poloka i totonu o le DDR AXI arbiter. Ata 4 · Ata Fa'alotoifale poloka o le DDR AXI Arbiter

O ala faitau ta'itasi e fa'aoso pe a maua se fa'ailo maualuga i totonu o le read_req_(x)_i input. Ona o lea

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O ala faitau ta'itasi e fa'aoso pe a maua se fa'ailo maualuga i totonu o le read_req_(x)_i input. Ona sampo le tuatusi AXI amata ma le paita e faitau ai mea e fa'aoga mai le matai fafo. E fa'ailoa e le alaleo le matai i fafo e ala i le tosoina o le read_ack_(x)_o. O le alalaupapa e fa'agasolo ai mea e fa'aogaina ma fa'atupuina ai fefa'ataua'iga mana'omia AXI e faitau ai fa'amaumauga mai le DDR-SDRAM. O faʻamaumauga e faitau i le 64-bit AXI faʻatulagaina o loʻo teuina i totonu o le pa puipui. A mae'a ona faitau fa'amatalaga mana'omia ma teu i totonu o le pa'u i totonu, e fa'agaoioia le un-packer module. O le un-packer module e tatalaina upu ta'i 64-bit i totonu o le umi o fa'amaumauga o fa'amatalaga e mana'omia mo lena auala patino mo ex.amppe afai e fa'atulagaina le alalaupapa e pei o le 32-bit le lautele o fa'amaumauga, o upu ta'itasi 64-bit e lafo i fafo o ni upu fa'amaumauga e lua 32-bit. Mo le alalaupapa 1 o se alalaupapa 24-bit, e tatala e le un-packer upu ta'i 64-bit i fa'amaumauga 24-bit. Ona o le 64 e le o se numera tele o le 24, o le un-packer mo le faitau alalaupapa 1 e tuʻufaʻatasia se vaega o upu 64-bit e tolu e maua ai le valu 24-bit upu faʻamaumauga. O lenei mea e tuʻuina ai se faʻalavelave i luga o le faitau ala 1 e tatau ona vaʻavaʻaia e le matai fafo o faʻamaumauga e talosagaina e le matai fafo e 8. Faitau laina 2, 3, ma le 4 e mafai ona faʻatulagaina e pei o le 8-bit, 24bit, ma le 32-bit le lautele o faʻamatalaga, o le fuafuaina e le g_RD_CHANNEL(X) _VIDEO_DATA_WIDTH ta'otoga fetuutuunai lalolagi. Afai o loʻo faʻatulagaina e pei o le 24-bit, o le faʻatapulaʻaina o loʻo taʻua i luga o le a faʻaoga foi ia i latou taʻitoʻatasi. Ae afai latou te faʻatulagaina e pei o le 8-bit poʻo le 32-bit, e leai se faʻalavelave e pei o le 64 o le tele o le 32 ma le 8. I nei tulaga, o upu 64-bit taʻitasi e tatalaina i totonu o le lua 32-bit upu faʻamaumauga poʻo le valu 8. - upu fa'amatalaga bit.
Faitau le Alalaupapa 1 tatala fa'amaumauga 64-bit upu faitau mai le DDR-SDRAM i le 24-bit fa'amatalaga fa'amatalaga i vaega o 48 64-bit upu, o so'o se taimi lava e maua ai le 48 64-bit upu i totonu o le pa puipui o le faitau laina 1, e amata ona tatala e le un-packer e tuʻuina atu faʻamatalaga 24-bit. Afai e itiiti ifo i le 48 64-bit upu o lo'o talosagaina fa'amaumauga e faitau, o le un-packer e faatoa mafai lava pe a uma ona faitau fa'amaumauga atoa mai le DDR-SDRAM. I isi laina faitau e tolu, o le un-packer e amata ona tuʻuina atu faʻamatalaga faitau pe a maeʻa ona faitau atoa le numera o paita mai le DDR-SDRAM.
A fa'atulagaina se ala faitau mo le 24-bit le lautele o le gaosiga, o le tuatusi amata faitau e tatau ona fa'aoga i le 24-bytes tuaoi. E mana'omia lenei mea e fa'amalieina ai le fa'atumauina e le un-packer e tatala se vaega o upu 64-bit e tolu e maua ai le valu 24-bit upu fa'atino.
O ala faitau uma e fa'atupuina le faitau ua faia i le matai i fafo pe a mae'a ona tu'uina atu i le matai fafo.
I le tulaga o ala tusitusi, e tatau i le matai i fafo ona tuʻuina atu faʻamatalaga manaʻomia i le auala faapitoa. O le ala tusitusi e ave faʻamatalaga faʻapipiʻi ma faʻapipiʻi i upu 64-bit ma teu i totonu o le teuina i totonu. A maeʻa ona teuina faʻamatalaga manaʻomia, e tatau i le matai fafo ona tuʻuina atu le talosaga tusitusi faʻatasi ai ma le tuatusi amata ma bytes e tusi ai. I luga o le sampI le tu'uina atu o nei fa'aoga, o le ala tusitusi e fa'ailoa ai le matai i fafo. A maeʻa lenei mea, o le auala e faʻatupuina ai le AXI tusitusi fefaʻatauaiga e tusi ai faʻamaumauga teuina i DDR-SDRAM. O auala tusitusi uma e fa'atupuina ai le tusitusi na faia i le matai fafo pe a uma ona tusia bytes talosaga i le DDR-SDRAM. A maeʻa ona tuʻuina atu se talosaga tusitusi i soʻo se auala tusitusi, e le tatau ona tusia ni faʻamatalaga fou i totonu o le ala tusitusi, seʻia oʻo i le faʻamaeʻaina o fefaʻatauaiga o loʻo i ai nei e faʻaalia i le faʻamaoniga a wr_done_(x)_o
Tusi ala 1 ma 2 e mafai ona configured e 8-bit, 24-bit, ma 32-bit le lautele o faamatalaga, lea e fuafuaina e g_WR_CHANNEL(X)_VIDEO_DATA_WIDTH global configuration parameter. Afai e fa'atulagaina e pei o le 24bit, o le paita e tusia e tatau ona tele i le valu a'o fa'apipi'i e le tagata fa'apipi'i totonu le valu 24-bit upu fa'amaumauga e fa'atupu ai le tolu 64-bit upu fa'amaumauga. Ae afai latou te faʻatulagaina e pei o le 8-bit poʻo le 32-bit, e leai se faʻalavelave faʻapea.
Mo se alalaupapa 32-bit, e tatau ona faitau le itiiti ifo i le lua upu 32-bit. Mo se alaleo 8-bit, e manaʻomia ona faitau le itiiti ifo o le 8-bit upu, aua e leai se padding e saunia e le arbiter module. I ala faitau ma tusitusi uma, o le loloto o puipui i totonu o le tele o le faʻaaliga lautele lautele. O le loloto o le paluga i totonu o loʻo fuafua e faʻapea:
g_RD_CHANNEL(X)_HORIZONTAL_RESOLUTION* g_RD_CHANNEL(X)_VIDEO_DATA_WIDTH * g_RD_CHANNEL(X)_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
O fea, X = Numera alalaupapa

O le lautele o le pa puipui i totonu e fuafua e le AXI faʻamaumauga pasi lautele o lona uiga, faʻasologa o mea

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O le lautele o le pa puipui i totonu e fuafuaina e le AXI faʻamaumauga pasi lautele o lona uiga, configuration parameter g_AXI_DWIDTH.
O le AXI faitau ma tusitusi fefaʻatauaiga e faia e tusa ai ma faʻamatalaga ARM AMBA AXI. Ole tele o fefaʻatauaiga mo faʻamatalaga taʻitasi e faʻamautu ile 64-bit. O le poloka e maua ai fefa'atauaiga a le AXI o le umi o le pa'u tumau o le 16 pa'i. E siaki foi e le poloka pe so'o se pa'u tasi e sopoia le tuaoi o le tuatusi AXI o le 4 KByte. Afai e sopoia e se pa se tasi le tuaoi 4 KByte, e vaevaeina le pa i le 2 pa i le tuaoi 4 KByte.

3.3

Fa'atutuga Parata
O le laulau o loʻo i lalo o loʻo lisiina ai faʻasologa faʻatulagaina o loʻo faʻaaogaina i le faʻatinoga o meafaigaluega a le DDR AXI Arbiter. O fa'asologa lautele ia ma e mafai ona fesuia'i fa'atatau i mana'oga o talosaga.

Fuafuaga 2 · Fa'atutuga Parata
Igoa g_AXI_AWIDTH g_AXI_DWIDTH g_RD_CHANNEL1_AXI_BUFF_AWIDTH
g_RD_CHANNEL2_AXI_BUFF_AWIDTH
g_RD_CHANNEL3_AXI_BUFF_AWIDTH
g_RD_CHANNEL4_AXI_BUFF_AWIDTH
g_WR_CHANNEL1_AXI_BUFF_AWIDTH
g_WR_CHANNEL2_AXI_BUFF_AWIDTH
g_RD_CHANNEL1_HORIZONTAL_RESOLUTION g_RD_CHANNEL2_HORIZONTAL_RESOLUTION g_RD_CHANNEL3_HORIZONTAL_RESOLUTION g_RD_CHANNEL4_HORIZONTAL_RESOLUTION g_WR_CHANNEL1_HORIZONTAL_RESOLUTION g_HORIZONTAL_RESOLUTION g_RD_CHANNEL2_HORIZONTAL_RESOLUTION g_WR_CHANNEL1_HORIZONTAL_RESOLUTION 2_VIDEO_FATA_WIDTH g_RD_CHANNEL3_VIDEO_DATA_WIDTH g_RD_CHANNEL4_VIDEO_DATA_WIDTH g_RD_CHANNEL1_VIDEO_DATA_WIDTH FFER_LINE_STORAGE

Fa'amatalaga
AXI tuatusi pasi lautele
AXI fa'amaumauga pasi lautele
Fa'asalalau le lautele o le pasi mo le fa'asalalauina o le Ala 1 i totonu, lea e teu ai fa'amaumauga a le AXI.
Fa'asalalau le lautele o le pasi mo le fa'asalalauina o le Ala 2 i totonu, lea e teu ai fa'amaumauga a le AXI.
Fa'asalalau le lautele o le pasi mo le fa'asalalauina o le Ala 3 i totonu, lea e teu ai fa'amaumauga a le AXI.
Fa'asalalau le lautele o le pasi mo le fa'asalalauina o le Ala 4 i totonu, lea e teu ai fa'amaumauga a le AXI.
Fa'asalalau le lautele o le pasi mo le tusi Channel 1 totonu pa puipui, lea e teu ai le AXI tusitusi faʻamaumauga.
Fa'asalalau le lautele o le pasi mo le tusi Channel 2 totonu pa puipui, lea e teu ai le AXI tusitusi faʻamaumauga.
Fa'aali vitiō fa'ai'uga fa'alava mo le faitau Ala 1
Fa'aali vitiō fa'ai'uga fa'alava mo le faitau Ala 2
Fa'aali vitiō fa'ai'uga fa'alava mo le faitau Ala 3
Fa'aali vitiō fa'ai'uga fa'alava mo le faitau Ala 4
Fa'aali vitiō fa'ai'uga fa'ata'atia mo le tusiaina o Alavai 1
Fa'aali vitiō fa'ai'uga fa'ata'atia mo le tusiaina o Alavai 2
Faitau le Alalauata 1 le lautele o le ata vitio
Faitau le Alalauata 2 le lautele o le ata vitio
Faitau le Alalauata 3 le lautele o le ata vitio
Faitau le Alalauata 4 le lautele o le ata vitio
Tusi le Auala 1 vitiō Fa'aaofia bit lautele.
Tusi le Auala 2 vitiō Fa'aaofia bit lautele.
Le loloto o le pa puipui i totonu mo le faitau Ala 1 i tulaga o le numera o faʻaaliga laina laina. O le loloto o le pa puipui o le g_RD_CHANNEL1_HORIZONTAL_RESOLUTION * g_RD_CHANNEL1_VIDEO_DATA_WIDTH * g_RD_CHANNEL1_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH

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3.4

Igoa g_RD_CHANNEL2_BUFFER_LINE_STORAGE g_RD_CHANNEL3_BUFFER_LINE_STORAGE g_RD_CHANNEL4_BUFFER_LINE_STORAGE g_WR_CHANNEL1_BUFFER_LINE_STORAGE g_WR_CHANNEL2_BUFFER_LINE_STORAGE

Fa'amatalaga
Le loloto o le pa puipui i totonu mo le faitau Ala 2 i tulaga o le numera o faʻaaliga laina laina. O le loloto o le pa puipui o le g_RD_CHANNEL2_HORIZONTAL_RESOLUTION * g_RD_CHANNEL2_VIDEO_DATA_WIDTH * g_RD_CHANNEL2_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Le loloto o le pa puipui i totonu mo le faitau Ala 3 i tulaga o le numera o faʻaaliga laina laina. O le loloto o le pa puipui o le g_RD_CHANNEL3_HORIZONTAL_RESOLUTION * g_RD_CHANNEL3_VIDEO_DATA_WIDTH * g_RD_CHANNEL3_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Le loloto o le pa puipui i totonu mo le faitau Ala 4 i tulaga o le numera o faʻaaliga laina laina. O le loloto o le pa puipui o le g_RD_CHANNEL4_HORIZONTAL_RESOLUTION * g_RD_CHANNEL4_VIDEO_DATA_WIDTH * g_RD_CHANNEL4_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Le loloto o le pa puipui i totonu mo le tusia o le Alalaupapa 1 i tulaga o le numera o laina fa'aaliga fa'alava. O le loloto o le pa puipui o le g_WR_CHANNEL1_HORIZONTAL_RESOLUTION * g_WR_CHANNEL1_VIDEO_DATA_WIDTH * g_WR_CHANNEL1_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Le loloto o le pa puipui i totonu mo le tusia o le Alalaupapa 2 i tulaga o le numera o laina fa'aaliga fa'alava. O le loloto o le pa puipui o le g_WR_CHANNEL2_HORIZONTAL_RESOLUTION * g_WR_CHANNEL2_VIDEO_DATA_WIDTH * g_WR_CHANNEL2_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH

Ata o Taimi
O le ata o loʻo i lalo o loʻo faʻaalia ai le fesoʻotaʻiga o tusi talosaga faitau ma tusitusi, tuatusi manatua amata, paita e faitau pe tusi ai mea mai le matai fafo, faitau pe tusi le faʻamaonia, ma faitau pe tusi faʻamaeʻaina galuega na tuʻuina atu e le arbiter.

Ata 5 · Fa'asologa o Taimi mo Fa'ailoga o lo'o Fa'aaogaina ile Tusitusi/Fa'atauga ile AXI Interface

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O le ata o loʻo i lalo o loʻo faʻaalia ai le fesoʻotaʻiga i le va o faʻamatalaga tusitusia mai le matai fafo faʻatasi ai ma le faʻaogaina o faʻamatalaga e aoga mo auala tusitusi e lua. Ata 6 · Fa'asologa o Taimi mo le Tusia i totonu o le Teuga
O le ata o loʻo i lalo o loʻo faʻaalia ai le fesoʻotaʻiga i le va o faʻamatalaga faitau tusi agai i le matai fafo faʻatasi ai ma faʻamatalaga faʻamatalaga aoga mo ala faitau uma 2, 3, ma 4. Ata 7 · Faʻasologa o Taimi mo Faʻamatalaga Mauaina e ala i le DDR AXI Arbiter mo Faitau Ala 2, 3 , ma 4
O le ata o loʻo i lalo o loʻo faʻaalia ai le fesoʻotaʻiga i le va o faʻamatalaga faitau faʻamatalaga mo le faitau Channel 1 pe a g_RD_CHANNEL 1_HORIZONTAL_RESOLUTION e sili atu i le 128 (i lenei tulaga = 256). Ata 8 · Fa'asologa o Taimi mo Fa'amaumauga na Maua e ala i le DDR AXI Arbiter Read Channel 1 (sili atu i le 128 bytes)

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O le ata o loʻo i lalo o loʻo faʻaalia ai le fesoʻotaʻiga i le va o faʻamatalaga faitau tusi mo le faitau Channel 1 pe a g_RD_CHANNEL 1_HORIZONTAL_RESOLUTION e itiiti ifo pe tutusa ma le 128 (i lenei tulaga = 64). Ata 9 · Fa'asologa o Taimi mo Fa'amatalaga Maua e ala i le DDR AXI Arbiter Read Channel 1 (itiiti ifo pe tutusa ile 128 bytes)

3.5

Su'ega Su'ega
O loʻo tuʻuina atu se suʻega suʻega e siaki ai le gaioiga o le DDR Arbiter core. O le laulau o loʻo i lalo o loʻo lisiina ai taʻaloga e mafai ona faʻatulagaina e tusa ai ma le talosaga.

Fuafuaga 3 · Su'ega Fa'atulagaina Parameter

Igoa IMAGE_1_FILE_NAME IMAGE_2_FILE_NAME g_DATA_WIDTH UMA AVAE

Fa'amatalaga Ulufale file igoa mo ata e tusia e ala i le tusi alaala 1 Ulufale file igoa mo le ata e tusia e ala i le tusitusi auala 2 Vitio fa'amatalaga lautele o le faitau po'o le tusitusi alavai Fa'atū sa'o o le ata e tusia ma faitau e le tusitusi ma faitau alavai Fa'aituau sa'o o le ata e tusia ma faitau e le tusi ma faitau. alavai

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O laasaga nei o loʻo faʻamatalaina ai le faʻaogaina o le testbench e faʻataʻitaʻi ai le autu e ala i le Libero SoC. 1. I le matala Design Flow, kiliki-matau Create SmartDesign ma kiliki Run e fatu ai se SmartDesign.
Ata 10 · Fausia SmartDesign

2. Ulufale le igoa o le mamanu fou e pei o le video_dma i le Fausia New SmartDesign dialog box ma kiliki OK. Ua faia se SmartDesign, ma o lo'o fa'aalia se tapoleni i le itu taumatau o le Design Flow pane.
Ata 11 · Fa'aigoaina SmartDesign

3. I le faamalama Catalog, faalautele Fofo-Vitio ma toso-ma-pa'ū SF2 DDR Memory Arbiter i le tapoleni SmartDesign.

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Ata 12 · DDR Memory Arbiter i Libero SoC Catalog

O le DDR Memory Arbiter Core o loʻo faʻaalia, e pei ona faʻaalia i le ata o loʻo i lalo. Fa'alua-kiliki le 'autu e fa'atulaga le arbiter pe a mana'omia.

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Ata 13 · DDR Memory Arbiter Core i SmartDesign Canvas

4. Filifili uma ports o le autu ma kiliki-saʻo ona kiliki lea Promote to Top Level, e pei ona faʻaalia i le

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4. Filifili uma ports o le autu ma kiliki-matau ona kiliki lea Promote to Top Level, e pei ona faʻaalia i le ata o loʻo i lalo. Ata 14 · Si'itia ile Tulaga Maualuga Filifiliga

Ia mautinoa e fa'alauiloa uma ports i luga ole tulaga a'o le'i kilikiina le fa'atupu vaega fa'aikona i le meafaigaluega.

5. Kiliki le Generate Component icon i le SmartDesign toolbar, e pei ona faʻaalia i le ata o loʻo i lalo.

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5. Kiliki le Generate Component icon i le SmartDesign toolbar, e pei ona faʻaalia i le ata o loʻo i lalo. O le vaega SmartDesign ua gaosia. Ata 15 · Fausia Vaega
6. Fa'asaga i View > Pupuni > Files. O le Files pusa talanoaga o loʻo faʻaalia. 7. Kiliki-matau le faila simulation ma kiliki Auina mai Files, e pei ona faʻaalia i le ata o loʻo i lalo.
Ata 16 · Fa'aulufale mai File

8. Ia faaulufale mai le faaosofia ata file, folau ma aumai se tasi o mea nei files ma kiliki Tatala.

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8. Ia faaulufale mai le faaosofia ata file, folau ma aumai se tasi o mea nei files ma kiliki Tatala. a. A sample RGB_in.txt file o loʻo tuʻuina atu i le testbench i le ala lea:
..Project_namecomponentMicrosemiSolutionCore ddr_memory_arbiter 2.0.0Stimulus
Ina ia faaulufale mai le sample nofoa su'ega ata fa'aoga, su'esu'e i le sample ata o lo'o i totonu o le testbench file, ma kiliki Tatala, e pei ona faaalia i le ata o loo i lalo. Ata 17 · Ata Ulufale File Filifiliga
e. Ina ia faaulufale mai se ata ese, su'esu'e i le pusa o lo'o iai le ata e mana'omia file, ma kiliki Tatala. O le fa'aulufaleina ata fa'aosofia file o lo'o lisiina i lalo o le fa'ata'ita'iga fa'atonu, e pei ona fa'aalia i le ata o lo'o mulimuli mai. Ata 18 · Ata Ulufale File i le Fa'ailoga Fa'ata'ita'iga

9. Fa'aulufale mai le ddr BFM files. Lua files e tutusa ma
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9. Fa'aulufale mai le ddr BFM files. Lua files lea e tutusa ma DDR BFM - ddr3.v ma ddr3_parameters.v o loʻo tuʻuina atu i le testbench i le ala lea: ..Project_namecomponentMicrosemiSolutionCoreddr_memory_arbiter 2.0.0Stimulus. Kiliki-matau le faila stimulus ma filifili Import Files filifiliga, ona filifili lea o le BFM ua taʻua i luga files. O le DDR BFM mai fafo files o lo'o lisiina i lalo o le stimulus, e pei ona fa'aalia i le ata o lo'o mulimuli mai. Ata 19 · Fa'aulufale mai File
10. Fa'asaga i File > Fa'aulufale mai > Isi. O le faaulufale mai Files pusa talanoaga o loʻo faʻaalia. Ata 20 · Fa'aulufale mai Su'ega Su'ega File

11. Fa'aulufale mai le su'ega ma le vaega MSS files (top_tb.cxf, mss_top_sb_MSS.cxf, mss_top.cxf, ma mss
..Project_namecomponentMicrosemiSolutionCoreddr_memory_arbiter 2.0.0Stimulus

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11.
DDR AXI Arbiter
Ata 21 · Fa'aulufale mai Su'ega Su'ega ma MSS Vaega Files
Ata 22 · top_tb Fausia

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DDR AXI Arbiter

3.5.1

Fa'ata'ita'iga MSS SmartDesign
O fa'atonuga nei o lo'o fa'amatalaina pe fa'apefea ona fa'atusa le MSS SmartDesign:
1. Kiliki le Design Hierarchy tab ma filifili Vaega mai le fa'aaliga fa'alalo lisi. O lo'o fa'aalia le MSS SmartDesign fa'aulufale mai.
2. Kiliki taumatau mss_top i lalo o le Galuega ma kiliki Open Component, e pei ona fa'aalia i le ata o lo'o i lalo. O lo'o fa'aalia le vaega mss_top_sb_0.
Ata 23 · Vaega Tatala

3. Kiliki taumatau le vaega mss_top_sb_0 ma kiliki le Configure, e pei ona faʻaalia i le ata o loʻo i lalo.

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3. Kiliki taumatau le vaega mss_top_sb_0 ma kiliki le Configure, e pei ona faʻaalia i le ata o loʻo i lalo. Ata 24 · Fa'atonu Vaega
O le MSS Configuration window o loʻo faʻaalia, e pei ona faʻaalia i le ata o loʻo i lalo. Ata 25 · MSS Configuration Window

4. Kiliki le Next e ala i faʻamaufaʻailoga uma, e pei ona faʻaalia i le ata o loʻo mulimuli mai.

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4. Kiliki le Next e ala i faʻamaufaʻailoga uma, e pei ona faʻaalia i le ata o loʻo mulimuli mai. Ata 26 · Fa'asagaga Tabs
O le MSS e faʻapipiʻiina pe a uma ona faʻapipiʻi le faʻalavelave faʻalavelave. O le ata o loʻo i lalo o loʻo faʻaalia ai le alualu i luma ole MSS Configuration. Ata 27 · MSS Configuration Window Ina ua uma le Configuration

5. Kiliki le Next pe a mae'a le fa'atulagaina. O lo'o fa'aalia le faamalama o le Memory Map, e pei ona fa'aalia i le ata lea.
Ata 28 · Fa'afanua Fa'amanatu

6. Kiliki Fa'auma.

7. Kiliki Fausia Vaega mai le SmartDesign toolbar e gaosia ai le MSS, e pei ona faʻaalia i le

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DDR AXI Arbiter
7. Kiliki Fausia Vaega mai le SmartDesign toolbar e gaosia ai le MSS, e pei ona faʻaalia i le ata o loʻo i lalo. Ata 29 · Fausia Vaega
8. I le Design Hierarchy window, kiliki-matau mss_top i lalo o le Galuega ma kiliki Set As Root, e pei ona faʻaalia i le ata o loʻo i lalo. Ata 30 · Seti MSS e fai ma Root

9. I le fa'amalama o le Fuafuaga, fa'alautele Fa'amaonia Fuafuaga Fa'amuamua i lalo ole Fausia Fuafuaga, kiliki-matau

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9. I le fa'amalama o le Fuafuaga, fa'alautele le Verify Pre-synthesized Design i lalo o le Create Design, kiliki-matau Simulate ma kiliki Open Interactively. E fa'atusa le MSS. Ata 31 · Fa'ata'ita'i le Fuafuaga Fa'amuamua
10. Kiliki Leai pe a fa'aalia se savali mataala e fa'afeso'ota'i le Testbench stimulus ma MSS. 11. Tapuni le faʻamalama Modelsim pe a maeʻa le faʻataʻitaʻiga.
Ata 32 · Fa'amalama Fa'ata'ita'iga

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3.5.2

Fa'ata'ita'iga Testbench
O fa'atonuga nei o lo'o fa'amatalaina pe fa'afefea ona fa'ata'ita'i le su'ega:
1. Filifili le top_tb SmartDesign Testbench ma kiliki Fausia Vaega mai le SmartDesign toolbar e faʻatupu ai le suʻega, e pei ona faʻaalia i le ata o loʻo i lalo.
Ata 33 · Fausiaina o se Vaega

2. I le faamalama Stimulus Hierarchy, kiliki-matau top_tb (top_tb.v) testbench file ma kiliki Seti e fai ma fa'amalosi malosi. O lo'o fa'agaoioia le stimulus mo le top_tb testbench file.

3. I le faamalama Stimulus Hierarchy, kiliki-matau top_tb (
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DDR AXI Arbiter
3. I le faamalama Stimulus Hierarchy, kiliki-matau top_tb (top_tb.v) testbench file ma kiliki Open Interactively mai Simulate Pre-Synth Design. O le mea lea e fa'atusa ai le 'autu mo le fa'avaa e tasi. Ata 34 · Fa'ata'ita'i Fuafuaga Fa'ata'ita'i

4. Afai e faʻalavelaveina le faʻataʻitaʻiga ona o le taimi faʻatapulaʻa i le DO file, faʻaaoga le taʻavale -all command e faʻamaeʻa ai le faʻataʻitaʻiga. A maeʻa le faʻataʻitaʻiga, faʻafeiloaʻi i View > Files > fa'ata'ita'iga i view le ata o le nofoa su'ega file i totonu o le pusa faʻataʻitaʻiga.
O le gaioiga o le faʻataʻitaʻiga o le tusitusiga e tutusa ma le tasi faʻavaa o le ata, o loʻo teuina i le Read_out_rd_ch(x).txt text file fa'atatau ile ala faitau fa'aaoga. E mafai ona liua lenei mea i se ata ma faʻatusatusa i le ata muamua.

3.6

Fa'aaogaina o Punaoa

Ole poloka DDR Arbiter o loʻo faʻatinoina ile M2S150T SmartFusion®2 System-on-Chip (SoC) FPGA i le

FC1152 afifi) ma PolarFire FPGA (MPF300TS_ES - 1FCG1152E afifi).

Fuafuaga 4 · Fa'aogaina o Punaoa mo le DDR AXI Arbiter

Punaoa DFFs 4-tuuina LUTs MACC RAM1Kx18

Fa'aoga 2992 4493 0 20

(Mo:

g_RD_CHANNEL(X)_HORIZONTAL_RESOLUTION = 1280

g_RD_CHANNEL(X)_BUFFER_LINE_STORAGE = 1

g_WR_CHANNEL(X)_BUFFER_LINE_STORAGE = 1

g_AXI_DWIDTH = 64

g_RD_CHANNEL(X)_VIDEO_DATA_WIDTH = 24

RAM64x18

g_WR_CHANNEL(X)_VIDEO_DATA_WIDTH = 32) 0

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DDR AXI Arbiter

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50200644

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Pepa / Punaoa

Microchip UG0644 DDR AXI Arbiter [pdf] Taiala mo Tagata Fa'aoga UG0644 DDR AXI Arbiter, UG0644, DDR AXI Arbiter, AXI Arbiter

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