F Tile Serial Lite IV Intel FPGA IP Taiala Fa'aaogāina

Mataupu lalafi

1 F Tile Serial Lite IV Intel FPGA IP

2 Pepa / Punaoa

2.1 Fa'asinomaga

3 Fa'amatalaga Fa'atatau

F Tile Serial Lite IV Intel FPGA IP

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F-Tile Serial Lite IV Intel® FPGA IP User Guide
Fa'afou mo Intel® Quartus® Prime Design Suite: 22.1 IP Version: 5.0.0

Online Version Lauina Manatu

UG-20324

ID: 683074 Fa'aliliuga: 2022.04.28

Mataupu
Mataupu
1. E uiga i le F-Tile Serial Lite IV Intel® FPGA IP User Guide…………………………………………………….. 4
2. F-Tile Serial Lite IV Intel FPGA IP Ovaview………………………………………………………. 6 2.1. Fa'asalalauga Fa'amatalaga…………………………………………………………………………………….7 2.2. Vaega Lagolago ……………………………………………………………………………………… 7 2.3. IP Version Lagolago Laasaga…………………………………………………………………………..8 2.4. Lagolago i Vasega Saosaoa o Meafaigaluega……………………………………………………………………..8 2.5. Fa'aaogāina o Punaoa ma le Taofia ……………………………………………………………………………9 2.6. Malosiaga Bandwidth ………………………………………………………………………………………. 9
3. Amataina …………………………………………………………………………………………………. 11 3.1. Fa'apipi'iina ma Laiseneina Intel FPGA IP Cores…………………………………………………… 11 3.1.1. Intel FPGA IP Evaluation Mode………………………………………………………………. 11 3.2. Fa'ama'otiina ole IP Parameter ma Filifiliga……………………………………………………………… 14 3.3. Fausia File Faatulagaga …………………………………………………………………………… 14 3.4. Fa'ata'ita'iga Intel FPGA IP Cores……………………………………………………………… 16 3.4.1. Fa'ata'ita'iga ma le Fa'amaoniaina o le Fuafuaga…………………………………………………….. 17 3.5. Fa'atasia IP Cores i Isi Meafaigaluega EDA………………………………………………………. 17 3.6. Tuufaatasia o le Fuafuaga Atoa…………………………………………………………………………..18
4. Fa'amatalaga Fa'atino…………………………………………………………………………………… 19 4.1. TX Datapath………………………………………………………………………………………………..20 4.1.1. TX MAC Fetuunaiga………………………………………………………………………….. 21 4.1.2. Faaofiina Upu Pule (CW)……………………………………………………………… 23 4.1.3. TX CRC……………………………………………………………………………………28 4.1.4. TX MII Encoder………………………………………………………………………………29 4.1.5. TX PCS ma le PMA………………………………………………………………………….. 30 4.2. RX Datapath…………………………………………………………………………………………. 30 4.2.1. RX PCS ma PMA………………………………………………………………………….. 31 4.2.2. RX MII Decoder………………………………………………………………………… 31 4.2.3. RX CRC…………………………………………………………………………………….. 31 4.2.4. RX Deskew………………………………………………………………………………….32 4.2.5. Aveese RX CW…………………………………………………………………………35 4.3. F-Tile Serial Lite IV Intel FPGA IP Clock Architecture…………………………………………. 36 4.4. Toe Seti ma So'oga Amataina…………………………………………………………………………..37 4.4.1. TX Toe Fa'atonu ma le Fa'asologa o le Fa'amataina ………………………………………………………. 38 4.4.2. RX Toe Seti ma le Fa'asologa o le Fa'asologa o le amataga…………………………………………………………. 39 4.5. Fua Faatatau o So'oga ma le Fa'atatauina o le Fa'atatauga o le Fa'atonuga ……………………………………………………….. 40
5. Parameter…………………………………………………………………………………………………………. 42
6. F-Tile Serial Lite IV Intel FPGA IP Interface Signals…………………………………………….. 44 6.1. Faailoga o le Uati……………………………………………………………………………………………….44 6.2. Toe Seti Faailoga…………………………………………………………………………………… 44 6.3. Faailoga MAC……………………………………………………………………………………………….. 45 6.4. Fa'ailoga Toe Fa'atonuga o Fa'ailoga ……………………………………………………………… 48 6.5. Faailoga PMA……………………………………………………………………………………………….. 49

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Mataupu
7. Fuafuaina ma le F-Tile Serial Lite IV Intel FPGA IP…………………………………………………… 51 7.1. Toe Seti Taiala…………………………………………………………………………………….. 51 7.2. Fa'atonuga o le Fa'afoeina o Measese…………………………………………………………………………..51
8. F-Tile Serial Lite IV Intel FPGA IP User Guide Archives…………………………………………. 52 9. Tala'aga Toe Iloiloga o Pepa mo le F-Tile Serial Lite IV Intel FPGA IP User Guide…….53

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1. E uiga i le F-Tile Serial Lite IV Intel® FPGA IP User Guide

O lenei pepa o loʻo faʻamatalaina uiga IP, faʻamatalaga faʻataʻitaʻiga, laasaga e gaosia, ma taʻiala e mamanuina le F-Tile Serial Lite IV Intel® FPGA IP e faʻaaoga ai le F-tile transceivers i masini Intel AgilexTM.

Tagata Fa'amoemoe

O lenei pepa e faʻamoemoe mo tagata faʻaoga nei:
· Fa'ata'ita'i fa'ata'ita'i e fai le filifiliga IP i le taimi o le fa'atulagaina o fuafuaga fa'atulagaina
· Faufautua meafaigaluega pe a tuʻufaʻatasia le IP i totonu o latou mamanu faʻatulagaina
· Enisinia faʻamaonia i le taimi o faʻataʻitaʻiga faʻavae ma vaega faʻamaonia meafaigaluega

Pepa Fa'atatau

O le laulau o lo'o i lalo o lo'o lisiina ai isi fa'amatalaga e feso'ota'i ma le F-Tile Serial Lite IV Intel FPGA IP.

Laulau 1.

Pepa Fa'atatau

Fa'asinomaga

F-Tile Serial Lite IV Intel FPGA IP Design Example User Guide

Intel Agilex Device Data Pepa

Fa'amatalaga
O lenei pepa o loʻo tuʻuina atu ai le faʻatupuina, taʻiala faʻaoga, ma faʻamatalaga galue o le F-Tile Serial Lite IV Intel FPGA IP design examples i masini Intel Agilex.
O lenei pepa o loʻo faʻamatalaina uiga eletise, suiga o uiga, faʻatulagaina faʻamatalaga, ma le taimi mo masini Intel Agilex.

Laulau 2.
CW RS-FEC PMA TX RX PAM4 NRZ

Acronyms ma Glossary Acronym Lisi
Acronym

Fa'alautele Upu Pulea Reed-Solomon Luma Fa'asa'oga Sese Fa'asa'oga Fa'apitoa Fa'apipi'i Medium Fa'apipi'i Transmitter Receiver Pulse-Amplitude Modulation 4-Level Le toe fo'i-i-zero

faaauau…

Intel Corporation. Ua taofia aia tatau uma. Intel, le Intel logo, ma isi fa'ailoga Intel o fa'ailoga fa'ailoga a le Intel Corporation po'o ona lala. E fa'amaonia e Intel le fa'atinoina o ana oloa FPGA ma semiconductor i fa'amatalaga o lo'o iai nei e tusa ai ma le fa'atonuga masani a Intel, ae fa'asaoina le aia tatau e fai ai suiga i so'o se oloa ma auaunaga i so'o se taimi e aunoa ma se fa'aaliga. E leai se tiute po'o se noataga e afua mai i le talosaga po'o le fa'aogaina o so'o se fa'amatalaga, oloa, po'o se auaunaga o lo'o fa'amatalaina i i'i se'i vagana ua malilie i ai i se faiga tusitusia e Intel. Ua fautuaina tagata fa'atau Intel ina ia maua le fa'amatalaga lata mai o fa'amatalaga masini a'o le'i fa'alagolago i so'o se fa'amatalaga fa'asalalau ma a'o le'i tu'uina atu oka mo oloa po'o tautua. *O isi igoa ma fa'ailoga e mafai ona ta'ua o se meatotino a isi.

ISO 9001:2015 Resitala

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PCS MII XGMII

Acronym

Fa'alautele Fa'asinomaga Fa'aletino Sublayer Fa'asalalauga Tuto'atasi Fa'afeso'ota'i 10 Gigabit Fa'asalalauga Tuto'atasi Fa'amatalaga

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2. F-Tile Serial Lite IV Intel FPGA IP Ovaview

Ata 1.

F-Tile Serial Lite IV Intel FPGA IP e fetaui lelei mo fesoʻotaʻiga faʻamaumauga maualuga bandwidth mo faʻaoga chip-to-chip, laupapa-i-board, ma backplane talosaga.

O le F-Tile Serial Lite IV Intel FPGA IP o loʻo faʻapipiʻiina ai le faʻaogaina o ala o fesoʻotaʻiga (MAC), faʻapipiʻi faʻasologa o le tino (PCS), ma poloka faʻapipiʻi faʻapitoa (PMA). E lagolagoina e le IP le saoasaoa o fesoʻotaʻiga e oʻo atu i le 56 Gbps i le laina ma le maualuga o le fa PAM4 laina poʻo le 28 Gbps i le laina ma le maualuga o le 16 NRZ laina. O lenei IP o loʻo ofoina atu le bandwidth maualuga, faʻavaʻa maualalo i luga o le ulu, maualalo le I / O numera, ma lagolagoina le maualuga maualuga i numera uma o laina ma le saoasaoa. O lenei IP e faigofie foʻi ona toe faʻaleleia ma le lagolago o le tele o fuainumera faʻamatalaga ma le Ethernet PCS mode o le F-tile transceiver.

O lenei IP e lagolagoina auala faʻasalalau e lua:
· Faiga fa'avae–Ose faiga fa'amama mama lea e lafo ai fa'amatalaga e aunoa ma le amataga-pepa, ta'amilosaga gaogao, ma le fa'ai'uga-o-pepa e fa'atele ai le bandwidth. O le IP e ave faʻamatalaga faʻamaonia muamua e avea ma amataga o se pa.
· Faiga atoa–O le faiga lea e fesiitai ai. I lenei faiga, e tuʻuina atu e le IP se paʻu ma se faʻasologa o le taamilosaga i le amataga ma le faʻaiʻuga o se afifi e fai ma faʻamaʻi.

F-Tile Serial Lite IV High Level Block Diagram

Avalon Streaming Interface TX

F-Tile Serial Lite IV Intel FPGA IP
MAC TX
TX USRIF_CTRL

64*n laina laina (NRZ mode)/ 2*n laina laina (PAM4 mode)

TX MAC

Fa'apipi'i INSERT

MII ENCODE

PCS fa'apitoa

TX PCS

TX MII

EMIB ENCODE SCRAMBLER FEC

TX PMA

n Lanes Bits (PAM4 mode)/ n Lanes Bits (NRZ mode)
TX Fa'asologa Fa'asologa

Avalon Streaming Interface RX
64*n laina laina (NRZ mode)/ 2*n laina laina (PAM4 mode)

RX PCS

CW RMV

DESKEW

MII

& FA'ASA'O LE DECODE

RX MII

EMIB

DECODE POLOKA SYNC & FEC DESCRAMBLER

RX PMA

CSR

2n Lanes Bits (PAM4 mode)/ n Lanes Bits (NRZ mode) RX Serial Interface
Avalon Memory-Mapped Interface Register Config

Tala'aga

Fa'aa'oa'oga mālū

Faigata faigata

ISO 9001:2015 Resitala

2. F-Tile Serial Lite IV Intel FPGA IP Ovaview 683074 | 2022.04.28

E mafai ona e gaosia F-Tile Serial Lite IV Intel FPGA IP design examples e aoao atili e uiga i foliga IP. Va'ai ile F-Tile Serial Lite IV Intel FPGA IP Design Example User Guide.
Fa'amatalaga Fa'atatau · Fa'amatalaga Fa'atino i le itulau 19 · F-Tile Serial Lite IV Intel FPGA IP Design Example User Guide

2.1. Fa'asalalau Fa'amatalaga

Intel FPGA IP versions e fetaui ma le Intel Quartus® Prime Design Suite versions software seia oo i le v19.1. Amata ile Intel Quartus Prime Design Suite software version 19.2, Intel FPGA IP o loʻo iai se polokalame faʻaliliu fou.

Ole numera ole Intel FPGA IP (XYZ) e mafai ona suia ile Intel Quartus Prime software version. Se suiga i:

· X o loʻo faʻaalia ai se suiga tele o le IP. Afai e te faʻafouina le polokalama Intel Quartus Prime, e tatau ona e toe faʻafouina le IP.
· Y faʻaalia le IP e aofia ai foliga fou. Toe fa'afouina lau IP e fa'aofi ai nei foliga fou.
· Z o loʻo faʻaalia ai le IP e aofia ai suiga laiti. Toe fa'afouina lau IP e fa'aofi ai nei suiga.

Laulau 3.

F-Tile Serial Lite IV Intel FPGA IP Fa'amatalaga Fa'amatalaga

Aitema IP Version Intel Quartus Prime Version Fa'asalalau Aso Fa'atonu Code

5.0.0 22.1 2022.04.28 IP-SLITE4F

Fa'amatalaga

2.2. Vaega Lagolago
O le laulau o loʻo i lalo o loʻo lisiina ai foliga o loʻo maua ile F-Tile Serial Lite IV Intel FPGA IP:

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Laulau 4.

F-Tile Serial Lite IV Intel FPGA IP Features

Fa'aaliga

Fa'amatalaga

Fa'aliliuga Fa'amatalaga

· Mo le PAM4 faiga:
- E na'o le 56.1, 58, ma le 116 Gbps e na'o le 4, XNUMX, ma le XNUMX Gbps e lagolagoina e le FHT ma le maualuga o le XNUMX laina.
— FGT lagolago i le 58 Gbps i le laina ma le maualuga o le 12 laina.
Va'ai ile Laulau 18 ile itulau 42 mo nisi fa'amatalaga ile fua faatatau o fa'amaumauga ole transceiver mo le PAM4 mode.
· Mo le NRZ mode:
- E na'o le 28.05 ma le 58 Gbps e lagolagoina e le FHT i le laina ma le maualuga o le 4 laina.
- FGT o loʻo lagolagoina e oʻo atu i le 28.05 Gbps i le laina ma le maualuga o le 16 laina.
Va'ai ile Laulau 18 ile itulau 42 mo nisi fa'amatalaga ile fua faatatau o fa'amaumauga ole transceiver mo le NRZ mode.
· Lagolagoina le fa'aauauina o le fa'aosoina (Basic) po'o le afifi (Full) modes.
· Lagolago afifi faavaa pito i luga.
· Lagolagoina byte granularity fesiitaiga mo soʻo se lapopoa pa.
· Lagolagoina le fa'aogaina o le auala e fa'aogaina e le tagata fa'aoga po'o le fa'aogaina otometi.
· Lagolagoina polokalamemable alignment vaitaimi.

PCS

· Fa'aaoga manatu IP faigata e feso'ota'i ma le Intel Agilex F-tile transceivers mo le fa'aitiitiga o punaoa fa'aleaogaina.
· Lagolagoina le faʻaogaina o le PAM4 mo le 100GBASE-KP4 faʻamatalaga. O le RS-FEC e mafai ona fa'aogaina i lenei faiga fa'aopoopo.
· Lagolago le NRZ ma le fa'aogaina o le fa'aogaina o le RS-FEC.
· Lagolago le 64b/66b encoding decoding.

Su'esu'eina ma le Taulimaina

· Lagolagoina le siakiina o mea sese a le CRC i luga o ala o faʻamatalaga TX ma RX. · Lagolago RX so'oga siaki sese. · Lagolago RX PCS mea sese iloa.

Fa'afeso'ota'i

· Lagolago na'o le fa'aliliuina o pepa fa'ato'a atoa ma so'oga tuto'atasi.
· Fa'aoga feso'ota'iga mata'itū i le tele o masini FPGA e maualalo le fa'aliliuina.
· Lagolagoina fa'atonuga fa'auigaina.

2.3. IP Version Lagolago Level

O le Intel Quartus Prime software ma le Intel FPGA device support mo le F-Tile Serial Lite IV Intel FPGA IP e fa'apea:

Laulau 5.

IP Version ma Lagolago Level

Intel Quartus Prime 22.1

Meafaigaluega Intel Agilex F-tile transceivers

IP Version Simulation Compilation Meafaigaluega Design

5.0.0

2.4. Lagolago Vaega Saosaoa Meafaitino
O le F-Tile Serial Lite IV Intel FPGA IP o lo'o lagolagoina fa'ailoga saoasaoa nei mo masini Intel Agilex F-tile: · Transceiver grade speed: -1, -2, ma -3 · Core speed grade: -1, -2, ma - 3

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Fa'amatalaga Fa'atatau
Intel Agilex Device Data Sheet Fa'amatalaga atili e uiga i le fua fa'amaumauga lagolago ile Intel Agilex F-tile transceivers.

2.5. Fa'aaogāina o Punaoa ma le Fa'agata

O punaoa ma le taofiofia mo le F-Tile Serial Lite IV Intel FPGA IP na maua mai le Intel Quartus Prime Pro Edition software version 22.1.

Laulau 6.

Intel Agilex F-Tile Serial Lite IV Intel FPGA IP Fa'aogaina Punaoa
O le fuaina o le latency e fa'avae i luga o le ta'amilosaga ta'amilosaga mai le TX fa'aulu i totonu o le RX autu.

Ituaiga Transceiver

Eseesega

Numera o Auala Fa'amatalaga Faiga RS-FEC ALM

Ta'amilosaga (TX core clock cycle)

FGT

28.05 Gbps NRZ 16

Fa'apitoa Fa'aletonu 21,691 65

Tino le atoatoa 22,135 65

Basic Enabled 21,915 189

Full Enabled 22,452 189

58 Gbps PAM4 12

Basic Enabled 28,206 146

Full Enabled 30,360 146

FHT

58 Gbps NRZ

Basic Enabled 15,793 146

Full Enabled 16,624 146

58 Gbps PAM4 4

Basic Enabled 15,771 154

Full Enabled 16,611 154

116 Gbps PAM4 4

Basic Enabled 21,605 128

Full Enabled 23,148 128

2.6. Fa'atosina ole Bandwidth

Laulau 7.

Fa'atosina ole Bandwidth

Fuafuaga Transceiver mode

PAM4

Faiga fa'afefe RS-FEC

Atoatoa Fa'aagaoi

Basic Enabled

Fa'asologa o feso'ota'iga i le Gbps (RAW_RATE)
Lapata'i tele o se fesiitaiga i le numera o upu (BURST_SIZE) (1)
Vaitaimi fa'aoga i le taamilosaga o le uati (SRL4_ALIGN_PERIOD)

56.0 2,048 4,096

56.0 4,194,304 4,096

Fa'atonu

NRZ

tumu

Fa'aletonu

Ua mafai

28.0

2,048

4,096

Fa'atonu Fa'aletonu 28.0

Fa'aola 28.0

4,194,304

4,096

4,096 faaauau…

(1) O le BURST_SIZE mo le fa'avae Fa'avae e fa'alatalata atu i le le i'u, o lea e fa'aaoga ai se numera tele.

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Fuafuaga

Fa'atonu

64/66b fa'ailoga

0.96969697 0.96969697 0.96969697 0.96969697 0.96969697 0.96969697

I luga a'e o le pa'u tele i le numera o upu (BURST_SIZE_OVHD)

2 (2)

0 (3)

2 (2)

0 (3)

Vaitaimi fa'avasega 81,915 ile taamilosaga uati (ALIGN_MARKER_PERIOD)

81,915

81,916

Fa'asagaga fa'ailoga lautele ile 5

taamilosaga uati

(ALIGN_MARKER_WIDTH)

Malosiaga lautele (4)

0.96821788 0.96916433 0.96827698 0.96822967 0.96922348 0.96917616

Fua faatatau lelei (Gbps) (5)

54.2202012 54.27320236 27.11175544 27.11043076 27.13825744 27.13693248

Ole tele ole taimi ole uati ole fa'aoga (MHz) (6)

423.59532225 424.00939437 423.62117875 423.6004806 424.0352725 424.01457

Fa'amatalaga Feso'ota'i Fua Fa'atatau ma le Fa'atatauina o le Fa'atonuga ole Bandwidth ile itulau 40

(2) I le tulaga atoa, o le BURST_SIZE_OVHD lapopo'a e aofia ai le START/END fa'aluaina Upu Pule i totonu o fa'amaumauga.
(3) Mo le faiga fa'avae, BURST_SIZE_OVHD e 0 aua e leai se START/END a'o fa'asolo.
(4) Va'ai i le So'oga Fua Fa'atatau ma le Fa'asologa o le Fa'asologa o Bandwidth mo le fa'atusatusaina o le fa'aogaina o le bandwidth.
(5) Va'ai i le So'oga Fua Fa'atatau ma le Fa'asologa o le Fa'asologa o Bandwidth mo le fa'atatauga lelei.
(6) Va'ai i le So'oga Fua Fa'atatau ma le Fa'asologa o le Bandwidth Efficiency Calculation mo le fa'atatauga o taimi ole uati aupito maualuga a tagata fa'aoga.

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3. Amataina

3.1. Fa'apipi'i ma Laisene Intel FPGA IP Cores

O le Intel Quartus Prime software installation e aofia ai le Intel FPGA IP library. O lenei faletusi e maua ai le tele o pusa IP aoga mo lau fa'aoga gaosiga e aunoa ma le mana'omia o se laisene fa'aopoopo. O nisi Intel FPGA IP cores e manaʻomia le faʻatauina o se laisene ese mo le faʻaogaina o le gaosiga. Ole Intel FPGA IP Evaluation Mode e mafai ai ona e iloiloina nei laisene Intel FPGA IP cores i faʻataʻitaʻiga ma meafaigaluega, aʻo leʻi filifili e faʻatau se laisene faʻaulu atoatoa IP. E na'o lou mana'omia e fa'atau se laisene fa'akomepiuta atoatoa mo le Intel IP cores pe a mae'a su'ega meafaigaluega ma ua sauni e fa'aoga le IP ile gaosiga.

O le Intel Quartus Prime software e faʻapipiʻi ai pusa IP i nofoaga nei ona o le faaletonu:

Ata 2.

Auala Fa'apipi'i IP Core
intelFPGA(_pro) quartus – E iai le Intel Quartus Prime software ip – E iai le Intel FPGA IP library ma isi vaega IP cores altera – E iai le Intel FPGA IP library source code - O loʻo iai le Intel FPGA IP puna files

Laulau 8.

Nofoaga Fa'apipi'i IP Core

Nofoaga

Polokalama

:intelFPGA_proquarttusipaltera

Intel Quartus Prime Pro Edition

:/intelFPGA_pro/quartus/ip/altera Intel Quartus Prime Pro Edition

Pupuni Pupuni* Linux*

Fa'aaliga:

O le polokalama Intel Quartus Prime e le lagolagoina avanoa i le auala faʻapipiʻi.

3.1.1. Intel FPGA IP Iloiloga Faiga
Ole ole Intel FPGA IP Evaluation Mode e mafai ai ona e iloilo ua laiseneina Intel FPGA IP cores ile fa'ata'ita'iga ma meafaigaluega a'o le'i fa'atau. Intel FPGA IP Evaluation Mode e lagolagoina iloiloga nei e aunoa ma se laisene faaopoopo:
· Fa'ata'ita'i le amio a le Intel FPGA IP core ua laiseneina i lau masini. · Faʻamaonia le faʻatinoga, tele, ma le saoasaoa o le IP autu vave ma faigofie. · Fa'atupuina polokalame fa'apolokalame masini fa'atapula'a taimi files mo mamanu e aofia ai pusa IP. · Polokalama se masini ma lau IP core ma faʻamaonia lau mamanu i meafaigaluega.

ISO 9001:2015 Resitala

3. Amataina
683074 | 2022.04.28
E lagolagoina e le Intel FPGA IP Evaluation Mode ia faiga fa'agaioiga nei:
· Tethered–Fa'ataga le fa'atinoina o le mamanu o lo'o i ai le laisene Intel FPGA IP mo se taimi fa'atasi ma se feso'ota'iga i le va o lau laupapa ma le komepiuta talimalo. Faiga fa'apipi'i e mana'omia ai se fa'asologa o su'ega tu'ufa'atasiga vaega (JTAG) uaea feso'ota'i i le va o le JTAG uafu i luga o lau laupapa ma le komepiuta talimalo, lea o loʻo faʻatautaia le Intel Quartus Prime Programmer mo le umi ole taimi ole iloiloga o meafaigaluega. E na'o le Polokalama e mana'omia le fa'apipi'iina o le polokalama Intel Quartus Prime, ma e le mana'omia se laisene Intel Quartus Prime. O le komepiuta talimalo e pulea le taimi o iloiloga e ala i le tuʻuina atu o se faʻailoga taimi i le masini e ala i le JTAG uafu. Afai e fa'amuta uma pusa IP ua laiseneina i le mamanu e lagolagoina le faiga, e alu le taimi o iloiloga se'ia mae'a so'o se iloiloga autu o le IP. Afai e lagolagoina uma e le IP cores le fa'atapula'aina o le taimi o iloiloga, e le fa'agata le masini.
· Untethered–Fa'ataga le fa'atinoina o le mamanu o lo'o iai le IP laiseneina mo se taimi fa'atapula'a. O le IP autu e toe foʻi i le untethered mode pe a motusia le masini mai le komepiuta talimalo o loʻo faʻaogaina le polokalama Intel Quartus Prime. O le IP core e toe fo'i i le untethered mode pe afai e le lagolagoina e se isi IP core ua laiseneina i totonu o le mamanu le auala tethered.
A maeʻa le taimi o iloiloga mo soʻo se Intel FPGA IP laiseneina i le mamanu, o le mamanu e le toe galue. O pusa IP uma e fa'aogaina le Intel FPGA IP Evaluation Mode e fa'agata i le taimi e tasi pe a uma so'o se IP i totonu o le mamanu. A mae'a le taimi o iloiloga, e tatau ona e toe fa'apolokalame le masini FPGA a'o le'i fa'aauauina le fa'amaoniga o meafaigaluega. Ina ia faʻalauteleina le faʻaogaina o le IP autu mo le gaosiga, faʻatau se laisene gaosiga atoatoa mo le IP autu.
E tatau ona e fa'atauina le laisene ma fa'atupu se ki atoa o le laisene gaosiga ae e te le'i fa'atupuina se polokalame masini e le fa'atapulaaina file. I le taimi ole Intel FPGA IP Evaluation Mode, o le Compiler e na'o le fa'atupuina o se polokalame masini fa'atapula'a taimi file ( _time_limited.sof) e muta i le taimi faatapulaaina.

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Ata 3.

Intel FPGA IP Iloiloga Faiga Fa'agasologa
Fa'apipi'i le Intel Quartus Prime Software ma le Intel FPGA IP Library

Fa'ata'atia ma fa'atupuina se Laisene Intel FPGA IP Core

Fa'amaonia le IP ile Simulator Lagolago

Tuufaatasia le Fuafuaga ile Intel Quartus Prime Software

Fausia se Polokalama Meafaigaluega Fa'atapula'a Taimi File

Polokalama le Intel FPGA Device ma Fa'amaonia le Fa'agaioiga i luga o le Komiti Fa'atonu
Leai se IP ua Sauni mo le Fa'aaogāga?
Ioe Fa'atau se Gaosiga Atoa
Laisene IP

Fa'aaliga:

Fa'aaofia le IP Laisene i Oloa Fa'atau
Va'ai i ta'iala fa'aoga a le IP ta'iala mo la'asaga fa'avasega ma fa'amatalaga fa'atinoga.
Intel laiseneina IP cores i luga o nofoa ta'itasi, fa'avae tumau. Ole totogi ole laisene e aofia ai le tausiga ole tausaga muamua ma le lagolago. E tatau ona e fa'afouina le konekarate fa'aleleia e maua ai fa'afouga, fa'aleleia o bug, ma lagolago fa'atekinisi i tua atu o le tausaga muamua. E tatau ona e fa'atauina se laisene gaosiga atoatoa mo Intel FPGA IP cores e mana'omia se laisene gaosiga, a'o le'i faia polokalame files e mafai ona e faʻaaogaina mo se taimi e le gata. I le taimi o le Intel FPGA IP Evaluation Mode, o le Compiler na o le faʻatupuina o se polokalame masini faʻatapulaʻa taimi file ( _time_limited.sof) e muta i le taimi faatapulaaina. Ina ia maua lau ki laisene gaosiga, asiasi i le Intel FPGA Self-Service Licensing Center.
Ole Intel FPGA Software License Agreements e pulea le faʻapipiʻiina ma le faʻaogaina o pusa IP laiseneina, le Intel Quartus Prime design software, ma mea uma e leʻi laiseneina IP cores.

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Fa'amatalaga Fa'atatau · Intel FPGA Licensing Support Center · Folasaga i le Intel FPGA Software Installation and Licensing
3.2. Fa'ailoaina le IP Parameters ma Filifiliga
O le IP parameter editor e mafai ai e oe ona faʻapipiʻi vave lau suiga masani IP. Fa'aoga laasaga nei e fa'amaonia ai filifiliga IP ma ta'iala ile polokalama Intel Quartus Prime Pro Edition.
1. Afai e te le'i i ai se poloketi Intel Quartus Prime Pro Edition e tu'ufa'atasia ai lau F-Tile Serial Lite IV Intel FPGA IP, e tatau ona e fatuina se tasi. a. I le Intel Quartus Prime Pro Edition, kiliki File Fou Project Wizard e fatu ai se poloketi fou a Quartus Prime, po'o File Tatala Poloketi e tatala ai se poloketi Quartus Prime. E fa'atonu oe e le wizard e fa'ailoa se masini. e. Fa'ailoa le aiga masini Intel Agilex ma filifili se masini F-tile e fa'amalieina mana'oga fa'avavevave mo le IP. i. Kiliki Finish.
2. I le IP Catalog, su'e ma filifili F-Tile Serial Lite IV Intel FPGA IP. Ua aliali mai le fa'amalama New IP Variation.
3. Fa'ailoa se igoa pito i luga mo lau suiga fou masani IP. E fa'asaoina e le fa'atonu fa'amaufa'ailoga le fa'atulagaina o suiga o le IP ile a file igoa .ip.
4. Kiliki OK. E aliali mai le fa'atonu fa'amaufa'ailoga. 5. Fa'ailoa fa'amaufa'ailoga mo lau fesuiaiga IP. Va'ai i le vaega Parameter mo
faʻamatalaga e uiga i F-Tile Serial Lite IV Intel FPGA IP tapulaʻa. 6. I le faitalia, ia fa'atupuina se su'ega fa'ata'ita'i po'o le tu'ufa'atasiga ma le fa'atulagaina o meafaigaluega
example, mulimuli i faatonuga i le Design Example User Guide. 7. Kiliki Fausia HDL. O lo'o fa'aalia le Pusa talanoaga o Tupulaga. 8. Fa'ailoa galuega faatino file filifiliga o tupulaga, ona kiliki lea o le Fausia. Ole fesuiaiga ole IP
files fa'atupu e tusa ai ma au fa'amatalaga. 9. Kiliki Fa'auma. E fa'aopoopo e le fa'atonu fa'amaufa'ailoga le pito i luga .ip file i le taimi nei
galuega faatino otometi. Afai e uunaia oe e faaopoopo ma le lima le .ip file i le poloketi, kiliki Project Add/Remove Files i Poloketi e fa'aopoopo le file. 10. A mae'a ona fa'atupuina ma fa'anatinati lau fesuiaiga o le IP, fai ni fa'ailoga pine talafeagai e fa'afeso'ota'i ai ports ma fa'atulaga so'o se ta'iala RTL talafeagai.
Fa'amatalaga Fa'atatau ile itulau 42
3.3. Fausia File Fauga
O le polokalama Intel Quartus Prime Pro Edition e fa'atupuina ai le fa'atinoina o le IP file fausaga.
Mo fa'amatalaga e uiga i le file fausaga o le mamanu example, faasino i le F-Tile Serial Lite IV Intel FPGA IP Design Example User Guide.

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Ata 4. F-Tile Serial Lite IV Intel FPGA IP Fausia Files
.ip – tu'ufa'atasia IP file

Suiga IP files

_ Suiga IP files

example_design

.cmp - ta'utinoga vaega VHDL file _bb.v – Verilog HDL pusa uliuli EDA synthesis file _inst.v ma le .vhd – Sample instantiation templates .xml- XML lipoti file

Example nofoaga mo lau mamanu autu IP example files. O le nofoaga e le masani ai o le example_design, ae ua uunaia oe e faʻamaonia se isi auala.

.qgsimc - Lisi faʻataʻitaʻiga faʻataʻitaʻiga e lagolago ai le toe faʻaleleia atili .qgsynthc – Lisi fa'asologa fa'asologa e lagolago ai le toe fa'atuputeleina

.qip – Lisi le fa'asologa o IP files

_generation.rpt- Lipoti augatupulaga IP

.sopcinfo- Tu'ufa'atasiga meafaigaluega-filifili polokalame file .html- So'oga ma fa'amaumauga fa'afanua manatua

.csv – Pin tofiga file

.spd - Tuʻufaʻatasia tusitusiga faʻataʻitaʻiga taʻitasi

sim Simulation files

fa'apipi'i IP files

.v Fa'ata'ita'iga maualuga file

.v Tulaga maualuga IP fa'amaopoopo file

Fa'amaumauga a le simulator

Subcore faletusi

synth
Fa'asologa o lalo files

sim
Subcore Simulation files

Laulau 9.

F-Tile Serial Lite IV Intel FPGA IP Fausia Files

File Igoa

Fa'amatalaga

.ip

Le fa'atulagaina o le Platform Designer po'o le suiga maualuga o le IP file. o le igoa lea e te tu'uina atu ai lau fesuiaiga IP.

.cmp

Le VHDL Component Declaration (.cmp) file ose tusitusiga file o lo'o iai fa'amatalaga fa'alotoifale ma fa'auigaga e mafai ona e fa'aogaina ile VHDL design files.

.html

O se lipoti o loʻo i ai faʻamatalaga fesoʻotaʻiga, o se faʻafanua manatua e faʻaalia ai le tuatusi o pologa taʻitasi e faʻatatau i matai taʻitasi e fesoʻotaʻi i ai, ma tofitofiga.

_generation.rpt

IP po'o le Platform Designer generation log file. O se aotelega o fe'au i le taimi o le fausiaina o IP.

.qgsimc

Lisi fa'ata'ita'iga fa'ata'ita'iga e lagolago ai le fa'atupuina fa'aopoopo.

.qgsynthc

Lisi fa'asologa fa'aopoopo e lagolago ai le fa'atupuina fa'aopoopo.

.qip

O loʻo i ai faʻamatalaga manaʻomia uma e uiga i le vaega IP e tuʻufaʻatasia ma tuʻufaʻatasia le vaega IP i le polokalama Intel Quartus Prime.
faaauau…

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File Igoa .sopcinfo
.csv .spd _bb.v _inst.v poʻo _inst.vhd .regmap
.svd
.v pe .vhd faufautua/ synopsys/vcs/ synopsys/vcsmx/xcelium/ submodules/ /

Fa'amatalaga
Fa'amatala feso'ota'iga ma fa'aputuga vaega o le IP i totonu o lau fa'atulagaina o le Platform Designer. E mafai ona e fa'avasegaina mea o lo'o i totonu e maua ai mana'oga pe a e atia'e masini komepiuta mo vaega IP. Meafaigaluega pito i lalo e pei o le Nios® II mea faigaluega filifili fa'aoga lenei file. O le .sopcinfo file ma le faiga.h file gaosia mo le filifili meafaigaluega Nios II e aofia ai faʻamatalaga faʻafanua tuatusi mo pologa taʻitasi e fesoʻotaʻi ma matai taʻitasi e maua le pologa. E eseese matai e ono iai se faafanua ese o tuatusi e maua ai se vaega o pologa.
O loʻo i ai faʻamatalaga e uiga i le faʻaleleia tulaga o le vaega IP.
Manaomia fa'aoga file mo ip-make-simscript e faʻatupu ai faʻataʻitaʻiga tusitusiga mo simulators lagolagoina. O le .spd file o lo'o i ai se lisi o files gaosia mo faʻataʻitaʻiga, faʻatasi ai ma faʻamatalaga e uiga i manatuaga e mafai ona e amataina.
E mafai ona e fa'aogaina le Verilog black-box (_bb.v) file e pei o se ta'utinoga module gaogao mo le fa'aoga o se pusa uliuli.
HDL example faʻataʻitaʻiga faʻataʻitaʻiga. E mafai ona e kopi ma faapipii mea o loʻo i totonu o lenei mea file i lau HDL file e faʻaalia le suiga o le IP.
Afai o le IP o loʻo i ai faʻamatalaga resitala, .regmap file fa'atupuina. Le .regmap file o lo'o fa'amatala ai le fa'amatalaga fa'afanua tusi resitala o feso'ota'iga matai ma pologa. Lenei file faaatoatoa le .sopcinfo file e ala i le tu'uina atu o fa'amatalaga resitara sili atu e uiga i le faiga. E mafai ai ona fa'aalia le resitala views ma fa'amaumauga fa'apitoa fa'apitoa i le System Console.
Fa'ataga meafaigāluega Debug System System (HPS) e view le resitalaina o faafanua o peripherals e feso'ota'i ma HPS i totonu o se faiga Fa'ata'ita'i Platform. I le taimi o le tuufaatasia, o le .svd files mo feso'ota'iga pologa o lo'o va'aia e matai System Console o lo'o teuina i le .sof file i le vaega debug. E faitau e le System Console lenei vaega, lea e mafai e le Platform Designer ona fesiligia mo le resitalaina o faʻamatalaga faʻafanua. Mo pologa faiga, Platform Designer e mafai ona maua le resitala ile igoa.
HDL files e fa'apena fa'ata'ita'i ta'iala ta'itasi po'o le IP tamaiti mo le tu'ufa'atasiga po'o le fa'atusa.
O lo'o iai se ModelSim*/QuestaSim* script msim_setup.tcl e fa'atutu ma fa'atino se fa'ata'ita'iga.
O lo'o iai se atigi script vcs_setup.sh e fa'atutu ma fa'atino se VCS* fa'ata'ita'iga. O lo'o iai se atigi tusitusiga vcsmx_setup.sh ma synopsys_sim.setup file e fa'atutu ma fa'atautaia se VCS MX simulation.
O lo'o iai se atigi tusitusiga xcelium_setup.sh ma isi seti files e fa'atutu ma fa'atautaia le fa'ata'ita'iga Xcelium*.
E iai le HDL files mo le IP submodules.
Mo fa'atonuga IP a tamaiti ta'itasi, e fa'atupuina e le Platform Designer le synth/ma le sim/sub-directories.

3.4. Fa'ata'ita'iga Intel FPGA IP Cores
O le Intel Quartus Prime software e lagolagoina le IP core RTL simulation i faʻataʻitaʻiga faʻapitoa EDA. O le fa'atupuina o le IP e mafai ona faia fa'atusa files, e aofia ai le faʻataʻitaʻiga faʻataʻitaʻiga galue, soʻo se suʻega (poʻo example design), ma fa'atau fa'atau-fa'apitoa fa'atulagaina fa'asologa o fa'amaumauga mo IP ta'itasi. E mafai ona e faʻaogaina le faʻataʻitaʻiga faʻataʻitaʻiga galue ma soʻo se suʻega suʻega poʻo se faʻataʻitaʻigaample mamanu mo simulation. O galuega fa'atupu IP e mafai fo'i ona aofia ai fa'amaumauga e tu'ufa'atasia ma fa'atino so'o se su'ega. O loʻo lisiina e tusitusiga faʻataʻitaʻiga uma poʻo faletusi e te manaʻomia e faʻataʻitaʻi ai lau IP autu.

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O le polokalama Intel Quartus Prime e tuʻufaʻatasia ma le tele o simulators ma lagolagoina le tele o faʻataʻitaʻiga tafe, e aofia ai au lava faʻasologa faʻasologa faʻasologa ma aganuʻu. Po o le a lava le tafe e te filifilia, IP faʻataʻitaʻiga autu e aofia ai laasaga nei:
1. Fausia le IP HDL, su'ega (po'o le example design), ma le faʻatulagaina o le simulator files.
2. Seti lau si'osi'omaga simulator ma so'o se fa'asologa fa'atusa.
3. Fa'aopoopo faletusi fa'ata'ita'iga.
4. Tamomoe lau simulator.

3.4.1. Fa'ata'ita'iga ma Fa'amaonia le Fuafuaga

Ona o le faaletonu, o le faatonu o le parameter e gaosia ai ni tusitusiga faʻapitoa simulator o loʻo i ai faʻatonuga e tuʻufaʻatasia, faʻamalamalamaina, ma faʻataʻitaʻi Intel FPGA IP faʻataʻitaʻiga ma faʻataʻitaʻiga faletusi files. E mafai ona e kopiina tulafono i lau faʻataʻitaʻiga testbench script, pe faʻasaʻo nei mea files e faʻaopoopo tulafono mo le tuʻufaʻatasia, faʻamalamalamaina, ma faʻataʻitaʻiina lau mamanu ma suʻega suʻega.

Laulau 10. Intel FPGA IP Core Simulation Scripts

Simulator

File Fa'asinomaga

ModelSim

_sim/mentor

QuestaSim

VCS

_sim/synopsys/vcs

VCS MX

_sim/synopsys/vcsmx

Xcelium

_sim/xcelium

Tusitusiga msim_setup.tcl (7)
vcs_setup.sh vcsmx_setup.sh synopsys_sim.setup xcelium_setup.sh

3.5. Fa'atasia IP Cores i Isi Meafaigaluega EDA
Ile filifiliga, fa'aaoga se isi meafaigaluega EDA lagolago e fa'apipi'i se mamanu e aofia ai le Intel FPGA IP cores. A e fa'atupuina le fa'asologa o le IP files mo le faʻaogaina ma meafaigaluega faʻapipiʻi EDA lona tolu, e mafai ona e fatuina se lisi o faʻasologa o vaega ma taimi. Ina ia mafai ona fa'atupuina, fa'aola le Fausia taimi ma tala fa'atatau o puna'oa mo mea faigaluega fa'aopoopo EDA lona tolu pe a fa'avasega lau fesuiaiga IP.
Ole lisi ole lisi ole vaega ole taimi ole fa'atatau ole feso'ota'iga ma le fausaga ole IP, ae le'o aofia ai fa'amatalaga e uiga ile fa'atinoga moni. O lenei fa'amatalaga e mafai ai e nisi o meafaigaluega fa'apipi'i vaega lona tolu e sili atu ona lelei lipoti o vaega ma taimi fa'atatau. E le gata i lea, e mafai e meafaigaluega faʻapipiʻi ona faʻaogaina faʻamatalaga taimi e ausia ai faʻataʻitaʻiga faʻatulagaina taimi ma faʻaleleia le lelei o taunuʻuga.
O le polokalama Intel Quartus Prime e gaosia ai le _syn.v netlist file i le Verilog HDL fa'atulagaina, tusa lava po'o le a le gaioiga file faatulagaga e te faamaotiina. Afai e te fa'aogaina le lisi o upegatafa'ilagi mo le tu'ufa'atasiga, e tatau ona e aofia ai le afifi autu o le IP file .v pe .vhd i lau poloketi Intel Quartus Prime.

(7) Afai e te leʻi setiina le filifiliga meafaigaluega a le EDA-lea e mafai ai ona e amata faʻataʻitaʻiga EDA vaega lona tolu mai le polokalama Intel Quartus Prime-faʻatautaia lenei tusitusiga i le ModelSim poʻo le QuestaSim simulator Tcl console (e le o le Intel Quartus Prime software. Tcl console) e aloese ai mai soʻo se mea sese.

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3.6. Tuufaatasia o le Fuafuaga Atoa
E mafai ona e fa'aogaina le fa'atonuga Amata Compilation i luga o le lisi Fa'agaioiga i le polokalama Intel Quartus Prime Pro Edition e tu'ufa'atasia ai lau mamanu.

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4. Fa'amatalaga Fa'atino

Ata 5.

F-Tile Serial Lite IV Intel FPGA IP e aofia ai MAC ma Ethernet PCS. O le MAC e fesoʻotaʻi ma PCS masani e ala i fesoʻotaʻiga MII.

E lagolagoina e le IP ni auala faʻaleleia e lua:
· PAM4– Tuuina atu le 1 i le 12 numera o laina mo filifiliga. O le IP e fa'aosoina i taimi uma ia laina PCS e lua mo laina ta'itasi ile faiga fa'aopoopo PAM4.
· NRZ– Tuuina atu le 1 i le 16 numera o laina mo filifiliga.

E lagolagoina e ta'iala ta'itasi ia fa'amaumauga e lua:
· Faiga fa'avae–Ose faiga fa'amama mama lea e lafo ai fa'amatalaga e aunoa ma le amataga-pepa, ta'amilosaga gaogao, ma le fa'ai'uga-o-pepa e fa'atele ai le bandwidth. O le IP e ave faʻamatalaga faʻamaonia muamua e avea ma amataga o se pa.

Fa'aliliuga Fa'amatalaga Fa'avae Autu tx_core_clkout tx_avs_ready

tx_avs_valid tx_avs_data rx_core_clkout rx_avs_ready

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_valid rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

ISO 9001:2015 Resitala

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Ata 6.

· Faiga atoa–O le fa'aliliuga lea o fa'amaumauga o fa'amaumauga. I lenei faiga, e tuʻuina atu e le IP se paʻu ma se faʻasologa o le taamilosaga i le amataga ma le faaiuga o se afifi e fai ma faʻamaʻi.

Fa'aliliuga Fa'amatalaga Fa'amatalaga atoa tx_core_clkout

tx_avs_ready tx_avs_valid tx_avs_startofpacket tx_avs_endofpacket
tx_avs_data rx_core_clkout rx_avs_ready rx_avs_valid rx_avs_startofpacket rx_avs_endofpacket

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

rx_avs_data

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9

Fa'amatalaga Fa'atatau · F-Tile Serial Lite IV Intel FPGA IP Overview i le itulau 6 · F-Tile Serial Lite IV Intel FPGA IP Design Example User Guide

4.1. TX Datapath
O le TX datapath e aofia ai vaega nei: · MAC adapter · Pulea upu faaofi poloka · CRC · MII encoder · PCS poloka · PMA poloka

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Ata 7. TX Datapath

Mai manatu fa'aoga

TX MAC

Avalon Streaming Interface

MAC Fetuuna'i

Pulea Upu Faaofi

CRC

MII Encoder

MII Interface Custom PCS
PCS ma PMA

TX Serial Interface i Isi FPGA Device

4.1.1. TX MAC Fetuunai
O le TX MAC adapter e pulea le tuʻuina atu o faʻamatalaga i le faʻaoga faʻaoga e faʻaaoga ai le Avalon® streaming interface. O lenei poloka e lagolagoina le tuʻuina atu o faʻamatalaga faʻamatalaga ma le pulea o le tafe.

Fa'aliliuina o Fa'amatalaga Fa'amatalaga Fa'atagata

I le Full mode, o le IP e maua ai le tx_is_usr_cmd faailo e mafai ona e faʻaogaina e amata ai faʻamatalaga faʻamatalaga faʻamatalaga e pei o le XOFF/XON transmission i le faʻaoga faʻaoga. E mafai ona e amataina le taamilosaga faʻamatalaga faʻamatalaga e faʻaogaina e le tagata e ala i le faʻaalia o lenei faailo ma faʻafeiloaʻi faʻamatalaga e faʻaaoga ai le tx_avs_data faʻatasi ai ma le faʻamaoniga o tx_avs_startofpacket ma tx_avs_valid faailoilo. Ona tu'u ai lea e le poloka le tx_avs_ready mo ta'amilosaga se lua.

Fa'aaliga:

O le fa'amatalaga fa'amatalaga fa'aoga e na'o le Full mode e maua.

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Ata 8.

Pulea o le tafe

O loʻo i ai tulaga e le o sauni le TX MAC e maua faʻamatalaga mai le faʻaogaina o le faʻaoga e pei o le taimi o le toe faʻaogaina o fesoʻotaʻiga poʻo le leai o se faʻamatalaga e maua mo le tuʻuina atu mai le faʻaoga faʻaoga. Ina ia aloese mai le leiloa o faʻamatalaga ona o nei tulaga, e faʻaaogaina e le IP le faailo tx_avs_ready e faʻatonutonu ai le tafe o faʻamatalaga mai le faʻaoga faʻaoga. O le IP e faʻaumatia le faailo pe a tulaʻi mai tulaga nei:
· A fa'ailoa mai le tx_avs_startofpacket, o le tx_avs_ready e fa'amuta mo le taamilosaga e tasi.
· A fa'ailoa mai le tx_avs_endofpacket, o le tx_avs_ready e fa'amuta mo le taamilosaga e tasi.
· A fa'apea mai so'o se CWs e fa'aluaina, tx_avs_ready e fa'amuta mo ta'amilosaga e lua.
· A o'o ina fa'aofiina fa'ailoga fa'aogaina RS-FEC i le fa'aoga masani a le PCS, e fa'amuta le tx_avs_ready mo taamilosaga e fa.
· E 17 ta'amilosaga uati autu uma a Ethernet i le fa'aogaina o le PAM4 fa'apea ma ta'amilosaga uma e 33 uati autu a Ethernet i le fa'aogaina o le NRZ. O le tx_avs_ready ua fa'amuta mo le taamilosaga uati e tasi.
· Pe a fa'aleaogaina e le fa'aoga manatu tx_avs_valid i le taimi e leai ni fa'amatalaga.

O fa'asologa o taimi o lo'o mulimuli mai eamples o le TX MAC adapter fa'aaoga tx_avs_ready mo le pulea o fa'amaumauga.

Pulea o le tafe ma le tx_avs_valid Deassertion ma START/END CWs Fa'atasi

tx_core_clkout

tx_avs_valid tx_avs_data

D1 D2 D3

Deasserts faailo aoga

O5 D6

tx_avs_ready tx_avs_startofpacket

Fa'ailoga fa'ailoga mo ta'amilosaga lua e fa'aofi END-STRT CW

tx_avs_endofpacket

usrif_data

D1 D2 D3

CW_data

DN END STRT D0 D1 D2 D3 GOSOA D4

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Ata 9.

Pulea o le tafe ma le Fa'aofiina o Fa'ailoga Fa'asaga
tx_core_clkout tx_avs_valid

tx_avs_data tx_avs_ready

DN-5 DN-4 DN-3 DN-2 DN-1

DN+1

01234

tx_avs_startofpacket tx_avs_endofpacket

usrif_data CW_data CRC_data MII_data

DN-1 DN DN DN DN DN DN DN+1 DN-1 DN DN DN DN DN DN+1 DN-1 DN DN DN DN DN DN DN+1 DN-1 DN DN DN DN DN DN+1

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

DN-1

DN+1

i_sl_tx_mii_c[7:0]

0x0

i_sl_tx_mii_am

01234

i_sl_tx_mii_am_pre3

01234

Ata 10.

Pulea o le tafe ma le START/END Paired CWs E Fa'atasi ma le Fa'aofiina o Fa'ailoga Fa'asaga

tx_core_clkout tx_avs_valid

tx_avs_data

DN-5 DN-4 DN-3 DN-2 DN-1

tx_avs_ready

012 345 6

tx_avs_startofpacket

tx_avs_endofpacket

usrif_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

CW_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

CRC_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

MII_data

DN-1 DN-1 DN-1 DN-1 DN-1 DN-1 END STRT D0

i_sl_tx_mii_valid

i_sl_tx_mii_d[63:0]

DN-1

FA'AI'U STRT D0

i_sl_tx_mii_c[7:0]

0x0

i_sl_tx_mii_am i_sl_tx_mii_am_pre3

01234

4.1.2. Faaofiina Upu Pule (CW).
O le F-Tile Serial Lite IV Intel FPGA IP e fausia ai CW e fa'avae i luga o fa'ailoga fa'aoga mai le fa'aoga fa'aoga. O le CWs o loʻo faʻaalia ai faʻamaʻi faʻapipiʻi, faʻamatalaga tulaga faʻasalalau poʻo faʻamatalaga tagata faʻaoga i le poloka PCS ma e maua mai i tulafono faʻatonutonu XGMII.
O le siata o lo'o i lalo o lo'o fa'aalia ai le fa'amatalaga o CWs lagolagoina:

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Laulau 11.
AMATA FA'AI'U FA'ASA'O

Fa'amatalaga o CWs Lagolago

Numera o Upu (1 upu

= 64 bits)

Ioe

EMPTY_CYC

Ioe

IDLE

Leai

FA'AMATALAGA

Ioe

I-faaili

Fa'amatalaga
Amataina o fa'amaumauga fa'amaumauga. Fa'ai'uga o le fa'ailoga fa'amaumauga. Pulea upu (CW) mo le RX alignment. Ta'amilosaga gaogao i se fa'aliliuga fa'amatalaga. IDLE (o ese mai le faaili). Totogi uta.

Laulau 12. CW Field Description
Field RSVD num_valid_bytes_eob
GALUEGA eop sop seop fa'aoga CRC32 usr

Fa'amatalaga
fanua faasao. E mafai ona faʻaaoga mo faʻaopoopoga i le lumanaʻi. Nonoa i le 0.
Numera o bytes aoga i le upu mulimuli (64-bit). Ole tau ole 3bit lea. · 3'b000: 8 paita · 3'b001: 1 paita · 3'b010: 2 paita · 3'b011: 3 paita · 3'b100: 4 paita · 3'b101: 5 paita · 3'b110: 6 paita · 3'b111: 7 paita
Numera o upu le aoga i le faaiuga o se pa.
Fa'ailoa mai le RX Avalon streaming interface e fa'ailoa ai se fa'ai'uga fa'ai'uga-o-packet.
Fa'ailoa mai le RX Avalon streaming interface e fa'ailoa ai se fa'ailoga amata-o-packet.
Fa'ailoa mai le RX Avalon streaming interface e fa'ailoa ai se amataga-o-packet ma se fa'ai'uga-o-pepa i le taamilosaga tutusa.
Siaki le RX alignment.
O le tau o le CRC fuafuaina.
Fa'ailoa mai o le 'upu fa'atonutonu (CW) o lo'o iai fa'amatalaga fa'auigaina e tagata fa'aoga.

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4.1.2.1. CW amata-o-pa

Ata 11. Fa'asologa o le CW amata-o-pa

AMATA

63:56

RSVD

55:48

RSVD

47:40

RSVD

fa'amaumauga

39:32 31:24

RSVD RSVD

23:16

sop usr align=0 seop

15:8

alavai

7:0

'hFB(AMATA)

pulea 7:0

Laulau 13.

I le Full mode, e mafai ona e fa'aofi le START CW e ala i le fa'ailoaina o le tx_avs_startofpacket faailo. A e fa'ailoa na'o le tx_avs_startofpacket fa'ailoga, ua seti le sop bit. A e fa'amauina uma le tx_avs_startofpacket ma tx_avs_endofpacket faailoilo, ua seti le seop bit.

AMATA LE CW Field Values
fanua sop/seop
usr (8)
fa'aogatonu

Taua

Faʻalagolago i le tx_is_usr_cmd faailo:

1: Pe a tx_is_usr_cmd = 1

0: Pe a tx_is_usr_cmd = 0

I le faiga fa'avae, e tu'uina atu e le MAC se START CW pe a mae'a le toe setiina. Afai e leai ni fa'amatalaga e maua, e fa'aauau pea ona lafo e le MAC EMPTY_CYC fa'atasi ma END ma START CWs se'ia e amata lafo fa'amaumauga.

4.1.2.2. Fa'ai'uga o le pa'u CW

Ata 12. Fa'ai'uga CW Fa'asologa

I'UGA

63:56

'hFD

55:48

CRC32[31:24]

47:40

CRC32[23:16]

faamatalaga 39:32 31:24

CRC32[15:8] CRC32[7:0]

23:16 eop=1 RSVD RSVD RSVD

RSVD

15:8

RSVD

GALUEGA

7:0

RSVD

num_valid_bytes_eob

pulea

7:0

(8) E na'o le tulaga atoa e lagolagoina.
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Laulau 14.

E fa'aofi e le MAC le END CW pe a fa'ailoa mai le tx_avs_endofpacket. O le END CW o lo'o i ai le numera o bytes aoga i le upu fa'amaumauga mulimuli ma fa'amatalaga CRC.

O le tau o le CRC o le 32-bit CRC i'uga mo fa'amaumauga i le va o le START CW ma le upu fa'amatalaga a'o le'i o'o i le END CW.

O le siata o lo'o i lalo o lo'o fa'aalia ai tau o fanua i le END CW.

Fa'ai'u CW Field Values
Field eop CRC32 num_valid_bytes_eob

Taua 1
CRC32 tau fa'atatau. Numera o paita aoga i le upu fa'amaumauga mulimuli.

4.1.2.3. Fa'asagaga Fa'atasi CW

Ata 13. Fa'asologa CW Fa'atasi

FA'ASA'O CW Fa'atasi ma le AMATA/I'U

64+8bits XGMII Feso'ota'iga

AMATA

63:56

RSVD

55:48

RSVD

47:40

RSVD

fa'amaumauga

39:32 31:24

RSVD RSVD

23:16 eop=0 sop=0 usr=0 align=1 seop=0

15:8

RSVD

7:0

'hFB

pulea 7:0

64+8bits XGMII Feso'ota'iga

I'UGA

63:56

'hFD

55:48

RSVD

47:40

RSVD

fa'amaumauga

39:32 31:24

RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

pulea 7:0

Ole ALIGN CW ole CW fa'atasi ma START/END po'o le END/START CWs. E mafai ona e fa'aofiina le ALIGN paid CW e ala i le fa'ailoaina o le tx_link_reinit fa'ailoga, seti le Fa'asologa o Vaitaimi fa'atau, po'o le amataina o se toe setiina. A fa'aofi le ALIGN paid CW, fa'atulaga le fanua fa'aoga i le 1 e amata ai le poloka fa'aogaina o le tali e siaki ai le fa'aogaina o fa'amaumauga i laina uma.

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Laulau 15.

FA'ASA'OGA CW Field Values
Fa'aoga fanua
eop sop usr seop

Taua 1 0 0 0 0

4.1.2.4. Ta'amilosaga gaogao CW

Ata 14. Fa'asologa CW ta'amilosaga gaogao

EMPTY_CYC Fa'atasi ma END/START

64+8bits XGMII Feso'ota'iga

I'UGA

63:56

'hFD

55:48

RSVD

47:40

RSVD

fa'amaumauga

39:32 31:24

RSVD RSVD

23:16 eop=0 RSVD RSVD RSVD

RSVD

15:8

RSVD

7:0

RSVD

pulea 7:0

64+8bits XGMII Feso'ota'iga

AMATA

63:56

RSVD

55:48

RSVD

47:40

RSVD

fa'amaumauga

39:32 31:24

RSVD RSVD

23:16

sop=0 usr=0 align=0 seop=0

15:8

RSVD

7:0

'hFB

pulea 7:0

Laulau 16.

A e fa'amalo le tx_avs_valid mo ta'amilosaga e lua i le taimi o le pa, fa'aofi e le MAC se EMPTY_CYC CW fa'atasi ma END/START CWs. E mafai ona e fa'aogaina lenei CW pe a leai ni fa'amatalaga e maua mo le fa'asalalauina mo sina taimi.

A e deassert tx_avs_valid mo le taamilosaga e tasi, o le IP deasserts tx_avs_valid mo faaluaina le vaitaimi o le tx_avs_valid deassertion e maua ai se pea END/START CWs.

EMPTY_CYC CW Fa'atauga Field
Fa'aoga fanua
eop

Taua 0 0

faaauau…

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Field sop usr seop

Taua 0 0 0

4.1.2.5. Fa'aletonu CW

Ata 15. Fa'ata'ita'i CW Fa'aoga

IDLE CW

63:56

'h07

55:48

'h07

47:40

'h07

fa'amaumauga

39:32 31:24

'h07 'h07

23:16

'h07

15:8

'h07

7:0

'h07

pulea 7:0

Faʻapipiʻi e le MAC le IDLE CW pe a leai se faʻasalalauga. I lenei vaitau, o le tx_avs_valid faailo e maualalo.
E mafai ona e fa'aogaina le IDLE CW pe a mae'a le fa'aliliuina o le fe'avea'i po'o le fa'asalalauina o lo'o i se tulaga fa'aletonu.

4.1.2.6. Upu Fa'amatalaga

O le upu fa'amaumauga o le uta lea o se afifi. Ole XGMII pu'upu'u pulea ua seti uma ile 0 ile fa'asologa o upu fa'amaumauga.

Ata 16. Fa'amaumauga Upu Fa'amatalaga

64+8 bits XGMII Feso'ota'iga

UPU FAAMATALAGA

63:56

fa'amatalaga tagata fa'aoga 7

55:48

fa'amatalaga tagata fa'aoga 6

47:40

fa'amatalaga tagata fa'aoga 5

fa'amaumauga

39:32 31:24

fa'amatalaga fa'aoga 4 fa'amatalaga fa'aoga 3

23:16

fa'amatalaga tagata fa'aoga 2

15:8

fa'amatalaga tagata fa'aoga 1

7:0

fa'amatalaga tagata fa'aoga 0

pulea 7:0

4.1.3. TX CRC
E mafai ona e faʻaogaina le poloka TX CRC e faʻaaoga ai le Enable CRC parameter i le IP Parameter Editor. O lo'o lagolagoina lenei fa'atusa i faiga fa'avae uma ma fa'aoga atoa.

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E fa'aopoopo e le MAC le tau o le CRC i le END CW e ala i le fa'ailoaina o le tx_avs_endofpacket fa'ailoga. I le BASIC mode, na'o le ALIGN CW fa'atasi ma le END CW o lo'o i ai se fanua CRC aoga.
O le poloka TX CRC e fesoʻotaʻi ma le TX Control Word Insertion ma le TX MII Encode poloka. O le poloka TX CRC e fa'atatauina le tau o le CRC mo fa'amatalaga 64-bit tau ta'amilosaga e amata mai i le START CW e o'o atu i le END CW.
E mafai ona e fa'ailoa le crc_error_inject fa'ailo e fa'aleaga ma le loto i ai fa'amatalaga i se ala fa'apitoa e fa'atupu ai fa'aletonu CRC.

4.1.4. TX MII Encoder

O le TX MII encoder e faʻaaogaina le faʻasalalauga mai le MAC i le TX PCS.

O le ata o loʻo i lalo o loʻo faʻaalia ai le faʻasologa o faʻamatalaga i luga o le 8-bit MII pasi ile PAM4 mode modulation. O le START ma le END CW e fa'aalia tasi i laina MII uma e lua.

Ata 17. PAM4 Modulation Mode MII Data Pattern

T'amilosaga 1

T'amilosaga 2

T'amilosaga 3

T'amilosaga 4

T'amilosaga 5

SOP_CW

FA'AMATALAGA_1

FA'AMATALAGA_9 FA'AMATALAGA_17

IDLE

DATA_DUMMY SOP_CW
DATA_DUMMY

FA'AMATALAGA_2 FA'AMATALAGA_3 FA'AMATALAGA_4

FA'AMATALAGA_10 FA'AMATALAGA_11 FA'AMATALAGA_12

FA'AMATALAGA_18 FA'AMATALAGA_19 FA'AMATALAGA_20

EOP_CW IDLE
EOP_CW

SOP_CW

FA'AMATALAGA_5 FA'AMATALAGA_13 FA'AMATALAGA_21

IDLE

DATA_DUMMY DATA_6 DATA_14 DATA_22 EOP_CW

SOP_CW DATA_DUMMY

FA'AMATALAGA_7 FA'AMATALAGA_8

FA'AMATALAGA_15 FA'AMATALAGA_16

FA'AMATALAGA_23 FA'AMATALAGA_24

IDLE EOP_CW

O le ata o loʻo i lalo o loʻo faʻaalia ai le faʻasologa o faʻamaumauga i luga o le 8-bit MII pasi ile NRZ mode modulation. O le START ma le END CW e aliali mai i laina MII uma.

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Ata 18. NRZ Modulation Mode MII Data Pattern

T'amilosaga 1

T'amilosaga 2

T'amilosaga 3

SOP_CW

FA'AMATALAGA_1

FA'AMATALAGA_9

SOP_CW

FA'AMATALAGA_2 FA'AMATALAGA_10

SOP_CW SOP_CW

FA'AMATALAGA_3 FA'AMATALAGA_4

FA'AMATALAGA_11 FA'AMATALAGA_12

SOP_CW

FA'AMATALAGA_5 FA'AMATALAGA_13

SOP_CW

FA'AMATALAGA_6 FA'AMATALAGA_14

SOP_CW

FA'AMATALAGA_7 FA'AMATALAGA_15

SOP_CW

FA'AMATALAGA_8 FA'AMATALAGA_16

T'amilosaga 4 FA'AMATALAGA_17 FA'AMATALAGA_18 FA'AMATALAGA_19 FA'AMATALAGA_20 FA'AMATALAGA_21 FA'AMATALAGA_22 FA'AMATALAGA_23 FA'AMATALAGA_24

T'amilosaga 5 EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW EOP_CW

4.1.5. TX PCS ma PMA
O le F-Tile Serial Lite IV Intel FPGA IP e faʻapipiʻi le F-tile transceiver i le Ethernet PCS mode.

4.2. RX Datapath
O le RX datapath e aofia ai vaega nei: · PMA poloka · PCS poloka · MII decoder · CRC · Deskew poloka · Pulea Upu aveese poloka

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Ata 19. RX Datapath

I le fa'aoga manatu Avalon Streaming Interface
RX MAC
Pulea le Aveesea o Upu
Deskew

CRC

MII Decoder

MII Interface Custom PCS
PCS ma PMA

RX Serial Interface Mai Isi FPGA Device
4.2.1. RX PCS ma PMA
O le F-Tile Serial Lite IV Intel FPGA IP fa'apipi'i le F-tile transceiver i le Ethernet PCS mode.
4.2.2. RX MII Decoder
O le poloka lea e fa'ailoa ai pe o iai fa'amatalaga o lo'o o'o mai o lo'o iai fa'ailoga fa'atonu ma fa'aoga fa'aoga. O le RX MII decoder e maua ai faʻamatalaga i le tulaga o le 1-bit valid, 1-bit marker indicator, 1bit control indicator, ma le 64-bit data i le laina.
4.2.3. RX CRC
E mafai ona e faʻaogaina le poloka TX CRC e faʻaaoga ai le Enable CRC parameter i le IP Parameter Editor. O lo'o lagolagoina lenei fa'atusa i faiga fa'avae uma ma fa'aoga atoa. O le poloka RX CRC e fesoʻotaʻi ma poloka RX Control Word Removal ma RX MII Decoder poloka. O le IP e faʻamaonia le rx_crc_error faʻailoga pe a tupu se mea sese CRC.

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O le IP e fa'amalo le rx_crc_error i so'o se oso fou. O se fa'atinoga i le fa'aoga fa'aoga mo le fa'aogaina o mea sese fa'aoga.
4.2.4. RX Deskew
O le poloka kesi RX e iloa ai faʻailoga faʻaoga mo laina taʻitasi ma toe faʻaogaina faʻamaumauga aʻo leʻi tuʻuina atu i le poloka aveese RX CW.
E mafai ona e filifili e tu'u le IP core e fa'aoga otometi fa'amaumauga mo laina ta'itasi pe a tupu se mea sese e ala i le setiina o le Enable Auto Alignment parameter i le IP parameter Editor. Afai e te faʻamalo le faʻaogaina otometi, o le IP autu e faʻamaonia le rx_error faailo e faʻaalia ai le faʻaogaina o mea sese. E tatau ona e fa'ailoa le rx_link_reinit e amata ai le fa'agasologa o le laina laina pe a tupu se fa'aletonu o le laina laina.
O le RX deskew e iloa ai fa'ailoga fa'aoga e fa'atatau i se masini a le setete. O le ata o loʻo i lalo o loʻo faʻaalia ai setete o loʻo i totonu ole poloka kesi RX.

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Ata 20.

RX Deskew Lane Alignment State Machine with Auto Alignment Enabled Flow Chart
Amata

IDLE

Toe seti = 1 ioe leai

PCS uma

leai

auala ua saunia?

ioe

FAATALI

Fa'ailoga sync uma Nu
iloa?
ioe
FAIGA

leai
ioe Taimi?

ioe
Ua leiloa le fa'aogaina?
leai se gataaga

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Ata 21.

RX Deskew Lane Alignment State Machine ma le Auto Alignment Disabled Flow Chart
Amata

IDLE

Toe seti = 1 ioe leai

PCS uma

leai

auala ua saunia?

ioe

ioe
rx_link_reinit =1
leai SESE

leai ioe Taimi?

FAATALI
leai Fa'ailoga sync uma
iloa?
ioe FA'ATU

ioe
Ua leiloa le fa'aogaina?
leai
Fa'ai'u
1. O le fa'agasologa e amata ile tulaga IDLE. O le poloka e alu i le WAIT state pe a sauni uma PCS lanes ma le rx_link_reinit ua fa'amalo.
2. I le WAIT state, e siaki e le poloka fa'ailoga uma ua iloa o lo'o fa'amauina i totonu o le taamilosaga tutusa. Afai e moni lenei tulaga, o le poloka e alu i le tulaga ALIGNED.
3. A o'o le poloka ile tulaga ALIGNED, e ta'u mai ai ua fa'aoga auala. I lenei setete, o loʻo faʻaauau pea ona mataʻituina e le poloka le faʻaogaina o laina ma siaki pe o iai faʻailoga uma i totonu o le taamilosaga tutusa. Afai e le itiiti ifo ma le tasi le maka e le o iai i le taamilosaga e tasi ma ua setiina le Enable Auto Alignment parameter, o le poloka e alu i le

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IDLE setete e toe amataina le faʻaogaina o le faʻagasologa. Afai e le o setiina le Enable Auto Alignment ma e le itiiti ifo ma le tasi le maka e le o iai i le taamilosaga e tasi, o le poloka e alu i le ERROR setete ma faʻatali mo le faʻaoga faʻaoga e faʻamaonia ai le rx_link_reinit faailo e amata ai le faʻaogaina o laina.

Ata 22. Toe Fa'atulagaina o Lane ma Enable Auto Alignment Enabled rx_core_clk

rx_link_up

rx_link_reinit

ma_uma_faailoga

Setete o Deskew

ALGNED

IDLE

FAATALI

ALGNED

AUTO_ALIGN = 1

Ata 23. Toe Fa'atulagaina o Lane ma Fa'aagaoioi le Fa'aoga Fa'atonu Fa'aletonu rx_core_clk

rx_link_up

rx_link_reinit

ma_uma_faailoga

Setete o Deskew

ALGNED

SESE

IDLE

FAATALI

ALGNED

AUTO_ALIGN = 0
4.2.5. RX CW Aveese
O lenei poloka e faʻavasegaina le CWs ma tuʻuina atu faʻamatalaga i le faʻaoga faʻaoga e faʻaaoga ai le Avalon streaming interface pe a maeʻa le aveeseina o CWs.
A leai ni fa'amatalaga fa'amaonia o lo'o maua, o le RX CW e fa'amalo poloka e fa'aleaga le rx_avs_valid fa'ailoga.
I le FULL mode, pe a faʻapipiʻi le tagata faʻaoga, o lenei poloka e faʻamaonia le rx_is_usr_cmd faʻailoga ma o faʻamatalaga i le taamilosaga muamua o le uati e faʻaaogaina e avea ma faʻamatalaga faʻamatalaga poʻo se faʻatonuga.
A fa'apea rx_avs_ready deasserts ma rx_avs_valid asserts, o le RX CW removal block e fa'atupuina ai se tulaga sese i le tagata fa'aoga.
O fa'ailo fa'asalalau Avalon e feso'ota'i ma lenei poloka e pei ona ta'ua i lalo: · rx_avs_startofpacket · rx_avs_endofpacket · rx_avs_channel · rx_avs_empty · rx_avs_data

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· rx_avs_valid
· rx_num_valid_bytes_eob
· rx_is_usr_cmd (na'o avanoa i le Full mode)
4.3. F-Tile Serial Lite IV Intel FPGA IP Clock Architecture
O le F-Tile Serial Lite IV Intel FPGA IP e fa fa'aoga uati e gaosia ai uati i poloka eseese: · Transceiver reference Clock (xcvr_ref_clk)–Input Clock from external clock
tupe meataalo po o oscillators e gaosia uati mo TX MAC, RX MAC, ma TX ma RX poloka PCS masani. Va'ai i Parameters mo le fa'aogaina o alaleo. · Uati autu TX (tx_core_clk)–O lenei uati e maua mai le transceiver PLL o loʻo faʻaaogaina mo TX MAC. O lenei uati o se uati fo'i mai le F-tile transceiver e fa'afeso'ota'i i le TX user logic. · Uati autu RX (rx_core_clk)–O lenei uati e maua mai le transceiver PLL o loʻo faʻaaogaina mo le RX deskew FIFO ma le RX MAC. O le uati fo'i lea o le uati fa'aola mai le F-tile transceiver e fa'afeso'ota'i i le RX user logic. · Uati mo le toe fetuutuunaiga o feso'ota'iga feso'ota'iga (reconfig_clk) – uati fa'aulu mai le uati i fafo po'o oscillators e gaosia ai uati mo le F-tile transceiver reconfiguration interface i TX ma RX datapaths. Ole taimi ole uati ole 100 ile 162MHz.
O le ata poloka o lo'o i lalo o lo'o fa'aalia ai F-Tile Serial Lite IV Intel FPGA IP clock domains ma feso'ota'iga i totonu ole IP.

F-Tile Serial Lite IV Intel® FPGA IP User Guide 36

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Ata 24.

F-Tile Serial Lite IV Intel FPGA IP Clock Architecture

Oscillator

FPGA1
F-Tile Serial Lite IV Intel FPGA IP Transceiver Reconfiguration Interface Clock
(reconfig_clk)

tx_core_clkout (fesoʻotaʻi i manatu faʻaoga)

tx_core_clk= clk_pll_div64[mid_ch]

FPGA2

F-Tile Serial Lite IV Intel FPGA IP

Transceiver Reconfiguration Interface Uati

(reconfig_clk)

Oscillator

rx_core_clk= clk_pll_div64[mid_ch]

rx_core_clkout (fesoʻotaʻi i manatu faʻaoga)

clk_pll_div64[mid_ch] clk_pll_div64[n-1:0]

Avalon Streaming Interface TX Data
TX MAC

serial_link[n-1:0]

Deskew

FIFO

Avalon Streaming Interface RX Data RX MAC

Avalon Streaming Interface RX Data
RX MAC

Deskew FIFO

rx_core_clkout (fesoʻotaʻi i manatu faʻaoga)

rx_core_clk= clk_pll_div64[mid_ch]

PCS fa'apitoa

serial_link[n-1:0]

TX MAC

Avalon Streaming Interface TX Data

tx_core_clk= clk_pll_div64[mid_ch]

tx_core_clkout (fesoʻotaʻi i manatu faʻaoga)

Transceiver Ref Clock (xcvr_ref_clk)
Transceiver Ref Clock (xcvr_ref_clk)

Oscillator*

Tala'aga

FPGA masini
TX autu uati vaega
RX autu uati vaega
Transceiver reference clock domain masini fafo Fa'ailoga Fa'amatalaga

4.4. Toe Seti ma So'oga Initialization
O le MAC, F-tile Hard IP, ma poloka reconfiguration e eseese faʻailoga faʻailoga: · TX ma RX MAC poloka faʻaoga tx_core_rst_n ma rx_core_rst_n reset signals. · tx_pcs_fec_phy_reset_n ma rx_pcs_fec_phy_reset_n toe setiina faailoilo taavale
le pule toe setiina vaivai e toe seti le F-tile Hard IP. · Toe fa'aogaina poloka e fa'aoga ai le fa'ailoga toe fa'afo'i le reconfig_reset.

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Ata 25. Toe Seti le Fa'ata'ita'iga
Avalon Streaming Interface TX Data
MAC
Avalon Streaming SYNC Interface RX Data

FPGA F-tile Serial Lite IV Intel FPGA IP

tx_mii rx_mii
phy_ehip_sauni phy_rx_pcs_sauni

F-tile malo IP

TX Fa'amatalaga Fa'asologa RX Fa'amatalaga Fa'asologa

tx_core_rstn rx_core_rstn tx_pcs_fec_phy_reset_n rx_pcs_fec_phy_reset_n reconfig_reset

Toe seti le Fa'atonu
Fa'amatalaga Fa'atatau · Toe Seti Ta'iala ile itulau 51 · F-Tile Serial Lite IV Intel FPGA IP Design Example User Guide
4.4.1. TX Toe Fa'atonu ma Fa'asologa Fa'asologa
O le faasologa toe setiina o le TX mo F-Tile Serial Lite IV Intel FPGA IP e faapea: 1. Fa'ailoa tx_pcs_fec_phy_reset_n, tx_core_rst_n, ma reconfig_reset
i le taimi lava e tasi e toe setiina ai le F-tile hard IP, MAC, ma le toe fetuutuunaiga poloka. Fa'asa'oloto le tx_pcs_fec_phy_reset_n ma toe fa'atulagaina pe a uma ona fa'atali mo le tx_reset_ack e fa'amautinoa ai o lo'o fa'atulaga lelei poloka. 2. O le IP ona fa'amaonia lea o le phy_tx_lanes_stable, tx_pll_locked, ma le phy_ehip_ready fa'ailoga pe a uma ona tu'uina atu le tx_pcs_fec_phy_reset_n reset, e ta'u mai ai le TX PHY ua sauni mo le fa'asalalauga. 3. O le tx_core_rst_n faailo e te'a pe a uma le phy_ehip_ready faailo e alu maualuga. 4. O le IP e amata fa'asalalau mata'itusi IDLE i luga o le MII interface pe a uma le MAC i le toe setiina. E leai se mana'oga mo le TX laina laina ma skewing aua o laina uma e fa'aoga tutusa le uati. 5. A'o fa'asalalau mata'itusi IDLE, fa'ailoa mai e le MAC le fa'ailoga tx_link_up. 6. Ona amata lea e le MAC ona tu'uina atu le ALI'I fa'atasi ma le START/END po'o le END/START CW i se vaitaimi fa'atulagaina e amata ai le fa'agasologa o le laina laina a le tagata fa'afeso'ota'i.

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Ata 26.

TX Toe Fa'atonu ma Fa'amatalaga Taimi Fa'amatalaga
reconfig_sl_clk

reconfig_clk

tx_core_rst_n

tx_pcs_fec_phy_reset_n 1

toeconfig_reset

toeconfig_sl_reset

tx_reset_ack

tx_pll _loka

phy_tx_lanes_stable

phy_ehip_ready

tx_li nk_up

7
5 6 8

4.4.2. RX Toe Seti ma Fa'asologa Fa'asologa
O le RX reset sequence mo F-Tile Serial Lite IV Intel FPGA IP e fa'apea:
1. Fa'ailoa rx_pcs_fec_phy_reset_n, rx_core_rst_n, ma reconfig_reset i le taimi lava e tasi e toe setiina ai le F-tile malo IP, MAC, ma reconfiguration poloka. Faʻasaʻo le rx_pcs_fec_phy_reset_n ma toe faʻatulagaina toe faʻatulagaina pe a uma ona faʻatali mo le rx_reset_ack e faʻamautinoa ai ua toe setiina poloka.
2. Ona fa'ailoa mai lea e le IP le fa'ailoga phy_rx_pcs_ready pe a uma ona tu'uina atu le toe setiina o PCS masani, e ta'u mai ai ua sauni le RX PHY mo le fa'asalalauga.
3. O le rx_core_rst_n faailo deasserts pe a uma le phy_rx_pcs_ready faailo alu maualuga.
4. O le IP e amata le fa'aogaina o le laina pe a uma ona tu'uina atu le RX MAC reset ma i luga o le mauaina o le ALIGN fa'atasi ma le START/END po'o le END/START CW.
5. O le poloka kesi RX e fa'ailoa mai ai le fa'ailoga rx_link_up pe a mae'a le fa'aogaina o auala uma.
6. O le IP ona fa'amaonia lea o le rx_link_up fa'ailoga i le fa'aoga fa'aoga e fa'ailoa mai ai ua sauni le feso'ota'iga RX e amata le mauaina o fa'amatalaga.

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Ata 27. RX Toe Seti ma Fa'amataina Taimi Ata
reconfig_sl_clk

reconfig_clk

rx_core_rst_n

rx_pcs_fec_phy_reset_n 1

toeconfig_reset

toeconfig_sl_reset

rx_reset_ack

rx_cdr_loka

rx_block_lock

rx_pcs_sauni

rx_link_up

3 3 3 2

4 5 5

6 7

4.5. So'oga Fua Faatatau ma Bandwidth Fa'atatau Lelei

O le F-Tile Serial Lite IV Intel FPGA IP fa'asologa o le bandwidth e fa'atatau i lalo:

Fa'aoga le lautele = raw_rate * 64/66 * (burst_size – burst_size_ovhd)/burst_size * [align_marker_period / (align_marker_period + align_marker_width)] * [(srl4_align_period – 2) / srl4_align_period]

Fuafuaga 17. Fa'amatalaga Fuafuaga Lelei o Bandwidth

Fesuia'i

Fa'amatalaga

raw_rate burst_size

O le fua laititi lea e maua e le fa'asologa fa'asologa. raw_rate = SERDES lautele * transceiver taimi uati Example: fua_mata = 64 * 402.812500 Gbps = 25.78 Gbps
Taua o le tele o le pa. Ina ia fa'atatau le fa'aogaina o le bandwidth, fa'aaoga le tau o le lapopo'a masani. Mo fua maualuga, fa'aaoga le tau maualuga o le pa'u.

burst_size_ovhd

O le tau fa'asili i luga ole lapopoa.
I le tulaga atoa, o le burst_size_ovhd value o lo'o fa'asino ile START ma le END CWs fa'atasi.
I le tulaga fa'avae, e leai se burst_size_ovhd ona e leai se START ma END CW fa'atasi.

align_marker_period

Le tau o le vaitaimi o lo'o fa'aofi ai se fa'ailoga fa'aoga. O le tau o le 81920 taamilosaga uati mo le tuufaatasia ma le 1280 mo faʻataʻitaʻiga vave. O lenei tau e maua mai le PCS hard logic.

align_marker_width srl4_align_period

Ole aofa'i o ta'amilosaga o le uati e fa'amaualuga ai se fa'ailoga fa'aoga talafeagai.
Ole numera ole taamilosaga ole uati ile va o fa'ailoga fa'aoga lua. E mafai ona e setiina lenei tau i le faʻaogaina o le Parameter Period Parameter i le IP Parameter Editor.

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Ole fa'atatau ole fua ole feso'ota'iga o lo'o i lalo: Fuafuaga lelei = fa'aogaina o le bandwidth * raw_rate E mafai ona e maua le maualuga ole fa'aogaina ole uati ole fa'atatau ile fa'atusa lea. Ole fa'atatau ole taimi ole uati ole tagata fa'aoga e fa'aauau pea le fa'asalalauina o fa'amaumauga ma e leai se fa'ata'amilosaga IDLE e tupu ile fa'atatau ole tagata. E taua lenei fua faatatau pe a mamanuina le fa'aoga manatu FIFO e aloese ai mai le lolofi mai FIFO. Ole maualuga ole taimi ole uati ole tagata fa'aoga = fua faatatau aoga / 64

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5. Parakalafa

Laulau 18. F-Tile Serial Lite IV Intel FPGA IP Parameter Fa'amatalaga

Parameter

Taua

Fa'atonu

Fa'amatalaga

Filifiliga Fuafuaga Lautele

PMA fa'aogaina ituaiga

· PAM4 · NRZ

PAM4

Filifili le faiga fa'alelei PCS.

Ituaiga PMA

· FHT · FGT

FGT

Filifilia le ituaiga transceiver.

PMA tau fa'amaumauga

· Mo le PAM4 faiga:
— FGT transceiver ituaiga: 20 Gbps 58 Gbps
— FHT transceiver ituaiga: 56.1 Gbps, 58 Gbps, 116 Gbps
· Mo le NRZ mode:
— FGT transceiver ituaiga: 10 Gbps 28.05 Gbps
- FHT transceiver ituaiga: 28.05 Gbps, 58 Gbps

56.1 (FGT/FHT PAM4)
28.05 Gbps (FGT/FHT NRZ)

Fa'ama'oti le fua faatatau lelei o fa'amaumauga i le gaosiga o le transceiver fa'apipi'i fa'asalalau ma isi fa'aulu. O le tau e fa'atatau e le IP e ala ile fa'ata'amilosaga ile 1 tesimale nofoaga ile Gbps unit.

faiga PMA

· Fa'atosina · Tx · Rx

Duplex

Mo FHT ituaiga transceiver, o le itu lagolago e na'o le lua. Mo FGT transceiver ituaiga, o le itu lagolago o le Duplex, Tx, ma Rx.

Numera ole PMA

· Mo le PAM4 faiga:

auala

— 1 i le 12

· Mo le NRZ mode:

— 1 i le 16

Filifili le numera o auala. Mo le mamanu faigofie, o le numera lagolago o laina ole 1.

Ole taimi ole uati ole fa'asino ole PLL

· Mo FHT transceiver ituaiga: 156.25 MHz
· Mo FGT transceiver ituaiga: 27.5 MHz 379.84375 MHz, e faalagolago i le fua faatatau o faamatalaga transceiver filifilia.

· Mo FHT transceiver ituaiga: 156.25 MHz
· Mo FGT transceiver ituaiga: 165 MHz

Fa'ama'oti le fa'asinoga o le uati fa'avevesi o le transceiver.

Faiga PLL

—

uati faasinomaga

taimi

170 MHz

Na'o avanoa mo le ituaiga FHT transceiver. Fa'amaoti le uati fa'asinoga PLL System ma o le a fa'aogaina e fai ma fa'aoga o F-Tile Reference ma System PLL Clock Intel FPGA IP e fa'atupuina ai le System PLL Clock.

Faiga PLL masani
Vaitaimi Fa'atonu

— 128 65536

Fa'aagaoi le RS-FEC

Fa'amalo

876.5625 MHz 128 Fa'aaga

Fa'ailoa mai le fa'asologa ole uati ole System PLL.
Fa'ailoa mai le vaitaimi o fa'ailoga fa'aoga. Ole tau e tatau ona x2. Ia ki ina ia mafai ai le vaega RS-FEC.
faaauau…

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Parameter

Taua

Fa'atonu

Fa'amatalaga

Fa'agata

Mo le PAM4 PCS fa'aogaina le fa'aogaina, RS-FEC e fa'aaga pea.

Fa'aoga Fa'aoga

Faiga fa'afefe

· TOTONU · FAʻAAVAE

tumu

Filifili le faʻasalalauga faʻamatalaga mo le IP.

Atoatoa: O lenei faiga e auina atu ai se taamilosaga amata-o-pepa ma fa'ai'uga-o-pepa i totonu o se faavaa.

Fa'avae: Ose faiga fa'amama mama lea e lafo ai fa'amatalaga e aunoa ma se amataga-o-pepa, gaogao, ma fa'ai'uga-o-pepa e fa'ateleina ai le bandwidth.

Fa'aaga le CRC

Faʻaleleia le avanoa

Fa'agata

Ki'i ina ia mafai ai ona su'esu'e ma faasa'oga sese CRC.

Fa'agaoioi le fa'aoga-ta'avale

Faʻaleleia le avanoa

Fa'agata

Ki'i ina ia mafai ai le fa'aoga otometi le fa'aogaina o le ala.

Fa'aagaoioi le debug endpoint

Faʻaleleia le avanoa

Fa'agata

A ON, o le F-Tile Serial Lite IV Intel FPGA IP e aofia ai se Debug Endpoint faʻapipiʻi e fesoʻotaʻi i totonu i le Avalon faʻafanua faʻapipiʻi manatua. E mafai e le IP ona faia nisi o suʻega ma faʻaogaina galuega e ala i le JTAG fa'aaoga le System Console. O le tau masani e Pe.

Fa'atasiga Simplex (E na'o le avanoa lenei fa'atulagaina pe a e filifilia le FGT lua simplex design.)

O le RSFEC ua mafai i luga o le isi Serial Lite IV Simplex IP na tu'u i le ala lava lea e tasi FGT(s)

Faʻaleleia le avanoa

Fa'agata

Liliu le filifiliga pe afai e te manaʻomia se faʻafefiloi o le faʻaogaina ma le RS-FEC ua mafai ma faʻaletonu mo le F-Tile Serial Lite IV Intel FPGA IP i se mamanu faigofie lua mo le NRZ transceiver mode, lea e tuʻu uma TX ma RX i luga ole FGT tutusa ala(s).

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6. F-Tile Serial Lite IV Intel FPGA IP Interface Signals

6.1. Faailoga Uati

Laulau 19. Fa'ailoga Uati

Igoa

Itulau Lautele

Fa'amatalaga

tx_core_clkout

Output TX core clock mo le TX custom PCS interface, TX MAC and user logics in

le TX faʻamaumauga.

O lenei uati e gaosia mai le poloka PCS masani.

rx_core_clkout

O le uati autu o le RX mo le RX masani PCS interface, RX deskew FIFO, RX MAC

ma fa'aoga fa'aoga i le RX datapath.

O lenei uati e gaosia mai le poloka PCS masani.

xcvr_ref_clk
reconfig_clk reconfig_sl_clk

Input Transceiver reference Clock.

A seti le ituaiga transceiver i le FGT, fa'afeso'ota'i le uati lea i le fa'ailo o le gaosiga (out_refclk_fgt_0) o le F-Tile Reference and System PLL Clock Intel FPGA IP. A seti le ituaiga transceiver i le FHT, faʻafesoʻotaʻi

lenei uati i le faailo o le gaosiga (out_fht_cmmpll_clk_0) o le F-Tile Reference and System PLL Clocks Intel FPGA IP.

Va'ai i Parameters mo le fa'aogaina o alaleo.

Ulufale Fa'aofi uati mo le fetuutuunaiga toe fetuutuunaiga.

Ole taimi ole uati ole 100 ile 162MHz.

Fa'afeso'ota'i le fa'ailo o le uati fa'aoga i le uati i fafo po'o oscillators.

Ulufale Fa'aofi uati mo le fetuutuunaiga toe fetuutuunaiga.

Ole taimi ole uati ole 100 ile 162MHz.

Fa'afeso'ota'i le fa'ailo o le uati fa'aoga i le uati i fafo po'o oscillators.

out_systempll_clk_ 1

Ulufale

Uati PLL faiga.
Fa'afeso'ota'i le uati lea i le fa'ailo o le gaosiga (out_systempll_clk_0) o le F-Tile Reference and System PLL Clock Intel FPGA IP.

Fa'amatalaga Fa'atatau ile itulau 42

6.2. Toe Seti Faailoga

Laulau 20. Toe Seti Fa'ailoga

Igoa

Itulau Lautele

tx_core_rst_n

Ulufale

Uati Domain Asynchronous

rx_core_rst_n

Ulufale

Asynchronous

tx_pcs_fec_phy_reset_n 1

Ulufale

Asynchronous

Fa'amatalaga

Fa'ailoga toe fa'aleleia-maualalo. Toe setiina le F-Tile Serial Lite IV TX MAC.

Fa'ailo toe setiina-maualalo. Toe setiina le F-Tile Serial Lite IV RX MAC.

Fa'ailoga toe fa'aleleia-maualalo.

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Igoa

Laufanua Uati Fa'asinoala Lautele

Fa'amatalaga

Toe setiina le F-Tile Serial Lite IV TX custom PCS.

rx_pcs_fec_phy_reset_n 1

Ulufale

Asynchronous

Fa'ailo toe setiina-maualalo. Toe setiina le F-Tile Serial Lite IV RX custom PCS.

toeconfig_reset

Ulufale

reconfig_clk Active-maualuga toe seti faailoilo.

Toe setiina le poloka o le fetuutuunaiga o le Avalon manatua-faafanua.

toeconfig_sl_reset

Ulufale reconfig_sl_clk Fa'ailoga toe setiina maualuga-maualuga.

Toe setiina le poloka o le fetuutuunaiga o le Avalon manatua-faafanua.

6.3. Fa'ailoga MAC

Laulau 21.

TX MAC faailoilo
I lenei laulau, o le N o lo'o fa'atusalia ai le aofa'i o laina o lo'o fa'atulaga ile fa'atonu o le IP.

Igoa

Lautele

Ituaiga Uati Domain

Fa'amatalaga

tx_avs_ready

Fa'ailo tx_core_clkout Avalon tafe mai.

Pe a faʻamaonia, faʻaalia o le TX MAC ua sauni e talia faʻamatalaga.

tx_avs_data

· (64*N)*2 (faiga PAM4)
· 64*N (faiga NRZ)

Ulufale

tx_core_clkout Avalon fa'amalo faailoilo. TX faʻamatalaga.

tx_avs_channel

Ulufale tx_core_clkout Avalon fa'amalo fa'ailo.

Le numera o le alalaupapa mo fa'amatalaga o lo'o fa'aliliuina i le ta'amilosaga o lo'o iai nei.

E le o maua lenei fa'ailo ile faiga fa'avae.

tx_avs_valid

Ulufale tx_core_clkout Avalon fa'amalo fa'ailo.

Pe a faʻamaonia, faʻaalia le faʻailoga faʻamatalaga TX e aoga.

tx_avs_startofpacket

Ulufale tx_core_clkout Avalon fa'amalo fa'ailo.

Pe a faʻamaonia, faʻaalia le amataga o se pusa faʻamatalaga TX.

Fa'ailoa mo na'o se taamilosaga uati e tasi mo taga ta'itasi.

E le o maua lenei fa'ailo ile faiga fa'avae.

tx_avs_endofpacket

Ulufale tx_core_clkout Avalon fa'amalo fa'ailo.

Pe a faʻamaonia, faʻaalia le iʻuga o se pusa faʻamatalaga TX.

Fa'ailoa mo na'o se taamilosaga uati e tasi mo taga ta'itasi.

E le o maua lenei fa'ailo ile faiga fa'avae.

tx_avs_empty

Ulufale tx_core_clkout Avalon fa'amalo fa'ailo.

Fa'ailoa le numera o upu le aoga i le fa'ai'uga o fa'amaumauga TX.

E le o maua lenei fa'ailo ile faiga fa'avae.

tx_num_valid_bytes_eob

Ulufale

tx_core_clkout

Fa'ailoa le aofa'i o paita aoga i le upu mulimuli o le pa mulimuli. E le o maua lenei fa'ailo ile faiga fa'avae.
faaauau…

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Igoa tx_is_usr_cmd
tx_link_up tx_link_reinit
crc_error_inject tx_error

Lautele 1
1 1
N 5

Ituaiga Uati Domain

Fa'amatalaga

Ulufale

tx_core_clkout

Pe a fa'ailoa mai, o le fa'ailoga lea e amatalia ai se fa'amatalaga fa'amatalaga e fa'aogaina e le tagata.
Fa'ailoa lenei fa'ailoga i le taamilosaga o le uati tutusa e pei o le tx_startofpacket fa'amatalaga.
E le o maua lenei fa'ailo ile faiga fa'avae.

Output tx_core_clkout A fa'ailoa mai, e fa'ailoa mai ai le feso'ota'iga o fa'amatalaga TX ua sauni mo le fa'asalalauina o fa'amatalaga.

Tuuina atu

tx_core_clkout

A fa'ailoa mai, o le fa'ailoga lea e amata ai le toe fa'aogaina o auala.
Fa'ailoa le fa'ailoga lea mo le taamilosaga o le uati e tasi e fa'aoso ai le MAC e lafo ALIGN CW.

Ulufale

tx_core_clkout A fa'ailoa mai, e tu'i e le MAC se mea sese CRC32 i laina filifilia.

Output tx_core_clkout Le fa'aaogaina.

O lo'o fa'aalia e le ata o lo'o ta'ua i lalo se example o TX fa'asalalauga fa'amatalaga o 10 upu mai le fa'aoga fa'aoga i luga ole 10 TX laina laina.

Ata 28.

TX Fa'amatalaga Fa'aliliuga Taimi Fa'asologa
tx_core_clkout

tx_avs_valid

tx_avs_ready

tx_avs_startofpackets

tx_avs_endofpackets

tx_avs_data

0,1..,19 10,11…19 …… N-10..

0,1,2,…,9

… N-10..

Lane 0

…………

STRT 0 10

N-10 FA'AI'U STRT 0

Lane 1

…………

STRT 1 11

N-9 FA'AI'U STRT 1

N-10 FA'AI'U FA'AVAE N-9 FA'AI'U FA'AVAE

Lane 9

…………

STRT 9 19

N-1 FA'AI'U STRT 9

N-1 FA'AI'U FA'AVAE

Laulau 22.

Faailoga RX MAC
I lenei laulau, o le N o lo'o fa'atusalia ai le aofa'i o laina o lo'o fa'atulaga ile fa'atonu o le IP.

Igoa

Lautele

Ituaiga Uati Domain

Fa'amatalaga

rx_avs_sauni

Fa'aulu le rx_core_clkout Avalon fa'amalo faailoilo.

A faʻamaonia, faʻaalia ua sauni le tagata faʻaoga e talia faʻamatalaga.

rx_avs_data

(64*N)*2 (faiga PAM4)
64*N (faiga NRZ)

Tuuina atu

rx_core_clkout Avalon fa'amalo faailoilo. RX faʻamatalaga.

rx_avs_channel

Fa'ailo rx_core_clkout Avalon tafe mai.

Ole numera ole auala mo fa'amaumauga

maua i le taamilosaga o lo'o iai nei.

E le o maua lenei fa'ailo ile faiga fa'avae.

rx_avs_valid

Fa'ailo rx_core_clkout Avalon tafe mai.

faaauau…

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Igoa

Lautele

Ituaiga Uati Domain

Fa'amatalaga

Pe a faʻamaonia, faʻaalia le faʻailoga faʻamatalaga RX e aoga.

rx_avs_startofpacket

Fa'ailo rx_core_clkout Avalon tafe mai.

A faʻamaonia, faʻaalia le amataga o se pusa faʻamatalaga RX.

Fa'ailoa mo na'o se taamilosaga uati e tasi mo taga ta'itasi.

E le o maua lenei fa'ailo ile faiga fa'avae.

rx_avs_endofpacket

Fa'ailo rx_core_clkout Avalon tafe mai.

A faʻamaonia, faʻaalia le iʻuga o se pusa faʻamatalaga RX.

Fa'ailoa mo na'o se taamilosaga uati e tasi mo taga ta'itasi.

E le o maua lenei fa'ailo ile faiga fa'avae.

rx_avs_gaogao

Fa'ailo rx_core_clkout Avalon tafe mai.

Fa'ailoa le numera o upu le aoga i le fa'ai'uga o fa'amaumauga RX.

E le o maua lenei fa'ailo ile faiga fa'avae.

rx_num_valid_bytes_eob

Tuuina atu

rx_core_clkout Fa'ailoa le aofa'i o bytes aoga i le upu mulimuli o le pa mulimuli.
E le o maua lenei fa'ailo ile faiga fa'avae.

rx_is_usr_cmd

Output rx_core_clkout Pe a fai mai, o lenei faailo e amata ai se tagata faʻaoga-

fa'asologa o fa'amatalaga.

Fa'ailoa lenei fa'ailoga i le taamilosaga o le uati tutusa e pei o le tx_startofpacket fa'amatalaga.

E le o maua lenei fa'ailo ile faiga fa'avae.

rx_link_up

Output rx_core_clkout Pe a faʻamaonia, faʻaalia le fesoʻotaʻiga faʻamatalaga RX

ua sauni mo le mauaina o fa'amaumauga.

rx_link_reinit

Ulufale rx_core_clkout A fa'ailoa mai, o le fa'ailoga lea e amata ai ala

toe fa'atulagaina.

Afai e te tapeina le Enable Auto Alignment, fai le faailo lea mo le taamilosaga e tasi e faʻaoso ai le MAC e toe faʻaoga auala. Afai ua seti le Enable Auto Alignment, otometi lava ona toe fa'aogaina e le MAC ia ala.

Aua le fa'ailoaina le fa'ailoga lea pe a seti le Enable Auto Alignment.

rx_error

(N*2*2)+3 (faiga PAM4)
(N*2)*3 (faiga NRZ)

Tuuina atu

rx_core_clkout

Pe a faʻamaonia, faʻaalia tulaga sese e tupu ile RX datapath.
· [(N*2+2):N+3] = Fa'ailoa sese PCS mo auala fa'apitoa.
· [N+2] = Fa'ailoa le fa'aoga sese. Toe fa'asolo le laina laina pe a fa'ailoa mai le vaega lea.
· [N+1]= Fa'ailoa ai fa'amatalaga e tu'uina atu i le fa'aoga fa'aoga pe a le'o sauni le fa'aoga.
· [N] = Fa'ailoa mai le leiloa o le fa'aogaina.
· [(N-1):0] = Fa'ailoa mai o fa'amaumauga o lo'o iai le CRC sese.

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6.4. Transceiver Reconfiguration faailoilo

Laulau 23.

Fa'ailoga Fa'atonu PCS
I lenei laulau, o le N o lo'o fa'atusalia ai le aofa'i o laina o lo'o fa'atulaga ile fa'atonu o le IP.

Igoa

Lautele

Ituaiga Uati Domain

Fa'amatalaga

reconfig_sl_read

Input reconfig_sl_ PCS reconfiguration faitau poloaiga

clk

faailoilo.

reconfig_sl_write

Ulufale reconfig_sl_ PCS reconfiguration tusi

clk

fa'ailoga fa'atonu.

toeconfig_sl_address

14 bits + clogb2N

Ulufale

reconfig_sl_ clk

Fa'ama'oti mai le PCS toe fa'atulagaina Avalon tuatusi fa'afanua fa'amata'u manatua i se laina filifilia.
O laina ta'itasi e 14 pa'u ma pito pito i luga e fa'atatau i le laina fa'asolo.
Example, mo se 4-lane NRZ/PAM4 mamanu, faatasi ai ma le reconfig_sl_address [13:0] e faasino i le tau o le tuatusi:
· reconfig_sl_address[15:1 4] seti i le 00 = tuatusi mo le laina 0.
· reconfig_sl_address[15:1 4] seti i le 01 = tuatusi mo le laina 1.
· reconfig_sl_address[15:1 4] seti i le 10 = tuatusi mo le laina 2.
· reconfig_sl_address[15:1 4] seti i le 11 = tuatusi mo le laina 3.

reconfig_sl_readdata

Output reconfig_sl_ Fa'ailoa mai PCS reconfiguration data

clk

e faitau e se taamilosaga sauni i a

ala filifilia.

toeconfig_sl_waitrequest

Output reconfig_sl_ Fa'atusa PCS reconfiguration

clk

Avalon fa'afanua fa'amaufa'ailoga

fa'ailo fa'atali ile ala ua filifilia.

reconfig_sl_writedata

Ulufale reconfig_sl_ Fa'ailoaina fa'amaumauga toe fa'atulagaina PCS

clk

ia tusia i luga o se taamilosaga tusitusi i le a

ala filifilia.

reconfig_sl_readdata_vali

Tuuina atu

reconfig_sl_ Fa'ailoa mai le toe fa'atulagaina o PCS

clk

maua fa'amatalaga e aoga ile filifilia

auala.

Laulau 24.

F-Tile Hard IP Reconfiguration faailoilo
I lenei laulau, o le N o lo'o fa'atusalia ai le aofa'i o laina o lo'o fa'atulaga ile fa'atonu o le IP.

Igoa

Lautele

Ituaiga Uati Domain

Fa'amatalaga

toeconfig_read

Ulufale reconfig_clk PMA toe fetuutuunai faitau

fa'ailoga fa'atonu.

reconfig_write

Ulufale reconfig_clk PMA toe fetuutuunai tusi

fa'ailoga fa'atonu.

toeconfig_address

18 bits + clog2bN

Ulufale

reconfig_clk

Fa'ailoa mai le tuatusi fa'akomupiuta a le PMA Avalon e manatua i totonu o se laina filifilia.
faaauau…

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Igoa
reconfig_readdata reconfig_waitrequest reconfig_writedata reconfig_readdatavalid

Lautele
32 1 32 1

Ituaiga Uati Domain

Fa'amatalaga

I le PAM4 ad NRZ modes, o laina taʻitasi e 18 bits ma o loʻo totoe pito i luga e faʻatatau i le laina offset.
Example, mo se mamanu 4-lane:
· reconfig_address[19:18] seti i le 00 = tuatusi mo le laina 0.
· reconfig_address[19:18] seti i le 01 = tuatusi mo le laina 1.
· reconfig_address[19:18] seti i le 10 = tuatusi mo le laina 2.
· reconfig_address[19:18] seti i le 11 = tuatusi mo le laina 3.

Tuuina atu

reconfig_clk Fa'amaoti fa'amatalaga PMA e faitau e se ta'amilosaga sauni i se laina filifilia.

Tuuina atu

reconfig_clk Fa'atusaina le PMA Avalon memorymapped interface fa'amalo fa'ailo i se auala filifilia.

Ulufale

reconfig_clk Fa'amaoti fa'amatalaga PMA e tusia i luga o se taamilosaga tusitusi i se laina filifilia.

Tuuina atu

reconfig_clk Fa'ama'oti PMA reconfiguration maua faʻamatalaga e aoga i se auala filifilia.

6.5. Faailoga PMA

Laulau 25.

PMA faailoilo
I lenei laulau, o le N o lo'o fa'atusalia ai le aofa'i o laina o lo'o fa'atulaga ile fa'atonu o le IP.

Igoa

Lautele

Ituaiga Uati Domain

Fa'amatalaga

phy_tx_lanes_stable

N*2 (faiga PAM4)
N (faiga NRZ)

Tuuina atu

Asynchronous Pe a faʻamaonia, faʻaalia TX datapath ua sauni e lafo faʻamatalaga.

tx_pll_loka

N*2 (faiga PAM4)
N (faiga NRZ)

Tuuina atu

Asynchronous Pe a faʻamaonia, faʻaalia le TX PLL ua ausia le tulaga loka.

phy_ehip_ready

N*2 (faiga PAM4)
N (faiga NRZ)

Tuuina atu

Asynchronous

Pe a fa'ailoa mai, fa'ailoa mai ua mae'a ona fa'aulufaleina le PCS masani ma ua sauni mo le fa'asalalauga.
O lenei faailo e faʻamaonia pe a uma le tx_pcs_fec_phy_reset_n ma tx_pcs_fec_phy_reset_nare deasserted.

tx_serial_data

Output TX uati fa'asologa TX pine fa'asologa.

rx_serial_data

Ulufale RX uati fa'asologa RX fa'amau fa'amau.

phy_rx_block_lock

N*2 (faiga PAM4)
N (faiga NRZ)

Tuuina atu

Asynchronous Pe a faʻamaonia, faʻaalia ua maeʻa le faʻaogaina o poloka 66b mo auala.

rx_cdr_loka

N*2 (faiga PAM4)

Tuuina atu

Asynchronous

A fa'ailoa mai, e fa'ailoa mai o uati ua toe maua o lo'o loka i fa'amaumauga.
faaauau…

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Igoa phy_rx_pcs_ready phy_rx_hi_ber

Lautele

Ituaiga Uati Domain

Fa'amatalaga

N (faiga NRZ)

N*2 (faiga PAM4)
N (faiga NRZ)

Tuuina atu

Asynchronous

Pe a faʻamaonia, faʻaalia o laina RX o le fesoʻotaʻiga Ethernet e fetaui lelei ma sauni e maua faʻamatalaga.

N*2 (faiga PAM4)
N (faiga NRZ)

Tuuina atu

Asynchronous

Pe a faʻamaonia, faʻaalia o le RX PCS o le laina fesoʻotaʻiga Ethernet o loʻo i totonu o se setete HI BER.

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7. Fuafuaina ma F-Tile Serial Lite IV Intel FPGA IP

7.1. Toe Seti Taiala
Mulimuli i ta'iala nei toe setiina e fa'atino ai lau fa'atulagaina o le tulaga fa'a-system.
· Nonoa tx_pcs_fec_phy_reset_n ma rx_pcs_fec_phy_reset_n faailoilo faatasi i le tulaga faiga ina ia toe setiina le TX ma RX PCS i le taimi e tasi.
· Fa'amautu tx_pcs_fec_phy_reset_n, rx_pcs_fec_phy_reset_n, tx_core_rst_n, rx_core_rst_n, ma reconfig_reset faailoilo i le taimi lava e tasi. Va'ai i le Toe Seti ma So'oga Initialization mo nisi fa'amatalaga e uiga i le toe setiina o le IP ma fa'asologa amata.
· Taofi tx_pcs_fec_phy_reset_n, ma rx_pcs_fec_phy_reset_n faailoilo maualalo, ma reconfig_reset faailo maualuga ma faatalitali mo tx_reset_ack ma rx_reset_ack e toe setiina lelei le F-tile malo IP ma le reconfiguration poloka.
· Ina ia maua le feso'ota'iga vave i le va o masini FPGA, toe fa'apipi'i le F-Tile Serial Lite IV Intel FPGA IP i le taimi e tasi. Va'ai ile F-Tile Serial Lite IV Intel FPGA IP Design Example User Guide mo faʻamatalaga e uiga i le mataʻituina o le IP TX ma le RX soʻotaga e faʻaaoga ai le meafaigaluega.
Fa'amatalaga Fa'atatau
· Toe Seti ma So'oga Initialization i le itulau 37
· F-Tile Serial Lite IV Intel FPGA IP Design Example User Guide

7.2. Fa'atonuga o le Taulimaina o Mease

Ole laulau o lo'o i lalo o lo'o lisiina ai ta'iala ile fa'aogaina o mea sese mo tulaga fa'aletonu e ono tupu ile F-Tile Serial Lite IV Intel FPGA IP design.

Laulau 26. Tulaga Sese ma Ta'iala Taulima

Tulaga Sese
E tasi pe sili atu auala e le mafai ona fa'atuina feso'ota'iga pe a mae'a se taimi fa'atulagaina.

Taiala
Fa'atino se faiga e toe fa'afo'i ai le so'otaga ile tulaga ole talosaga.

O se laina e leiloa fesootaiga pe a uma ona fausia fesootaiga.
O se laina e leiloa feso'ota'iga i le faagasologa o le kesi.

E ono tupu lenei mea pe a mae'a po'o le taimi o fa'asologa o fa'amatalaga. Fa'atino se su'esu'ega leiloa feso'ota'iga ile tulaga ole talosaga ma toe fa'afou le so'oga.
Fa'atino so'otaga toe fa'auluina faiga mo le auala sese. E tatau ona e faʻamautinoa e le sili atu i le 320 UI le taʻavale a le laupapa.

Fa'asa'o laina leiloa pe a uma ona fa'aoga auala uma.

E ono tupu lenei mea pe a mae'a po'o le taimi o felauaiga fa'amatalaga. Fa'atino se su'esu'ega leiloa o le laina i le tulaga o talosaga e toe amata ai le fa'agasologa ole laina.

ISO 9001:2015 Resitala

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8. F-Tile Serial Lite IV Intel FPGA IP User Guide Archives

IP versions e tutusa ma le Intel Quartus Prime Design Suite software versions up to v19.1. Mai le Intel Quartus Prime Design Suite software version 19.2 poʻo mulimuli ane, IP cores o loʻo i ai se polokalame faʻaliliuga IP fou.

Afai e le o lisiina se fa'asologa autu o le IP, e fa'aoga le ta'iala mo le fa'asologa muamua o le IP.

Intel Quartus Prime Version
21.3

IP Core Version 3.0.0

Taiala mo Tagata Fa'aoga F-Tile Serial Lite IV Intel® FPGA IP Taiala mo Tagata Fa'aoga

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9. Fa'amatalaga Toe Iloiloga o Pepa mo le F-Tile Serial Lite IV Intel FPGA IP User Guide

Tusitusiga Faʻamatalaga 2022.04.28
2021.11.16 2021.10.22 2021.08.18

Intel Quartus Prime Version
22.1
21.3 21.3 21.2

IP Version 5.0.0
3.0.0 3.0.0 2.0.0

Suiga
· Faʻafouina Laulau: F-Tile Serial Lite IV Intel FPGA IP Features - Faʻafouina Faʻamatalaga Faʻamatalaga Faʻamatalaga faʻatasi ai ma le lagolago faʻaopoopo FHT transceiver: 58G NRZ, 58G PAM4, ma le 116G PAM4
· Fa'afou Laulau: F-Tile Serial Lite IV Intel FPGA IP Parameter Fa'amatalaga - Fa'aopoopo le parakalafa fou · Fa'atonu PLL fa'asino taimi uati · Fa'aaga le debug endpoint - Fa'afou le Tulaga mo PMA fa'amaumauga - Fa'afou igoa fa'aigoa e fetaui ma le GUI
· Faʻafouina le faʻamatalaga mo le faʻaliliuina o faʻamatalaga i le Laulau: F-Tile Serial Lite IV Intel FPGA IP Features.
· Toe fa'aigoa igoa ole laulau IP ile F-Tile Serial Lite IV Intel FPGA IP Fa'amatalaga Fa'amatalaga ile vaega Fa'ata mo le manino.
· Fa'afou Laulau: IP tapula'a: — Fa'aopoopo se parakalafa fou–RSFEC fa'aaga i le isi Serial Lite IV Simplex IP tu'u i le ala FGT tutusa. - Fa'afouina tulaga fa'aletonu mo le fa'asologa o le uati fa'asino i le Transceiver.
Fa'asalalauga muamua.

ISO 9001:2015 Resitala

Pepa / Punaoa

	intel F Tile Serial Lite IV Intel FPGA IP [pdf] Taiala mo Tagata Fa'aoga F Tile Serial Lite IV Intel FPGA IP, F Tile Serial Lite IV, Intel FPGA IP
	intel F-Tile Serial Lite IV Intel FPGA IP [pdf] Taiala mo Tagata Fa'aoga F-Tile Serial Lite IV Intel FPGA IP, Serial Lite IV Intel FPGA IP, Lite IV Intel FPGA IP, IV Intel FPGA IP, FPGA IP, IP

Fa'asinomaga

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Pepa / Punaoa

Fa'asinomaga

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