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SILICON LABS AN1511 Single Layer Hardware

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Specifications

  • Product Name: SiMG301 Single-layer Smart Light Bulb Design
  • Wireless SoC: Series 3 SiMG301
  • Output Power: Up to +10 dBm
  • PCB Type: Single-layer metal core PCB
  • PCB Diameter: 40 mm

Manufacturing a product with multiple multilayer circuit boards is expensive. We offer a cost-effective solution for a single-PCB, single-layer smart light bulb design, powered by the Series 3 SiMG301 Wireless SoC, integrating a high-performance radio with up to +10 dBm output power and an LED pre-driver peripheral. The design example demonstrates the possibility of putting the mains power supply, the radio interface, and the LED power section on a single-layer metal core PCB with a diameter of 40 mm, enabling a lower cost of manufacturing and better thermal performance, while not compromising on RF performance.
Note: This release of the Application Note focuses on the RF performance aspects of such a design. The power supply and the LED driver will be documented in more detail in subsequent releases.

KEY POINTS

  • Mains power supply, radio interface, and LEDs all on a metal core single copper layer PCB
  • Integrated LED driver to reduce external component count
  • An aluminum core to enhance heat spreading
  • Nominal LED power of 8 W
  • 2.4 GHz +10 dBm with external monopole antenna

Introduction

What Problems Does the Design Solve?
This Application Note aims to help with the design of a smart light bulb with lower manufacturing costs. General guidelines are explored through the specific circuit board designed for this application, featuring a single-layer metal core PCB. The aluminum core enhances its thermal performance required by LED bulbs, while also serving as a ground plane for the antenna. The SiMG301 Wireless SoC integrates an LED pre-driver peripheral, optimizing board real estate and BOM costs.

Simplified System Block Diagram
This diagram shows the simplified architecture of the electronic part of the design. This does not include the recommended external current limiting resistor, nor the mechanical or thermal interfaces.SILICON-LABS-AN1511-Single-Layer-Hardware-fig (1)

SiMG301 LED Pre-Driver Peripheral and the Power Supply
This version of the Application Note does not describe the pre-driver peripheral in detail. A subsequent release will include the system-level design requirements, considerations,s and measurement results regarding the power electronics sections.

Layout Design Guidelines

Single-Layer Metal Core PCB
To comfortably fit in a small light bulb, the design was constrained to a circular shape with a diameter of 40 mm. On the board edge, the LEDs can be found with their pads extended by copper pours to enhance thermal coupling to the metal core, improving diode cooling capabilities. Two mounting holes are located on opposite sides of the board and are fitted with M2 screws from the top, placing them on the side opposite the antenna. These can be used to secure the PCB to an enclosure, tying it to the circuit ground (not Protective Ground). Since the circuit is entirely drawn on a single layer, with the added difficulty of having to keep high-voltage clearances, adequate ground connections could not be achieved. Thus, the screws are required to be populated even if they are not mechanically necessary.
The design files can be found according to 4.1 Reference Design Schematics and PCB design in the 4. Appendix.

Stackup
An aluminum core, single copper layer PCB was designed with the following layer structure, for a total thickness of 1.6 mm.SILICON-LABS-AN1511-Single-Layer-Hardware-fig (2)

The circuit was manufactured on the AL-01-B10 Aluminum-based Copper-Clad Laminate. For more information about the materials, refer to their documentation. To be able to use the same matching network element values, both the layer stackup and the matching network layout must be followed closely.

Metal Core as Ground Reference
Designing a radio frequency circuit on a single layer that complies with regulatory requirements is a challenge. The closest thing to a ground reference plane is the aluminum core itself, which is connected to the circuit ground both directly with two M2 screws and through capacitive coupling. Although this is not ideal compared to multilayer circuits, measurements supported the viability of this construction.

High Voltage Clearances
As the LED driver uses a voltage-increasing topology, the peak voltage difference between the high and low voltage parts of the circuit is given by adding the voltage of the LED chain to the rectified AC peak voltage. Supplied from 230 V mains, this results in a maximum difference of around 350 V, requiring attention from the designer.

SILICON-LABS-AN1511-Single-Layer-Hardware-fig (3)

Figure 2.1. High and low voltage sections (marked red and blue, respectively) illustrating class separation. Both include the FET drain (magenta)

Conformal Coating
Such a design must comply with the effective safety standards regarding minimum clearance and creepage for given potential differences. Although an off-board fuse can lower the necessary distances according to some regulations, minimizing the probability of dielectric breakdown is recommended to enhance product lifespan. Since the board has a circular outline with a diameter of only 40 mm, conformal coating is applied, reducing the required clearance distances, enabling the compact design with a lower probability of breakdown. Although this works on most of the board, only the outer surface is being protected; traces under components are not. As a rule, a clearance of 0.7 mm was used between high and low voltage sections, with manual care for keeping more separation in areas not coated.

Component Pin Clearances
Although smaller packages may be available that otherwise meet electrical requirements, for some of the components, larger packages must be selected just to meet the clearance requirements between their pins belonging to high voltage difference nets.

Through-Hole Component Mounting Options
Since an aluminum core was used, through-hole components must be mounted differently from typical designs. Every hole is drilled all the way through the metal core, leaving the bare aluminum shaft, which is tied to the ground. Fitting a TH part would short its leads to GND. This design utilizes a Bent Lead solution, which, along with an alternative mounting style, can be seen in Figure 2.2. Through-Hole component mounting options: Bent Lead on page 6, and Figure 2.3. Through-Hole component mounting options: Bottom Entry Connector on page 6.SILICON-LABS-AN1511-Single-Layer-Hardware-fig (4) SILICON-LABS-AN1511-Single-Layer-Hardware-fig (5)

RF Considerations
Vias cannot be used to stitch the top-layer ground to a ground plane below, nor can they be used to route signals beneath it. To create a sufficient ground plane for the antenna, multiple patches of ground pours are connected with jumpers, as seen in the following sections. To further improve the grounding, some of the unused GPIO pins are disabled and shorted to ground to provide a clear path for the ground return currents.

Matching Network Layout
A matching network layout was designed with simulation-tuned elements. If more filtering is necessary, extra tuning element slots are available in parallel.

SILICON-LABS-AN1511-Single-Layer-Hardware-fig (6)SILICON-LABS-AN1511-Single-Layer-Hardware-fig (7)

SILICON-LABS-AN1511-Single-Layer-Hardware-fig (8)

The designed layout was evaluated and tuned using EM simulation, with emphasis on third and fifth harmonic suppression. Figure 2.6 Simulated harmonic suppression on page 8 shows that the expected result performs adequately when compared to the BRD4407A 4-layer reference design. During the final PCB design process, slight modifications have been made to this layout. The ground plane was extended outwards as much as possible to improve antenna efficiency. Non-RF critical components have been added, replaced, or moved. Overall, no changes were made that would negatively impact RF performance.

Antenna
A simple monopole antenna is soldered to the antenna pad found in the center of the PCB. Its length is nominally 31.25 mm, which is a quarter wavelength at the 2.4 GHz band. This size can fit inside a typical light bulb. The area surrounding the antenna pad should be dedicated as a ground plane. Board real estate is limited, so a tradeoff must be made between RF performance and occupied area. The LED pre-driver enables the designer to use fewer external components, saving space, resulting in better potential radio performance.

Testing and Results

Safety Precautions
To reduce the risk of injury and damage, whenever reasonable, the device was powered externally from a 3.3 V source (typically the WSTK/WPK main board) during measurements, to leave the high-voltage section unused. However, if the setup required the HV power supply, other safety measures had to be in place. When planning to test the device on mains voltage, always ensure proper safety precautions are in place before powering the setup.

  • Utilize an isolation transformer. Have an easily accessible safety switch on the secondary.
  • Limit DUT current with a series power resistor of around 5-10 ohms, which also functions as a fuse.
  • When connecting the device to any equipment galvanically, ensure the wires, probes, and the equipment are rated for voltages up to at least 400 V. Note that connecting any equipment this way may affect isolation. Pay special attention to non-isolated probes, for example, a single-ended oscilloscope probe ground being connected to protective earth.
  • If possible, all communication interfaces between the DUT and a host should be galvanically isolated.

An isolation transformer and a Ground-Fault Current Interrupter (GFCI) cannot be used simultaneously when protective earth is galvanically connected to the device (for example, le through a single-ended probe referenced to GND). Leakage currents may make the GFCI trip, rendering the setup unreliable, and at the same time, referencing earth after isolation undermines the protective effect of the circuit interrupter.

RF Measurements

Matching Networks
The final matching network element values can be seen in Table 3.1, Bench tuned matching network element values on page 10, with Figure 3.1 Complete matching network on page 10 showing their arrangement. Note that these values are tuned for the particular matching network layout and board stackup used in this design. Both the layout and the stackup must be followed to obtain the same results without retuning.SILICON-LABS-AN1511-Single-Layer-Hardware-fig (9)

Table 3.1. Bench-tuned matching network element valuesSILICON-LABS-AN1511-Single-Layer-Hardware-fig (10)

The PA matching network was assembled using simulation-tuned elements, terminated by a 50-ohm resistor. An RF “pigtail” probe was soldered to the RF output pad, setting the reference plane to the output of the IC, where the optimal PA termination impedance is known for a range of metrics. The BRD4407A Radio Board was used for reference; measured port parameters are plotted over the 10 dBm PA output power load pull measurement of the SiMG301. Since the simulation-tuned elements resulted in an acceptable impedance at the fundamental, no change was made at this stage.SILICON-LABS-AN1511-Single-Layer-Hardware-fig (11)

In a different setup, a quarter-wave monopole antenna was soldered to the center pad. Since the PA matching network is designed for optimal RF performance considering a 50-ohm termination, the antenna impedance was tuned to 50 ohms, as seen in Figure 3.3 Antenna match impedance curve on page 11.SILICON-LABS-AN1511-Single-Layer-Hardware-fig (12) SILICON-LABS-AN1511-Single-Layer-Hardware-fig (13)

Figure 3.4 Antenna match return loss [dB] on page 12 shows that the return loss of the ANT match is at least 16.6 dB over the 2.4 GHz band.

Radiated TX Power
An anechoic chamber was used to determine EIRP at the fundamental and harmonic frequencies. The following are two sets of tables, containing data from two power settings at the band edges and the center frequency.

Table 3.2. Worst Case Radiated Harmonic Emissions at Maximum Power (CW tone)

SILICON-LABS-AN1511-Single-Layer-Hardware-fig (14)

Table 3.3. Worst Case Radiated Harmonic Emissions at Raw Power Level 21 (CW tone) SILICON-LABS-AN1511-Single-Layer-Hardware-fig (15)

It is apparent that the third harmonic fails the regulatory margin, but this is somewhat expected as the fundamental output power is over the 10 dBm that the SiMG301 is rated for. Due to the antenna gain in the maximum direction of radiation, 16.5 dBm is observed at the fundamental – actual output power, without the effects of an antenna can be found in Table 3.3 Worst Case Radiated Harmonic Emissions at Raw Power Level 21 (CW tone) on page 13. Lowering the raw power level until all requirements are met yields level 21, as seen in the following table.\

If more output power is required, tuning the matching network elements could raise the possible maximum power level still meeting requirements. As Table 3.3 Worst Case Radiated Harmonic Emissions at Raw Power Level 21 (CW tone) on page 13 shows, the third harmonic is high; however, since the measurements were performed with a CW tone, an extra margin can be added to the limiting harmonics, depending on the used modulation. See the modulation relaxation values determined for EFR32MG24 in the BRD4188B Reference Manual. The values for SiMG301 can be considered similar. These tables contain the measured levels among the three frequencies (2402, 2450, and 2480 MHz), compiling the lowest margin for every harmonic. More detailed results are available in the Appendix under 4.2 Complete TX Measurement Results for Maximum Power Level and 4.3 Complete TX Measurement Results for Raw Power Level 21, where each of these frequencies has its own table, for power levels 95 and 21, respectively.

Conducted TX Power
To measure the output power, the antenna pad was replaced with a u.FL connector. Different raw power levels were used to evaluate the design. These were the following

  1. 95 – maximum possible output power
  2. 21 – level at which the design passed radiated harmonic measurements (with the initial matching network)
  3. 37 – where the nominal output power of 10 dBm is observed at the center frequency

Table 3.4. Conducted Harmonic Emissions at Given Power Levels (CW tone)

SILICON-LABS-AN1511-Single-Layer-Hardware-fig (16)

Note: Following the noise of the spectrum analyzer.

The power level of 21 (raw) is the limit at which the filtering of the matching network still suppresses the radiated harmonics below regulatory limits. At this setting, the measured conducted output power on the fundamental is 8.2 dBm at the band center. This falls short of the value rating of the +10 dBm PA, however, due to the high-gain antenna, the maximum direction EIRP reaches that value (as seen in Table 3.3 Worst Case Radiated Harmonic Emissions at Raw Power Level 21 (CW tone) on page 13). Further tuning is required if achieving maximum conducted output power is critical.

Conducted RX measurements and RX regulatory compliance (ETSI) 

Measurement conditions

  • Powered by the WSTK main board, not the onboard HV power supply
  • Radio control via RAIL, maximum power setting
  • M2 screws inserted to connect the aluminum plane to GND
  • Instrument settings: 100 kHz RBW
  • Measured frequencies
    • 2450 MHz: no amplification
    • 4900 MHz and 7350 MHz: through an amplifier chainSILICON-LABS-AN1511-Single-Layer-Hardware-fig (17) SILICON-LABS-AN1511-Single-Layer-Hardware-fig (18)

For easier visualization, each of the cuts has its respective orientation of the 3D model attached. All the traces are normalized to their local plot maximum. To get an absolute radiated pattern, use the EIRP results from 3.2.2 Radiated TX Power to denormalize them. These radiation patterns can be used as a guide to measure the device only in the maximum direction to avoid having to do a full sweep for quick adjustments in the matching network, for example. Tuning for better suppression, especially at the third harmonic, can be done more effectively this way.

Conducted RX Sensitivity

Measurement conditions

  • RF shielded box
  • 10 dB attenuator (to reduce noise figure)
  • 2FSK, BLE (1 Mbps)
  • u.FL connector instead of antenna pad

The datasheet sensitivity value for 1 Mbps GFSK is -98.6 dBm. Since the values below were measured using binary FSK modulation, slight differences might have occurred. Hence, the BRD4407 Radio Board was also measured in the same setup for reference.

  • SILICON-LABS-AN1511-Single-Layer-Hardware-fig (19)

Overall, as shown in Figure 3.5 Receiver sensitivity results on page 16, the metal core design performed comparably, even slightly better than the Radio Board.

Appendix

Reference Design Schematics and PCB design

All design files will be included in the BRD4407A design package.

Complete TX Measurement Results for Maximum Power Level

Table 4.1. Radiated Harmonic Emissions at Raw Power Level 95 (Max) at 2402 MHzSILICON-LABS-AN1511-Single-Layer-Hardware-fig (20)

Table 4.2. Radiated Harmonic Emissions at Raw Power Level 95 (Max) at 2450 MHzSILICON-LABS-AN1511-Single-Layer-Hardware-fig (21)

Table 4.3. Radiated Harmonic Emissions at Raw Power Level 95 (Max) at 2480 MHzSILICON-LABS-AN1511-Single-Layer-Hardware-fig (22)

Complete TX Measurement Results for Raw Power Level 21

Table 4.4. Radiated Harmonic Emissions at Raw Power Level 21 at 2402 MHzSILICON-LABS-AN1511-Single-Layer-Hardware-fig (23)

Table 4.5. Radiated Harmonic Emissions at Raw Power Level 21 at 2450 MHzSILICON-LABS-AN1511-Single-Layer-Hardware-fig (24)

Table 4.6. Radiated Harmonic Emissions at Raw Power Level 21 at 2480 MHzSILICON-LABS-AN1511-Single-Layer-Hardware-fig (25)

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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use Silicon Labs products. Characterization data, available modules and peripherals, memory sizes, and memory addresses refer to each specific device, and “Typical” parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. SiliconLabs reserves the right to make changes without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to th accuracy or completeness of the included information. Without prior notification, Silicon Labs may update product firmware during the manufacturing process for security or reliability reasons. Such changes will not alter the specifications or the performance of the product. Silicon Labs shall have no liability for the consequences ofthe use of the information supplied in this document. This document does not imply or expressly grant any license to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any FDA Class III devices, applications for which FDA premarket approval is required, or Life Support Systems without the specific written consent of Silicon Labs. A “Life Support System” is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass destdestructionncluding (but not limited to) nuclear, biological, or chemical weapons, or missiles capable of delivering such weapons. Silicon Labs disclaims all express and implied warranties and shall not be responsible or liable for any injuries or damages related to use of a Silicon Labs product in such unauthorized applications.

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FAQs

Documents / Resources

SILICON LABS AN1511 Single Layer Hardware [pdf] Instructions
AN1511 Single Layer Hardware, AN1511, Single Layer Hardware, Layer Hardware, Hardware

References

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