SEMIKRON DANFOSS AB501645260489en Electronics Point

• Revision: 04
• Issue date: 2024-10-10
• Prepared by: Andreas Giessmann
• Approved by: Dr. A.Wintrich, J.Lamp
• Keyword: Inductance, 3-Level, Oscillation

Oscillation Influence of DC-Link Inductance on Switching Performance and Power Losses

Introduction

The power dissipation Eon/Eoff of the IGBT and Err of the diode specified in the data sheets are measured under certain parameters. In addition to parameters such as the DC-Link voltage, current, junction temperature, gate resistance and gate-emitter voltage, the losses also depend on the inductance of the commutation loop. Figure 1 shows the three main inductive parameters of the commutation loop as centered elements using a simplified inductive equivalent circuit diagram. The power module shown as a half-bridge has an internal module inductance LCE. The DC-Link inductance Ls consists of the internal inductance of the DC-Link capacitors LCap and the busbar inductance LBusbar. These two quantities are determined by the type of capacitor, the number of capacitors connected in series and in parallel and the busbar design. This inevitably leads to different DC-Link inductances Ls used at Semikron Danfoss and at the customer. The aim of this Application Note is to illustrate the influence of the DC-Link inductance Ls on the power losses and the switching behavior. Furthermore, measures to reduce overvoltage when using standard half-bridge modules to build a NPC 3-level topology are presented.

Device Under Test and Test Setup

As shown in Figure 2, the device under test is a 600A/1200V rated power module SEMiX603GB12E4p [2] that belongs to the SEMiX3p product family. It is a standard half-bridge module consisting of a TOP and BOT IGBT/Diode. It uses IGBT E4 and Diode CAL4F technology. For the test setup 12 capacitors (type: EPCOS 420uF B2520-B1227-A101) are connected in parallel that form together with the laminated busbar the DC-Link. The power module is mounted on a heatsink and screwed to the DC-Link. The DC-Link inductance Ls is increased by increasing the distance between the DC-Link and the power module. This Application Note examines the switching behavior and losses for the following DC-Link inductances: Ls=35/60/85nH
The investigations at very high DC-Link inductances (Ls=85nH) are mainly used to illustrate the challenges of overvoltage issues of 3-level topologies based on standard half-bridge modules. The statements on DC-Link inductances can be transferred to other current ratings if the inductance per ampere is considered. Thus, a 60nH inductance for a 600A rated module would be comparable to 120nH inductance for a 300A rated module.

Influence of Ls on Switching Performance and Power Losses

Overview
Figure 3 shows the quantities whose dependence on Ls is discussed in this Application Note.

Influence of Ls on power losses 

3.2.1 Influence of Ls on IGBT turn-on losses Eon Figure 4 shows the influence of Ls on the IGBT turn-on losses Eon. With increasing inductance the voltage drop of the Vce voltage increases. In this case one speaks of inductive voltage drop. Due to the constant DC-Link voltage, the di/dt decreases with increasing inductance, which is visible from the turn-on current Ic. The multiplication of Vce and Ic results in the turn-on losses Eon for the three DC-Link inductances. As the turn-on resistance Rgon increases, the Ls caused difference in turn-on losses remains almost constant. Only towards low turn-on currents the differences decrease, because the inductive voltage drop disappears more and more. At 600V, 600A, 2, 150°C the turn-on losses decrease by 25% in the range of Ls=35 to 85nH.

Influence of Ls on IGBT turn-off losses Eoff
Figure 5 shows the influence of Ls on the IGBT turn-off losses Eoff. With increasing inductance the overvoltage across the IGBT increases. Due to the increasing overvoltage and the decreasing di/dt, the switching losses increase with increasing DC-Link inductance. With increasing turn-off resistance Rgoff the difference in turn-off losses remains almost constant. Only towards small turn-off currents do the differences decrease. At 600V, 600A, 2, 150°C the turn-off losses increase by 14% in the range of Ls=35 to 85nH.

Influence of Ls on IGBT total losses Esw
Figure 6 shows Eon, Eoff and the sum of both Esw as relative values over the DC-Link inductance Ls. The total switching losses Esw refer to the reference value at Ls=35nH. Eon, Eoff refer to the respective total losses Esw at the corresponding DC-Link inductance. At 600V, 600A, 2, 150°C, the total switching losses decrease by about 10% in the range of Ls=35 to 85nH.

Influence of Ls on diode turn-off losses Err
Figure 7 shows the influence of Ls on the diode turn-off losses Err. With increasing inductance the course of the voltage rise over the diode changes, the di/dt decreases and the losses increase. With increasing turn-on resistance Rgon the difference in turn-off losses remains almost constant. Only towards small turn-off currents do the differences decrease. At 600V, 600A, 2omega, 150°C the turn-off losses increase by 14% in the range of Ls=35 to 85nH.

Influence of Ls on overvoltage 

Influence of Ls on IGBT overvoltage during Turn-off
Figure 8 shows the influence of Ls on IGBT overvoltage during turn-off. All curves are synchronized with each other at the gate-emitter voltage Vge. With increasing inductance the overvoltage and the oscillations increase. The oscillations are visible in the Vge, Vce voltage and the switched current. The overvoltage as a function of Rgoff shows a typical IGBT4 behavior. It first increases with increasing resistance and then decreases again. At 600V, 400A, 2, 25°C the overvoltage related to Vdc doubles (528V overvoltage compared to 260V) in the range of Ls=35 to 85nH.

Influence of Ls on diode overvoltage during turn-off
Figure 9 shows the influence of Ls on Diode overvoltage during turn-off. All curves are synchronized with each other at the gate-emitter voltage Vge. With increasing inductance the overvoltage and the oscillations increase. The oscillations are visible in the Vge, Vce voltage and the switched current. The overvoltage as a function of Rgon shows that from a gate resistance of 4 or 6 no overvoltage occurs anymore. However, this is accompanied by an increase in the IGBT turn-on losses Eon (refer to Figure 4). At 600V, 25A, 2, 25°C the overvoltage related to Vdc quadruples in the range of Ls=35 to 85nH.

Influence of Ls on delay times 

Influence of Ls on turn-on delay time td_on
Figure 10 shows the influence of Ls on turn-on delay time td_on. All curves are synchronized with each other at the gate-emitter voltage Vge. With increasing inductance the di/dt changes what causes the turn-on delay time only slightly to change. At 600V, 600A, 2, 150°C the influence on the turn-on delay time can be neglected in the range of Ls=35 to 85nH.

Influence of Ls on turn-off delay time td_off
Figure 11 shows the influence of Ls on turn-off delay time td_off. All curves are synchronized with each other at the gate-emitter voltage Vge. With increasing inductance the di/dt changes what causes the turn-off delay time on slightly to change. At 600V, 600A, 2 omega 150°C the influence on the turn-on delay time can be neglected in the range of Ls=35 to 85nH.

Influence of Ls on diode reverse recovery behavior 

Influence of Ls on maximum reverse recovery peak current Irrm
Figure 12 shows the influence of Ls on the maximum reverse recovery peak current Irrm. All curves are synchronized with each other at the gate-emitter voltage Vge. With increasing inductance the Irrm changes only slightly. The differences in Irrm keep constant also at higher Rgon.

Level Topologies based on Standard Half-Bridge Modules

NPC topology based on SEMiX3p 

3-level topologies are state of the art and are used in grid tie inverters mainly in wind, solar and UPS applications. In Figure 13 a Neutral Point Clamp (NPC) topology is shown, which is constructed from three standard half-bridge modules. Due to the terminal connections for DC+/DC-/N and AC, the DC-Link cannot be designed in such a way that the potentials overlap completely. This leads to an increased DC-Link inductance, which differs significantly from that specified in the data sheet of the module.

Commutation loops 

Commutation loops at power factor = 1
The commutation loops over an output period are shown for the power factor = 1 in Figure 14. The phase angle between the idealized output voltage and current is 0°. For positive and negative output current, fast commutation takes place exclusively within a half-bridge module. The commutation inductance is of the same order of magnitude as that specified in the module data sheet. From the point of view of overvoltage limitation, the voltage zero crossing must be considered here when fast commutation changes from DC+/N to N/DC- or vice versa. In this commutation case all three modules are involved. Due to the single switching event within an output period, the gate resistances for T2/T3 can be chosen large, however, so that the switching losses can be neglected.

Commutation loops at power factor = -1
The commutation loops over an output period are shown for the power factor = -1 in Figure 15. The phase angle between the idealized output voltage and current is 180°. For positive and negative output current, all three half-bridge modules are always involved in the fast commutation. The commutation inductance is much higher than the values given in the data sheet and can reach values of 100nH or even more.

Figure 16 shows the overvoltage curves to be expected when switching off the IGBT T2/T3 and the diodes D1/4 as a function of the commutation inductance (see Figure 8/Figure 9). For the IGBT, the overvoltage increases with falling temperature and rising turn-off currents. In this example, an overvoltage of 1128V at 400A/Ls=85nH occurs at the IGBT. For the diode, low currents and high temperatures are critical. Here an overvoltage of 1106V at 25A/Ls=85nH occurs. In both cases the maximum overvoltage of approx. 70V 90V is only slightly below the maximum permissible blocking voltage of 1200V.

Figure 17 shows the overvoltage characteristics of the IGBT and diode as a function of the gate resistance. The characteristic of Ls=100nH is estimated and symbolized by a dotted line. Corresponding to the maximum turn-off current, the Rgoff must be increased for a given DC-Link design to remain below the maximum blocking voltage. In this example, the IGBT overvoltage exceeds the maximum blocking voltage of 1200V at an inductance of 100nH. To achieve the same 860V overvoltage at Ls=100nH as at 35nH would require to increase Rgoff from 2 omega to well more than 10omega, if it is achieved at all. With increasing Rgoff the losses increase (see Figure 5). It can be seen from Figure 9 that the maximum overvoltage of the diode occurs at approx. 25A, which is in the range of 5% of the nominal chip current. This current value always occurs near the current zero crossing regardless of the maximum output power. To generate the same overvoltage at the diode at Ls=100nH as at 35nH, the Rgon would have to be increased from 2 to 5.5. Referring to Figure 4, the turn-on losses are almost doubled if the Rgon is increased from 2 to 5.5omega

Summary

In this Application Note, the influence of the DC-Link inductance on the switching behavior and the power losses was examined. It was shown that with increasing DC-Link inductance Ls, the IGBT turn-on losses decrease, whereas IGBT and diode turn-off losses increase. Eon in particular is reduced more than Eoff and Err increase. This is the reason why Ls is given in the data sheet, otherwise the losses can be assumed too optimistically. Furthermore, the overvoltage and the tendency to oscillate increase with increasing inductance for both the IGBT and the diode. This makes it necessary to increase the gate resistance with increasing stray inductance, which leads to higher losses. The influence on the turn-on and turn-off delay time can be neglected. Even though increased DC-Link inductance results in reduced Eon, a low-inductance DC-Link design should still be aimed for, since low overvoltage peaks are essential for reliable operation. In addition, a low-inductance DC-Link design is necessary in order to turn-off high output currents even in the event of a short circuit and to limit the overvoltage and oscillations on the IGBT and the diode during turn-off (EMI). In the case of 3-level NPC topologies based on standard half-bridge modules, other gate resistances than those specified in the data sheet must be used, as in this case the commutation inductance can be much higher than that specified in the data sheet. Furthermore, when comparing power dissipation in different data sheets, it is important to note at which inductance they were measured.

Symbols and Terms

Letter Symbol	Term
AC	Output terminal
DC+	Positive potential (terminal) of a direct voltage source
DC-	Negative potential (terminal) of a direct voltage source
di/dt	change of current per time
DUT	Device Under Test
dv/dt	change of voltage per time
Eoff	Energy dissipation during IGBT turn-off time
Eon	Energy dissipation during IGBT turn-on time
Err	Energy dissipation during reverse recovery (diode)
Esw	Energy dissipation during IGBT turn-off and turn-on time
Ic	Continuous collector current
IF	Diode forward current
IGBT	Insulated Gate Bipolar Transistor
Inom	Nominal current
Irrm	Peak reverse recovery current
LCE	Parasitic collector-emitter inductance
Ls	DC-Link stray inductance
N	Neutral potential (terminal) of a direct voltage source midpoint between DC+ and DC
Rgon	Gate turn-on resistor
Rgoff	Gate turn-off resistor
t	Time
td off	Turn-off delay time
td on	Turn-on delay time
tf	Fall time
tr	Rise time
Vce	Collector-emitter voltage
Vces	Collector-emitter voltage with gate-emitter short circuited
Vdc	Total supply voltage (DC+ to DC-)
VFWD	Voltage across free-wheeling diode
Vge	Gate-Emitter voltage
VRRM	Repetitive peak reverse voltage (Diode)
Tj	Junction temperature
0)t	Conduction angle

A detailed explanation of the terms and symbols can be found in the “Application Manual Power Semiconductors” [3].

References

1. www.semikron-danfoss.com
2. SEMiX603GB12E4p, data sheet, Rev. 2.0 – 25.01.2017
3. A. Wintrich, U. Nicolai, W. Tursky, T. Reimann, “Application Manual Power Semiconductors”, 2nd edition, ISLE Verlag 2015, ISBN 978-3-938843-83-3

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Documents / Resources

SEMIKRON DANFOSS AB501645260489en Electronics Point [pdf] User Guide AB501645260489en Electronics Point, AB501645260489en, Electronics Point, Point

References

• User Manual