UG0644 DDR AXI Arbiter
Zambiri Zamalonda
DDR AXI Arbiter ndi gawo la hardware lomwe limapereka a
64-bit AXI master interface kwa DDR-SDRAM pa-chip controller.
Amagwiritsidwa ntchito kwambiri pamapulogalamu amakanema a buffering ndi
kukonza kwa data ya pixel yamavidiyo. Buku logwiritsa ntchito mankhwala limapereka
zambiri ndi malangizo a hardware kukhazikitsa,
kayeseleledwe, ndi kagwiritsidwe ntchito ka zinthu.
Kukhazikitsa kwa Hardware
DDR AXI Arbiter idapangidwa kuti igwirizane ndi DDR-SDRAM
pa-chip controller. Imapereka mawonekedwe a 64-bit AXI master
zomwe zimathandizira kukonza mwachangu data ya pixel yamavidiyo. Wogwiritsa ntchito mankhwala
Bukuli limapereka tsatanetsatane wa mapangidwe a DDR AXI
Arbiter ndi kukhazikitsa kwake kwa hardware.
Kuyerekezera
Buku logwiritsa ntchito mankhwala limapereka malangizo oyerekeza
DDR AXI Arbiter pogwiritsa ntchito zida za MSS SmartDesign ndi Testbench. Izi
zida zimathandiza wosuta kutsimikizira kulondola kwa mapangidwe ndi
kuonetsetsa kugwira ntchito moyenera kwa gawo la hardware.
Kugwiritsa Ntchito Zida
DDR AXI Arbiter imagwiritsa ntchito zida zamakina monga malingaliro
ma cell, zotchinga zokumbukira, ndi zida zowongolera. Wogwiritsa ntchito mankhwala
Bukuli limapereka lipoti latsatanetsatane lakugwiritsa ntchito zida zomwe
ikufotokoza zofunikira za DDR AXI Arbiter. Izi
zambiri zitha kugwiritsidwa ntchito kuwonetsetsa kuti gawo la hardware limatha
zigwiritsidwe ntchito muzinthu zomwe zilipo.
Malangizo Ogwiritsira Ntchito Zogulitsa
Malangizo otsatirawa akupereka chitsogozo cha momwe mungagwiritsire ntchito
DDR AXI Arbiter:
Gawo 1: Kukhazikitsa kwa Hardware
Gwiritsani ntchito gawo la hardware la DDR AXI Arbiter kuti muwoneke
ndi DDR-SDRAM pa-chip controller. Tsatirani mapangidwe
kufotokozera zomwe zaperekedwa mu bukhu la ogwiritsa ntchito kuti zitsimikizire kuti ndizoyenera
kukhazikitsa gawo la hardware.
Gawo 2: Kayeseleledwe
Tsanzirani kapangidwe ka DDR AXI Arbiter pogwiritsa ntchito MSS SmartDesign ndi
Zida za Testbench. Tsatirani malangizo omwe aperekedwa muzogulitsa
buku la ogwiritsa ntchito kutsimikizira kulondola kwa kapangidwe kake ndikuwonetsetsa
kugwira ntchito moyenera kwa gawo la hardware.
Gawo 3: Kugwiritsa Ntchito Zothandizira
Review lipoti la kagwiritsidwe ntchito ka zinthu zomwe zaperekedwa muzogulitsa
Buku la ogwiritsa ntchito kuti mudziwe zofunikira za DDR AXI
Arbiter. Onetsetsani kuti gawo la hardware likhoza kukhazikitsidwa
mkati mwazinthu zomwe zilipo.
Potsatira malangizowa, mutha kugwiritsa ntchito bwino DDR
Chigawo cha Hardware cha AXI Arbiter cha kubisa kwa data ya pixel yamavidiyo ndi
processing mu mavidiyo ntchito.
Chithunzi cha UG0644
DDR AXI Arbiter
February 2018
DDR AXI Arbiter
Zamkatimu
1 Revision History …………………………………………………………………………………………………………………….. 1
1.1 Kubwereza 5.0 …………………………………………………………………………………………………………………………… 1 1.2 Kubwereza 4.0 ……………………………………………………………………………………………………………………………………………………………………………………………. 1 1.3 Kubwereza 3.0 ………………………………………………………………………………………………………………………………………………………………………………………… 1 1.4 Kubwereza 2.0 ……………………………………………………………………………………………………………………………………………………………………………………………. 1 1.5 Kubwereza 1.0 ………………………………………………………………………………………………………………………………………………………………………………………………. 1
2 Chiyambi ………………………………………………………………………………………………………………………….. 2 3 Hardware Kukonzekera ………………………………………………………………………………………………………
3.1 Kufotokozera Mapangidwe …………………………………………………………………………………………………………….. 3 3.2 Configuration Parameters ……… …………………………………………………………………………………………………. 5 3.3 Zithunzi za Nthawi …………………………………………………………………………………………………………………. 13 3.4 Testbench ……………………………………………………………………………………………………….. 14
3.5.1 Simulating MSS SmartDesign ……………………………………………………………………………………………………. 25 3.5.2 Simulating Testbench ……………………………………………………………………………………………………………. 30 3.6 Kagwiritsidwe Ntchito Zothandizira ……………………………………………………………………………………………………………….. 31
UG0644 Upangiri Wogwiritsa Ntchito 5.0
DDR AXI Arbiter
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Mbiri Yobwereza
Mbiri yokonzanso ikufotokoza zosintha zomwe zidakhazikitsidwa muzolemba. Zosinthazo zandandalikidwa ndi kubwereza, kuyambira ndi zofalitsa zamakono.
1.1
Kusintha kwa 5.0
Pokonzanso 5.0 ya chikalatachi, gawo la Resource Utilization ndi Resource Utilization Report
zidasinthidwa. Kuti mudziwe zambiri, onani Kugwiritsa Ntchito Zothandizira (onani tsamba 31).
1.2
Kusintha kwa 4.0
Zotsatirazi ndi chidule cha zosintha mu revision 4.0 ya chikalata ichi.
Onjezani magawo a testbench patebulo. Kuti mudziwe zambiri, onani Configuration Parameters (onani tsamba 16) . Zowonjezera kuti muyesere pachimake pogwiritsa ntchito testbench. Kuti mudziwe zambiri, onani Testbench (onani tsamba 16). Kusintha kwa Resource Utilization pamitengo ya DDR AXI Arbiter patebulo. Kuti mudziwe zambiri, onani Kugwiritsa Ntchito Zothandizira (onani tsamba 31).
1.3
Kusintha kwa 3.0
Zotsatirazi ndi chidule cha zosintha mu revision 3.0 ya chikalata ichi.
Zowonjezera za 8-bit zolembera tchanelo 1 ndi 2. Kuti mudziwe zambiri, onani Kufotokozera Kwamapangidwe (onani tsamba 3). Kusinthidwa gawo la Testbench. Kuti mudziwe zambiri, onani Testbench (onani tsamba 16).
1.4
Kusintha kwa 2.0
Pokonzanso 2.0 ya chikalatachi, ziwerengero ndi matebulo muzosinthidwa mu gawo la Testbench.
Kuti mudziwe zambiri, onani Testbench (onani tsamba 16).
1.5
Kusintha kwa 1.0
Revision 1.0 inali yoyamba kusindikizidwa kwa chikalatachi
UG0644 Upangiri Wogwiritsa Ntchito 5.0
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DDR AXI Arbiter
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Mawu Oyamba
Memory ndi gawo lofunikira pamakanema aliwonse ndi makanema ojambula. Amagwiritsidwa ntchito kubisa data ya pixel yamavidiyo. Mmodzi wamba wamba wakale wakaleample ndi ma buffers a chimango momwe data yonse ya pixel ya kanema ya chimango imasungidwa kukumbukira.
Dual data rate (DDR) -synchronous DRAM (SDRAM) ndi chimodzi mwazokumbukiro zomwe zimagwiritsidwa ntchito nthawi zambiri pamakanema opangira mavidiyo. SDRAM imagwiritsidwa ntchito chifukwa cha liwiro lake lomwe limafunikira pakukonza mwachangu pamakina amakanema.
Chithunzi chotsatira chikuwonetsa wakaleample la chithunzi cha mulingo wadongosolo la DDR-SDRAM memory yolumikizana ndi pulogalamu yamavidiyo.
Chithunzi 1 · DDR-SDRAM Memory Interfacing
Mu Microsemi SmartFusion®2 System-on-Chip (SoC), pali ma controller awiri a DDR omwe ali ndi 64-bit advanced extensible interface (AXI) ndi 32-bit advanced high-performance bus (AHB) yolumikizira akapolo kupita kumunda. nsalu yotchinga (FPGA). Mawonekedwe apamwamba a AXI kapena AHB amafunikira kuti muwerenge ndikulemba kukumbukira kwa DDR-SDRAM komwe kumalumikizidwa ndi olamulira a pa-chip DDR.
UG0644 Upangiri Wogwiritsa Ntchito 5.0
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DDR AXI Arbiter
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Kukhazikitsa kwa Hardware
3.1
Kufotokozera Kwapangidwe
DDR AXI Arbiter imapereka mawonekedwe apamwamba a 64-bit AXI kwa DDR-SDRAM olamulira pa-chip.
Zida za SmartFusion2. DDR AXI Arbiter ili ndi mayendedwe anayi owerengera ndi njira ziwiri zolembera ku
logic ya ogwiritsa ntchito. The block arbitrates pakati pa njira zinayi zowerengera kuti apereke mwayi wowerengera AXI
njira m'njira yozungulira robin. Malingana ngati pempho lowerengedwa la master 1 liri lalitali, AXI
Read Channel yaperekedwa kwa iyo. Werengani tchanelo 1 chili ndi makulidwe okhazikika a 24-bit. Werengani mayendedwe 2, 3,
ndipo 4 ikhoza kukhazikitsidwa ngati 8-bit, 24-bit, kapena 32-bit deta yotulutsa m'lifupi. Izi zimasankhidwa ndi global
configuration parameter.
Chotchingacho chimagwirizanitsanso pakati pa njira ziwiri zolembera kuti zitheke kupeza njira yolembera ya AXI mozungulira. Njira zonse zolembera zili ndi zofunikira zofanana. Lembani tchanelo 1 ndi 2 zitha kukhazikitsidwa ngati 8-bit, 24-bit, kapena 32-bit data wide.
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DDR AXI Arbiter
Chithunzi chotsatira chikuwonetsa chithunzi chapamwamba cha DDR AXI Arbiter. Chithunzi 2 · Chithunzi cha Block-Level Block cha DDR AXI Arbiter Block
UG0644 Upangiri Wogwiritsa Ntchito 5.0
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DDR AXI Arbiter
Chithunzi chotsatira chikuwonetsa chojambula chapamwamba kwambiri cha kachitidwe ka DDR AXI Arbiter block chojambulidwa mu chipangizo cha SmartFusion2. Chithunzi 3 · Chithunzi cha Block-Level Block cha DDR AXI Arbiter pa SmartFusion2 Chipangizo
3.2
Zolowetsa ndi Zotuluka
Gome lotsatirali likulemba zolowetsa ndi zotuluka za DDR AXI Arbiter.
Tebulo 1 · Madoko Olowetsa ndi Zotulutsa a DDR AXI Arbiter
Dzina la Signal RESET_N_I
Mayendedwe Olowera
M'lifupi
SYS_CLOCK_I BUFF_READ_CLOCK_I
Zolowetsa
rd_req_1_i rd_ack_o
Lowetsani Kutulutsa
rd_done_1_oyamba_kuwerenga_addr_1_i
Linanena bungwe Lowetsani
ma bytes_to_read_1_i
Zolowetsa
kanema_rdata_1_o
Zotulutsa
[(g_AXI_AWIDTH-1):0] [(g_RD_CHANNEL1_AXI_BUFF_ AWIDTH + 3) – 1 : 0] [(g_RD_CHANNEL1_VIDEO_DATA_WIDTH1):0]Kufotokozera
Chizindikiro chokhazikika chokhazikika chokhazikika kuti chipangidwe
Wotchi yoyang'anira
Lembani wotchi yowerengera mkati mwa tchanelo, ikuyenera kuwirikiza kawiri SYS_CLOCK_I pafupipafupi
Werengani pempho la Master 1
Kuvomereza kwa Arbiter kuti awerenge pempho kuchokera kwa Master 1
Werengani kumaliza kwa Master 1
Adilesi ya DDR kuchokera komwe kuwerenga kumayenera kuyambika kuti muwerenge tchanelo 1
Ma byte oti awerengedwe kuchokera pa tchanelo 1 chowerengedwa
Kutulutsa kwa data yamavidiyo kuchokera ku kanema wowerengera 1
UG0644 Upangiri Wogwiritsa Ntchito 5.0
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DDR AXI Arbiter
Dzina la Signal rdata_valid_1_o rd_req_2_i rd_ack_2_o
rd_done_2_oyamba_kuwerenga_addr_2_i
ma bytes_to_read_2_i
kanema_rdata_2_o
rdata_valid_2_o rd_req_3_i rd_ack_3_o
rd_done_3_oyamba_kuwerenga_addr_3_i
ma bytes_to_read_3_i
kanema_rdata_3_o
rdata_valid_3_o rd_req_4_i rd_ack_4_o
rd_done_4_oyamba_kuwerenga_addr_4_i
ma bytes_to_read_4_i
kanema_rdata_4_o
rdata_valid_4_o wr_req_1_i wr_ack_1_o
wr_done_1_o kuyamba_write_addr_1_i
mabayiti_kuti_lemba_1_i
kanema_wdata_1_i
wdata_valid_1_i wr_req_2_i
Kutulutsa Kwamayendedwe Kutulutsa
Linanena bungwe Lowetsani
Zolowetsa
Zotulutsa
Zotulutsa Zotulutsa
Linanena bungwe Lowetsani
Zolowetsa
Zotulutsa
Zotulutsa Zotulutsa
Linanena bungwe Lowetsani
Zolowetsa
Zotulutsa
Zotulutsa Zotulutsa
Linanena bungwe Lowetsani
Zolowetsa
Zolowetsa
Zolowetsa
M'lifupi
[(g_AXI_AWIDTH-1):0] [(g_RD_CHANNEL2_AXI_BUFF_AWIDTH + 3) – 1 : 0] [(g_RD_CHANNEL2_VIDEO_DATA_WIDTH1):0] [(g_AXI_AWIDTH-1)_FFRID_0):3] – 3 : 1] [(g_RD_CHANNEL0_VIDEO_DATA_WIDTH3 ):1] [(g_AXI_AWIDTH-0):1] [(g_RD_CHANNEL0_AXI_BUFF_AWIDTH + 4) – 3 : 1] [(g_RD_CHANNEL0_VIDEO_DATA_WIDTH4):1] [(g_AXI_AWID0_BU_X_1) + 0) – 1:3 ] [(g_WR_CHANNEL1_VIDEO_DATA_WIDTH0):1]
Kufotokozera Werengani deta yovomerezeka kuchokera ku tchanelo chowerengera 1 Werengani pempho lochokera kwa Master 2 Arbiter kuvomereza kuti muwerenge pempho lochokera kwa Master 2 Werengani kumaliza kwa Master 2 DDR adilesi kuchokera pomwe iyenera kuyambika kuti tchanelo 2 Byte liwerengedwe kuchokera ku data yowerengera tchanelo 2 zotuluka kuchokera ku tchanelo chowerenga 2 Werengani deta yovomerezeka kuchokera ku tchanelo chowerengera 2 Werengani pempho lochokera kwa Master 3 Arbiter kuvomereza kuti muwerenge pempho lochokera kwa Master 3 Werengani kumaliza ku Master 3 DDR adilesi pomwe iyenera kuyambika kuti muwerenge tchanelo 3 Byte kuti awerengedwe. tchanelo 3 Kutulutsa kwa data ya kanema kuchokera ku tchanelo chowerengera 3 Werengani zomwe zili zovomerezeka kuchokera ku tchanelo chowerengedwa 3 Werengani pempho lochokera kwa Master 4 Arbiter kuvomereza kuti muwerenge pempho lochokera kwa Master 4 Werengani kumaliza ku adilesi ya Master 4 DDR kuchokera pomwe iyenera kuyambika kuti tchanelo 4 Byte likhale werengani kuchokera ku kuwerenga tchanelo 4 Kutulutsa kwa data ya kanema kuchokera ku njira yowerengera 4 Werengani deta yovomerezeka kuchokera ku njira yowerengera 4 Lembani pempho lochokera kwa Master 1 Arbiter kuvomereza kuti mulembe pempho kuchokera kwa Master 1 Lembani kumaliza kwa Master 1 DDR adilesi komwe kulembera kuyenera kuchitika kuchokera pa njira yolembera 1 Ma Byte oti alembedwe kuchokera ku tchanelo 1 Kanema wa data Kulowetsa kuti mulembe tchanelo 1
Lembani zomwe zilipo kuti mulembe tchanelo 1 Lembani pempho kuchokera kwa Master 1
UG0644 Upangiri Wogwiritsa Ntchito 5.0
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DDR AXI Arbiter
Dzina la Signal wr_ack_2_o
Kutulutsa kwamayendedwe
wr_done_2_o kuyamba_write_addr_2_i
Linanena bungwe Lowetsani
mabayiti_kuti_lemba_2_i
Zolowetsa
kanema_wdata_2_i
Zolowetsa
wdata_valid_2_i AXI I/F siginecha Werengani Adilesi Channel m_arid_o
Lowetsani Kutulutsa
m_araddr_o
Zotulutsa
m_arlen_o
Zotulutsa
m_arsize_o m_arburst_o
Zotulutsa
m_arlock_o
Zotulutsa
m_arcache_o
Zotulutsa
m_arprot_o
Zotulutsa
M'lifupi
[(g_AXI_AWIDTH-1):0] [(g_WR_CHANNEL2_AXI_BUFF_AWIDTH + 3) – 1 : 0] [(g_WR_CHANNEL2_VIDEO_DATA_WIDTH1):0]
Kufotokozera Arbiter kuvomereza kuti alembe pempho kuchokera kwa Master 2 Lembani kumaliza kwa Master 2 DDR adiresi yomwe kulembera kuyenera kuchitika kuchokera pa njira yolembera 2 Bytes kuti ilembedwe kuchokera ku njira yolembera 2 Data data Input to write channel 2
Lembani deta yovomerezeka kuti mulembe tchanelo 2
Werengani ID ya adilesi. Chizindikiritso tag kwa gulu lowerengera la ma adilesi azizindikiro.
Werengani adilesi. Imapereka adilesi yoyambira yowerengera. Adilesi yoyambira yokha ya kuphulika imaperekedwa.
Kuphulika kutalika. Amapereka chiwerengero chenicheni cha kusamutsidwa mu kuphulika. Izi zimatsimikizira kuchuluka kwa kusamutsa kwa data komwe kumakhudzana ndi adilesi
Kuphulika kukula. Kukula kwa mayendedwe aliwonse pakuphulika
Mtundu wophulika. Kuphatikizidwa ndi chidziwitso cha kukula, tsatanetsatane wa momwe adilesi ya kusamutsa kulikonse mkati mwa kuphulika kumawerengedwera.
Zokhazikika ku 2'b01 ku adilesi yowonjezereka
Mtundu wa loko. Amapereka zambiri za mawonekedwe a atomiki a kusamutsa.
Zokhazikika ku 2'b00 ku Normal Access
Mtundu wa cache. Amapereka zambiri zokhuza zosunga zosungika za kusamutsa.
Zokhazikika ku 4'b0000 à Non-cacheable and non-bufferable
Mtundu wa chitetezo. Amapereka zidziwitso zamagawo achitetezo pazogulitsa.
Zokhazikika ku 3'b000 à Normal, mwayi wotetezedwa wa data
UG0644 Upangiri Wogwiritsa Ntchito 5.0
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DDR AXI Arbiter
Dzina la Signal m_arvalid_o
Kutulutsa kwamayendedwe
M'lifupi
m_kale_ine
Zolowetsa
Werengani Data Channel
m_ndi_i
Zolowetsa
[3:0]m_rdata_ine m_rresp_i
m_rlast_i m_rvalid_i
Zolowetsa
[(g_AXI_DWIDTH-1):0] [1:0]Zolowetsa
m_ready_o
Zotulutsa
Lembani Adilesi Channel
m_awid_o
Zotulutsa
m_waddr_o
Zotulutsa
[3:0] [(g_AXI_AWIDTH-1):0]UG0644 Upangiri Wogwiritsa Ntchito 5.0
Kufotokozera Werengani adilesi ndiyovomerezeka.
Pamene HIGH, adilesi yowerengedwa ndi zowongolera ndizovomerezeka ndikukhalabe pamwamba mpaka chizindikiro chovomereza adilesi, m_arready, chikukwera.
`1' = Adilesi ndi zidziwitso zowongolera ndizovomerezeka
`0' = Adilesi ndi zidziwitso zowongolera sizolondola. Werengani adilesi yakonzeka. Kapolo ali wokonzeka kuvomereza adilesi ndi zizindikiro zowongolera:
1 = kapolo wokonzeka
0 = kapolo wosakonzeka.
Werengani ID tag. ID tag wa gulu lowerengedwa la data la zizindikiro. Mtengo wa m_rid umapangidwa ndi Kapolo ndipo uyenera kufanana ndi mtengo wa m_rid wa zomwe akuwerengazo. Werengani zambiri. Werengani yankho.
Mkhalidwe wa kusamutsidwa kowerengedwa. Mayankho ovomerezeka ndi OK, EXOKAY, SLVERR, ndi DECERR. Werengani komaliza.
Kusamutsidwa komaliza mu kuwerenga kwambiri. Werengani zovomerezeka. Zofunikira zowerengera zilipo ndipo kutumiza kowerengera kumatha kumaliza:
1 = werengani zomwe zilipo
0 = kuwerenga zomwe sizikupezeka. Werengani mwakonzeka. Master akhoza kuvomereza zomwe zawerengedwa komanso mayankho:
1= master okonzeka
0 = master not ready.
Lembani ID ya adilesi. Chizindikiritso tag kwa gulu lolembera ma adilesi azizindikiro. Lembani adilesi. Imapereka adilesi yakusamutsa koyamba pakanthawi kochepa. Zizindikiro zowongolera zomwe zimagwirizana zimagwiritsidwa ntchito kudziwa maadiresi a kusamutsidwa kotsalira pakuphulika.
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DDR AXI Arbiter
Dzina la Signal m_awlen_o
Kutulutsa kwamayendedwe
Kukula [3:0]
m_awsize_o
Zotulutsa
[2:0]m_awburst_o
Zotulutsa
[1:0]m_awlock_o
Zotulutsa
[1:0]m_awcache_o
Zotulutsa
[3:0]m_awprot_o
Zotulutsa
[2:0]m_awvalid_o
Zotulutsa
Kufotokozera
Kuphulika kutalika. Amapereka chiwerengero chenicheni cha kusamutsidwa mu kuphulika. Izi zimatsimikizira kuchuluka kwa kusamutsa kwa data komwe kumakhudzana ndi adilesi.
Kuphulika kukula. Kukula kwa mayendedwe aliwonse pakuphulika. Ma Byte lane strobe amawonetsa ndendende njira zomwe ziyenera kusinthidwa.
Zokhazikika ku 3'b011 à 8 bytes pakusamutsa kwa data kapena kusamutsa kwa 64-bit
Mtundu wophulika. Kuphatikizidwa ndi chidziwitso cha kukula, tsatanetsatane wa momwe adilesi ya kusamutsa kulikonse mkati mwa kuphulika kumawerengedwera.
Zokhazikika ku 2'b01 ku adilesi yowonjezereka
Mtundu wa loko. Amapereka zambiri za mawonekedwe a atomiki a kusamutsa.
Zokhazikika ku 2'b00 ku Normal Access
Mtundu wa cache. Imawonetsa kusungika, kusungika, kulemba, kulemba, ndi kugawa zomwe zachitikazo.
Zokhazikika ku 4'b0000 à Non-cacheable and non-bufferable
Mtundu wa chitetezo. Imawonetsa mulingo wabwinobwino, wamwayi, kapena wotetezedwa pamalondawo komanso ngati ntchitoyo ndi mwayi wopeza data kapena mwayi wofikira malangizo.
Zokhazikika ku 3'b000 à Normal, mwayi wotetezedwa wa data
Lembani adilesi yoyenera. Imawonetsa adilesi yoyenera yolembera ndi chiwongolero
zambiri zilipo:
1 = adilesi ndi chidziwitso chowongolera chomwe chilipo
0 = adilesi ndi chidziwitso chowongolera sichikupezeka. Adilesi ndi zidziwitso zowongolera zimakhalabe zokhazikika mpaka adilesi yovomereza chizindikiro, m_awready, ipita KWAMBIRI.
UG0644 Upangiri Wogwiritsa Ntchito 5.0
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DDR AXI Arbiter
Dzina la Signal m_awready_i
Mayendedwe Olowera
M'lifupi
Lembani Data Channel
m_wid_o
Zotulutsa
[3:0]m_wdata_o m_wstrb_o
Zotulutsa
[(g_AXI_DWIDTH-1):0]AXI_DWDITH magawo[7:0]
m_wlast_o m_wvalid_o
Zotulutsa
m_wready_i
Zolowetsa
Lembani Mayankho Channel Signals
m_bid_i
Zolowetsa
[3:0]m_bresp_i m_bvalid_i
Zolowetsa
[1:0]Zolowetsa
m_bready_o
Zotulutsa
Kufotokozera Lembani adilesi yokonzeka. Zikuwonetsa kuti kapoloyo ndi wokonzeka kuvomereza adilesi ndi zizindikiro zowongolera:
1 = kapolo wokonzeka
0 = kapolo wosakonzeka.
Lembani ID tag. ID tag wa kulemba deta kusamutsa. Mtengo wa m_wid uyenera kufanana ndi mtengo wa m_awid wa zolembazo. Lembani deta
Lembani strobes. Chizindikirochi chikuwonetsa mayendedwe a byte omwe angasinthidwe mu kukumbukira. Pali zilembo zisanu ndi zitatu zilizonse za basi yolemba data Lembani komaliza. Kusintha komaliza pakuphulika kolemba. Lembani zovomerezeka. Zolemba zovomerezeka ndi ma strobe zilipo:
1 = lembani deta ndi ma strobes omwe alipo
0 = lembani deta ndi strobes palibe. Lembani okonzeka. Kapolo amatha kuvomera zolemba: 1 = kapolo wokonzeka
0 = kapolo wosakonzeka.
ID Yankho. Chizindikiritso tag ya kulemba yankho. Mtengo wa m_bid uyenera kufanana ndi mtengo wa m_awid wa zomwe kapolo akuyankha. Lembani yankho. Momwe mungalembetsere. Mayankho ovomerezeka ndi OK, EXOKAY, SLVERR, ndi DECERR. Lembani yankho lolondola. Yankho lovomerezeka likupezeka:
1 = lembani yankho likupezeka
0 = kulemba yankho silikupezeka. Yankho lokonzeka. Master atha kuvomera zomwe akuyankha.
1 = mbuye wokonzeka
0 = master not ready.
Chithunzi chotsatira chikuwonetsa chithunzi chamkati cha DDR AXI arbiter.
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Chithunzi chotsatira chikuwonetsa chithunzi chamkati cha DDR AXI arbiter. Chithunzi 4 · Chithunzi cha Block Internal cha DDR AXI Arbiter
Njira iliyonse yowerengera imayambika ikapeza chizindikiro cholowera kwambiri pa read_req_(x)_i. Ndiye izo
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Njira iliyonse yowerengera imayambika ikapeza chizindikiro cholowera kwambiri pa read_req_(x)_i. Ndiye samples adilesi yoyambira ya AXI ndi ma byte kuti muwerenge zolowetsa zomwe zimalowetsedwa kuchokera kwa mbuye wakunja. Kanemayo amavomereza katswiri wakunja potembenuza read_ack_(x)_o. Kanemayo amakonza zolowetsa ndikupanga zochitika za AXI kuti muwerenge zambiri kuchokera ku DDR-SDRAM. Zomwe zimawerengedwa mu mtundu wa 64-bit AXI zimasungidwa mu buffer yamkati. Zomwe zimafunikira zitawerengedwa ndikusungidwa mu buffer yamkati, gawo la un-packer limayatsidwa. Module ya un-packer imatsegula liwu lililonse la 64-bit mu kutalika kwa data yomwe ikufunika panjirayo ya ex.ampLe ngati tchanelocho chakonzedwa kukhala 32-bit yotulutsa deta m'lifupi, liwu lililonse la 64-bit limatumizidwa ngati mawu awiri otulutsa 32-bit. Kwa tchanelo 1 chomwe ndi tchanelo cha 24-bit, chosapakira chimamasula liwu lililonse la 64-bit mu data ya 24-bit. Popeza 64 si kuchuluka kwa 24, cholembera kuti muwerenge tchanelo 1 chimaphatikiza gulu la mawu atatu a 64-bit kuti apange mawu asanu ndi atatu a data 24-bit. Izi zimayika chopinga pa kuwerenga tchanelo 1 kuti ma byte a data omwe adafunsidwa ndi master wakunja ayenera kugawidwa ndi 8. Werengani ma tchanelo 2, 3, ndi 4 akhoza kukhazikitsidwa ngati 8-bit, 24bit, ndi 32-bit data wide, yomwe ndi kutsimikiziridwa ndi g_RD_CHANNEL(X) _VIDEO_DATA_WIDTH zochunira zapadziko lonse lapansi. Ngati asinthidwa kukhala 24-bit, zopinga zomwe tazitchulazi zitha kugwiritsidwanso ntchito kwa aliyense waiwo. Koma ngati asinthidwa kukhala 8-bit kapena 32-bit, palibe choletsa ngati 64 ndi kuchuluka kwa 32 ndi 8. Muzochitika izi, liwu lililonse la 64-bit limatulutsidwa m'mawu awiri a data 32-bit kapena eyiti 8. - mawu ochepa a data.
Werengani Channel 1 imatsegula mawu a data a 64-bit omwe amawerengedwa kuchokera ku DDR-SDRAM kupita ku mawu a data a 24-bit m'magulu a mawu 48 64-bit, ndiye nthawi iliyonse mawu 48 64-bit amapezeka mu buffer yamkati ya tchanelo 1, un-packer akuyamba kuwamasula kuti apereke data ya 24-bit. Ngati ma byte omwe afunsidwa kuti muwerenge ali osakwana mawu a 48 64-bit, chosungira chimatsegulidwa kokha deta yonse ikawerengedwa kuchokera mu DDR-SDRAM. M'matchanelo atatu otsala omwe amawerengedwa, osapakira amayamba kutumiza zowerengera pokhapokha kuchuluka komwe adafunsidwa kuwerengedwa kuchokera ku DDR-SDRAM.
Pamene tchanelo chowerengedwa chakonzedwera 24-bit kutulutsa m'lifupi, adilesi yoyambira iyenera kulumikizidwa ndi malire a 24-bytes. Izi zimafunikira kuti mukwaniritse zoletsa kuti wosapakira amatsegula gulu la mawu atatu a 64-bit kuti apange mawu asanu ndi atatu a 24-bit.
Makanema onse owerengera amapanga zomwe zawerengedwa kwa mbuye wakunja pambuyo poti ma byte omwe afunsidwa atumizidwa kwa mbuye wakunja.
Pakakhala ma tchanelo, mbuye wakunja amayenera kuyika zomwe zikufunika kunjira inayake. Njira yolembera imatenga zomwe zalowa ndikuziyika m'mawu a 64-bit ndikuzisunga mosungira mkati. Deta yofunikira ikasungidwa, mbuye wakunja ayenera kupereka pempho lolemba limodzi ndi adilesi yoyambira ndi ma byte kuti alembe. Pa sampKulowetsa izi, njira yolembera imavomereza mbuye wakunja. Pambuyo pake, njirayo imapanga zolemba za AXI kuti zilembe zomwe zasungidwa mu DDR-SDRAM. Njira zonse zolembera zimapanga zomwe zalembedwa kwa mbuye wakunja pomwe ma byte omwe adafunsidwa alembedwa mu DDR-SDRAM. Pempho lolemba litaperekedwa ku njira iliyonse yolembera, zatsopano siziyenera kulembedwa munjira yolembera, mpaka kukwaniritsidwa kwaposachedwa kuwonetsedwe ndi chitsimikiziro cha wr_done_(x)_o
Kulemba tchanelo 1 ndi 2 kutha kusinthidwa kukhala 8-bit, 24-bit, ndi 32-bit data wide, zomwe zimatsimikiziridwa ndi g_WR_CHANNEL(X)_VIDEO_DATA_WIDTH configuration parameter. Ngati asinthidwa kukhala 24bit, ndiye kuti ma byte oti alembedwe ayenera kukhala angapo mwa asanu ndi atatu popeza wonyamula mkati amanyamula mawu asanu ndi atatu a 24-bit kuti apange mawu atatu a data 64-bit. Koma ngati asinthidwa kukhala 8-bit kapena 32-bit, palibe choletsa chotero.
Pa njira ya 32-bit, mawu osachepera awiri a 32-bit ayenera kuwerengedwa. Pa njira ya 8-bit, mawu osachepera 8-bit ayenera kuwerengedwa, chifukwa palibe padding yoperekedwa ndi gawo la arbiter. M'matchanelo onse owerengera ndi kulemba, kuya kwa ma buffers amkati kumachulukitsa kuchuluka kwa mawonekedwe opingasa. Kuzama kwa buffer yamkati kumawerengedwa motere:
g_RD_CHANNEL(X)_HORIZONTAL_RESOLUTION* g_RD_CHANNEL(X)_VIDEO_DATA_WIDTH * g_RD_CHANNEL(X)_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Kumene, X = Nambala ya Channel
Kukula kwa buffer kwamkati kumatsimikiziridwa ndi AXI data bus wide ndiko kuti, configuration parameter
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Kukula kwa buffer kwamkati kumatsimikiziridwa ndi AXI data bus wide ndiko kuti, configuration parameter g_AXI_DWIDTH.
Kuwerengera ndi kulemba kwa AXI kumachitika molingana ndi mafotokozedwe a ARM AMBA AXI. Kukula kwapang'onopang'ono kwa kusamutsa deta kulikonse kumakhazikika ku 64-bit. Chidacho chimapanga zochitika za AXI zokhazikika kutalika kwa ma beats 16. Chotchingacho chimayang'ananso ngati kuphulika kumodzi kumadutsa malire a AXI a 4 KByte. Ngati kuphulika kumodzi kudutsa malire a 4 KByte, kuphulika kumagawanika kukhala 2 kuphulika pamalire a 4 KByte.
3.3
Zosintha Zosintha
Gome lotsatirali limatchula magawo osinthika omwe amagwiritsidwa ntchito pokhazikitsa zida za DDR AXI Arbiter. Izi ndizomwe zimapangidwira ndipo zimatha kusiyanasiyana kutengera zomwe mukufuna.
Gulu 2 · Zosintha Zosintha
Dzina g_AXI_AWIDTH g_AXI_DWIDTH g_RD_CHANNEL1_AXI_BUFF_AWIDTH
g_RD_CHANNEL2_AXI_BUFF_AWIDTH
g_RD_CHANNEL3_AXI_BUFF_AWIDTH
g_RD_CHANNEL4_AXI_BUFF_AWIDTH
g_WR_CHANNEL1_AXI_BUFF_AWIDTH
g_WR_CHANNEL2_AXI_BUFF_AWIDTH
g_RD_CHANNEL1_HORIZONTAL_RESOLUTION g_RD_CHANNEL2_HORIZONTAL_RESOLUTION g_RD_CHANNEL3_HORIZONTAL_RESOLUTION g_RD_CHANNEL4_HORIZONTAL_RESOLUTION g_WR_CHANNEL1_HORIZONTAL_RESOLUTION g_RD_CHANNEL2_HORIZONTAL_RESOLUTION g_WR_CHANNEL1_HORIZONTAL_RESOLUZONTAL_RESOLUTION_GLONNEL_ RD_CHANNEL2_VIDEO_DATA_WIDTH g_RD_CHANNEL3_VIDEO_DATA_WIDTH g_RD_CHANNEL4_VIDEO_DATA_WIDTH g_RD_CHANNEL1_VIDEO_DATA_WIDTH g_WR_CHANNEL2_VIDEO_DATA_WIDTH g_WR_CHANNELD_CHANNELD_BUDTH_G_WR_CHANNELD_CHANNEL1 AGE
Kufotokozera
AXI m'lifupi mwa basi
AXI data bus wide
M'lifupi mwa mabasi omwe amawerengedwa mkati mwa Channel 1, yomwe imasunga deta yowerengera ya AXI.
M'lifupi mwa mabasi omwe amawerengedwa mkati mwa Channel 2, yomwe imasunga deta yowerengera ya AXI.
M'lifupi mwa mabasi omwe amawerengedwa mkati mwa Channel 3, yomwe imasunga deta yowerengera ya AXI.
M'lifupi mwa mabasi omwe amawerengedwa mkati mwa Channel 4, yomwe imasunga deta yowerengera ya AXI.
M'lifupi mwa mabasi omwe amalembedwa mkati mwa Channel 1 buffer, yomwe imasunga zolemba za AXI.
M'lifupi mwa mabasi omwe amalembedwa mkati mwa Channel 2 buffer, yomwe imasunga zolemba za AXI.
Kanema wowoneka mopingasa kuti awerenge Channel 1
Kanema wowoneka mopingasa kuti awerenge Channel 2
Kanema wowoneka mopingasa kuti awerenge Channel 3
Kanema wowoneka mopingasa kuti awerenge Channel 4
Kanema akuwonetsa kusanja kopingasa kuti alembe Channel 1
Kanema akuwonetsa kusanja kopingasa kuti alembe Channel 2
Werengani Channel 1 kanema linanena bungwe pokha m'lifupi
Werengani Channel 2 kanema linanena bungwe pokha m'lifupi
Werengani Channel 3 kanema linanena bungwe pokha m'lifupi
Werengani Channel 4 kanema linanena bungwe pokha m'lifupi
Lembani Channel 1 kanema Kulowetsa pang'ono m'lifupi.
Lembani Channel 2 kanema Kulowetsa pang'ono m'lifupi.
Kuzama kwa buffer yamkati kuti muwerenge Channel 1 malinga ndi kuchuluka kwa mizere yopingasa yowonetsera. Kuya kwa bafa ndi g_RD_CHANNEL1_HORIZONTAL_RESOLUTION * g_RD_CHANNEL1_VIDEO_DATA_WIDTH * g_RD_CHANNEL1_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
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3.4
Dzina g_RD_CHANNEL2_BUFFER_LINE_STORAGE g_RD_CHANNEL3_BUFFER_LINE_STORAGE g_RD_CHANNEL4_BUFFER_LINE_STORAGE g_WR_CHANNEL1_BUFFER_LINE_STORAGE g_WR_CHANNEL2_BUFFER_LINE_STORAGE
Kufotokozera
Kuzama kwa buffer yamkati kuti muwerenge Channel 2 malinga ndi kuchuluka kwa mizere yopingasa yowonetsera. Kuya kwa bafa ndi g_RD_CHANNEL2_HORIZONTAL_RESOLUTION * g_RD_CHANNEL2_VIDEO_DATA_WIDTH * g_RD_CHANNEL2_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Kuzama kwa buffer yamkati kuti muwerenge Channel 3 malinga ndi kuchuluka kwa mizere yopingasa yowonetsera. Kuya kwa bafa ndi g_RD_CHANNEL3_HORIZONTAL_RESOLUTION * g_RD_CHANNEL3_VIDEO_DATA_WIDTH * g_RD_CHANNEL3_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Kuzama kwa buffer yamkati kuti muwerenge Channel 4 malinga ndi kuchuluka kwa mizere yopingasa yowonetsera. Kuya kwa bafa ndi g_RD_CHANNEL4_HORIZONTAL_RESOLUTION * g_RD_CHANNEL4_VIDEO_DATA_WIDTH * g_RD_CHANNEL4_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Kuzama kwa buffer yamkati polemba Channel 1 malinga ndi kuchuluka kwa mizere yopingasa yowonetsera. Kuya kwa bafa ndi g_WR_CHANNEL1_HORIZONTAL_RESOLUTION * g_WR_CHANNEL1_VIDEO_DATA_WIDTH * g_WR_CHANNEL1_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Kuzama kwa buffer yamkati polemba Channel 2 malinga ndi kuchuluka kwa mizere yopingasa yowonetsera. Kuya kwa bafa ndi g_WR_CHANNEL2_HORIZONTAL_RESOLUTION * g_WR_CHANNEL2_VIDEO_DATA_WIDTH * g_WR_CHANNEL2_BUFFER_LINE_STORAGE) / g_AXI_DWIDTH
Zithunzi za Nthawi
Chithunzi chotsatirachi chikuwonetsa kulumikizana kwa zopempha zowerengera ndi kulemba, ma adilesi oyambira, ma byte oti muwerenge kapena kulemba zolowa kuchokera kwa akatswiri akunja, kuwerenga kapena kulemba kuvomereza, ndikuwerenga kapena kulemba zomwe mwamaliza zomwe zaperekedwa ndi arbiter.
Chithunzi 5 · Chithunzi cha Nthawi ya Zizindikiro Zogwiritsidwa Ntchito Polemba/Kuwerenga kudzera mu Chiyankhulo cha AXI
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Chithunzi chotsatirachi chikuwonetsa kugwirizana pakati pa kuyika kwa deta yolemba kuchokera kwa mbuye wakunja pamodzi ndi kuyika kwa deta komwe kuli koyenera kwa njira zonse zolembera. Chithunzi 6 · Chithunzi cha Nthawi Yolemba mu Zosungira Zamkati
Chithunzi chotsatirachi chikuwonetsa kugwirizana pakati pa kuwerengera kwa deta yowerengedwa kwa mbuye wakunja pamodzi ndi zotsatira za deta zovomerezeka pazitsulo zonse zowerengera 2, 3, ndi 4. Chithunzi 7 · Chithunzi cha Nthawi ya Deta Yolandiridwa kupyolera mu DDR AXI Arbiter for Read Channels 2, 3 ,ndi 4
Chithunzi chotsatirachi chikuwonetsa kulumikizana pakati pa zomwe zidawerengedwa zomwe zidawerengedwa pa Channel 1 pomwe g_RD_CHANNEL 1_HORIZONTAL_RESOLUTION ikuposa 128 (pano = 256). Chithunzi 8 · Chithunzi cha Nthawi ya Deta Yolandilidwa kudzera mu DDR AXI Arbiter Read Channel 1 (yokulirapo kuposa 128 byte)
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Chithunzi chotsatirachi chikuwonetsa kulumikizana pakati pa zomwe zidawerengedwa potulutsa Channel 1 pomwe g_RD_CHANNEL 1_HORIZONTAL_RESOLUTION ili yochepera kapena yofanana ndi 128 (pankhaniyi = 64). Chithunzi 9 · Chithunzi cha Nthawi ya Deta Yolandilidwa kudzera ku DDR AXI Arbiter Read Channel 1 (yochepera kapena yofanana ndi ma byte 128)
3.5
Testbench
Testbench imaperekedwa kuti iwonetse magwiridwe antchito a DDR Arbiter pachimake. Gome lotsatirali limatchula magawo omwe angakonzedwe molingana ndi pulogalamuyo.
Table 3 · Testbench Configuration Parameters
Dzina IMAGE_1_FILE_NAME IMAGE_2_FILE_NAME g_DATA_WIDTH WIDTH WIDTH HEIGHT
Kufotokozera Kulowetsa file dzina la fano kuti lilembedwe ndi kulemba njira 1 Input file dzina la chithunzi kuti lilembedwe ndi tchanelo 2 Kanema wa data wamtundu wa tchanelo chowerengera kapena cholembera Chokhazikika cha chithunzicho kuti chilembedwe ndikuwerengedwa ndi njira zolembera ndi zowerengera Kukhazikika kwa chithunzicho kuti chilembedwe ndikuwerengedwa ndi kulemba ndi kuwerenga. njira
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Njira zotsatirazi zikufotokozera momwe testbench imagwiritsidwira ntchito kutengera pachimake kudzera pa Libero SoC. 1. Pazenera la Design Flow, dinani kumanja Pangani SmartDesign ndikudina Thamangani kuti mupange SmartDesign.
Chithunzi 10 · Pangani SmartDesign
2. Lowetsani dzina la mapangidwe atsopano monga video_dma mu bokosi la zokambirana la Create New SmartDesign ndipo dinani OK. SmartDesign imapangidwa, ndipo chinsalu chimawonetsedwa kumanja kwa gawo la Design Flow.
Chithunzi 11 · Naming SmartDesign
3. Mu Catalog zenera, kukulitsa Mayankho-Video ndi kuukoka-ndi dontho SF2 DDR Memory Arbiter mu SmartDesign chinsalu.
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Chithunzi 12 · DDR Memory Arbiter mu Libero SoC Catalog
DDR Memory Arbiter Core ikuwonetsedwa, monga momwe tawonetsera pa chithunzi chotsatira. Dinani kawiri pachimake kuti mukonze arbiter ngati pakufunika.
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Chithunzi 13 · DDR Memory Arbiter Core mu SmartDesign Canvas
4. Sankhani madoko onse pachimake ndikudina-kumanja ndiyeno dinani Limbikitsani ku Top Level, monga momwe zikusonyezedwera mu
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4. Sankhani madoko onse a pachimake ndikudina kumanja ndikudina Limbikitsani Kumtunda Wapamwamba, monga momwe tawonetsera pachithunzichi. Chithunzi 14 · Limbikitsani ku Njira Yapamwamba Kwambiri
Onetsetsani kuti mukukweza madoko onse kuti akhale apamwamba musanadina chizindikiro cha chigawo chomwe chili pazida.
5. Dinani chizindikiro cha Pangani Chigawo mu SmartDesign toolbar, monga momwe chithunzichi chikusonyezera.
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5. Dinani chizindikiro cha Pangani Chigawo mu SmartDesign toolbar, monga momwe chithunzichi chikusonyezera. Chigawo cha SmartDesign chimapangidwa. Chithunzi 15 · Pangani Chigawo
6. Yendetsani ku View > Windows > Files. The Files dialog box ikuwonetsedwa. 7. Dinani kumanja chikwatu kayeseleledwe ndi kumadula Import Files, monga momwe tawonetsera pa chithunzi chotsatirachi.
Chithunzi 16 · Tengani File
8. Kuitanitsa chithunzi chokondoweza file, yendani ndikulowetsa chimodzi mwa izi files ndikudina Open.
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8. Kuitanitsa chithunzi chokondoweza file, yendani ndikulowetsa chimodzi mwa izi files ndikudina Open. a. A sampndi RGB_in.txt file amaperekedwa ndi testbench m'njira zotsatirazi:
..Project_namecomponentMicrosemiSolutionCore ddr_memory_arbiter 2.0.0Stimulus
Kutumiza kunja kwa sample test bench yolowetsa chithunzi, sakatulani ku sample testbench yolowetsa chithunzi file, ndipo dinani Open, monga momwe chithunzi chotsatirachi chikusonyezera. Chithunzi 17 · Chithunzi cholowetsa File Kusankha
b. Kuti mutenge chithunzi china, sakani ku chikwatu chomwe chili ndi chithunzi chomwe mukufuna file, ndikudina Open. Chokondoweza chazithunzi chotumizidwa kunja file zandandalikidwa pansi pa chikwatu kayeseleledwe, monga momwe chithunzi chotsatirachi. Chithunzi 18 · Chithunzi cholowetsa File mu Simulation Directory
9. Lowetsani ddr BFM files. Awiri files omwe ali ofanana ndi
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9. Lowetsani ddr BFM files. Awiri files omwe ali ofanana ndi DDR BFM - ddr3.v ndi ddr3_parameters.v amaperekedwa ndi testbench pa njira yotsatirayi: ..Project_namecomponentMicrosemiSolutionCoreddr_memory_arbiter 2.0.0Stimulus. Dinani kumanja chikwatu chikwatu ndi kusankha Import Files, ndiyeno sankhani BFM yomwe tatchulayi files. DDR BFM yotumizidwa kunja files alembedwa pansi pa zokondoweza, monga momwe tawonetsera pa chithunzi chotsatirachi. Chithunzi 19 · Zochokera kunja File
10. Yendetsani ku File > Tengani > Zina. The Import Files dialog box ikuwonetsedwa. Chithunzi 20 · Tengani Testbench File
11. Tengani testbench ndi gawo la MSS files (top_tb.cxf, mss_top_sb_MSS.cxf, mss_top.cxf, ndi mss
..Project_namecomponentMicrosemiSolutionCoreddr_memory_arbiter 2.0.0Stimulus
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Chithunzi 21 · Tengani Testbench ndi MSS Component Files
Chithunzi 22 · top_tb Created
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3.5.1
Kutengera MSS SmartDesign
Malangizo otsatirawa akufotokoza momwe mungatsatire MSS SmartDesign:
1. Dinani Design Hierarchy tabu ndikusankha Chigawo kuchokera pamndandanda wotsitsa wawonetsero. MSS SmartDesign yotumizidwa kunja ikuwonetsedwa.
2. Dinani kumanja mss_top pansi pa Ntchito ndikudina Tsegulani Chigawo, monga momwe chithunzichi chikusonyezera. Gawo la mss_top_sb_0 likuwonetsedwa.
Chithunzi 23 · Open Component
3. Dinani pomwepo mss_top_sb_0 chigawo ndikudina Konzani, monga momwe chithunzi chotsatirachi chikusonyezera.
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3. Dinani pomwepo mss_top_sb_0 chigawo ndikudina Konzani, monga momwe chithunzi chotsatirachi chikusonyezera. Chithunzi 24 · Konzani Chigawo
Zenera la MSS Configuration likuwonetsedwa, monga momwe chithunzi chotsatirachi chikusonyezera. Chithunzi 25 · MSS Configuration Window
4. Dinani Chotsatira kupyolera muzitsulo zonse zokonzekera, monga momwe tawonetsera pa chithunzi chotsatira.
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4. Dinani Chotsatira kupyolera muzitsulo zonse zokonzekera, monga momwe tawonetsera pa chithunzi chotsatira. Chithunzi 26 · Ma Tabu Okonzekera
MSS imakonzedwa pambuyo poti tabu ya Interrupts yakhazikitsidwa. Chithunzi chotsatira chikuwonetsa kupita patsogolo kwa Kusintha kwa MSS. Chithunzi 27 · MSS Configuration Window After Configuration
5. Dinani Kenako pambuyo kasinthidwe watha. Zenera la Memory Map likuwonetsedwa, monga momwe tawonetsera pachithunzichi.
Chithunzi 28 · Memory Map
6. Dinani kumaliza.
7. Dinani Pangani Chigawo ku SmartDesign toolbar kuti mupange MSS, monga momwe tawonetsera mu
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7. Dinani Pangani Chigawo kuchokera pa toolbar ya SmartDesign kuti mupange MSS, monga momwe chithunzichi chikusonyezera. Chithunzi 29 · Pangani Chigawo
8. Pazenera la Design Hierarchy, dinani kumanja mss_top pansi pa Ntchito ndikudina Khalani Monga Muzu, monga momwe chithunzichi chikusonyezera. Chithunzi 30 · Khazikitsani MSS ngati Muzu
9. Pazenera la Design Flow, kulitsani Verify Pre-synthesized Design pansi pa Pangani Design, dinani kumanja
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DDR AXI Arbiter
9. Pazenera la Design Flow, kulitsani Verify Pre-synthesized Design pansi pa Pangani Design, dinani kumanja kwa Sanzanitsa ndikudina Open Interactively. Imafanana ndi MSS. Chithunzi 31 · Tsanzirani Mapangidwe Osasinthika
10. Dinani Ayi ngati uthenga wochenjeza ukuwonetsedwa kuti ugwirizane ndi kukondoweza kwa Testbench ndi MSS. 11. Tsekani zenera la Modelsim mutatha kuyerekezera.
Chithunzi 32 · Zenera Loyerekeza
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DDR AXI Arbiter
3.5.2
Kuyerekeza Testbench
Malangizo otsatirawa akufotokoza momwe mungayesere testbench:
1. Sankhani top_tb SmartDesign Testbench ndipo dinani Pangani Chigawo kuchokera ku SmartDesign toolbar kuti mupange testbench, monga momwe chithunzichi chikusonyezera.
Chithunzi 33 · Kupanga Chigawo
2. Pazenera la Stimulus Hierarchy, dinani kumanja kwa top_tb (top_tb.v) testbench file ndikudina Set ngati chokondoweza chogwira. Kukondoweza kumayatsidwa kwa top_tb testbench file.
3. Pazenera la Stimulus Hierarchy, dinani kumanja top_tb (
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DDR AXI Arbiter
3. Pazenera la Stimulus Hierarchy, dinani kumanja kwa top_tb (top_tb.v) testbench file ndikudina Open Interactively kuchokera ku Mulate Pre-Synth Design. Izi zimatengera maziko a chimango chimodzi. Chithunzi 34 · Kutsanzira Mapangidwe a Pre-Synthesis
4. Ngati kuyerekezera kumasokonezedwa chifukwa cha malire a nthawi yothamanga mu DO file, gwiritsani ntchito run -all command kuti mumalize kuyerekezera. Mukamaliza kuyerekezera, pitani ku View > Files > kuyerekezera kwa view chithunzi chotulutsa benchi yoyeserera file mu chikwatu kayeseleledwe.
Kutulutsa koyerekeza mawu ofanana ndi chimango chimodzi cha chithunzicho, kumasungidwa m'mawu a Read_out_rd_ch(x).txt file kutengera njira yowerengera yogwiritsidwa ntchito. Izi zitha kusinthidwa kukhala chithunzi ndikuyerekeza ndi chithunzi choyambirira.
3.6
Kugwiritsa Ntchito Zida
Chida cha DDR Arbiter chimakhazikitsidwa pa M2S150T SmartFusion®2 System-on-Chip (SoC) FPGA mu
FC1152 phukusi) ndi PolarFire FPGA (MPF300TS_ES - 1FCG1152E phukusi).
Gulu 4 · Kugwiritsa Ntchito Zothandizira pa DDR AXI Arbiter
Zothandizira DFFs 4-zolowetsa LUTs MACC RAM1Kx18
Gwiritsani ntchito 2992 4493 0 20
(Za:
g_RD_CHANNEL(X)_HORIZONTAL_RESOLUTION = 1280
g_RD_CHANNEL(X)_BUFFER_LINE_STORAGE = 1
g_WR_CHANNEL(X)_BUFFER_LINE_STORAGE = 1
g_AXI_DWIDTH = 64
g_RD_CHANNEL(X)_VIDEO_DATA_WIDTH = 24
RAM64x18
g_WR_CHANNEL(X)_VIDEO_DATA_WIDTH = 32) 0
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DDR AXI Arbiter
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50200644
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Zolemba / Zothandizira
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Microchip UG0644 DDR AXI Arbiter [pdf] Buku Logwiritsa Ntchito UG0644 DDR AXI Arbiter, UG0644, DDR AXI Arbiter, AXI Arbiter |
