Intel FPGA Integer Arithmetic IP Cores User Guide

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1 FPGA Integer Arithmetic IP Cores

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FPGA Integer Arithmetic IP Cores

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Intel FPGA Integer Arithmetic IP Cores User Guide
Zasinthidwa kwa Intel® Quartus® Prime Design Suite: 20.3

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ID: 683490 Mtundu: 2020.10.05

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1. Intel FPGA Integer Arithmetic IP Cores……………………………………………………………….. 5
2. LPM_COUNTER (Counter) IP Core……………………………………………………………………….. 7 2.1. Features………………………………………………………………………………………………………… Verilog HDL Prototype………………………………………………………………………………….. 7 2.2. VHDL Component Declaration………………………………………………………………………….8 2.3. VHDL LIBRARY_USE Declaration……………………………………………………………………………………………………………………………………………………………………… Madoko………………………………………………………………………………………………………..8 2.4. Parameters…………………………………………………………………………………………………… 9
3. LPM_DIVIDE (Divider) Intel FPGA IP Core………………………………………………………….. 12 3.1. Mawonekedwe………………………………………………………………………………………………. 12 3.2. Verilog HDL Prototype……………………………………………………………………………………… 12 3.3. VHDL Component Declaration……………………………………………………………………….. 13 3.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 13 3.5. Madoko………………………………………………………………………………………………………… 13 3.6. Parameters………………………………………………………………………………………………………
4. LPM_MULT (Multiplier) IP Core……………………………………………………………………………. 16 4.1. Mawonekedwe………………………………………………………………………………………………. 16 4.2. Verilog HDL Prototype…………………………………………………………………………………… 17 4.3. VHDL Component Declaration………………………………………………………………………….. 17 4.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 17 4.5. Zizindikiro……………………………………………………………………………………………………… 18 4.6. Zoyendera za Stratix V, Arria V, Cyclone V, ndi Intel Cyclone 10 LP Devices ……………… 18 4.6.1. General Tab…………………………………………………………………………………………18 4.6.2. General 2 Tab………………………………………………………………………………………… 19 4.6.3. Pipelining Tab……………………………………………………………………………………… 19 4.7. Ma Parameter a Intel Stratix 10, Intel Arria 10, ndi Intel Cyclone 10 GX Devices ……….. 20 4.7.1. General Tab………………………………………………………………………………………20 4.7.2. General 2 Tab…………………………………………………………………………………… 20 4.7.3. Kupaka mapaipi…………………………………………………………………………………………
5. LPM_ADD_SUB (Adder/Subtractor)………………………………………………………………………… 22 5.1. Mawonekedwe………………………………………………………………………………………………. 22 5.2. Verilog HDL Prototype……………………………………………………………………………………… 23 5.3. VHDL Component Declaration……………………………………………………………………….. 23 5.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 23 5.5. Madoko…………………………………………………………………………………………………………… 23 5.6. Parameters……………………………………………………………………………………………………
6. LPM_COMPARE (Comparator)…………………………………………………………………………………………………………………………………………………………………………………… Mawonekedwe………………………………………………………………………………………………. 26 6.1. Verilog HDL Prototype…………………………………………………………………………………… 26 6.2. VHDL Component Declaration……………………………………………………………………….. 27 6.3. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 27 6.4. Madoko…………………………………………………………………………………………………………… 27 6.5. Parameters……………………………………………………………………………………………………

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7. ALTECC (Khodi Yokonza Zolakwika: Encoder/Decoder) IP Core…………………………………………
7.1. ALTECC Encoder Features……………………………………………………………………………..31 7.2. Verilog HDL Prototype (ALTECC_ENCODER)…………………………………………………………. 32 7.3. Verilog HDL Prototype (ALTECC_DECODER)…………………………………………………………. 32 7.4. VHDL Component Declaration (ALTECC_ENCODER)………………………………………………33 7.5. VHDL Component Declaration (ALTECC_DECODER)…………………………………………………33 7.6. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 33 7.7. Encoder Ports……………………………………………………………………………………………… 33 7.8. Decoder Ports………………………………………………………………………………………………… Encoder Parameters……………………………………………………………………………………… 34 7.9. Decoder Parameters …………………………………………………………………………………… 34
8. Intel FPGA Chulutsa Adder IP Core…………………………………………………………………………. 36
8.1. Mawonekedwe………………………………………………………………………………………………. 37 8.1.1. Pre-adder…………………………………………………………………………………….. 38 8.1.2. Systolic Delay Register……………………………………………………………………….. 40 8.1.3. Pre-load Constant……………………………………………………………………………… 43 8.1.4. Double Accumulator…………………………………………………………………………… 43
8.2. Verilog HDL Prototype………………………………………………………………………………… 44 8.3. VHDL Component Declaration……………………………………………………………………….. 44 8.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………. 44 8.5. Zizindikiro…………………………………………………………………………………………………… 44 8.6. Parameters………………………………………………………………………………………………… 47
8.6.1. General Tab……………………………………………………………………………………47 8.6.2. Extra Modes Tab…………………………………………………………………………….. 47 8.6.3. Multipliers Tab……………………………………………………………………………….. 49 8.6.4. Preadder Tab……………………………………………………………………………………. 51 8.6.5. Accumulator Tab…………………………………………………………………………….. 53 8.6.6. Systolic/Chainout Tabu……………………………………………………………………… 55 8.6.7. Pipelining Tab…………………………………………………………………………………… 56
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core……………………… 57
9.1. Mawonekedwe………………………………………………………………………………………………. 57 9.2. Verilog HDL Prototype…………………………………………………………………………………… 58 9.3. VHDL Component Declaration……………………………………………………………………….. 58 9.4. Madoko…………………………………………………………………………………………………………… 59 9.5. Parameters………………………………………………………………………………………………… 59
10. ALTMULT_ACCUM (Kuchulukitsa-Kunjikana) IP Core……………………………………………………
10.1. Features…………………………………………………………………………………………………….. 62 10.2. Verilog HDL Prototype………………………………………………………………………………..62 10.3. VHDL Component Declaration……………………………………………………………………………… 63 10.4. VHDL LIBRARY_USE Declaration…………………………………………………………………………… Madoko……………………………………………………………………………………………………………. 63 10.5. Parameters………………………………………………………………………………………………. 63
11. ALTMULT_ADD (Multiply-Adder) IP Core……………………………………………………………..69
11.1. Features………………………………………………………………………………………………….. 71 11.2. Verilog HDL Prototype………………………………………………………………………………..72 11.3. VHDL Component Declaration…………………………………………………………………………… 72 11.4. VHDL LIBRARY_USE Declaration……………………………………………………………………….72

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11.5. Madoko……………………………………………………………………………………………………………. 72 11.6. Parameters………………………………………………………………………………………………. 73
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core………………………………………………… 86 12.1. Complex Multiplication………………………………………………………………………………. 86 12.2. Canonical Representation……………………………………………………………………………… 87 12.3. Conventional Representation………………………………………………………………………… 87 12.4. Features………………………………………………………………………………………………….. 88 12.5. Verilog HDL Prototype………………………………………………………………………………..88 12.6. VHDL Component Declaration………………………………………………………………………… 89 12.7. VHDL LIBRARY_USE Declaration…………………………………………………………………………89 12.8. Zizindikiro………………………………………………………………………………………………………. 89 12.9. Parameters………………………………………………………………………………………………. 90
13. ALTSQRT (Integer Square Root) IP Core……………………………………………………………… Features………………………………………………………………………………………………….. 92 13.1. Verilog HDL Prototype……………………………………………………………………………..92 13.2. VHDL Component Declaration…………………………………………………………………………… 92 13.3. VHDL LIBRARY_USE Declaration……………………………………………………………………………93 13.4. Madoko……………………………………………………………………………………………………………. 93 13.5. Parameters………………………………………………………………………………………………. 93
14. PARALLEL_ADD (Parallel Adder) IP Core………………………………………………………….. 95 14.1. Nkhani………………………………………………………………………………………………….95 14.2. Verilog HDL Prototype………………………………………………………………………………..95 14.3. VHDL Component Declaration…………………………………………………………………………… 96 14.4. VHDL LIBRARY_USE Declaration……………………………………………………………………………96 14.5. Madoko……………………………………………………………………………………………………………. 96 14.6. Parameters………………………………………………………………………………………………. 97
15. Integer Arithmetic IP Cores User Guide Document Archives …………………………………… 98
16. Document Revision History for Intel FPGA Integer Arithmetic IP Cores User Guide…. 99

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1. Intel FPGA Integer Arithmetic IP Cores

Mutha kugwiritsa ntchito ma Intel® FPGA integer IP cores kuti mugwiritse ntchito masamu pamapangidwe anu.

Ntchito izi zimapereka kaphatikizidwe koyenera komanso kachitidwe kachipangizo kuposa kulemba ntchito zanu. Mutha kusintha ma IP cores kuti agwirizane ndi kapangidwe kanu.

Intel integer arithmetic IP cores agawidwa m'magulu awiri otsatirawa: · Library of parameterized modules (LPM) IP cores · Intel-specific (ALT) IP cores

Tebulo ili pansipa likuwonetsa ma IP cores onse a masamu.

Table 1.

Mndandanda wa IP Cores

IP Cores

LPM IP cores

LPM_COUNTER

LPM_GAWANI

LPM_MULT

LPM_ADD_SUB
LPM_COMPARE
Intel-specific (ALT) IP cores ALTECC

Ntchito Yonseview Counter Divider Multiplier
Adder kapena subtractor Comparator
ECC Encoder/Decoder

Chida Chothandizira
Arria® II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone® IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP,
Intel Cyclone 10 GX, MAX® II, MAX V, MAX 10, Stratix® IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX 10, Stratix IV, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel Cyclone 10 LP, MAX 10, MAX
II, MAX V, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V inapitilira…

Malingaliro a kampani Intel Corporation Maumwini onse ndi otetezedwa. Intel, logo ya Intel, ndi zizindikiro zina za Intel ndi zizindikiro za Intel Corporation kapena mabungwe ake. Intel imatsimikizira kugwira ntchito kwa FPGA yake ndi zida za semiconductor malinga ndi zomwe zili pano malinga ndi chitsimikizo cha Intel, koma ili ndi ufulu wosintha zinthu ndi ntchito zilizonse nthawi iliyonse popanda kuzindikira. Intel sakhala ndi udindo kapena udindo chifukwa cha kugwiritsa ntchito kapena kugwiritsa ntchito zidziwitso zilizonse, malonda, kapena ntchito zomwe zafotokozedwa pano kupatula monga momwe Intel adavomerezera momveka bwino. Makasitomala a Intel amalangizidwa kuti apeze mtundu waposachedwa kwambiri wamakina a chipangizocho asanadalire zidziwitso zilizonse zosindikizidwa komanso asanayike maoda azinthu kapena ntchito. *Mayina ena ndi mtundu zitha kunenedwa kuti ndi za ena.

ISO 9001:2015 Adalembetsedwa

1. Intel FPGA Integer Arithmetic IP Cores 683490 | 2020.10.05

IP Cores Intel FPGA Kuchulukitsa Adder kapena ALTERA_MULT_ADD ALTMEMMULT
ALTMULT_ACCUM ALTMULT_ADD ALTMULT_COMPLEX
Zithunzi za ALTSQRT
PARALLEL_ADD

Ntchito Yonseview Multiplier-Adder
Memory-based Constant Coefficient Multiplier
Multiplier-Accumulator Multiplier-Adder
Complex Multiplier
Integer Square Root
Parallel Adder

Chida Chothandizira
Arria V, Stratix V, Cyclone V, Intel Stratix 10, Intel Arria 10, Intel Cyclone
10 GX
Arria II GX, Arria II GZ, Arria V, Intel Arria 10 (Intel Quartus® Prime Standard Edition), Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Cyclone 10 LP, MAX II, MAX V, MAX 10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX, Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Cyclone IV E, Cyclone IV GX,Intel Cyclone 10 LP, MAX 10, MAX II, MAX V, Stratix IV
Arria II GX, Arria II GZ, Intel Arria 10, Arria V, Arria V GZ, Cyclone IV E, Cyclone IV GX, Cyclone V, Intel
Cyclone 10 GX, Intel Cyclone 10 LP, MAX 10, Stratix V, Intel Stratix 10
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V
Arria II GX, Arria II GZ, Arria V, Intel Arria 10, Cyclone IV E, Cyclone IV GX,
Cyclone V, Intel Cyclone 10 LP, Intel Cyclone 10 GX, MAX II, MAX V, MAX
10, Stratix IV, Stratix V

Zambiri Zogwirizana
· Intel FPGAs ndi Notes Release Devices Programmable
· Mau oyamba a Intel FPGA IP Cores Amapereka zambiri za Intel FPGA IP Cores.
· Floating-Point IP Cores User Guide Amapereka zambiri za Intel FPGA Floating-Point IP cores.
· Mau oyamba a Intel FPGA IP Cores Amapereka zambiri za Intel FPGA IP cores, kuphatikiza parameterizing, kupanga, kukweza, ndi kuyerekezera ma IP cores.
· Kupanga Zolemba Zodziyimira pawokha za IP ndi Qsys Simulation script Pangani zolemba zofananira zomwe sizikufuna kusinthidwa pamanja pa mapulogalamu kapena kukweza kwa mtundu wa IP.
· Kasamalidwe ka Ntchito Malangizo Abwino Kwambiri pakuwongolera bwino ndi kusuntha kwa projekiti yanu ndi IP files.
· Integer Arithmetic IP Cores User Guide Document Archives patsamba 98 Imapereka mndandanda wamalangizo ogwiritsira ntchito mitundu yam'mbuyomu ya Integer Arithmetic IP cores.

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2. LPM_COUNTER (Counter) IP Core

Chithunzi 1.

LPM_COUNTER IP core ndi kauntala ya binary yomwe imapanga zowerengera, zowerengera pansi ndi zowerengera zam'mwamba kapena zotsika zotulutsa mpaka ma bits 256 m'lifupi.

Chithunzi chotsatira chikuwonetsa madoko a LPM_COUNTER IP core.

LPM_COUNTER Madoko

LPM_COUNTER

ssclr sload seti data[]

q[]

zosinthidwa

koma

aclr katundu

clk_en cnt_en cin
inst

2.1. Mbali
LPM_COUNTER IP core ili ndi izi: · Imapanga zowerengera mmwamba, pansi, ndi zokwera/zotsika · Amapanga mitundu yotsatsira iyi:
- Binary Binary- kuchulukitsa kowerengera kuyambira ziro kapena kutsika kuyambira 255
- Modulus-kuchulukitsa kwa kauntala kapena kutsika kuchokera pamtengo wotchulidwa ndi wogwiritsa ntchito ndikubwereza
· Imathandizira kumveketsa bwino, kunyamula, ndikuyika madoko olowera · Imathandizira kumveka bwino, kunyamula, ndi kukhazikitsa madoko · Imathandizira kuwerengera kosankha, yambitsani mawotchi olowera · Imathandizira madoko olowera mwakufuna ndi kunyamula

ISO 9001:2015 Adalembetsedwa

2. LPM_COUNTER (Counter) IP Core
683490 | 2020.10.05
2.2. Verilog HDL Prototype
Chitsanzo chotsatira cha Verilog HDL chili mu Verilog Design File (.v) lpm.v mu edasynthesis directory.
module lpm_counter (q, data, wotchi, cin, cout, clk_en, cnt_en, updown, aset, aclr, aload, sset, sclr, sload, eq); parameter lpm_type = "lpm_counter"; chizindikiro lpm_width = 1; chizindikiro lpm_modulus = 0; parameter lpm_direction = "ZOSAVUTA"; parameter lpm_avalue = "ZOSAGWIRITSA NTCHITO"; parameter lpm_svalue = "ZOSAGWIRITSA NTCHITO"; parameter lpm_pvalue = "ZOSAGWIRITSA NTCHITO"; chizindikiro lpm_port_updown = "PORT_CONNECTIVITY"; parameter lpm_hint = "ZOSAGWIRITSA NTCHITO"; zotuluka [lpm_width-1:0] q; zotulutsa; zotuluka [15:0] eq; cholembera cin; zolowetsa [lpm_width-1:0] data; wotchi yolowetsa, clk_en, cnt_en, chokwera; zolowetsa aset, aclr, aload; lowetsani sset, sclr, sload; endmodule
2.3. Chidziwitso Chachigawo cha VHDL
Chidziwitso cha gawo la VHDL chili mu VHDL Design File (.vhd) LPM_PACK.vhd mu libraryvhdllpm directory.
gawo LPM_COUNTER generic ( LPM_WIDTH : chilengedwe; LPM_MODULUS : chilengedwe := 0; LPM_DIRECTION : chingwe := "ZOSAGWIRITSA NTCHITO"; LPM_AVALUE : chingwe := "ZOSAGWIRITSA NTCHITO"; LPM_SVALUE : chingwe := "ZOSAGWIRITSA NTCHITO"; LPM_PORTIVPD; LPM_PORTIVPD ; LPM_PVALUE : chingwe := "ZOSAGWIRITSA NTCHITO"; LPM_TYPE : chingwe := L_COUNTER; LPM_HINT : string := "ZOSAGWIRITSA NTCHITO"); port (DATA : mu std_logic_vector(LPM_WIDTH-1 downto 0):= (OTHERS =>
'0'); WACHI: mu std_logic; CLK_EN : mu std_logic := '1'; CNT_EN : mu std_logic := '1'; UPDOWN : mu std_logic := '1'; SLOAD : mu std_logic := '0'; SSET : mu std_logic := '0'; SCLR : mu std_logic := '0'; ALOAD : mu std_logic := '0'; ASET : mu std_logic := '0'; ACLR : mu std_logic := '0'; CIN : mu std_logic := '1'; COUT : out std_logic := '0'; Q: kunja std_logic_vector (LPM_WIDTH-1 kutsika mpaka 0); EQ: kunja std_logic_vector (15 downto 0));
mapeto chigawo;

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2.4. VHDL LIBRARY_USE Declaration
Chilengezo cha VHDL LIBRARY-USE sichifunikira ngati mugwiritsa ntchito VHDL Component Declaration.
LAIBULALE LPM; GWIRITSANI NTCHITO lpm.lpm_components.all;

2.5. Madoko

Matebulo otsatirawa akuwonetsa zolowetsa ndi zotuluka za LPM_COUNTER IP core.

Table 2.

LPM_COUNTER Madoko Olowetsa

Dzina la Port

Chofunikira

Kufotokozera

zambiri[]

Ayi

Kuyika kwa data kofananira ku kauntala. Kukula kwa doko lolowera kumatengera LPM_WIDTH parameter mtengo.

koloko

Inde

Kulowetsa koloko kochititsa chidwi.

clk_en

Ayi

Wotchi imathandizira zolowetsa kuti zitheke zochitika zonse zogwirizana. Ngati yasiyidwa, mtengo wokhazikika ndi 1.

cnt_en

Ayi

Kuwerengera yambitsani zolowetsa kuti muyimitse kuwerengera ngati kutsika popanda kukhudza sload, sset, kapena sclr. Ngati yasiyidwa, mtengo wokhazikika ndi 1.

zosinthidwa

Ayi

Imawongolera komwe kumawerengera. Akatsindikiza (1), kuwerengera komwe kumakwera, ndipo kutsika (0), komwe kumawerengera kumakhala pansi. Ngati parameter ya LPM_DIRECTION ikugwiritsidwa ntchito, doko lokwera silingalumikizidwe. Ngati LPM_DIRECTION sikugwiritsidwa ntchito, doko lakumtunda ndilosankha. Ngati sichinasinthidwe, mtengo wokhazikika umakwera (1).

cin

Ayi

Pitirizani mpaka pang'onopang'ono. Kwa ma counters, machitidwe a cin input ndi

zofanana ndi zomwe cnt_en zolowetsa. Ngati yasiyidwa, mtengo wokhazikika ndi 1

(VCC).

aclr

Ayi

Asynchronous zomveka bwino. Ngati zonse aset ndi aclr zikugwiritsidwa ntchito ndikutsimikiziridwa, aclr imachotsa aset. Ngati sichinasinthidwe, mtengo wokhazikika ndi 0 (wolemala).

katundu

Ayi

Kuyika kwa Asynchronous. Imatchula q[] zotuluka ngati ma 1 onse, kapena pamtengo wofotokozedwa ndi LPM_AVALUE parameter. Ngati madoko onse a asset ndi aclr agwiritsidwa ntchito ndikutsimikiziridwa, mtengo wa aclr port umaposa mtengo wa aset port. Ngati sichinasinthidwe, mtengo wokhazikika ndi 0, woyimitsidwa.

katundu

Ayi

Kuyika kwa Asynchronous load komwe kumadzaza motsatizana ndi mtengo wa data. Pamene doko la katundu likugwiritsidwa ntchito, doko la data[] liyenera kulumikizidwa. Ngati sichinasinthidwe, mtengo wokhazikika ndi 0, woyimitsidwa.

sclr

Ayi

Kulowetsa momveka bwino komwe kumachotsa kauntala m'mphepete mwa wotchi yotsatira. Ngati madoko onse a sset ndi sclr agwiritsidwa ntchito ndikutsimikiziridwa, mtengo wa sclr port umaposa mtengo wa sset port. Ngati sichinasinthidwe, mtengo wokhazikika ndi 0, woyimitsidwa.

sset

Ayi

Kulowetsa kolumikizana komwe kumayika kauntala m'mphepete mwa wotchi yotsatira. Imatchula mtengo wazotulutsa q monga ma 1 onse, kapena pamtengo womwe wafotokozedwa ndi LPM_SVALUE parameter. Ngati madoko onse a sset ndi sclr agwiritsidwa ntchito ndikutsimikiziridwa,
mtengo wa sclr port umaposa mtengo wa sset port. Ngati sichinasinthidwe, mtengo wokhazikika ndi 0 (wolemala).

katundu

Ayi

Kulowetsa kofananira komwe kumadzaza data ndi data[] pawotchi yotsatira. Pamene doko la sload likugwiritsidwa ntchito, doko la data[] liyenera kulumikizidwa. Ngati sichinasinthidwe, mtengo wokhazikika ndi 0 (wolemala).

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Table 3.

LPM_COUNTER Zotuluka

Dzina la Port

Chofunikira

Kufotokozera

q[]

Ayi

Kutulutsa kwa data kuchokera pakauntala. Kukula kwa doko lotulutsa kumadalira pa

LPM_WIDTH mtengo wagawo. Mwina q[] kapena doko limodzi la eq[15..0]

ziyenera kulumikizidwa.

eq[15..0]

Ayi

Counter decode output. Doko la eq[15..0] silikupezeka mu mkonzi wa parameter chifukwa parameter imangothandiza AHDL.
Doko la q[] kapena eq[] liyenera kulumikizidwa. Mpaka madoko a c eq angagwiritsidwe ntchito (0 <= c <= 15). Makhalidwe 16 otsika kwambiri okha ndi omwe amasankhidwa. Mtengo wowerengera ukakhala c, kutulutsa kwa eqc kumatsimikizidwa kwambiri (1). Za example, pamene chiwerengero ndi 0, eq0 = 1, pamene chiwerengero ndi 1, eq1 = 1, ndipo pamene chiwerengero chiri 15, eq 15 = 1. Kutulutsa kosindikizidwa kwa chiwerengero cha 16 kapena kukulirapo kumafuna kutulutsa kunja. Zotsatira za eq[15..0] ndizofanana ndi q[] zotuluka.

koma

Ayi

Tsegulani doko la kauntala ya MSB bit. Itha kugwiritsidwa ntchito polumikizana ndi kauntala ina kuti mupange kauntala yayikulu.

2.6. Magawo

Gome ili pansipa likuwonetsa magawo a LPM_COUNTER IP core.

Table 4.

LPM_COUNTER Ma Parameters

Dzina la Parameter

Mtundu

LPM_WIDTH

Nambala

LPM_DIRECTION

Chingwe

LPM_MODULUS LPM_AVALUE

Nambala
Nambala / Chingwe

LPM_SVALUE LPM_HINT

Nambala / Chingwe
Chingwe

LPM_TYPE

Chingwe

Zofunika Inde Ayi Ayi Ayi
Ayi Ayi
Ayi

Kufotokozera
Imatchula m'lifupi mwa madoko [] ndi q[], ngati agwiritsidwa ntchito.
Miyezo ndi YAMKULU, PASI, ndi YOSAGWIRITSA NTCHITO. Ngati parameter ya LPM_DIRECTION ikugwiritsidwa ntchito, doko lokwera silingalumikizidwe. Pamene doko lokwera silinalumikizidwe, chokhazikika cha LPM_DIRECTION mtengo ndi UP.
Chiwerengero chachikulu, kuphatikiza chimodzi. Chiwerengero cha zigawo zapadera pa kauntala. Ngati mtengo wa katunduyo ndi waukulu kuposa parameter ya LPM_MODULUS, machitidwe a kauntala sanatchulidwe.
Mtengo wokhazikika womwe umakwezedwa pamene katundu watsitsidwa kwambiri. Ngati mtengo womwe watchulidwa ndi waukulu kuposa kapena wofanana nawo , machitidwe a kauntala ndi mulingo wamalingaliro wosadziwika (X), pomwe ndi LPM_MODULUS, ngati ilipo, kapena 2 ^ LPM_WIDTH. Intel ikulimbikitsa kuti mutchule mtengo uwu ngati nambala yachiwerengero ya mapangidwe a AHDL.
Mtengo wanthawi zonse womwe umakwezedwa m'mphepete mwa doko lokwera pomwe doko la sset latsitsidwa kwambiri. Intel ikulimbikitsa kuti mutchule mtengo uwu ngati nambala yachiwerengero ya mapangidwe a AHDL.
Mukakhazikitsa laibulale ya parameterized modules (LPM) ntchito mu VHDL Design File (.vhd), muyenera kugwiritsa ntchito parameter ya LPM_HINT kuti mufotokoze za Intel-specific parameter. Za example: LPM_HINT = “CHAIN_SIZE = 8, ONE_INPUT_IS_CONSTANT = INDE”
Mtengo wokhazikika ndi UNUSED.
Imazindikiritsa dzina labungwe la library of parameterized modules (LPM) mu kapangidwe ka VHDL files.
anapitiriza…

Intel FPGA Integer Arithmetic IP Cores User Guide 10

Tumizani Ndemanga

2. LPM_COUNTER (Kauntala) IP Core 683490 | 2020.10.05

Dzina lazigawo INTENDED_DEVICE_FAMILY CARRY_CNT_EN
LABWIDE_SCLR
LPM_PORT_UPDOWN

Type String String
Chingwe
Chingwe

Zofunikira No
Ayi
Ayi

Kufotokozera
Parameter iyi imagwiritsidwa ntchito popanga zitsanzo komanso zoyeserera zamakhalidwe. Parameter iyi imagwiritsidwa ntchito popanga zitsanzo komanso zoyeserera zamakhalidwe. Mkonzi wa parameter amawerengera mtengo wa chizindikiro ichi.
Intel-specific parameter. Muyenera kugwiritsa ntchito parameter ya LPM_HINT kuti mutchule CARRY_CNT_EN parameter mu kapangidwe ka VHDL files. Makhalidwe ndi SMART, ON, OFF, ndi UNUSED. Imayatsa ntchito ya LPM_COUNTER kufalitsa siginecha ya cnt_en kudzera pamaketani onyamula. Nthawi zina, zochunira CARRY_CNT_EN zochunira zimatha kukhala ndi vuto pang'ono pa liwiro, kotero mungafune kuzimitsa. Mtengo wokhazikika ndi SMART, womwe umapereka malonda abwino kwambiri pakati pa kukula ndi liwiro.
Intel-specific parameter. Muyenera kugwiritsa ntchito parameter ya LPM_HINT kuti mufotokoze za LABWIDE_SCLR mu kapangidwe ka VHDL files. Makhalidwe ndi OYANTHA, WOZIMA, kapena OSAGWIRITSA NTCHITO. Mtengo wokhazikika ndi ON. Imakulolani kuti muyimitse kugwiritsa ntchito gawo la LABwide sclr lomwe limapezeka m'mabanja a zida zomwe zatha. Kuzimitsa njira iyi kumawonjezera mwayi wogwiritsa ntchito mokwanira ma LAB odzazidwa pang'ono, motero kungapangitse kukanika kwamalingaliro pamene SCLR sikugwira ntchito ku LAB yathunthu. Parameter iyi imapezeka kuti igwirizane ndi kumbuyo, ndipo Intel akukulimbikitsani kuti musagwiritse ntchito chizindikiro ichi.
Imatanthawuza kugwiritsidwa ntchito kwa doko lolowera mmwamba. Ngati sichinasinthidwe mtengowo ndi PORT_CONNECTIVITY. Mtengo wa doko ukakhazikitsidwa ku PORT_USED, doko limatengedwa ngati lagwiritsidwa ntchito. Mtengo wa doko ukakhazikitsidwa ku PORT_UNUSED, doko limatengedwa ngati losagwiritsidwa ntchito. Mtengo wa doko ukakhazikitsidwa ku PORT_CONNECTIVITY, kugwiritsidwa ntchito kwa doko kumatsimikiziridwa ndikuwona kulumikizidwa kwa doko.

Tumizani Ndemanga

Intel FPGA Integer Arithmetic IP Cores User Guide 11

683490 | 2020.10.05 Tumizani Ndemanga

3. LPM_DIVIDE (Divider) Intel FPGA IP Core

Chithunzi 2.

LPM_DIVIDE Intel FPGA IP core imagwiritsa ntchito chogawa kuti chigawanitse mtengo wolowetsa manambala ndi mtengo wolowetsamo denominator kuti apange quotient ndi yotsalira.

Chithunzi chotsatira chikuwonetsa madoko a LPM_DIVIDE IP core.

LPM_DIVIDE Madoko

LPM_GAWANI

nambala[] denom[] wotchi

quotient[] khalani[]

konda aclr

inst

3.1. Mbali
IP core ya LPM_DIVIDE ili ndi izi: · Imapanga chogawa chomwe chimagawaniza mtengo wolowetsa manambala ndi mawu a denominator
mtengo kutulutsa quotient ndi zotsalira. · Imathandizira kukula kwa data kwa 1 bits. · Imathandizira mtundu wa data womwe wasainidwa komanso wosasainidwa pa manambala onse
ndi ma denominator values. · Imathandizira kukhathamiritsa kwa dera kapena liwiro. · Amapereka mwayi wofotokozera zotsalira zabwino. · Imathandiza pipelining configurable linanena bungwe latency. · Imathandizira ma asynchronous momveka bwino komanso mawotchi amathandizira madoko.

3.2. Verilog HDL Prototype
Chitsanzo chotsatira cha Verilog HDL chili mu Verilog Design File (.v) lpm.v mu edasynthesis directory.
gawo lpm_gawani (quotient, khalani, nambala, denom, wotchi, clken, aclr); parameter lpm_type = "lpm_divide"; chizindikiro lpm_widthn = 1; chizindikiro lpm_widthd = 1; parameter lpm_nrepresentation = "OSAGNDWA"; parameter lpm_drepresentation = "OSAGENEDWA"; parameter lpm_remainderpositive = "CHOONADI"; parameter lpm_pipeline = 0;

ISO 9001:2015 Adalembetsedwa

3. LPM_DIVIDE (Divider) Intel FPGA IP Core 683490 | 2020.10.05

parameter lpm_hint = "ZOSAGWIRITSA NTCHITO"; wotchi yolowetsa; cholembera cholembera; kulowa aclr; lowetsani [lpm_widthn-1:0] nambala; kulowa [lpm_widthd-1:0] denom; kutulutsa [lpm_widthn-1:0] quotient; zotuluka [lpm_widthd-1:0] zitsalira; endmodule

3.3. Chidziwitso Chachigawo cha VHDL
Chidziwitso cha gawo la VHDL chili mu VHDL Design File (.vhd) LPM_PACK.vhd mu libraryvhdllpm directory.
gawo LPM_DIVIDE generic (LPM_WIDTHN : zachilengedwe; LPM_WIDTHD : zachilengedwe;
LPM_NREPRESENTATION : chingwe := "OSASIGNDWA"; LPM_DREPRESENTATION : chingwe := "OSASINIKA"; LPM_PIPELINE : zachilengedwe := 0; LPM_TYPE : chingwe := L_DIVIDE; LPM_HINT : string := "ZOSAGWIRITSA NTCHITO"); port (NUMER : mu std_logic_vector(LPM_WIDTHN-1 downto 0); DENOM : mu std_logic_vector(LPM_WIDTHD-1 downto 0); ACLR : mu std_logic:= '0'; CLOCK : mu std_logic := '0 : LKd inst'; := '1'; QUOTIENT : out std_logic_vector(LPM_WIDTHN-1 downto 0); KHALANI : out std_logic_vector(LPM_WIDTHD-1 downto 0)); mapeto chigawo;

3.4. VHDL LIBRARY_USE Declaration
Chilengezo cha VHDL LIBRARY-USE sichifunikira ngati mugwiritsa ntchito VHDL Component Declaration.
LAIBULALE LPM; GWIRITSANI NTCHITO lpm.lpm_components.all;

3.5. Madoko

Matebulo otsatirawa akuwonetsa zolowetsa ndi zotuluka za LPM_DIVIDE IP core.

Table 5.

LPM_DIVIDE Malo Olowetsa

Dzina la Port

Chofunikira

nambala[]

Inde

chipembedzo[]

Inde

Kufotokozera
Kulowetsa kwa Nambala. Kukula kwa doko lolowera kumatengera LPM_WIDTHN parameter mtengo.
Kuyika kwa data ya Denominator. Kukula kwa doko lolowera kumatengera LPM_WIDTHD parameter mtengo.
anapitiriza…

Tumizani Ndemanga

Intel FPGA Integer Arithmetic IP Cores User Guide 13

3. LPM_DIVIDE (Divider) Intel FPGA IP Core 683490 | 2020.10.05

Port Name wotchi clken
aclr

Zofunikira No
Ayi

Kufotokozera
Kuyika kwa wotchi kuti mugwiritse ntchito mapaipi. Pamiyezo ya LPM_PIPELINE kupatula 0 (zosakhazikika), cholumikizira wotchi chiyenera kuyatsidwa.
Wotchi imathandizira kugwiritsa ntchito mapaipi. Pamene doko la clken likunenedwa kuti ndi lalitali, ntchito yogawa imachitika. Chizindikiro chikatsika, palibe ntchito yomwe imachitika. Ngati yasiyidwa, mtengo wokhazikika ndi 1.
Doko lowoneka bwino losasinthika lomwe limagwiritsidwa ntchito nthawi iliyonse kukhazikitsanso mapaipi onse '0's molumikizana ndi mawotchi.

Table 6.

LPM_DIVIDE Zotulutsa

Dzina la Port

Chofunikira

Kufotokozera

gawo[]

Inde

Kutulutsa kwa data. Kukula kwa doko lotulutsa kumadalira LPM_WIDTHN

mtengo wa parameter.

khalani[]

Inde

Kutulutsa kwa data. Kukula kwa doko lotulutsa kumadalira LPM_WIDTHD

mtengo wa parameter.

3.6. Magawo

Gome lotsatirali likuwonetsa magawo a LPM_DIVIDE Intel FPGA IP core.

Dzina la Parameter

Mtundu

Chofunikira

Kufotokozera

LPM_WIDTHN

Nambala

Inde

Imatchula m'lifupi mwa nambala[] ndi

quotient[] madoko. Miyezo ndi 1 mpaka 64.

LPM_WIDTHD

Nambala

Inde

Imatchula m'lifupi mwa denom[] ndi

khalani[] madoko. Miyezo ndi 1 mpaka 64.

LPM_NREPRESENTATION LPM_DREPRESENTATION

Chingwe Chachingwe

Ayi

Chiwonetsero cha chizindikiro cha kulowetsa kwa manambala.

Makhalidwe NDI OSAINIKA NDIPOSASINIKA. Pamene izi

parameter yakhazikitsidwa ku SIGNED, chogawa

amatanthauzira manambala[] ngati asainidwa awiri

wowonjezera.

Ayi

Kuyimira chizindikiro cha kulowetsa kwa denominator.

Makhalidwe NDI OSAINIKA NDIPOSASINIKA. Pamene izi

parameter yakhazikitsidwa ku SIGNED, chogawa

amatanthauzira mawu a denom[] ngati asainidwa awiri

wowonjezera.

LPM_TYPE

Chingwe

Ayi

Imazindikiritsa laibulale ya parameterized

ma modules (LPM) dzina lachinthu mu kapangidwe ka VHDL

filendi (.vhd).

LPM_HINT

Chingwe

Ayi

Pamene inu instantiate laibulale ya

parameterized modules (LPM) ntchito mu a

VHDL Design File (.vhd), muyenera kugwiritsa ntchito

LPM_HINT parameter kuti mufotokozere Intel-

enieni parameter. Za example: LPM_HINT

= “CHAIN_SIZE = 8,

ONE_INPUT_IS_CONSTANT = INDE” The

mtengo wokhazikika ndi USUSED.

LPM_REMAINDERPOSITIVE

Chingwe

Ayi

Intel-specific parameter. Muyenera kugwiritsa ntchito

LPM_HINT magawo kuti mufotokozere

LPM_REMAINDERPOSITIVE magawo mkati

Kupanga kwa VHDL files. Miyezo ndi ZOONA kapena ZABODZA.

Ngati parameter iyi yakhazikitsidwa ku TRUE, ndiye kuti

mtengo wotsalira[] doko uyenera kukhala wokulirapo

anapitiriza…

Intel FPGA Integer Arithmetic IP Cores User Guide 14

Tumizani Ndemanga

3. LPM_DIVIDE (Divider) Intel FPGA IP Core 683490 | 2020.10.05

Dzina la Parameter

Mtundu

MAXIMIZE_SPEED

Nambala

LPM_PIPELINE

Nambala

INTENDED_DEVICE_FAMILY SKIP_BITS

Nambala Yachingwe

Zofunikira No
Ayi Ayi Ayi

Kufotokozera
kuposa kapena kufanana ndi ziro. Ngati parameter iyi yayikidwa ku TRUE, ndiye kuti mtengo wotsalira[] doko ndi ziro, kapena mtengo wake ndi chizindikiro chomwecho, chabwino kapena choyipa, monga mtengo wa doko la manambala. Pofuna kuchepetsa dera ndikuwongolera liwiro, Intel imalimbikitsa kukhazikitsa gawoli kukhala TRUE pochita zomwe zotsalazo ziyenera kukhala zabwino kapena zotsalazo ndizosafunika.
Intel-specific parameter. Muyenera kugwiritsa ntchito parameter ya LPM_HINT kuti mutchule MAXIMIZE_SPEED magawo mu kapangidwe ka VHDL files. Makhalidwe ndi [0..9]. Ngati atagwiritsidwa ntchito, pulogalamu ya Intel Quartus Prime imayesa kukhathamiritsa chinthu china cha LPM_DIVIDE mwachangu m'malo mosinthasintha, ndikupitilira kukhazikitsidwa kwa njira ya Optimization Technique logic. Ngati MAXIMIZE_SPEED sichigwiritsidwa ntchito, mtengo wa Optimization Technique umagwiritsidwa ntchito m'malo mwake. Ngati mtengo wa MAXIMIZE_SPEED ndi 6 kapena kupitilira apo, Compiler imakulitsa pakati pa LPM_DIVIDE IP kuti ikhale yothamanga kwambiri pogwiritsa ntchito ma tcheni; ngati mtengo ndi 5 kapena kuchepera, wophatikizayo amagwiritsa ntchito mapangidwewo popanda unyolo wonyamula.
Imatchula kuchuluka kwa mawotchi a latency okhudzana ndi quotient[] ndi kutsalira[] zotuluka. Mtengo wa ziro (0) umasonyeza kuti palibe latency yomwe ilipo, komanso kuti ntchito yophatikizika yokha imakhazikitsidwa. Ngati sichinasinthidwe, mtengo wokhazikika ndi 0 (wopanda mapaipi). Simungatchule mtengo wa LPM_PIPELINE wokwera kuposa LPM_WIDTHN.
Parameter iyi imagwiritsidwa ntchito popanga zitsanzo komanso zoyeserera zamakhalidwe. Mkonzi wa parameter amawerengera mtengo wa chizindikiro ichi.
Amalola kuti magawo azigawo ang'onoang'ono azitha kuwongolera malingaliro pazigawo zotsogola popereka kuchuluka kwa GND kupita ku LPM_DIVIDE IP core. Tchulani chiwerengero cha GND yotsogolera pa quotient kutulutsa kwa parameter iyi.

Tumizani Ndemanga

Intel FPGA Integer Arithmetic IP Cores User Guide 15

683490 | 2020.10.05 Tumizani Ndemanga

4. LPM_MULT (Multiplier) IP Kore

Chithunzi 3.

LPM_MULT IP pachimake imagwiritsa ntchito chochulukitsira kuti ichulukitse milingo iwiri ya data kuti ipange chinthu ngati chotuluka.

Chithunzi chotsatira chikuwonetsa madoko a LPM_MULT IP core.

LPM_Mult Ports

LPM_MULT data ya wotchi[] zotsatira[] datab[] aclr/sclr clken
inst

Nkhani Zogwirizana nazo patsamba 71

4.1. Mbali
LPM_MULT IP pachimake imapereka zinthu zotsatirazi: · Imapanga chochulukitsira chomwe chimachulukitsa mitundu iwiri ya data yolowetsa · Imathandizira kukula kwa data 1 bits · Imathandizira mawonekedwe oyimira deta osayinidwa ndi osasainidwa njira yokhazikitsira pakudzipereka kwa ma sign a digito (DSP)
block circuitry kapena logic elements (LEs) Zindikirani: Mukamanga zochulutsa zazikulu kuposa kukula komwe kumathandizidwa pakhoza kukhala/
kudzakhala kukhudzidwa kwa magwiridwe antchito chifukwa cha kutsika kwa midadada ya DSP. · Imathandizira kumveka kowoneka bwino komanso wotchi imathandizira madoko olowera · Imathandizira kumveka bwino kwa Intel Stratix 10, Intel Arria 10 ndi Intel Cyclone 10 GX

ISO 9001:2015 Adalembetsedwa

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05
4.2. Verilog HDL Prototype
Chitsanzo chotsatira cha Verilog HDL chili mu Verilog Design File (.v) lpm.v mu edasynthesis directory.
module lpm_mult ( zotsatira, dataa, datab, sum, clock, clken, aclr ) parameter lpm_type = "lpm_mult"; parameter lpm_widtha = 1; chizindikiro lpm_widthb = 1; chizindikiro lpm_widths = 1; chizindikiro lpm_widthp = 1; parameter lpm_representation = "OSAGNIKA"; parameter lpm_pipeline = 0; parameter lpm_hint = "ZOSAGWIRITSA NTCHITO"; wotchi yolowera; cholembera cholembera; kulowa aclr; zolowetsa [lpm_widtha-1:0] dataa; lowetsani [lpm_widthb-1:0] datab; kulowetsa [lpm_widths-1:0] ndalama; zotsatira [lpm_widthp-1:0]; endmodule
4.3. Chidziwitso Chachigawo cha VHDL
Chidziwitso cha gawo la VHDL chili mu VHDL Design File (.vhd) LPM_PACK.vhd mu libraryvhdllpm directory.
component LPM_MULT generic ( LPM_WIDTHA : natural; LPM_WIDTHB : natural; LPM_WIDTHS : natural := 1; LPM_WIDTHP : natural;
LPM_REPRESENTATION : chingwe := "OSASINIKA"; LPM_PIPELINE : zachilengedwe := 0; LPM_TYPE: chingwe := L_MULT; LPM_HINT : string := "ZOSAGWIRITSA NTCHITO"); port ( DATAA : mu std_logic_vector(LPM_WIDTHA-1 downto 0); DATAB : mu std_logic_vector(LPM_WIDTHB-1 downto 0); ACLR : mu std_logic:= '0'; CLOCK : mu std_logic := '0 : LK : 1'; := '1'; SUM : mu std_logic_vector(LPM_WIDTHS-0 kutsika mpaka 0) := (ENA => '1'); ZOPHUNZITSA : out std_logic_vector(LPM_WIDTHP-0 downto XNUMX)); mapeto chigawo;
4.4. VHDL LIBRARY_USE Declaration
Chilengezo cha VHDL LIBRARY-USE sichifunikira ngati mugwiritsa ntchito VHDL Component Declaration.
LAIBULALE LPM; GWIRITSANI NTCHITO lpm.lpm_components.all;

Tumizani Ndemanga

Intel FPGA Integer Arithmetic IP Cores User Guide 17

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

4.5. Zizindikiro

Table 7.

LPM_MULT Zizindikiro Zolowetsa

Dzina la Signal

Chofunikira

Kufotokozera

deta[]

Inde

Kuyika kwa data.

Pazida za Intel Stratix 10, Intel Arria 10, ndi Intel Cyclone 10 GX, kukula kwa chizindikiro cholowera kumadalira mtengo wapakatikati wa Dataa.

Pazida zakale komanso za Intel Cyclone 10 LP, kukula kwa siginecha yolowera kumatengera LPM_WIDTHA parameter mtengo.

datab[]

Inde

Kuyika kwa data.

Pazida za Intel Stratix 10, Intel Arria 10, ndi Intel Cyclone 10 GX, kukula kwa chizindikiro cholowera kumatengera kuchuluka kwa datab wide parameter.

Kwa zida zakale ndi Intel Cyclone 10 LP, kukula kwa chizindikiro cholowera kumadalira

pa LPM_WIDTHB parameter mtengo.

koloko

Ayi

Kuyika kwa wotchi kuti mugwiritse ntchito mapaipi.

Pazida zakale komanso za Intel Cyclone 10 LP, chizindikiro cha wotchi chiyenera kuyatsidwa pamitengo ya LPM_PIPELINE kupatula 0 (yosasinthika).

Pazida za Intel Stratix 10, Intel Arria 10, ndi Intel Cyclone 10 GX, chizindikiro cha wotchi chiyenera kuyatsidwa ngati mtengo wa Latency uli wosiyana ndi 1 (chosakhazikika).

kolokani

Ayi

Wotchi imalola kugwiritsa ntchito mapaipi. Pamene chizindikiro cha clken chikutsimikiziridwa kuti chikukwera,

ntchito adder/subtractor ikuchitika. Chizindikiro chikakhala chochepa, palibe ntchito

zimachitika. Ngati yasiyidwa, mtengo wokhazikika ndi 1.

aclr scl

Ayi

Chizindikiro chowoneka bwino chowoneka bwino chomwe chimagwiritsidwa ntchito nthawi iliyonse kukhazikitsanso payipi ku ma 0s onse,

asynchronously ku chizindikiro cha wotchi. Njirayi imayambira ku undefined (X)

logic level. Zotulukapo ndizosasinthasintha, koma zopanda ziro.

Ayi

Synchronous chizindikiro chomveka chomwe chimagwiritsidwa ntchito nthawi iliyonse kukonzanso mapaipi ku ma 0s onse,

synchronously kwa chizindikiro cha wotchi. Njirayi imayambira ku undefined (X)

logic level. Zotulukapo ndizosasinthasintha, koma zopanda ziro.

Table 8.

LPM_MULT zotuluka

Chizindikiro Dzina

Chofunikira

Kufotokozera

zotsatira[]

Inde

Kutulutsa kwa data.

Pazida zakale komanso za Intel Cyclone 10 LP, kukula kwa chizindikirocho kumadalira mtengo wa LPM_WITDHP. Ngati LPM_WIDTHP < max (LPM_WIDTHA + LPM_WIDTHB, LPM_WIDTHS) kapena (LPM_WIDTHA + LPM_WIDTHS), ndi ma MSB a LPM_WIDTHP okha omwe alipo.

Kwa Intel Stratix 10, Intel Arria 10 ndi Intel Cyclone 10 GX, kukula kwa ma siginecha otulutsa kumadalira gawo la Result wide.

4.6. Ma Parameter a Stratix V, Arria V, Cyclone V, ndi Intel Cyclone 10 LP Devices

4.6.1. General Tab

Table 9.

General Tab

Parameter

Mtengo

Kusintha kwa Multiplier

Chulukitsani kulowetsa kwa 'data' ndi kulowetsa kwa 'datab'

Mtengo Wofikira

Kufotokozera

Chulukitsani kulowetsa kwa 'data' ndi kulowetsa kwa 'datab'

Sankhani kasinthidwe mukufuna kwa multiplier.
anapitiriza…

Intel FPGA Integer Arithmetic IP Cores User Guide 18

Tumizani Ndemanga

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

Parameter
Kodi mawu a 'dataa' akuyenera kukhala otambalala bwanji? Kodi mawu a 'datab' akuyenera kukhala otambalala bwanji? Kodi m'lifupi mwa zotsatira za 'zotsatira' ziyenera kudziwika bwanji? Kuletsa m'lifupi

Mtengo
Chulukitsani zolowetsa za 'dataa' palokha (squaring operation)
1-256 mphindi

Mtengo Wofikira

Kufotokozera

8 biti

Tchulani m'lifupi mwa doko la dataa[].

1-256 mphindi

8 biti

Tchulani m'lifupi mwa doko la datab[].

Dziwerengereni zokha m'lifupi Limbikitsani m'lifupi
1-512 mphindi

Mwadzidzidzi y kuwerengera m'lifupi

Sankhani njira yomwe mukufuna kudziwa kukula kwa chotsatira[] doko.

16 biti

Tchulani m'lifupi mwazotsatira[] doko.
Mtengo uwu udzakhala wothandiza ngati mutasankha Kuletsa m'lifupi mu mtundu wa parameter.

4.6.2. General 2 Tab

Table 10. General 2 Tab

Parameter

Mtengo

Kuyika kwa Datab

Kodi basi ya 'datab' imakhala ndi mtengo wokhazikika?

Ayi Inde

Mtundu Wochulukitsa

Mtundu uti wa

Osasainidwa

kuchulutsa mukufuna? Sayinidwa

Kukhazikitsa

Ndi kuchulukitsa kotani komwe kukuyenera kugwiritsidwa ntchito?

Gwiritsani ntchito kukhazikitsa kokhazikika
Gwiritsani ntchito ma circuitry odzipatulira ochulukitsa (Sizipezeka kwa mabanja onse)
Gwiritsani ntchito mfundo zomveka

Mtengo Wofikira

Kufotokozera

Ayi

Sankhani Inde kuti mutchule mtengo wokhazikika wa

`datab' yolowetsa basi, ngati ilipo.

Osasainidwa

Tchulani mtundu woyimira wa dataa[] ndi datab[] zolowetsa.

Gwiritsani ntchito ion yokhazikika yokhazikika

Sankhani njira yomwe mukufuna kudziwa kukula kwa chotsatira[] doko.

4.6.3. Pipelining Tab

Table 11. Mapaipi Tabu

Parameter

Kodi mukufuna kutsitsa No

ntchito?

Inde

Mtengo

Pangani 'aclr'

—

Asynchronous clear port

Mtengo Wofikira

Kufotokozera

Ayi

Sankhani Inde kuti mulowetse kulembetsa kwa mapaipi ku

multiplier's linanena bungwe ndi kufotokoza zomwe mukufuna

kutulutsa latency mu wotchi yozungulira. Kuthandizira kwa

pipeline registry imawonjezera latency yowonjezera ku

zotuluka.

Osasankhidwa

Sankhani njira iyi kuti mutsegule doko la aclr kuti ligwiritse ntchito momveka bwino polembetsa mapaipi.
anapitiriza…

Tumizani Ndemanga

Intel FPGA Integer Arithmetic IP Cores User Guide 19

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

Parameter
Pangani wotchi ya 'clken'
Kukhathamiritsa
Mukufuna kukhathamiritsa kwamtundu wanji?

Mtengo -
Default Speed Area

Mtengo Wofikira

Kufotokozera

Osasankhidwa

Imatchula mphamvu ya wotchi yayikulu padoko la kaundula wa mapaipi

Zosasintha

Tchulani kukhathamiritsa komwe mukufuna kwa IP core.
Sankhani Default kuti mulole pulogalamu ya Intel Quartus Prime kuti idziwe kukhathamiritsa kwa IP pachimake.

4.7. Ma Parameter a Intel Stratix 10, Intel Arria 10, ndi Intel Cyclone 10 GX Devices

4.7.1. General Tab

Table 12. General Tab

Parameter

Mtengo

Mtengo Wofikira

Kufotokozera

Multiplier Configuration Type
Deta Port Widths

Chulukitsani kulowetsa kwa 'data' ndi kulowetsa kwa 'datab'
Chulukitsani zolowetsa za 'dataa' palokha (squaring operation)

Chulukitsani kulowetsa kwa 'data' ndi kulowetsa kwa 'datab'

Sankhani kasinthidwe mukufuna kwa multiplier.

Kuchuluka kwa data

1-256 mphindi

8 biti

Tchulani m'lifupi mwa doko la dataa[].

Datab wide

1-256 mphindi

8 biti

Tchulani m'lifupi mwa doko la datab[].

Kodi m'lifupi mwa zotsatira za 'zotsatira' ziyenera kudziwika bwanji?

Mtundu

Dziwerengereni m'lifupi mwake
Kuletsa m'lifupi

Mwadzidzidzi y kuwerengera m'lifupi

Sankhani njira yomwe mukufuna kudziwa kukula kwa chotsatira[] doko.

Mtengo

1-512 mphindi

16 biti

Tchulani m'lifupi mwazotsatira[] doko.
Mtengo uwu udzakhala wothandiza ngati mutasankha Kuletsa m'lifupi mu mtundu wa parameter.

Zotsatira m'lifupi

1-512 mphindi

—

Imawonetsa m'lifupi mwazotsatira[] doko.

4.7.2. General 2 Tab

Table 13. General 2 Tab

Parameter

Kuyika kwa Datab

Kodi basi ya 'datab' imakhala ndi mtengo wokhazikika?

Ayi Inde

Mtengo

Mtengo Wofikira

Kufotokozera

Ayi

Sankhani Inde kuti mutchule mtengo wokhazikika wa

`datab' yolowetsa basi, ngati ilipo.

anapitiriza…

Intel FPGA Integer Arithmetic IP Cores User Guide 20

Tumizani Ndemanga

4. LPM_MULT (Multiplier) IP Core 683490 | 2020.10.05

Parameter

Mtengo

Mtengo uliwonse woposa 0

Mtundu Wochulukitsa

Mtundu uti wa

Osasainidwa

kuchulutsa mukufuna? Sayinidwa

Kachitidwe kachitidwe

Ndi kuchulukitsa kotani komwe kukuyenera kugwiritsidwa ntchito?

Gwiritsani ntchito kukhazikitsa kokhazikika
Gwiritsani ntchito multiplier circuitry
Gwiritsani ntchito mfundo zomveka

Mtengo Wofikira

Kufotokozera

Tchulani mtengo wokhazikika wa doko la datab[].

Osasainidwa

Tchulani mtundu woyimira wa dataa[] ndi datab[] zolowetsa.

Gwiritsani ntchito ion yokhazikika yokhazikika

Sankhani njira yomwe mukufuna kudziwa kukula kwa chotsatira[] doko.

4.7.3. Kupaka mapaipi

Table 14. Mapaipi Tabu

Parameter

Mtengo

Kodi mukufuna kutsitsa ntchitoyi?

Chipaipi

Ayi Inde

Latency Clear Signal Type

Mtengo uliwonse woposa 0.
Palibe ACLR SCLR

Pangani wotchi ya 'clken'

—

yambitsani wotchi

Mukufuna kukhathamiritsa kwamtundu wanji?

Mtundu

Default Speed Area

Mtengo Wofikira

Kufotokozera

Ayi 1 AYI
—

Sankhani Inde kuti mutsegule kaundula wa mapaipi ku zotulutsa zochulukitsa. Kuyang'anira kaundula wa mapaipi kumawonjezera kuchedwa kwina pazotulutsa.
Tchulani zomwe mukufuna kutulutsa mu clock cycle.
Tchulani mtundu wa kukonzanso kwa kaundula wa mapaipi. Sankhani KUKHALA ngati simugwiritsa ntchito kaundula wa mapaipi. Sankhani ACLR kuti mugwiritse ntchito asynchronous clear polembetsa mapaipi. Izi zipanga doko la ACLR. Sankhani SCLR kuti mugwiritse ntchito synchronous clear polembetsa mapaipi. Izi zipanga doko la SCLR.
Imatchula mphamvu ya wotchi yayikulu padoko la kaundula wa mapaipi

Zosasintha

Tchulani kukhathamiritsa komwe mukufuna kwa IP core.
Sankhani Zosintha kuti mulole pulogalamu ya Intel Quartus Prime kuti idziwe kukhathamiritsa kwa IP pachimake.

Tumizani Ndemanga

Intel FPGA Integer Arithmetic IP Cores User Guide 21

683490 | 2020.10.05 Tumizani Ndemanga

5. LPM_ADD_SUB (Adder/Subtractor)

Chithunzi 4.

LPM_ADD_SUB IP core imakulolani kugwiritsa ntchito adder kapena subtractor kuti muwonjezere kapena kuchotsa ma data kuti mutulutse zomwe zili ndi kuchuluka kapena kusiyana kwa zomwe zalowetsa.

Chithunzi chotsatira chikuwonetsa madoko a LPM_ADD_SUB IP core.

LPM_ADD_SUB Madoko

LPM_ADD_SUB add_sub cin

deta[]

clock clken datab[] aclr

zotsatira[] zosefukira

inst

5.1. Mbali
LPM_ADD_SUB IP core ili ndi izi: · Imapanga adder, subtractor, ndi adder/subtractor zosinthika mosinthika.
ntchito. · Imathandizira kukula kwa data kwa 1 bits. · Imathandizira mawonekedwe oyimira deta monga osainidwa ndi osasainidwa. · Imathandizira kunyamula mwasankha (kubwereketsa), momveka bwino, ndipo wotchi imathandizira
madoko olowera. · Imathandizira kunyamula (kubwereketsa) ndi madoko osefukira. · Imapatsa mabasi amodzi omwe amalowetsamo nthawi zonse. · Imathandiza mapaipi ndi configurable linanena bungwe latency.

ISO 9001:2015 Adalembetsedwa

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05
5.2. Verilog HDL Prototype
Chitsanzo chotsatira cha Verilog HDL chili mu Verilog Design File (.v) lpm.v mu edasynthesis directory.
module lpm_add_sub (zotsatira, cout, kusefukira,add_sub, cin, dataa, datab, wotchi, clken, aclr); parameter lpm_type = "lpm_add_sub"; chizindikiro lpm_width = 1; parameter lpm_direction = "ZOSAVUTA"; parameter lpm_representation = "ZOSAINIWA"; parameter lpm_pipeline = 0; parameter lpm_hint = "ZOSAGWIRITSA NTCHITO"; lowetsani [lpm_width-1:0] data, datab; lowetsani add_sub, cin; wotchi yolowera; cholembera cholembera; kulowa aclr; zotsatira [lpm_width-1:0]; kutulutsa, kusefukira; endmodule
5.3. Chidziwitso Chachigawo cha VHDL
Chidziwitso cha gawo la VHDL chili mu VHDL Design File (.vhd) LPM_PACK.vhd mu libraryvhdllpm directory.
gawo LPM_ADD_SUB generic (LPM_WIDTH : zachilengedwe;
LPM_DIRECTION : chingwe := "ZOSAGWIRITSA NTCHITO"; LPM_REPRESENTATION: zingwe := "ZOSAINA"; LPM_PIPELINE : zachilengedwe := 0; LPM_TYPE : chingwe := L_ADD_SUB; LPM_HINT : string := "ZOSAGWIRITSA NTCHITO"); doko (DATAA : mu std_logic_vector(LPM_WIDTH-1 downto 0); DATAB : mu std_logic_vector(LPM_WIDTH-1 downto 0); ACLR : mu std_logic:= '0'; CLOCK : mu std_logic := '0' mu CLK_logic; := '1'; CIN : in std_logic := 'Z'; ADD_SUB : in std_logic := '1'; RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0); COUT : out std_logic; OVERFLOW: out std_logic); mapeto chigawo;
5.4. VHDL LIBRARY_USE Declaration
Chilengezo cha VHDL LIBRARY-USE sichifunikira ngati mugwiritsa ntchito VHDL Component Declaration.
LAIBULALE LPM; GWIRITSANI NTCHITO lpm.lpm_components.all;
5.5. Madoko
Matebulo otsatirawa akuwonetsa zolowetsa ndi zotuluka za LPM_ADD_SUB IP core.

Tumizani Ndemanga

Intel FPGA Integer Arithmetic IP Cores User Guide 23

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05

Table 15. LPM_ADD_SUB IP Core Input Ports

Dzina la Port

Chofunikira

Kufotokozera

cin

Ayi

Pitirizani mpaka pang'onopang'ono. Pazowonjezera, mtengo wokhazikika ndi 0. Kwa

kuchotsa ntchito, mtengo wokhazikika ndi 1.

deta[]

Inde

Kuyika kwa data. Kukula kwa doko lolowera kumatengera LPM_WIDTH parameter mtengo.

datab[]

Inde

Kuyika kwa data. Kukula kwa doko lolowera kumatengera LPM_WIDTH parameter mtengo.

add_sub

Ayi

Posankha polowera kuti muthe kusinthana pakati pa adder ndi subtractor

ntchito. Ngati LPM_DIRECTION parameter ikugwiritsidwa ntchito, add_sub singagwiritsidwe ntchito. Ngati

zosiyidwa, mtengo wokhazikika ndi ADD. Intel imalimbikitsa kuti mugwiritse ntchito

LPM_DIRECTION parameter kuti mufotokoze momwe ntchito ya LPM_ADD_SUB ikuyendera,

m'malo mopereka nthawi zonse ku doko la add_sub.

koloko

Ayi

Zolowetsa kuti mugwiritse ntchito mapaipi. Doko la wotchi limapereka kulowetsa kwa wotchi yapaipi

ntchito. Pamiyezo ya LPM_PIPELINE kupatula 0 (chosasintha), cholumikizira wotchi chiyenera kukhala

tsegulani.

kolokani

Ayi

Wotchi imalola kugwiritsa ntchito mapaipi. Pamene doko la clken likunenedwa lalitali, adder /

ntchito ya subtractor ikuchitika. Chizindikiro chikatsika, palibe ntchito yomwe imachitika. Ngati

zasiyidwa, mtengo wokhazikika ndi 1.

aclr

Ayi

Asynchronous clear kuti agwiritse ntchito mapaipi. Njirayi imayambira ku undefined (X)

logic level. Doko la aclr lingagwiritsidwe ntchito nthawi iliyonse kukhazikitsanso mapaipi ku ma 0s onse,

asynchronously ku chizindikiro cha wotchi.

Gulu 16. LPM_ADD_SUB IP Core Output Ports

Dzina la Port

Chofunikira

Kufotokozera

zotsatira[]

Inde

Kutulutsa kwa data. Kukula kwa doko lotulutsa kumadalira parameter ya LPM_WIDTH

mtengo.

koma

Ayi

Kubweza (kubwereketsa) kofunikira kwambiri (MSB). Doko la cout lili ndi thupi

kutanthauzira monga kutengera (kubwereketsa) kwa MSB. Khomo la cout limazindikira

kusefukira mu ntchito ZOSAVUTA. Cout port imagwira ntchito mofananamo

ZOSAyinidwa komanso ZOSASINIKA.

kusefukira

Ayi

Kupatulapo kusefukira kwapadera. Doko losefukira lili ndi kutanthauzira kwenikweni ngati

XOR ya kunyamula kupita ku MSB ndi kunyamula kwa MSB. Doko losefukira

zimatsimikizira ngati zotsatira zikupitilira kulondola komwe kulipo, ndipo zimagwiritsidwa ntchito pokhapokha ngati chiwongolero cha

LPM_REPRESENTATION mtengo ndi SIGNED.

5.6. Magawo

Gome lotsatirali lili ndi LPM_ADD_SUB IP core parameters.

Gulu 17. LPM_ADD_SUB IP Core Parameters

Dzina lazigawo LPM_WIDTH

Lembani Nambala

Zofunikira Inde

Kufotokozera
Imatchula m'lifupi mwa dataa[], datab[], ndi madoko[] otuluka.

LPM_DIRECTION

Chingwe

Ayi

Makhalidwe ndi ADD, SUB, ndi UNUSED. Ngati sichinasinthidwe, mtengo wokhazikika ndi DEFAULT, womwe umatsogolera parameter kuti itenge mtengo wake kuchokera ku add_sub port. Doko la add_sub silingagwiritsidwe ntchito ngati LPM_DIRECTION ikugwiritsidwa ntchito. Intel ikukulimbikitsani kuti mugwiritse ntchito parameter ya LPM_DIRECTION kuti mufotokoze momwe ntchito ya LPM_ADD_SUB ikuyendera, m'malo mopereka nthawi zonse ku doko la add_sub.
anapitiriza…

Intel FPGA Integer Arithmetic IP Cores User Guide 24

Tumizani Ndemanga

5. LPM_ADD_SUB (Adder/Subtractor) 683490 | 2020.10.05

Dzina lazigawo LPM_REPRESENTATION LPM_PIPELINE LPM_HINT LPM_TYPE ONE_INPUT_IS_CONSTANT MAXIMIZE_SPEED
INTENDED_DEVICE_FAMILY

Lembani String Integer String String String Integer
Chingwe

Zofunika Ayi Ayi Ayi Ayi Ayi Ayi Ayi
Ayi

Kufotokozera
Imatchula mtundu wowonjezera womwe wachitika. Makhalidwe NDI OSAINIKA NDIPOSASINIKA. Ngati sichinasinthidwe, mtengo wokhazikika ndi WOSAyinidwa. Parameter iyi ikayikidwa KUSINIKIDWA, adder/subtractor amatanthauzira zomwe zalowetsedwa ngati zomwe zasainidwa ziwiri.
Imatchula kuchuluka kwa mawotchi a latency okhudzana ndi zotsatira[] zotulutsa. Mtengo wa ziro (0) umasonyeza kuti palibe latency yomwe ilipo, komanso kuti ntchito yosakanikirana idzakhazikitsidwa. Ngati sichinasinthidwe, mtengo wokhazikika ndi 0 (wopanda mapaipi).
Imakulolani kuti mutchule magawo apadera a Intel mu kapangidwe ka VHDL filendi (.vhd). Mtengo wokhazikika ndi UNUSED.
Imazindikiritsa dzina labungwe la library of parameterized modules (LPM) mu kapangidwe ka VHDL files.
Intel-specific parameter. Muyenera kugwiritsa ntchito parameter ya LPM_HINT kuti mufotokozere ONE_INPUT_IS_CONSTANT mu kapangidwe ka VHDL files. Makhalidwe ndi INDE, AYI, ndi OSATUMIKIZWA. Amapereka kukhathamiritsa kwakukulu ngati kulowetsa kumodzi kumakhala kosasintha. Ngati sichinasinthidwe, mtengo wokhazikika ndi NO.
Intel-specific parameter. Muyenera kugwiritsa ntchito parameter ya LPM_HINT kuti mutchule MAXIMIZE_SPEED magawo mu kapangidwe ka VHDL files. Mutha kutchula mtengo pakati pa 0 ndi 10. Ngati agwiritsidwa ntchito, pulogalamu ya Intel Quartus Prime imayesa kukhathamiritsa gawo linalake la LPM_ADD_SUB pa liwiro m'malo mosinthasintha, ndipo imadutsa njira ya Optimization Technique logic. Ngati MAXIMIZE_SPEED sichigwiritsidwa ntchito, mtengo wa Optimization Technique umagwiritsidwa ntchito m'malo mwake. Ngati zochunira za MAXIMIZE_SPEED zili 6 kapena kupitilira apo, Compiler imakonzekeretsa pakati pa LPM_ADD_SUB IP kuti ikhale yothamanga kwambiri pogwiritsa ntchito maunyolo; ngati zoyikazo zili 5 kapena kuchepera, Wopangayo amagwiritsa ntchito kapangidwe kake popanda unyolo. Izi ziyenera kufotokozedwa pazida za Cyclone, Stratix, ndi Stratix GX pokhapokha ngati doko la add_sub silikugwiritsidwa ntchito.
Parameter iyi imagwiritsidwa ntchito popanga zitsanzo komanso zoyeserera zamakhalidwe. Mkonzi wa parameter amawerengera mtengo wa chizindikiro ichi.

Tumizani Ndemanga

Intel FPGA Integer Arithmetic IP Cores User Guide 25

683490 | 2020.10.05 Tumizani Ndemanga

6. LPM_COMPARE (Wofananizira)

Chithunzi 5.

LPM_COMPARE IP core imafanizira mtengo wamagulu awiri a data kuti adziwe ubale womwe ulipo pakati pawo. Mwanjira yake yosavuta, mutha kugwiritsa ntchito chipata chokha-OR kuti muwone ngati magawo awiri a data ndi ofanana.

Chithunzi chotsatira chikuwonetsa madoko a LPM_COMPARE IP core.

LPM_COMPARE Madoko

LPM_COMPARE

kolokani

alb

aeb

deta[]

agb

datab[]

ageb

koloko

aneb

aclr

aleb

inst

6.1. Mbali
LPM_COMPARE IP pachimake imapereka zinthu zotsatirazi: · Imapanga ntchito yofananira kuti ifananize ma seti awiri a data · Imathandizira kuchuluka kwa data kwa ma bits 1 · Imathandizira mawonekedwe oyimira deta monga osainidwa ndi osasainidwa · Amapanga mitundu yotsatirayi:
— alb (zolowetsa A ndizocheperapo B) — aeb (zolowetsa A ndizofanana ndi B) — agb (zolowetsa A ndizokulirapo kuposa zolowetsa B) — ageb (zolowetsa A ndizokulirapo kapena zofanana ndi B) — aneb ( kulowetsa A sikufanana ndi kulowetsa B) — aleb (zolowetsa A ndizocheperapo kapena zofanana ndi zomwe B) · Imathandizira kumveketsa bwino kosasinthika ndipo wotchi imalola madoko olowera · Imapatsa zolowetsa za datab[] mosadukiza · Imathandizira kuyika mapaipi ndi kuchedwa kotuluka

ISO 9001:2015 Adalembetsedwa

6. LPM_COMPARE (Woyerekeza) 683490 | 2020.10.05
6.2. Verilog HDL Prototype
Chitsanzo chotsatira cha Verilog HDL chili mu Verilog Design File (.v) lpm.v mu edasynthesis directory.
module lpm_compare ( alb, aeb, agb, aleb, aneb, ageb, dataa, datab, wotchi, clken, aclr); parameter lpm_type = "lpm_compare"; chizindikiro lpm_width = 1; parameter lpm_representation = "OSAGNIKA"; parameter lpm_pipeline = 0; parameter lpm_hint = "ZOSAGWIRITSA NTCHITO"; lowetsani [lpm_width-1:0] data, datab; wotchi yolowetsa; cholembera cholembera; kulowa aclr; output alb, aeb, agb, aleb, aneb, ageb; endmodule
6.3. Chidziwitso Chachigawo cha VHDL
Chidziwitso cha gawo la VHDL chili mu VHDL Design File (.vhd) LPM_PACK.vhd mu libraryvhdllpm directory.
gawo LPM_COMPARE generic (LPM_WIDTH : zachilengedwe;
LPM_REPRESENTATION : chingwe := "OSASINIKA"; LPM_PIPELINE : zachilengedwe := 0; LPM_TYPE: chingwe := L_COMPARE; LPM_HINT : string := "ZOSAGWIRITSA NTCHITO"); doko (DATAA : mu std_logic_vector(LPM_WIDTH-1 downto 0); DATAB : mu std_logic_vector(LPM_WIDTH-1 downto 0); ACLR : mu std_logic:= '0'; CLOCK : mu std_logic := '0' mu CLK_logic; := '1'; AGB : out std_logic; AGEB : out std_logic; AEB : out std_logic; ANEB : out std_logic; ALB : out std_logic; ALEB : out std_logic); mapeto chigawo;
6.4. VHDL LIBRARY_USE Declaration
Chilengezo cha VHDL LIBRARY-USE sichifunikira ngati mugwiritsa ntchito VHDL Component Declaration.
LAIBULALE LPM; GWIRITSANI NTCHITO lpm.lpm_components.all;
6.5. Madoko
Matebulo otsatirawa akuwonetsa zolowetsa ndi zotuluka za LMP_COMPARE IP core.

Tumizani Ndemanga

Intel FPGA Integer Arithmetic IP Cores User Guide 27

6. LPM_COMPARE (Woyerekeza) 683490 | 2020.10.05

Gulu 18. LPM_COMPARE IP core Input Ports

Dzina la Port

Chofunikira

Kufotokozera

deta[]

Inde

Kuyika kwa data. Kukula kwa doko lolowera kumatengera LPM_WIDTH parameter mtengo.

datab[]

Inde

Kuyika kwa data. Kukula kwa doko lolowera kumatengera LPM_WIDTH parameter mtengo.

koloko

Ayi

Kuyika kwa wotchi kuti mugwiritse ntchito mapaipi. Doko la wotchi limapereka kulowetsa kwa wotchi yapaipi

ntchito. Pamiyezo ya LPM_PIPELINE kupatula 0 (chosasintha), cholumikizira wotchi chiyenera kukhala

tsegulani.

kolokani

Ayi

Wotchi imalola kugwiritsa ntchito mapaipi. Pamene doko la clken likunenedwa kuti ndi lalitali, ndi

ntchito yofananitsa ikuchitika. Chizindikiro chikatsika, palibe ntchito yomwe imachitika. Ngati

zasiyidwa, mtengo wokhazikika ndi 1.

aclr

Ayi

Asynchronous clear kuti agwiritse ntchito mapaipi. Njirayi imayambira kumalingaliro osadziwika (X).

mlingo. Doko la aclr lingagwiritsidwe ntchito nthawi iliyonse kukhazikitsanso mapaipi ku ma 0s onse,

asynchronously ku chizindikiro cha wotchi.

Gulu 19. LPM_COMPARE IP core Output Ports

Dzina la Port

Chofunikira

Kufotokozera

alb

Ayi

Doko lotulutsa kwa wofananira. Amati ngati cholowetsa A chili chocheperapo B.

aeb

Ayi

Doko lotulutsa kwa wofananira. Amanenedwa ngati cholowetsa A chili chofanana ndi B.

agb

Ayi

Doko lotulutsa kwa wofananira. Amati ngati cholowetsa A chili chachikulu kuposa B.

ageb

Ayi

Doko lotulutsa kwa wofananira. Amatsimikiziridwa ngati cholowetsa A chili chachikulu kuposa kapena chofanana ndi kulowetsa

aneb

Ayi

Doko lotulutsa kwa wofananira. Amatsimikiziridwa ngati kulowetsa A sikuli kofanana ndi kulowetsa B.

aleb

Ayi

Doko lotulutsa kwa wofananira. Amatsimikiziridwa ngati cholowetsa A chili chocheperako kapena chofanana ndi B.

6.6. Magawo

Gome lotsatirali likuwonetsa magawo a LPM_COMPARE IP core.

Gulu 20. LPM_COMPARE IP core Parameters

Dzina la Parameter

Mtundu

Chofunikira

LPM_WIDTH

Nambala Inde

LPM_REPRESENTATION

Chingwe

Ayi

LPM_PIPELINE

Nambala nambala

LPM_HINT

Chingwe

Ayi

Kufotokozera
Imatchula m'lifupi mwa madoko a dataa[] ndi datab[].
Imatchula mtundu wa kufananitsa kochitidwa. Makhalidwe NDI OSAINIKA NDIPOSASINIKA. Ngati sichinasinthidwe, mtengo wokhazikika ndi WOSAVUTA. Mtengo wa parameterwu ukakhazikitsidwa kukhala SIGNED, wofananitsayo amatanthauzira zomwe zalembedwazo ngati zikugwirizana ndi ziwiri.
Imatchula kuchuluka kwa mawotchi a latency yolumikizidwa ndi alb, aeb, agb, ageb, aleb, kapena aneb kutulutsa. Mtengo wa ziro (0) umasonyeza kuti palibe latency yomwe ilipo, komanso kuti ntchito yosakanikirana idzakhazikitsidwa. Ngati sichinasinthidwe, mtengo wokhazikika ndi 0 (wopanda mapaipi).
Imakulolani kuti mutchule magawo apadera a Intel mu kapangidwe ka VHDL filendi (.vhd). Mtengo wokhazikika ndi UNUSED.
anapitiriza…

Intel FPGA Integer Arithmetic IP Cores User Guide 28

Tumizani Ndemanga

6. LPM_COMPARE (Woyerekeza) 683490 | 2020.10.05
Dzina lazigawo LPM_TYPE INTENDED_DEVICE_FAMILY
ONE_INPUT_IS_CONSTANT

Type String String
Chingwe

Zofunikira No
Ayi

Kufotokozera
Imazindikiritsa dzina labungwe la library of parameterized modules (LPM) mu kapangidwe ka VHDL files.
Parameter iyi imagwiritsidwa ntchito popanga zitsanzo komanso zoyeserera zamakhalidwe. Mkonzi wa parameter amawerengera mtengo wa chizindikiro ichi.
Intel-specific parameter. Muyenera kugwiritsa ntchito parameter ya LPM_HINT kuti mufotokozere ONE_INPUT_IS_CONSTANT mu kapangidwe ka VHDL files. Makhalidwe ndi INDE, AYI, kapena OSAGWIRITSA NTCHITO. Amapereka kukhathamiritsa kwakukulu ngati kulowetsako kumakhala kosasintha. Ngati sichinasinthidwe, mtengo wokhazikika ndi NO.

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Intel FPGA Integer Arithmetic IP Cores User Guide 29

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7. ALTECC (Khodi Yowonongeka Yolakwika: Encoder / Decoder) IP Core

Chithunzi 6.

Intel imapereka maziko a ALTECC IP kuti agwiritse ntchito ECC. ECC imazindikira deta yowonongeka yomwe imapezeka kumbali yolandira panthawi yotumiza deta. Njira yokonza zolakwikayi ndiyoyenera kwambiri pakachitika zolakwika mwachisawawa m'malo mophulika.

ECC imazindikira zolakwika kudzera pakuyika ma encoding ndi decoding. Za example, ECC ikagwiritsidwa ntchito potumiza, zomwe zimawerengedwa kuchokera kugwero zimasungidwa musanatumizidwe kwa wolandila. Zotulutsa (mawu a code) kuchokera ku encoder zimakhala ndi data yaiwisi yowonjezeredwa ndi kuchuluka kwa ma bits ofananira. Chiwerengero chenicheni cha ma parity bits owonjezeredwa chimadalira kuchuluka kwa ma bits mu data yolowetsa. Mawu a code omwe amapangidwa amatumizidwa kumalo komwe akupita.

Wolandira amalandira mawu a code ndikuwamasulira. Chidziwitso chopezedwa ndi decoder chimatsimikizira ngati cholakwika chapezeka. Decoder imazindikira zolakwika zapang'ono-pang'ono ndi pawiri, koma zimatha kukonza zolakwika zapang'onopang'ono pazowonongeka. Mtundu uwu wa ECC ndi single error correction double error discovering (SECDED).

Mutha kukhazikitsa encoder ndi decoder ntchito za ALTECC IP core. Kuyika kwa data ku encoder kumasungidwa kuti apange mawu achinsinsi omwe ali ophatikizana ndi kuyika kwa data ndi ma bits opangidwa ofanana. Mawu a code omwe amapangidwa amatumizidwa ku gawo la decoder kuti asinthe asanafike pamalo omwe akupita. Decoder imapanga vector ya syndrome kuti idziwe ngati pali cholakwika chilichonse pamawu olandila. Decoder imakonza deta pokhapokha ngati cholakwika chapang'onopang'ono chikuchokera ku data bits. Palibe chizindikiro chomwe chimasonyezedwa ngati cholakwika chapang'ono-chimodzi chikuchokera ku ma bits ofananira. Decoder ilinso ndi zikwangwani zosonyeza momwe deta idalandidwira komanso zomwe wachita ndi decoder, ngati zilipo.

Ziwerengero zotsatirazi zikuwonetsa madoko a ALTECC IP pachimake.

ALTECC Encoder Ports

ALTECC_ENCODER

zambiri[]

q[]

koloko

aclr

inst

ISO 9001:2015 Adalembetsedwa

7. ALTECC (Khodi Yolakwika Yolakwika: Encoder / Decoder) IP Core 683490 | 2020.10.05

Chithunzi 7. ALTECC Decoder Ports

ALTECC_DECODER

data[] koloko

q[] err_detected err_corrected
err_fatal

aclr

inst

7.1. Mawonekedwe a ALTECC Encoder

ALTECC encoder IP core imapereka izi: · Imasunga ma encoding pogwiritsa ntchito Hamming Coding scheme · Imathandizira kukula kwa data 2 bits · Imathandizira mawonekedwe oyimira deta osayinidwa ndi osasainidwa asynchronous clear ndi wotchi imathandizira madoko

ALTECC encoder IP core imatenga ndikuyika deta pogwiritsa ntchito Hamming Coding scheme. Chiwembu cha Hamming Coding chimatenga ma bits ofananira ndikuwonjezera ku data yoyambirira kuti apange mawu otulutsa. Kuchuluka kwa ma bits omwe akuwonjezeredwa kumadalira kukula kwa deta.

Gome lotsatirali likuwonetsa kuchuluka kwa ma bits omwe amawonjezedwa pamitundu yosiyanasiyana ya makulidwe a data. Chigawo cha Total Bits chikuyimira chiwerengero chonse cha ma bits olowa ndi ma bits owonjezera.

Table 21.

Chiwerengero cha Parity Bits ndi Code Word Malinga ndi Data Width

Deta Width

Chiwerengero cha Parity Bits

Total Bits (Code Word)

2-4

3+1

6-8

5-11

4+1

10-16

12-26

5+1

18-32

27-57

6+1

34-64

58-64

7+1

66-72

Parity bit derivation imagwiritsa ntchito kuwunika kofanana. 1 pang'ono (yowonetsedwa patebulo ngati +1) imawonjezedwa ku ma bits ngati MSB ya mawu a code. Izi zimatsimikizira kuti mawu a code ali ndi nambala yofanana ya 1. Za example, ngati m'lifupi deta ndi 4 bits, 4 parity bits amawonjezeredwa deta kuti akhale mawu code ndi okwana 8 bits. Ngati 7 bits kuchokera ku LSB ya 8-bit code word ili ndi nambala yosamvetseka ya 1, 8th bit (MSB) ya code word ndi 1 kupanga chiwerengero cha 1 mu code word kukhala mofanana.
Chithunzi chotsatirachi chikuwonetsa mawu opangidwa ndi ma code komanso makonzedwe a ma bits ndi ma data bits mu 8-bit data input.

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Intel FPGA Integer Arithmetic IP Cores User Guide 31

7. ALTECC (Khodi Yolakwika Yolakwika: Encoder / Decoder) IP Core 683490 | 2020.10.05

Chithunzi 8.

Parity Bits ndi Data Bits Kukonzekera mu 8-Bit Generated Code Word

MSB

LSB

4 parity bits

4 magawo a data

ALTECC encoder IP core imangovomereza m'lifupi mwake 2 mpaka 64 bits nthawi imodzi. M'lifupi mwake 12 bits, 29 bits, ndi 64 bits, zomwe zimagwirizana bwino ndi zida za Intel, zimapanga zotulutsa 18 bits, 36 bits, ndi 72 bits motsatana. Mutha kuwongolera malire a bitselection mu mkonzi wa parameter.

7.2. Verilog HDL Prototype (ALTECC_ENCODER)
Chitsanzo chotsatira cha Verilog HDL chili mu Verilog Design File (.v) lpm.v mu edasynthesis directory.
module altecc_encoder #( parameter purpose_device_family = “osagwiritsidwa ntchito”, parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = “altecc_encoder”, parameter lpm_hint = “unused wireclr, input input waya wotchi, waya wolowetsa [width_dataword-1:0] data, waya wotuluka [width_codeword-1:0] q); endmodule

7.3. Mtundu wa Verilog HDL (ALTECC_DECODER)
Chitsanzo chotsatira cha Verilog HDL chili mu Verilog Design File (.v) lpm.v mu edasynthesis directory.
module altecc_decoder #( parameter purpose_device_family = “osagwiritsidwa ntchito”, parameter lpm_pipeline = 0, parameter width_codeword = 8, parameter width_dataword = 8, parameter lpm_type = “altecc_decoder”, parameter lpm_hint = “unused wireclr, input input waya wotchi, waya wolowetsa [width_codeword-1:0] data, waya wotuluka err_corrected, output wire err_detected, outout wire err_fatal, output wire [width_dataword-1:0] q); endmodule

Intel FPGA Integer Arithmetic IP Cores User Guide 32

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7. ALTECC (Khodi Yolakwika Yolakwika: Encoder / Decoder) IP Core 683490 | 2020.10.05
7.4. VHDL Component Declaration (ALTECC_ENCODER)
Chidziwitso cha gawo la VHDL chili mu VHDL Design File (.vhd) altera_mf_components.vhd mu libraryvhdlaltera_mf directory.
component altecc_encoder generic (cholinga_device_family: chingwe := "osagwiritsidwa ntchito"; lpm_pipeline: Natural := 0; width_codeword:natural:= 8; width_dataword:natural:= 8; lpm_hint:string := "UNUSED "typeal":cclpte ”); port ( aclr: mu std_logic := '0'; wotchi: mu std_logic := '0'; wotchi: mu std_logic := '1'; deta: mu std_logic_vector (width_dataword-1 downto 0); q: kunja std_logic_vector (width_codeword -1 mpaka 0)); mapeto chigawo;
7.5. VHDL Component Declaration (ALTECC_DECODER)
Chidziwitso cha gawo la VHDL chili mu VHDL Design File (.vhd) altera_mf_components.vhd mu libraryvhdlaltera_mf directory.
component altecc_decoder generic ( cholinga_device_family: chingwe : = "osagwiritsidwa ntchito"; lpm_pipeline: Natural := 0; width_codeword: natural := 8; width_dataword: natural := 8; lpm_hint:string := "UNUSED "typeal: cclpte"; ”); port( aclr:mu std_logic := '0'; wotchi: mu std_logic := '0'; wotchi: mu std_logic := '1'; deta: mu std_logic_vector(width_codeword-1 downto 0); err_corrected: out std_logic; err_detected : out std_logic; q: out std_logic_vector(width_dataword-1 downto 0); syn_e: out std_logic); mapeto chigawo;
7.6. VHDL LIBRARY_USE Declaration
Chilengezo cha VHDL LIBRARY-USE sichifunikira ngati mugwiritsa ntchito VHDL Component Declaration.
LAIBULALE atera_mf; GWIRITSANI ntchito altera_mf.altera_mf_components.all;
7.7. Encoder Ports
Matebulo otsatirawa akulemba madoko olowera ndi otuluka a ALTECC encoder IP core.

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Intel FPGA Integer Arithmetic IP Cores User Guide 33

7. ALTECC (Khodi Yolakwika Yolakwika: Encoder / Decoder) IP Core 683490 | 2020.10.05

Table 22. ALTECC Encoder Input Ports

Dzina la Port

Chofunikira

Kufotokozera

zambiri[]

Inde

Doko lolowetsa data. Kukula kwa doko lolowera kumatengera WIDTH_DATAWORD

mtengo wa parameter. Doko la data[] lili ndi data yomwe iyenera kusungidwa.

koloko

Inde

Doko lolowetsa mawotchi lomwe limapereka chizindikiro cha wotchi kuti mulunzanitse kabisidwe.

Doko la wotchi likufunika pamene mtengo wa LPM_PIPELINE uli waukulu kuposa 0.

koloko

Ayi

Wotchi imathandizira. Ngati yasiyidwa, mtengo wokhazikika ndi 1.

aclr

Ayi

Asynchronous zomveka bwino. Chizindikiro chogwira ntchito cha aclr chingagwiritsidwe ntchito nthawi iliyonse kuti

asynchronously chotsani zolembera.

Table 23. ALTECC Encoder Output Ports

Dzina Lamadoko q[]

Zofunikira Inde

Kufotokozera
Doko lotulutsa data losungidwa. Kukula kwa doko lotulutsa kumadalira WIDTH_CODEWORD mtengo.

7.8. Decoder Ports

Matebulo otsatirawa amalemba zolowetsa ndi zotuluka za ALTECC decoder IP core.

Table 24. ALTECC Decoder Input Ports

Dzina la Port

Chofunikira

Kufotokozera

zambiri[]

Inde

Doko lolowetsa data. Kukula kwa doko lolowera kumatengera WIDTH_CODEWORD mtengo wagawo.

koloko

Inde

Doko lolowetsa mawotchi lomwe limapereka chizindikiro cha wotchi kuti mulunzanitse kabisidwe. Doko la wotchi likufunika pamene mtengo wa LPM_PIPELINE uli waukulu kuposa 0.

koloko

Ayi

Wotchi imathandizira. Ngati yasiyidwa, mtengo wokhazikika ndi 1.

aclr

Ayi

Asynchronous zomveka bwino. Chizindikiro chogwira ntchito cha aclr chingagwiritsidwe ntchito nthawi iliyonse kuti muchotsere ma registry mwachisawawa.

Table 25. ALTECC Decoder Output Ports

Dzina Lamadoko q[]

Zofunikira Inde

Kufotokozera
Decoded data linanena bungwe port. Kukula kwa doko lotulutsa kumadalira WIDTH_DATAWORD mtengo.

err_anazindikira Inde

Lembani chizindikiro chosonyeza momwe data yalandilidwa ndikutchula zolakwika zilizonse zomwe zapezeka.

err_correct Inde d

Lembani chizindikiro chosonyeza momwe data yalandirira. Imatanthawuza cholakwika chapang'onopang'ono chomwe chapezedwa ndikukonzedwa. Mutha kugwiritsa ntchito deta chifukwa idakonzedwa kale.

err_fatal

Inde

Lembani chizindikiro chosonyeza momwe data yalandirira. Imatanthawuza cholakwika chapawiri chomwe chapezeka, koma chosakonzedwa. Musagwiritse ntchito deta ngati chizindikirochi chikutsimikiziridwa.

syn_e

Ayi

Chizindikiro chotulutsa chomwe chimakwera kwambiri pakapezeka cholakwika chimodzi pagawo

zidutswa.

7.9. Encoder Parameters
Gome lotsatirali likulemba magawo a ALTECC encoder IP core.

Intel FPGA Integer Arithmetic IP Cores User Guide 34

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7. ALTECC (Khodi Yolakwika Yolakwika: Encoder / Decoder) IP Core 683490 | 2020.10.05

Table 26. ALTECC Encoder Parameters

Dzina la Parameter

Mtundu

Chofunikira

Kufotokozera

WIDTH_DATAWORD

Nambala Inde

Imatchula m'lifupi mwa data yaiwisi. Miyezo imachokera ku 2 mpaka 64. Ngati yasiyidwa, mtengo wokhazikika ndi 8.

WIDTH_CODEWORD

Nambala Inde

Imatchula m'lifupi mwamawu ofananira nawo. Miyezo yovomerezeka ndi kuyambira 6 mpaka 72, kupatula 9, 17, 33, ndi 65. Ngati zisiyidwa, mtengo wokhazikika ndi 13.

LPM_PIPELINE

Nambala nambala

Imatchula payipi yozungulira. Makhalidwe amachokera ku 0 mpaka 2. Ngati mtengo ndi 0, madoko sanalembetsedwe. Ngati mtengo ndi 1, madoko otuluka amalembetsedwa. Ngati mtengo ndi 2, madoko olowera ndi zotuluka amalembetsedwa. Ngati yasiyidwa, mtengo wokhazikika ndi 0.

7.10. Decoder Parameters

Gome lotsatirali limatchula magawo a IP a ALTECC decoder.

Table 27. ALTECC Decoder Parameters

Dzina lazigawo WIDTH_DATAWORD

Lembani Nambala

Chofunikira

Kufotokozera

Inde

Imatchula m'lifupi mwa data yaiwisi. Makhalidwe ndi 2 mpaka 64. The

mtengo wokhazikika ndi 8.

WIDTH_CODEWORD

Nambala

Inde

Imatchula m'lifupi mwamawu ofananira nawo. Ma values ndi 6

mpaka 72, kupatula 9, 17, 33, ndi 65. Ngati zitasiyidwa, mtengo wokhazikika

ndi 13.

LPM_PIPELINE

Nambala

Ayi

Imatchula kaundula wa dera. Makhalidwe amachokera ku 0 mpaka 2. Ngati

mtengo ndi 0, palibe kaundula yemwe akugwiritsidwa ntchito. Ngati mtengo ndi 1, ndiye

zotuluka zimalembetsedwa. Ngati mtengo ndi 2, zonse zolowetsa ndi za

zotuluka amalembetsedwa. Ngati mtengo ndi waukulu kuposa 2, onjezerani

ma registas amakhazikitsidwa pazotulutsa zowonjezera

kuchedwa. Ngati yasiyidwa, mtengo wokhazikika ndi 0.

Pangani doko la 'syn_e'

Nambala

Ayi

Yatsani chizindikiro ichi kuti mupange doko la syn_e.

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Intel FPGA Integer Arithmetic IP Cores User Guide 35

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8. Intel FPGA Kuchulukitsa Adder IP Core

Chithunzi 9.

The Intel FPGA Multiply Adder (Intel Stratix 10, Intel Arria 10, ndi Intel Cyclone 10 GX zipangizo) kapena ALTERA_MULT_ADD (Arria V, Stratix V, ndi Cyclone V zipangizo) IP core imakupatsani mwayi wogwiritsa ntchito zowonjezera-adder.

Chithunzi chotsatira chikuwonetsa madoko a Intel FPGA Multiply Adder kapena ALTERA_MULT_ADD IP core.

Intel FPGA Kuchulukitsa Adder kapena ALTERA_MULT_ADD Madoko

Intel FPGA Kuchulukitsa Adder kapena ALTERA_MULT_ADD

dataa[] signa datab[] signb datac[] coefsel0[] coefsel1[] coefsel2[] coefsel3[] addnsub1 addnsub3 aclr/sclr[] scanina[] wotchi0 koloko1 koloko2 ena0 ena1 ena2 sload_accum
accum_sloadchainin[]

scanouta[] chotsatira[]

acl0 acl1

inst
Wochulukitsa amavomereza zolowetsa, kuchulutsa zikhalidwe pamodzi kenako ndikuwonjezera kapena kuchotsa kuzinthu zamagulu ena onse.
Ngati m'lifupi mwake ndi 9-bits m'lifupi kapena mocheperapo, ntchitoyi imagwiritsa ntchito 9 x 9 bit input multiplier kasinthidwe mu chipika cha DSP pazida zomwe zimathandiza 9 x 9 kasinthidwe. Ngati sichoncho, chipika cha DSP chimagwiritsa ntchito zochulukitsa 18 × 18-bit pokonza deta ndi m'lifupi pakati pa 10 bits ndi 18 bits. Ngati ma Intel FPGA Multiply Adder kapena ALTERA_MULT_ADD IP cores amachitika pamapangidwe, ntchitozo zimagawidwa ngati

ISO 9001:2015 Adalembetsedwa

8. Intel FPGA Kuchulukitsa Adder IP Core 683490 | 2020.10.05
midadada yosiyanasiyana ya DSP momwe mungathere kuti njira yopita ku midadada iyi ikhale yosinthika. Ochulutsa ochepa pa chipika cha DSP amalola kusankha njira zambiri mu chipika pochepetsa njira zopita ku chipangizo china.
Ma regista ndi zolembera zamapaipi owonjezera azizindikiro zotsatirazi amayikidwanso mkati mwa chipika cha DSP: · Kuyika kwa data · Osaina kapena osankhidwa osasainidwa · Onjezani kapena chotsani zosankhidwa · Zogulitsa zochulukitsa.
Pankhani ya zotsatira zotuluka, zolembera zoyamba zimayikidwa mu block ya DSP. Komabe zolembera zowonjezera za latency zimayikidwa muzinthu zomveka kunja kwa chipikacho. Kuzungulira kwa chipika cha DSP, kuphatikiza zolowetsa za data kwa ochulukitsa, zolowetsa zowongolera, ndi zotuluka za adder, gwiritsani ntchito njira yokhazikika kuti mulankhule ndi zida zonse. Malumikizidwe onse mu ntchitoyi amagwiritsa ntchito njira zodzipatulira mkati mwa block ya DSP. Mayendedwe odzipatulirawa akuphatikizanso ma registas osinthira mukasankha kusamutsa deta yolembetsedwa ya ochulukitsa kuchokera ku chochulukitsira chimodzi kupita ku chochulukitsira choyandikana.
Kuti mumve zambiri za ma block a DSP pamtundu uliwonse wa Stratix V, ndi Arria V, onani mutu wa DSP Blocks m'mabuku omwe ali patsamba la Literature and Technical Documentation.
Zambiri Zofananira AN 306: Kukhazikitsa Zochulukitsa mu Zida za FPGA
Amapereka zambiri pakukhazikitsa zochulukitsa pogwiritsa ntchito DSP ndi ma block block mu zida za Intel FPGA.
8.1. Mbali
Intel FPGA Multiply Adder kapena ALTERA_MULT_ADD IP core ili ndi izi: · Imapanga zochulutsa kuti zichulukitse magawo awiri ovuta.
manambala Zindikirani: Mukamanga zochulukitsa zokulirapo kuposa kukula komwe kumathandizidwa pakhoza /
kudzakhala kukhudzidwa kwa magwiridwe antchito chifukwa cha kutsika kwa midadada ya DSP. · Imathandizira makulidwe a data a 1 256 bits · Imathandizira mawonekedwe oyimira deta osayinidwa ndi osasainidwa · Imathandizira kuyika mapaipi okhala ndi configurable input latency · Amapereka mwayi wosinthira pakati pa chithandizo cha data chomwe chasainidwa ndi chosasainidwa kusankha kosinthika komanso kofananira bwino komanso wotchi kumathandizira madoko olowetsa · Imathandizira kulembetsa kuchedwa kwa systolic · Imathandizira pre-adder ndi ma coefficients 8 olemetsa pachochulutsa chilichonse · Imathandizira kulemetsa kosalekeza kuti zigwirizane ndi mayankho osonkhanitsa

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Intel FPGA Integer Arithmetic IP Cores User Guide 37

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8.1.1. Pre-adder
Ndi pre-adder, kuwonjezera kapena kuchotsera kumachitika musanadyetse chochulukitsa.
Pali mitundu isanu ya adder: · Njira yosavuta · Coefficient mode · Malo olowetsa · Square mode · Constant mode

Zindikirani:

Pamene pre-adder ikugwiritsidwa ntchito (pre-adder coefficient/input/square mode), zonse zolowetsa deta ku multiplier ziyenera kukhala ndi wotchi yofanana.

8.1.1.1. Pre-adder Simple Mode

Munjira iyi, ma operands onse awiri amachokera ku madoko olowera ndipo pre-adder sagwiritsidwa ntchito kapena kulambalalitsidwa. Iyi ndiye njira yokhazikika.

Chithunzi 10. Pre-adder Simple Mode
ndi 0 b0

Mulu 0

zotsatira

8.1.1.2. Pre-adder Coefficient Mode
Munjira iyi, operand imodzi yochulukitsa imachokera ku pre-adder, ndipo operand ina imachokera ku coefficient yosungirako mkati. The coefficient yosungirako amalola mpaka 8 preset constants. Zizindikiro za coefficient kusankha ndi coefsel[0..3].
Mawonekedwe awa akufotokozedwa mu equation yotsatira.

Zotsatirazi zikuwonetsa pre-adder coefficient mode ya chochulukitsira.

Chithunzi 11. Pre-adder Coefficient Mode

Preadder

Mulu 0

+/-

zotsatira

coefsel0 ng'ombe

Intel FPGA Integer Arithmetic IP Cores User Guide 38

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8. Intel FPGA Kuchulukitsa Adder IP Core 683490 | 2020.10.05
8.1.1.3. Mmene Mungalowetsere Adder Munjira iyi, ntchito yochulutsa imodzi imachokera ku pre-adder, ndipo operand ina imachokera ku datac[] lolowetsa. Mawonekedwe awa akufotokozedwa mu equation yotsatira.

Zotsatirazi zikuwonetsa mawonekedwe a pre-adder alowetsamo chochulukitsa.

Chithunzi 12. Pre-adder Input Mode
ndi 0 b0

Mulu 0

+/-

zotsatira

8.1.1.4. Pre-adder Square Mode Njira iyi ikuwonetsedwa mu equation yotsatira.

Zotsatirazi zikuwonetsa pre-adder square mode ya zochulukitsa ziwiri.

Chithunzi 13. Pre-adder Square Mode
ndi 0 b0

Mulu 0

+/-

zotsatira

8.1.1.5. Pre-adder Constant Mode
Munjira iyi, operand imodzi yochulukitsa imachokera ku doko lolowera, ndipo operand ina imachokera ku coefficient yosungirako mkati. The coefficient yosungirako amalola mpaka 8 preset constants. Zizindikiro za coefficient kusankha ndi coefsel[0..3].
Mawonekedwe awa akufotokozedwa mu equation yotsatira.

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Intel FPGA Integer Arithmetic IP Cores User Guide 39

8. Intel FPGA Kuchulukitsa Adder IP Core 683490 | 2020.10.05

Chithunzi chotsatira chikuwonetsa mawonekedwe a pre-adder mosalekeza a multiplier.

Chithunzi 14. Pre-adder Constant Mode
a0

Mulu 0

zotsatira

gawo 0
khofi
8.1.2. Systolic Delay Register
Muzomangamanga za systolic, zomwe zalowetsedwa zimalowetsedwa m'marejista angapo omwe amakhala ngati buffer ya data. Kaundula aliyense amapereka zolowetsa sample ku chochulukitsira pomwe chimachulukitsidwa ndi koyefiyeti. The chain adder imasunga zotsatira zophatikizika pang'onopang'ono kuchokera ku chochulukitsira ndi zotsatira zolembetsedwa kale kuchokera ku khomo lolowera la chainin[] kuti apange chotsatira chomaliza. Chilichonse chowonjezera chochulukitsa chiyenera kuchedwetsedwa ndi kuzungulira kumodzi kuti zotsatira zigwirizane bwino zikaphatikizidwa. Kuchedwa kulikonse kotsatizana kumagwiritsidwa ntchito kuthana ndi ma coefficient memory ndi bafa ya data ya zinthu zawo zochulukitsa-owonjezera. Za example, kuchedwa kumodzi kwa gawo lowonjezera lachiwiri, kuchedwa kuwiri kwa chinthu chachitatu chochulukitsa, ndi zina zotero.
Chithunzi 15. Systolic Registers
Zizindikiro za Systolic

x(t) c(0)

S -1

c(1)

S -1

c(2)

S -1

c(N-1)

S -1

S -1 y(t)

x(t) imayimira zotsatira zochokera kumayendedwe opitilira samples ndi y (t)
imayimira chidule cha seti ya zolowetsa samples, ndipo m'kupita kwa nthawi, kuchulukitsa ndi awo
ma coefficients osiyanasiyana. Zonse zolowetsa ndi zotuluka zimayenda kuchokera kumanzere kupita kumanja. The c(0) to c(N-1) amatanthauza coefficients. Ma regista akuchedwa kwa systolic amawonetsedwa ndi S-1, pomwe 1 imayimira kuchedwa kwa wotchi imodzi. Ma regista akuchedwa a Systolic amawonjezedwa pa
zolowetsa ndi zotulukapo za pipelining m'njira yomwe imatsimikizira zotsatira kuchokera ku
multiplier operand ndi ndalama zomwe zasonkhanitsidwa zimakhala zogwirizana. Izi processing chinthu
imapangidwanso kuti ipange dera lomwe limaphatikiza ntchito yosefera. Ntchito iyi ndi
kuwonetsedwa mu equation yotsatira.

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N imayimira kuchuluka kwa data yomwe yalowa mu accumulator, y (t) imayimira zotuluka pa nthawi t, A (t) imayimira kulowetsa pa nthawi t, ndipo B (i) ndi ma coefficients. The t ndi i mu equation zimagwirizana ndi nthawi ina yake mu nthawi, kotero kuwerengera zotuluka s.ample y(t) pa nthawi t, gulu la zolowetsa sampkuchepera pa N malo osiyanasiyana mu nthawi, kapena A(n), A(n-1), A(n-2), … A(n-N+1) ndiyofunika. Gulu la N zolowetsa sampLes amachulukitsidwa ndi ma coefficients a N ndikuphatikizidwa pamodzi kupanga chotsatira chomaliza y.
Zomangamanga za systolic registry zimapezeka pamitundu ya sum-of-2 ndi sum-of-4. Pamitundu yonse ya zomangamanga za systolic, chizindikiro choyamba cha chainin chiyenera kumangirizidwa ku 0.
Chithunzi chotsatira chikuwonetsa kukhazikitsidwa kwa kaundula kwa systolic kwa 2 ochulukitsa.
Chithunzi 16. Systolic Delay Registry Kukhazikitsidwa kwa 2 Multipliers
unyolo

Mulu 0

+/-

Mulu 1

+/-

zotsatira
Chiwerengero cha ochulukitsa awiri chikufotokozedwa mu equation ili pansipa.
Chithunzi chotsatira chikuwonetsa kukhazikitsidwa kwa kaundula kwa systolic kwa 4 ochulukitsa.

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Chithunzi 17. Systolic Delay Registry Kukhazikitsidwa kwa 4 Multipliers
unyolo

Mulu 0

+/-

Mulu 1

+/-

Mulu 2

+/-

Mulu 3

+/-

zotsatira
Chiwerengero cha ochulukitsa anayi chikufotokozedwa mu equation ili pansipa. Chithunzi 18. Chiwerengero cha 4 Ochulukitsa
Zotsatirazi zikulemba advantages of systolic registry kukhazikitsa: · Imachepetsa kugwiritsa ntchito zinthu za DSP

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8.1.3. Ingotsitsani Constant
The pre-load mosalekeza imayendetsa ntchito yolimbikitsira ndikukwaniritsa mayankho a accumulator. Zolondola LOADCONST_VALUE zimayambira 0. Mtengo wokhazikika ndi wofanana ndi 64N, pomwe N = LOADCONST_VALUE. Pamene LOADCONST_VALUE yakhazikitsidwa ku 2, mtengo wokhazikika ndi wofanana ndi 64. Izi zitha kugwiritsidwa ntchito ngati kuzungulira kokondera.
Chithunzi chotsatirachi chikuwonetsa kukhazikitsidwa kokhazikika kokhazikika.
Chithunzi 19. Pre-load Constant

Ndemanga za Accumulator

mosalekeza

Mulu 0

+/-

Mulu 1

+/b1

zotsatira

accum_sload sload_accum

Onani ma IP cores otsatirawa pakuchulutsa kwina: · ALTMULT_ACCUM · ALTMEMMULT · LPM_MULT
8.1.4. Double Accumulator
The double accumulator Mbali amawonjezera kaundula zina mu accumulator mayankho njira. Kaundula wa accumulator wapawiri amatsata zolembera zotulutsa, zomwe zimaphatikizapo wotchi, wotchiyo, ndi aclr. Regista yowonjezera yowonjezera imabweretsa zotsatira ndi kuchedwa kwa mkombero umodzi. Izi zimakuthandizani kuti mukhale ndi ma accumulator njira ziwiri zowerengera zomwe zimagwiritsidwa ntchito.
Chithunzi chotsatirachi chikuwonetsa kukhazikitsidwa kwapawiri accumulator.

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Chithunzi 20. Double Accumulator

Mutha kulembetsa ku Accu mulator

Accu mulator feedba ck

Mulu 0

+/-

Mulu 1

+/b1

Kaundula wa Zotuluka Zotuluka

8.2. Verilog HDL Prototype
Mutha kupeza mtundu wa Intel FPGA Multiply Adder kapena ALTERA_MULT_ADD Verilog HDL prototype file (altera_mult_add_rtl.v) mu librarymegafunctions directory.
8.3. Chidziwitso Chachigawo cha VHDL
Chidziwitso cha gawo la VHDL chili mu altera_lnsim_components.vhd mu libraryvhdl altera_lnsim directory.
8.4. VHDL LIBRARY_USE Declaration
Chilengezo cha VHDL LIBRARY-USE sichifunikira ngati mugwiritsa ntchito VHDL Component Declaration.
LAIBULALE atera_mf; GWIRITSANI ntchito altera_mf.altera_mf_components.all;

8.5. Zizindikiro

Matebulo otsatirawa akuwonetsa zolowetsa ndi zotuluka za Multiply Adder Intel FPGA IPor ALTERA_MULT_ADD IP core.

Table 28. Chulukitsani Zizindikiro za Adder Intel FPGA IPor ALTERA_MULT_ADD

Chizindikiro

Chofunikira

Kufotokozera

dataa_0[]/dataa_1[]/

Inde

dataa_2[]/data_3[]

Kulowetsa kwa data ku chochulukitsira. Malo olowera [NUMBER_OF_MULTIPLIERS * WIDTH_A – 1 … 0] lonse
anapitiriza…

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Chizindikiro cha datab_0[]/datab_1[]/ datab_2[]/datab_3[] datac_0[] /datac_1[]/ datac_2[]/datac_3[] wotchi[1:0] aclr[1:0] sclr[1:0] ena [1:0] chizindikiro
chizindikiro
scanina[] accum_sload

Zofunika Inde Ayi
Ayi Ayi Ayi Ayi Ayi
Ayi
Ayi Ayi

Kufotokozera
Mtundu woyerekeza wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) kuzizindikirozi. Mukapereka mtengo wa X kuzizindikirozi, mtengo wa X umafalikira pazizindikiro zotuluka.
Kulowetsa kwa data ku chochulukitsira. Lowetsani chizindikiro [NUMBER_OF_MULTIPLIERS * WIDTH_B – 1 … 0] m'lifupi Mtundu wofananira wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) pazizindikirozi. Mukapereka mtengo wa X kuzizindikirozi, mtengo wa X umafalikira pazizindikiro zotuluka.
Kulowetsa kwa data ku chochulukitsira. Lowetsani chizindikiro [NUMBER_OF_MULTIPLIERS * WIDTH_C – 1, … 0] wide Sankhani INPUT ya Sankhani preadder mode parameter kuti mutsegule ma siginowa. Mtundu woyerekeza wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) kuzizindikirozi. Mukapereka mtengo wa X kuzizindikirozi, mtengo wa X umafalikira pazizindikiro zotuluka.
Doko lolowera koloko ku kaundula wogwirizana. Chizindikiro ichi chitha kugwiritsidwa ntchito ndi kaundula aliyense pakatikati pa IP. Mtundu woyerekeza wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) kuzizindikirozi. Mukapereka mtengo wa X kuzizindikirozi, mtengo wa X umafalikira pazizindikiro zotuluka.
Asynchronous zomveka bwino ku register yofananira. Mtundu woyerekeza wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) kuzizindikirozi. Mukapereka mtengo wa X kuzizindikirozi, mtengo wa X umafalikira pazizindikiro zotuluka.
Kulowetsa momveka bwino kwa kaundula kofananira. Mtundu woyerekeza wa IP iyi umathandizira kufunikira kwa X komwe sikunadziwike pazizindikirozi. Mukapereka mtengo wa X kuzizindikirozi, mtengo wa X umafalikira pazizindikiro zotuluka
Yambitsani kulowetsa kwa siginecha ku regista yofananira. Mtundu woyerekeza wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) kuzizindikirozi. Mukapereka mtengo wa X kuzizindikirozi, mtengo wa X umafalikira pazizindikiro zotuluka.
Imatchula chiwerengero cha kuchulukitsa kowonjezera A. Ngati chizindikiro cha siginecha chili chapamwamba, chochulukitsa chimagwira chizindikiro cha ochulukitsa A ngati nambala yosainidwa. Ngati chizindikiro cha siginecha chili chochepa, wochulukitsa amatengera chizindikiro chochulukitsa A ngati nambala yosasainidwa. Sankhani VARIABLE ya mtundu wanji woyimira wa Multipliers A zolowetsa kuti mutsegule chizindikirochi. Mtundu woyerekeza wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) ku siginecha iyi. Mukapereka mtengo wa X pazowonjezera izi, mtengo wa X umafalikira pazizindikiro zotuluka.
Imatchula chiwonetsero cha manambala cha chizindikiro cha B chochulukitsa. Ngati chizindikiro cha signb ndichokwera, chochulukitsa chimatengera chizindikiro cha B chochulukitsa ngati nambala yofananira ya awiri omwe asainidwa. Ngati chizindikiro cha signb chili chochepa, chochulukitsa chimatengera chizindikiro cha B chochulukitsa ngati nambala yosasainidwa. Mtundu woyerekeza wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) ku siginecha iyi. Mukapereka mtengo wa X pazowonjezera izi, mtengo wa X umafalikira pazizindikiro zotuluka.
Cholowetsa cha sikani A. Chizindikiro cholowetsa [WIDTH_A – 1, … 0] lonse. Pamene INPUT_SOURCE_A parameter ili ndi mtengo wa SCANA, scanina[] siginecha imafunika.
Mwamphamvu imatchula ngati mtengo wa accumulator ndi wokhazikika. Ngati chizindikiro cha accum_sload ndichotsika, ndiye kuti zochulukitsa zimayikidwa mu accumulator. Osagwiritsa ntchito accum_sload ndi sload_accum nthawi imodzi.
anapitiriza…

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Signal sload_acum
chainin[] addnsub1
kuwonjezera3
coefsel0[] coefsel1[] coefsel2[] coefsel3[]

Zofunikira No
Ayi Ayi
Ayi
Ayi Ayi Ayi Ayi

Kufotokozera
Mtundu woyerekeza wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) ku siginecha iyi. Mukapereka mtengo wa X pazowonjezera izi, mtengo wa X umafalikira pazizindikiro zotuluka.
Mwamphamvu imatchula ngati mtengo wa accumulator ndi wokhazikika. Ngati chizindikiro cha sload_acum ndichokwera, ndiye kuti zochulukitsa zimayikidwa mu accumulator. Osagwiritsa ntchito accum_sload ndi sload_accum nthawi imodzi. Mtundu woyerekeza wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) ku siginecha iyi. Mukapereka mtengo wa X pazowonjezera izi, mtengo wa X umafalikira pazizindikiro zotuluka.
Mabasi otengera zotsatira za Adder kuchokera m'ma s am'mbuyomotage. Chizindikiro cholowetsa [WIDTH_CHAININ – 1, … 0] lonse.
Onjezani kapena kuchotsera pazotuluka kuchokera pagulu loyamba la ochulutsa. Lowetsani 1 kuti muwonjezere chizindikiro cha addnsub1 kuti muwonjezere zotuluka kuchokera paochulutsa awiri oyamba. Lowetsani 0 ku chizindikiro cha addnsub1 kuti muchotse zotuluka kuchokera kwa ochulutsa awiri oyamba. Mtundu woyerekeza wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) ku siginecha iyi. Mukapereka mtengo wa X pazowonjezera izi, mtengo wa X umafalikira pazizindikiro zotuluka.
Onjezani kapena kuchotsera pazotuluka kuchokera pagulu loyamba la ochulutsa. Lowetsani 1 kuti muwonjezere chizindikiro cha addnsub3 kuti muwonjezere zotuluka kuchokera pagulu lachiwiri la ochulukitsa. Lowetsani 0 ku chizindikiro cha addnsub3 kuti muchotse zotuluka kuchokera kwa ochulukitsa oyamba. Mtundu woyerekeza wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) ku siginecha iyi. Mukapereka mtengo wa X pazowonjezera izi, mtengo wa X umafalikira pazizindikiro zotuluka.
Chizindikiro cholowera[0:3] mpaka chochulukitsa choyamba. Mtundu woyerekeza wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) ku siginecha iyi. Mukapereka mtengo wa X pazowonjezera izi, mtengo wa X umafalikira pazizindikiro zotuluka.
Chizindikiro cholowera molingana[0:3] mpaka chochulukitsa chachiwiri. Mtundu woyerekeza wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) ku siginecha iyi. Mukapereka mtengo wa X pazowonjezera izi, mtengo wa X umafalikira pazizindikiro zotuluka.
Chizindikiro cha coefficient[0:3] mpaka chochulukitsa chachitatu. Mtundu woyerekeza wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) ku siginecha iyi. Mukapereka mtengo wa X pazowonjezera izi, mtengo wa X umafalikira pazizindikiro zotuluka.
Chizindikiro chothandizira [0:3] mpaka chochulukitsa chachinayi. Mtundu woyerekeza wa IP iyi umathandizira mtengo wolowera womwe sunadziwike (X) ku siginecha iyi. Mukapereka mtengo wa X pazowonjezera izi, mtengo wa X umafalikira pazizindikiro zotuluka.

Table 29. Kuchulukitsa Adder Intel FPGA IP Kutulutsa Zizindikiro

Chizindikiro

Chofunikira

Kufotokozera

zotsatira []

Inde

Multiplier linanena bungwe chizindikiro. Chizindikiro chotulutsa [WIDTH_RESULT – 1 … 0] lonse

Mtundu woyerekeza wa IP iyi umathandizira mtengo wosazindikirika (X). Mukapereka mtengo wa X monga cholowetsa, mtengo wa X umafalitsidwa pa chizindikiro ichi.

scanout []

Ayi

Kutulutsa kwa sikeni A. Chizindikiro chotulutsa [WIDTH_A – 1..0] lonse.

Sankhani kupitilira 2 pa manambala ochulutsa ndikusankha Scan chain input ya Kodi kulowa A ndi chiyani kwa chochulukitsa cholumikizidwa ndi parameter kuti mutsegule chizindikirochi.

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8.6. Magawo

8.6.1. General Tab

Table 30. General Tab

Parameter

IP Yopangidwa ndi Parameter

Mtengo

Kodi ochulukitsa ndi chiyani?

chiwerengero_cha_m 1 - 4 zowonjezera

Kodi mabasi olowetsa A ayenera kukhala otambalala bwanji?

1-256

Kodi mabasi a B width_b akuyenera kukhala otambalala bwanji?

1-256

Kodi mabasi a 'zotsatira' akuyenera kukhala otambalala bwanji?

wide_result

1-256

Pangani wotchi yogwirizana nayo wotchi iliyonse

gui_associate Pa d_clock_enable Off e

8.6.2. Zowonjezera Ma Mode Tab

Table 31. Njira Zowonjezera Tab

Parameter

IP Yopangidwa ndi Parameter

Mtengo

Kukonzekera kwa Zotuluka

Lembani zotuluka za adder unit

gui_output_re On

gister

Kuzimitsa

Kodi mawotchi amachokera kuti?

gui_output_re gister_clock

Clock0 Clock1 Clock2

Kodi magwero omveka bwino asynchronous ndi ati?

gui_output_re gister_aclr

Palibe ACLR0 ACLR1

Kodi gwero la mawu omveka bwino a synchronous ndi chiyani?

gui_output_re gister_sclr

Palibe SCLR0 SCLR1

Ntchito ya Adder

Ndi ntchito yotani yomwe iyenera kuchitidwa pazotulutsa zamagulu awiri oyamba ochulukitsa?

gui_multiplier 1_direction

ADD, SUB, ARIABLE

Mtengo Wofikira 1
16

Kufotokozera
Chiwerengero cha ochulukitsa oti awonjezedwe palimodzi. Miyezo ndi 1 mpaka 4. Tchulani m'lifupi mwa doko la dataa[].

Tchulani m'lifupi mwa doko la datab[].

Tchulani m'lifupi mwazotsatira[] doko.

Kuzimitsa

Sankhani izi kuti mupange wotchi kuti igwire

pa koloko iliyonse.

Mtengo Wofikira

Kufotokozera

Off Clock0
PALIBE

Sankhani izi kuti mutsegule kaundula wa gawo la adder.
Sankhani Clock0, Clock1 kapena Clock2 kuti mutsegule ndikutchula komwe mawotchi amayambira. Muyenera kusankha Register zotuluka za adder unit kuti mutsegule izi.
Imatchula gwero lomveka bwino la kaundula wa adder. Muyenera kusankha Register zotuluka za adder unit kuti mutsegule izi.
Imatchula gwero lomveka bwino la kaundula wa adder. Muyenera kusankha Register zotuluka za adder unit kuti mutsegule izi.

ADD

Sankhani ntchito yowonjezeretsa kapena yochotsera kuti mugwiritse ntchito pazotulutsa pakati pa ochulukitsa oyamba ndi achiwiri.
· Sankhani ADD kuti muchite ntchito yowonjezera.
· Sankhani SUB kuti mugwire ntchito yochotsa.
· Sankhani VARIABLE kuti mugwiritse ntchito doko la addnsub1 pakuwongolera kowonjezera / kuchotsa.
anapitiriza…

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Parameter

IP Yopangidwa ndi Parameter

Mtengo

Lembani 'addnsub1' zolowetsa

gui_addnsub_ Pa multiplier_reg Off ister1

Kodi mawotchi amachokera kuti?

gui_addnsub_ multiplier_reg ister1_clock

Clock0 Clock1 Clock2

Kodi magwero omveka bwino asynchronous ndi ati?

gui_addnsub_ multiplier_aclr 1

Palibe ACLR0 ACLR1

Kodi gwero la mawu omveka bwino a synchronous ndi chiyani?

gui_addnsub_ multiplier_sclr 1

Palibe SCLR0 SCLR1

Ndi ntchito yotani yomwe iyenera kuchitidwa pazotulutsa za gulu lachiwiri la zochulukitsa?

gui_multiplier 3_direction

ADD, SUB, ARIABLE

Lembani 'addnsub3' zolowetsa

gui_addnsub_ Pa multiplier_reg Off ister3

Kodi mawotchi amachokera kuti?

gui_addnsub_ multiplier_reg ister3_clock

Clock0 Clock1 Clock2

Mtengo Wofikira
Off Clock0 PALIBE WOWONJEZA
Off Clock0

Kufotokozera
Pomwe VARIABLE mtengo wasankhidwa: · Thamangitsani chizindikiro cha addnsub1 kupita pamwamba kwa
ntchito yowonjezera. · Yendetsani chizindikiro cha addnsub1 mpaka chotsika
ntchito kuchotsa. Muyenera kusankha ochulukitsa opitilira awiri kuti mutsegule izi.
Sankhani izi kuti mutsegule zolembera za addnsub1 port. Muyenera kusankha KUSINTHA pa Zomwe ntchito iyenera kuchitidwa pazotsatira za ochulutsa awiri oyamba kuti izi zitheke.
Sankhani Clock0, Clock1 kapena Clock2 kuti mutchule chizindikiro cha wotchi ya addnsub1. Muyenera kusankha Kulembetsa 'addnsub1' kuti mutsegule izi.
Imatchula gwero lomveka bwino la kaundula wa addnsub1. Muyenera kusankha Kulembetsa 'addnsub1' kuti mutsegule izi.
Imatchula gwero lomveka bwino la kaundula wa addnsub1. Muyenera kusankha Kulembetsa 'addnsub1' kuti mutsegule izi.
Sankhani ntchito yowonjezera kapena yochotsera kuti mugwiritse ntchito pazotuluka pakati pa ochulukitsa achitatu ndi achinayi. · Sankhani ADD kuti muwonjezere
ntchito. · Sankhani SUB kuti muchotse
ntchito. · Sankhani VARIABLE kugwiritsa ntchito addnsub1
doko la kuwongolera kowonjezera / kuchotsa. Mtengo wa VARIABLE ukasankhidwa: · Yendetsani chizindikiro cha addnsub1 kupita pamwamba kuti muwonjezere ntchito. · Yendetsani chizindikiro cha addnsub1 mpaka chotsika kuti muchotse. Muyenera kusankha mtengo 4 wa ochulukitsa ndi chiyani? kuti mutsegule parameter iyi.
Sankhani izi kuti mutsegule zolembera za addnsub3 chizindikiro. Muyenera kusankha KUSINTHA pa Zomwe ntchito iyenera kuchitidwa pazotsatira za gulu lachiwiri la ochulutsa kuti izi zitheke.
Sankhani Clock0, Clock1 kapena Clock2 kuti mutchule chizindikiro cha wotchi ya addnsub3. Muyenera kusankha Register 'addnsub3′ athandizira kuti athe chizindikiro.
anapitiriza…

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Parameter
Kodi magwero omveka bwino asynchronous ndi ati?

IP Yopangidwa ndi Parameter

Mtengo

gui_addnsub_ multiplier_aclr 3

Palibe ACLR0 ACLR1

Kodi gwero la mawu omveka bwino a synchronous ndi chiyani?

gui_addnsub_ multiplier_sclr 3

Palibe SCLR0 SCLR1

Polarity Yambitsani `use_subadd'

gui_use_subn On

onjezani

Kuzimitsa

8.6.3. Multipliers Tab

Table 32. Multipliers Tab

Parameter

IP Yopangidwa ndi Parameter

Mtengo

Ndi chiyani

gui_represent

mawonekedwe oyimira_a

kwa Multipliers A zolowetsa?

ZOSAINIKA, ZOSASINIKA, ZOSINTHA

Lembani zolemba za `signa'

gui_register_s Yatsegulidwa

ine

Kuzimitsa

Kodi mawotchi amachokera kuti?

gui_register_s igna_clock

Clock0 Clock1 Clock2

Kodi magwero omveka bwino asynchronous ndi ati?

gui_register_s igna_aclr

Palibe ACLR0 ACLR1

Kodi gwero la mawu omveka bwino a synchronous ndi chiyani?

gui_register_s igna_sclr

Palibe SCLR0 SCLR1

Ndi chiyani

gui_represent

mawonekedwe oyimira_b

kwa Multipliers B zolowetsa?

ZOSAINIKA, ZOSASINIKA, ZOSINTHA

Lembani zolemba za `signb'

gui_register_s Yatsegulidwa

igb

Kuzimitsa

Mtengo Wofikira Palibe
PALIBE

Kufotokozera
Imatchula gwero lomveka bwino la kaundula wa addnsub3. Muyenera kusankha Kulembetsa 'addnsub3' kuti mutsegule izi.
Imatchula gwero lomveka bwino la kaundula wa addnsub3. Muyenera kusankha Register 'addnsub3′ athandizira kuti athe chizindikiro.

Kuzimitsa

Sankhani njira iyi kuti musinthe ntchitoyi

ya addnsub input port.

Thamangani addnsub mpaka m'mwamba kuti muchotse.

Thamangani addnsub mpaka pansi kuti muwonjezere ntchito.

Mtengo Wofikira

Kufotokozera

ZOSASINDWA Tchulani mtundu woyimira pazowonjezera A.

Kuzimitsa

Sankhani izi kuti mutsegule siginecha

kulembetsa.

Muyenera kusankha VARIABLE mtengo wa Kodi mawonekedwe oyimira a Multipliers A? parameter kuti mutsegule izi.

Koloko0

Sankhani Clock0 , Clock1 kapena Clock2 kuti mutsegule ndikutchula chizindikiro cha wotchi yolowetsamo zolembera.
Muyenera kusankha Kulembetsa `signa' kulowa kuti mutsegule izi.

PALIBE

Imatchula gwero lomveka bwino la kaundula wa siginecha.
Muyenera kusankha Kulembetsa `signa' kulowa kuti mutsegule izi.

PALIBE

Imatchula gwero lomveka bwino la kaundula wa zikwangwani.
Muyenera kusankha Kulembetsa `signa' kulowa kuti mutsegule izi.

ZOSASINDWA Tchulani mtundu woyimira pazowonjezera B zochulukitsa.

Kuzimitsa

Sankhani izi kuti mutsegule signb

kulembetsa.

anapitiriza…

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Parameter

IP Yopangidwa ndi Parameter

Mtengo

Mtengo Wofikira

Kodi mawotchi amachokera kuti?

gui_register_s ignb_clock

Clock0 Clock1 Clock2

Koloko0

Kodi magwero omveka bwino asynchronous ndi ati?

gui_register_s igb_aclr

Palibe ACLR0 ACLR1

Kodi gwero la mawu omveka bwino a synchronous ndi chiyani?

gui_register_s igb_sclr

Palibe SCLR0 SCLR1

Kuyika Kosintha
Lembani zolowetsa A za ochulukitsa
Kodi mawotchi amachokera kuti?

gui_input_reg On

ine_a

Kuzimitsa

gui_input_reg ister_a_clock

Clock0 Clock1 Clock2

PALIBE
Off Clock0

Kodi magwero omveka bwino asynchronous ndi ati?

gui_input_reg ister_a_aclr

Palibe ACLR0 ACLR1

Kodi gwero la mawu omveka bwino a synchronous ndi chiyani?

gui_input_reg ister_a_sclr

Palibe SCLR0 SCLR1

Lembani zolowetsa B za zochulukitsa
Kodi mawotchi amachokera kuti?

gui_input_reg On

ine_b

Kuzimitsa

gui_input_reg ister_b_clock

Clock0 Clock1 Clock2

PALIBE OCHOKERA PA Clock0

Kodi magwero omveka bwino asynchronous ndi ati?

gui_input_reg ister_b_aclr

Palibe ACLR0 ACLR1

PALIBE

Kodi gwero la mawu omveka bwino a synchronous ndi chiyani?

gui_input_reg ister_b_sclr

Palibe SCLR0 SCLR1

PALIBE

Kodi cholowetsa A chochulukitsa cholumikizidwa ndi chiyani?

gui_multiplier Multiplier input Multiplier

_a_zolowera

Jambulani zolowetsa za unyolo

Kufotokozera
Muyenera kusankha VARIABLE mtengo wa Kodi mawonekedwe oyimira pazolowetsa za Multipliers B ndi chiyani? parameter kuti mutsegule izi.
Sankhani Clock0 , Clock1 kapena Clock2 kuti mutsegule ndikutchula chizindikiro cha wotchi yolowera polembetsa. Muyenera kusankha Kulembetsa `signb' kuti muthandizire izi.
Imatchula gwero lomveka bwino la kaundula wa signb. Muyenera kusankha Kulembetsa `signb' kuti muthandizire izi.
Imatchula gwero lomveka bwino la kaundula wa zikwangwani. Muyenera kusankha Kulembetsa `signb' kuti muthandizire izi.
Sankhani izi kuti mutsegule zolembera zamabasi olowetsa data.
Sankhani Clock0, Clock1 kapena Clock2 kuti mutsegule ndikutchula chizindikiro cha wotchi yolembetsa ya basi yolowetsa data. Muyenera kusankha Kulembetsa kulowa A kwa chochulukitsa kuti mutsegule izi.
Imatchula gwero losasinthika la basi yolowetsa data. Muyenera kusankha Kulembetsa kulowa A kwa chochulukitsa kuti mutsegule izi.
Imatchula gwero lomveka bwino la basi ya dataa. Muyenera kusankha Kulembetsa kulowa A kwa chochulukitsa kuti mutsegule izi.
Sankhani izi kuti mutsegule zolembera zamabasi olowetsa datab.
Sankhani Clock0, Clock1 kapena Clock2 kuti mutsegule ndikutchula chizindikiro cha wotchi yolembetsa ya basi yolowetsa datab. Muyenera kusankha Lembani zolowetsa B za chochulukitsa kuti mutsegule izi.
Imatchula gwero losasinthika la basi yolowetsa datab. Muyenera kusankha Lembani zolowetsa B za chochulukitsa kuti mutsegule izi.
Imatchula gwero lomveka bwino la mabasi a datab. Muyenera kusankha Lembani zolowetsa B za chochulukitsa kuti mutsegule izi.
Sankhani gwero lolowera kuti mulowetse A pa chochulukitsa.
anapitiriza…

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Parameter

IP Yopangidwa ndi Parameter

Mtengo

Scanout A Registry Configuration

Lembani zotuluka za scan chain

gui_scanouta Pa

_lembetsa

Kuzimitsa

Kodi mawotchi amachokera kuti?

gui_scanouta _register_clock k

Clock0 Clock1 Clock2

Kodi magwero omveka bwino asynchronous ndi ati?

gui_scanouta _register_aclr

Palibe ACLR0 ACLR1

Kodi gwero la mawu omveka bwino a synchronous ndi chiyani?

gui_scanouta _register_sclr

Palibe SCLR0 SCLR1

8.6.4. Preadder Tab

Table 33. Preadder Tab

Parameter

IP Yopangidwa ndi Parameter

Mtengo

Sankhani pread mode

preadder_mo de

SIMPLE, COEF, INPUT, SQUARE, CONSTANT

Mtengo Wofikira

Kufotokozera
Sankhani Multiplier input kuti mugwiritse ntchito dataa input basi monga gwero la zochulutsa. Sankhani Scan chain input kuti mugwiritse ntchito basi ya scanin monga gwero la chochulukitsira ndi kuyatsa mabasi otuluka. Izi zilipo mukasankha 2, 3 kapena 4 ya Kodi ochulukitsa ndi otani? parameter.

Off Clock0 PALIBE

Sankhani njira iyi kuti mutsegule kaundula wa basi ya scanouta.
Muyenera kusankha Scan chain input ya Kodi kulowa A kwa chochulukitsa cholumikizidwa ku chiyani? parameter kuti mutsegule izi.
Sankhani Clock0, Clock1 kapena Clock2 kuti mutsegule ndikutchula chizindikiro cha wotchi yolembetsa ya basi yotuluka.
Muyenera kuyatsa Register zotuluka pa scan chain parameter kuti mutsegule izi.
Imatchula gwero losasinthika la basi ya scanouta.
Muyenera kuyatsa Register zotuluka pa scan chain parameter kuti mutsegule izi.
Imatchula gwero lomveka bwino la kaundula wa basi ya scanouta.
Muyenera kusankha Register zotuluka za scan chain parameter kuti mutsegule izi.

Mtengo Wofikira
ZOPEZA

Kufotokozera
Imatchula mawonekedwe ogwirira ntchito a preadder module. ZOTHANDIZA: Njira iyi idutsa preadder. Iyi ndiye njira yokhazikika. COEF: Njira iyi imagwiritsa ntchito mabasi olowetsa preadder ndi coefsel monga zolowetsa ku zochulukitsa. ZOTHANDIZA: Njirayi imagwiritsa ntchito kutulutsa kwa preadder ndi datac yolowetsa basi monga zolowera ku ochulukitsa. SQUARE: Njira iyi imagwiritsa ntchito kutulutsa kwa preadder monga zolowetsa zonse zochulukitsa.
anapitiriza…

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Parameter

IP Yopangidwa ndi Parameter

Mtengo

Sankhani mayendedwe otsogolera

gui_preadder ADD,

_njira

SUB

Kodi mabasi a C width_c akuyenera kukhala otambalala bwanji?

1-256

Kusintha kwa Kaundula wa Data C

Lembani zolowetsa za datac

gui_datac_inp On

ut_register

Kuzimitsa

Kodi mawotchi amachokera kuti?

gui_datac_inp ut_register_cl ock

Clock0 Clock1 Clock2

Kodi magwero omveka bwino asynchronous ndi ati?

gui_datac_inp ut_register_a clr

Palibe ACLR0 ACLR1

Kodi gwero la mawu omveka bwino a synchronous ndi chiyani?

gui_datac_inp ut_register_sc lr

Palibe SCLR0 SCLR1

Coefficients
Kodi m'lifupi mwake ng'ombeyo ikhale yotambasuka bwanji?

wide_coef

1-27

Kusintha kwa Registry ya Coef

Lembani zolowetsa za coefsel

gui_coef_regi On

ster

Kuzimitsa

Kodi mawotchi amachokera kuti?

gui_coef_regi ster_clock

Clock0 Clock1 Clock2

Mtengo Wofikira
ADD
16

Kufotokozera
CONSTANT: Njira iyi imagwiritsa ntchito basi yolowetsa data yokhala ndi preadder yolambalala ndi mabasi a coefsel monga zolowetsa ku zochulukitsa.
Imatchula ntchito ya pread. Kuti muyambitse izi, sankhani zotsatirazi kuti musankhe preadder mode: · COEF · INPUT · SQUARE or · CONSTANT
Imatchula kuchuluka kwa mabasi olowetsa C. Muyenera kusankha INPUT ya Sankhani preadder mode kuti mutsegule izi.

Pa Clock0 PALIBE

Sankhani izi kuti mutsegule zolembera zamabasi olowetsa datac. Muyenera kukhazikitsa INPUT kuti Sankhani preadder mode parameter kuti mutsegule izi.
Sankhani Clock0, Clock1 kapena Clock2 kuti mutchule chizindikiro cha wotchi yolowetsamo datac. Muyenera kusankha Register datac input kuti mutsegule parameter iyi.
Imatchula gwero lomveka bwino la kaundula wa datac. Muyenera kusankha Register datac input kuti mutsegule parameter iyi.
Imatchula gwero lomveka bwino la kaundula wa datac. Muyenera kusankha Register datac input kuti mutsegule parameter iyi.

Imatchula kuchuluka kwa ma bits a

basi ya coefsel.

Muyenera kusankha COEF kapena CONSTANT ya preadder mode kuti izi zitheke.

Pa Clock0

Sankhani izi kuti mutsegule kaundula wa mabasi a coefsel. Muyenera kusankha COEF kapena CONSTANT ya preadder mode kuti izi zitheke.
Sankhani Clock0, Clock1 kapena Clock2 kuti mutchule chizindikiro cha wotchi yolowetsamo kaundula wa coefsel. Muyenera kusankha Lembani zolowetsa za coefsel kuti mutsegule izi.
anapitiriza…

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Parameter
Kodi magwero omveka bwino asynchronous ndi ati?

IP Yopangidwa ndi Parameter

Mtengo

gui_coef_regi ster_aclr

Palibe ACLR0 ACLR1

Kodi gwero la mawu omveka bwino a synchronous ndi chiyani

gui_coef_regi ster_sclr

Palibe SCLR0 SCLR1

Coefficient_0 Kusintha

coef0_0 mpaka coef0_7

0x00000 0xFFFFFF

Coefficient_1 Kusintha

coef1_0 mpaka coef1_7

0x00000 0xFFFFFF

Coefficient_2 Kusintha

coef2_0 mpaka coef2_7

0x00000 0xFFFFFF

Coefficient_3 Kusintha

coef3_0 mpaka coef3_7

0x00000 0xFFFFFF

8.6.5. Accumulator Tab

Table 34. Accumulator Tab

Parameter

IP Yopangidwa ndi Parameter

Mtengo

Yambitsani accumulator?

akucumulator

INDE, AYI

Kodi ntchito ya accumulator ndi yotani?

accum_directi ADD,

SUB

Mtengo Wofikira Palibe
PALIBE
0x0000000 0
0x0000000 0
0x0000000 0
0x0000000 0

Kufotokozera
Imatchula gwero lomveka bwino la kaundula wa coefsel. Muyenera kusankha Lembani zolowetsa za coefsel kuti mutsegule izi.
Imatchula gwero lomveka bwino la kaundula wa coefsel. Muyenera kusankha Lembani zolowetsa za coefsel kuti mutsegule izi.
Imatchula kuchuluka kwa coefficient pa chochulukitsira choyamba ichi. Chiwerengero cha ma bitti chikhale chofanana ndi chomwe chafotokozedwera Kodi m'lifupi mwa ng'ombe iyenera kukhala yayikulu bwanji? parameter. Muyenera kusankha COEF kapena CONSTANT ya preadder mode kuti izi zitheke.
Imatchula kuchuluka kwa coefficient ya chochulukitsira chachiwirichi. Chiwerengero cha ma bitti chikhale chofanana ndi chomwe chafotokozedwera Kodi m'lifupi mwa ng'ombe iyenera kukhala yayikulu bwanji? parameter. Muyenera kusankha COEF kapena CONSTANT ya preadder mode kuti izi zitheke.
Imatchula kuchuluka kwa coefficient pa chochulukitsa chachitatu. Chiwerengero cha ma bitti chikhale chofanana ndi chomwe chafotokozedwera Kodi m'lifupi mwa ng'ombe iyenera kukhala yayikulu bwanji? parameter. Muyenera kusankha COEF kapena CONSTANT ya preadder mode kuti izi zitheke.
Imatchula kuchuluka kwa coefficient pa chochulukitsa chachinayi. Chiwerengero cha ma bitti chikhale chofanana ndi chomwe chafotokozedwera Kodi m'lifupi mwa ng'ombe iyenera kukhala yayikulu bwanji? parameter. Muyenera kusankha COEF kapena CONSTANT ya preadder mode kuti izi zitheke.

Mtengo Wofikira NO
ADD

Kufotokozera
Sankhani YES kuti muwongolere accumulator. Muyenera kusankha Kulembetsa kutulutsa kwa adder unit mukamagwiritsa ntchito accumulator.
Imatchula ntchito ya cholimbikitsira: · ADD powonjezera ntchito · SUB pochotsa. Muyenera kusankha YES kuti Yambitsani accumulator? parameter kuti mutsegule izi.
anapitiriza…

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Parameter
Kwezani Nthawi Zonse Yambitsani kutsitsa mosalekeza

IP Yopangidwa ndi Parameter

Mtengo

gui_ena_prelo On

ad_const

Kuzimitsa

Kodi doko la accumulate lolumikizidwa ndi chiyani?

gui_accumula ACCUM_SLOAD, te_port_select SLOAD_ACCUM

Sankhani mtengo wa preload loadconst_val 0 - 64

mosalekeza

Kodi mawotchi amachokera kuti?

gui_accum_sl oad_register_ wotchi

Clock0 Clock1 Clock2

Kodi magwero omveka bwino asynchronous ndi ati?

gui_accum_sl oad_register_ aclr

Palibe ACLR0 ACLR1

Kodi gwero la mawu omveka bwino a synchronous ndi chiyani?

gui_accum_sl oad_register_ sclr

Palibe SCLR0 SCLR1

Yambitsani kuchulukitsa kawiri

gui_double_a On

ccm

Kuzimitsa

Mtengo Wofikira

Kufotokozera

Kuzimitsa

Yambitsani accum_sload kapena

sload_accum zizindikiro ndi zolembera zolembera

kuti musankhe mwanzeru zolowetsa ku

chosakanizira.

Pamene accum_sload ili yotsika kapena sload_accum, zochulukitsa zimadyetsedwa mu accumulator.

Pamene accum_sload ili yokwera kapena sload_accum, wogwiritsa ntchito nthawi zonse amapatsidwa chakudya mu accumulator.

Muyenera kusankha YES kuti Yambitsani accumulator? parameter kuti mutsegule izi.

ACCUM_SL OAD

Imatchula machitidwe a accum_sload/ sload_accum sign.
ACCUM_SLOAD: Thamangitsani accum_sload low kuti mukweze zotulutsa zochulukitsa ku accumulator.
SLOAD_ACCUM: Yendetsani sload_accum m'mwamba kuti mukweze zotulutsa zochulukitsa ku accumulator.
Muyenera kusankha Yambitsani kutsitsa kosalekeza kuti mutsegule izi.

Tchulani mtengo wokhazikika wokhazikika.

Mtengo uwu ukhoza kukhala 2N pomwe N ndiye mtengo wokhazikika wokhazikika.

Pamene N = 64, imayimira ziro nthawi zonse.

Muyenera kusankha Yambitsani kutsitsa kosalekeza kuti mutsegule izi.

Koloko0

Sankhani Clock0, Clock1 kapena Clock2 kuti mutchule chizindikiro cha wotchi ya accum_sload/sload_accum.
Muyenera kusankha Yambitsani kutsitsa kosalekeza kuti mutsegule izi.

PALIBE

Imatchula gwero lomveka bwino la accum_sload/sload_accum.
Muyenera kusankha Yambitsani kutsitsa kosalekeza kuti mutsegule izi.

PALIBE

Imatchula gwero lomveka bwino la accum_sload/sload_accum.
Muyenera kusankha Yambitsani kutsitsa kosalekeza kuti mutsegule izi.

Kuzimitsa

Imayatsa kaundula wa double accumulator.

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8.6.6. Systolic/Chainout Tab

Table 35. Systolic / Chainout Adder Tab

Parameter Yambitsani chainout adder

IP Yopangidwa ndi Parameter

Mtengo

chainout_onjezani INDE,

AYI

Kodi chainout adder operation ndi chiyani?

chainout_onjezani ADD,

er_direction

SUB

Yambitsani zolowetsa za 'negate' za chainout adder?

Port_negate

PORT_USED, PORT_UNUSED

Lembetsani zolowetsa 'zotsutsa'? negate_regist er

WOSALEMBIKITSA, CLOCK0, CLOCK1, CLOCK2, CLOCK3

Kodi magwero omveka bwino asynchronous ndi ati?

negate_aclr

Palibe ACLR0 ACLR1

Kodi gwero la mawu omveka bwino a synchronous ndi chiyani?

negate_sclr

Palibe SCLR0 SCLR1

Kuchedwa kwa Systolic
Yambitsani zolembera zakuchedwa kwa systolic

gui_systolic_d On

pang'ono

Kuzimitsa

Kodi mawotchi amachokera kuti?

gui_systolic_d CLOCK0,

elay_clock

WACHI1,

Mtengo Wofikira
AYI

Kufotokozera
Sankhani YES kuti mutsegule gawo la chainout adder.

ADD

Imatchula ntchito ya chainout adder.
Pochotsa, SIGNED iyenera kusankhidwa ya Kodi mtundu wanji woyimira pazolowetsa za Multipliers A? ndi mtundu wanji woyimira pazolowetsa za Multipliers B? mu Multipliers Tab.

PORT_UN USED

Sankhani PORT_USED kuti mutsegule siginecha yosagwirizana.
Izi ndizosavomerezeka ngati chainout adder yayimitsidwa.

ONANI KULEMBIKITSA ERED

Kuti mutsegule registry yolowera kuti musayine siginecha yolowera ndikutchula chizindikiro cha wotchi yolowera pa regista yolakwika.
Sankhani ZOSAWHALIDWA ngati zolembera zosagwirizana nazo sizikufunika
Izi ndizolakwika mukasankha:
· AYI pa Yambitsani chowongola cholumikizira kapena
· PORT_UNUSED pa Yambitsani zolowetsa za 'negate' za chainout adder? parameter kapena

PALIBE

Imatchula gwero lomveka bwino la regista yotsutsa.
Izi ndizolakwika mukasankha:
· AYI pa Yambitsani chowongola cholumikizira kapena
· PORT_UNUSED pa Yambitsani zolowetsa za 'negate' za chainout adder? parameter kapena

PALIBE

Imatchula gwero lomveka bwino la kaundula wa negate.
Izi ndizolakwika mukasankha:
· AYI pa Yambitsani chowongola cholumikizira kapena
· PORT_UNUSED pa Yambitsani zolowetsa za 'negate' za chainout adder? parameter kapena

Kuchokera CLOCK0

Sankhani izi kuti mutsegule mawonekedwe a systolic. Parameter iyi imapezeka mukasankha 2, kapena 4 ya Kodi ochulukitsa ndi otani? parameter. Muyenera kuloleza kutulutsa kwa Register kwa adder unit kuti mugwiritse ntchito zolembera zochedwa systolic.
Imatchula chizindikiro cha wotchi yolowetsa ya regista yochedwa ya systolic.
anapitiriza…

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Parameter

IP Yopangidwa ndi Parameter

Mtengo

WACHI2,

Kodi magwero omveka bwino asynchronous ndi ati?

gui_systolic_d elay_aclr

Palibe ACLR0 ACLR1

Kodi gwero la mawu omveka bwino a synchronous ndi chiyani?

gui_systolic_d elay_sclr

Palibe SCLR0 SCLR1

Mtengo Wofikira
PALIBE
PALIBE

Kufotokozera
Muyenera kusankha yambitsa zolembetsa zochedwa za systolic kuti mutsegule izi.
Imatchula gwero lomveka bwino la regista yochedwa ya systolic. Muyenera kusankha yambitsa zolembetsa zochedwa za systolic kuti mutsegule izi.
Imatchula gwero lomveka bwino la regista yochedwa ya systolic. Muyenera kusankha yambitsa zolembetsa zochedwa za systolic kuti mutsegule izi.

8.6.7. Pipelining Tab

Table 36. Mapaipi Tabu

Kukonzekera kwa Parameter Pipelining

IP Yopangidwa ndi Parameter

Mtengo

Kodi mukufuna kuwonjezera kaundula wa mapaipi pazolowetsa?

gui_pipelining Ayi, Inde

Mtengo Wofikira
Ayi

Chonde tchulani

kuchedwa

nambala ya latency clock

mikombero

Mtengo uliwonse woposa 0

Kodi mawotchi amachokera kuti?

gui_input_mochedwa ncy_clock

CLOCK0, CLOCK1, CLOCK2

Kodi magwero omveka bwino asynchronous ndi ati?

gui_input_late ncy_aclr

Palibe ACLR0 ACLR1

Kodi gwero la mawu omveka bwino a synchronous ndi chiyani?

gui_input_late ncy_sclr

Palibe SCLR0 SCLR1

CLOCK0 PALIBE

Kufotokozera
Sankhani Inde kuti muwonjezere kaundula wa mapaipi ku ma siginolo olowetsa. Muyenera kutchula mtengo wokulirapo kuposa 0 wa Chonde tchulani kuchuluka kwa magawo ozungulira koloko.
Imatchula latency yomwe mukufuna pamawotchi. Mulingo umodzi wa kaundula wa mapaipi = 1 latency mu wotchi yozungulira. Muyenera kusankha YES pa Kodi mukufuna kuwonjezera kaundula wa mapaipi pazolowera? kuti mutsegule izi.
Sankhani Clock0, Clock1 kapena Clock2 kuti mutsegule ndikutchula chizindikiro cha wotchi yolembera mapaipi. Muyenera kusankha YES pa Kodi mukufuna kuwonjezera kaundula wa mapaipi pazolowera? kuti mutsegule izi.
Imatchula gwero losasinthika la kaundula wa mapaipi owonjezera. Muyenera kusankha YES pa Kodi mukufuna kuwonjezera kaundula wa mapaipi pazolowera? kuti mutsegule izi.
Imatchula gwero lomveka bwino la kaundula wowonjezera wamapaipi. Muyenera kusankha YES pa Kodi mukufuna kuwonjezera kaundula wa mapaipi pazolowera? kuti mutsegule izi.

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9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core

Chenjerani:

Intel yachotsa chithandizo cha IP iyi mu Intel Quartus Prime Pro Edition 20.3. Ngati maziko a IP pamapangidwe anu amayang'ana zida za Intel Quartus Prime Pro Edition, mutha kusintha IP ndi LPM_MULT Intel FPGA IP kapena kupanganso IP ndikuphatikiza kapangidwe kanu pogwiritsa ntchito pulogalamu ya Intel Quartus Prime Standard Edition.

ALTMEMMULT IP pachimake imagwiritsidwa ntchito kupanga zochulukitsa zokumbukira pogwiritsa ntchito ma block memory a onchip omwe amapezeka mu Intel FPGAs (yokhala ndi M512, M4K, M9K, ndi MLAB memory blocks). IP pachimake ichi ndi chothandiza ngati mulibe zida zokwanira kuti mugwiritse ntchito zochulukitsira muzinthu zomveka (LEs) kapena zochulukitsa zodzipatulira.
The ALTMEMMULT IP pachimake ndi ntchito synchronous kuti amafuna wotchi. The ALTMEMMULT IP pachimake imagwiritsa ntchito chochulukitsira ndi kutulutsa kochepa kwambiri komanso latency yotheka pagawo lopatsidwa la magawo ndi mafotokozedwe.
Chithunzi chotsatira chikuwonetsa madoko a ALTMEMMULT IP pachimake.

Chithunzi 21. ALTMEMMULT Madoko

ALTEMMULT

data_mu[] sload_data coeff_in[]

zotsatira[]zotsatira_zovomerezeka load_done

sload_coeff

wotchi ya sclr
inst

Nkhani Zogwirizana nazo patsamba 71

9.1. Mbali
ALTMEMMULT IP core ili ndi izi: · Imapanga zochulutsa zokumbukira zokha pogwiritsa ntchito ma block memory a on-chip omwe amapezeka mu
Intel FPGAs · Imathandizira kukula kwa data kwa 1 bits · Imathandizira mawonekedwe oyimira deta osayinidwa ndi osasainidwa

ISO 9001:2015 Adalembetsedwa

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05
+ Imasunga zochulukira zochulukira mumakumbukiro opezeka mwachisawawa (RAM)
· Amapereka mwayi kusankha RAM chipika mtundu
· Imathandizira madoko olowetsamo osakanikirana bwino komanso owongolera katundu
9.2. Verilog HDL Prototype
Chitsanzo chotsatira cha Verilog HDL chili mu Verilog Design File (.v) atera_mf.v mu eda synthesis directory.
module altmemmult #( parameter coeff_representation = “SIGNED”, parameter coefficient0 = “UNUSED”, parameter data_representation = “SIGNED”, parameter purpose_device_family = “osagwiritsidwa ntchito”, parameter max_clock_cycles_per_result = 1, parameter number_of_block =1, parameter nambala_of_block =1, parameter_to_block =1 total_latency = 1, parameter width_c = 1, parameter width_d = 1, parameter width_r = 1, parameter width_s = 0, parameter lpm_type = "altmemmult", parameter lpm_hint = "osagwiritsidwa ntchito") ( wotchi yolowera, waya wolowetsa [width_c-1: 0]coeff_in, waya wolowetsa [width_d-1:0] data_in, waya wotuluka load_done, waya wotuluka [width_r-1:0] chotsatira, chotuluka waya chotsatira_valid, cholowetsa waya sclr, waya wolowetsa [width_s-1:XNUMX] sel, input waya sload_coeff, waya wolowetsa sload_data)/* synthesis syn_black_box=XNUMX */; endmodule
9.3. Chidziwitso Chachigawo cha VHDL
Chidziwitso cha gawo la VHDL chili mu VHDL Design File (.vhd) altera_mf_components.vhd mu libraryvhdlaltera_mf directory.
component altmemmult generic ( coeff_representation: chingwe := "SIGNED"; coefficient0:string := "OSASUSED"; data_representation:string := "SIGNED"; purpose_device_family:string := "osagwiritsidwa ntchito"; max_clock_cycles_per_result:_result_result: := 1; ram_block_type:string := “AUTO”; total_latency: Natural; width_c: Natural; width_d: Natural; width_r: Natural; width_s: Natural: = 1; lpm_hint:string := "UNUSED"; lpm_type: chingwe:= "altmemmult"); port ( wotchi: mu std_logic; coeff_in: mu std_logic_vector (width_c-1 downto 1) := (ena => '0'); data_in: mu std_logic_vector (width_d-0 downto 1);

Intel FPGA Integer Arithmetic IP Cores User Guide 58

Tumizani Ndemanga

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

load_done:out std_logic; zotsatira: out std_logic_vector(width_r-1 downto 0); result_valid:out std_logic; sclr:mu std_logic := '0'; sel:mu std_logic_vector(width_s-1 downto 0) := (ena => '0'); sload_coeff:mu std_logic := '0'; sload_data:mu std_logic := '0'); mapeto chigawo;

9.4. Madoko

Matebulo otsatirawa amalemba zolowetsa ndi zotuluka za ALTMEMMULT IP pachimake.

Table 37. ALTMEMMULT Madoko Olowetsa

Dzina la Port

Chofunikira

Kufotokozera

koloko

Inde

Kulowetsa koloko ku chochulukitsira.

coeff_mu[]

Ayi

Cholowa cha coefficient port chochulukitsa. Kukula kwa doko lolowera kumatengera WIDTH_C parameter mtengo.

zambiri_mu[]

Inde

Doko lolowetsa data ku chochulukitsira. Kukula kwa doko lolowera kumatengera WIDTH_D parameter mtengo.

sclr

Ayi

Kulowetsa momveka bwino. Ngati sichigwiritsidwa ntchito, mtengo wokhazikika umakhala wokwera kwambiri.

gulitsa[]

Ayi

Kusankha kokwanira kokhazikika. Kukula kwa doko lolowera kumatengera WIDTH_S

mtengo wa parameter.

sload_coeff

Ayi

Doko lolowera la synchronous load coefficient. Imalowetsa mtengo wa coefficient womwe wasankhidwa ndi mtengo womwe wafotokozedwa mu coeff_in.

sload_data

Ayi

Doko lolowera la data la synchronous. Chizindikiro chomwe chimatchula ntchito yatsopano yochulutsa ndikuletsa ntchito iliyonse yochulutsa yomwe ilipo. Ngati MAX_CLOCK_CYCLES_PER_RESULT parameter ili ndi mtengo wa 1, doko la sload_data limanyalanyazidwa.

Table 38. ALTMEMMULT Zotulutsa Zotulutsa

Dzina la Port

Chofunikira

Kufotokozera

zotsatira[]

Inde

Multiplier linanena bungwe port. Kukula kwa doko lolowera kumatengera WIDTH_R parameter mtengo.

zotsatira_zovomerezeka

Inde

Imawonetsa pamene zotulukazo ndizotsatira zovomerezeka za kuchulukitsa kokwanira. Ngati MAX_CLOCK_CYCLES_PER_RESULT parameter ili ndi mtengo umodzi, result_valid output port sigwiritsidwa ntchito.

load_yachita

Ayi

Imawonetsa pamene coefficient yatsopano yatha kutsitsa. Chizindikiro cha load_done chimatsimikizira kuti coefficient yatsopano ikamaliza kutsegula. Pokhapokha ngati chizindikiro cha load_done chili chokwera, palibe mtengo wina wokwanira womwe ungakwezedwe kukumbukira.

9.5. Magawo

Gome lotsatirali likulemba magawo a ALTMEMMULT IP pachimake.

Table 39.
WIDTH_D WIDTH_C

Zithunzi za ALTMEMMULT
Dzina la Parameter

Mtundu Wofunika

Kufotokozera

Nambala Inde

Imatchula m'lifupi mwa doko la data_in[].

Nambala Inde

Imatchula m'lifupi mwa doko la coeff_in[]. anapitiriza…

Tumizani Ndemanga

Intel FPGA Integer Arithmetic IP Cores User Guide 59

9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 683490 | 2020.10.05

Dzina lazigawo WIDTH_R WIDTH

Zolemba / Zothandizira

Intel FPGA Integer Arithmetic IP Cores [pdf] Buku Logwiritsa Ntchito
FPGA Integer Arithmetic IP Cores, Integer Arithmetic IP Cores, Arithmetic IP Cores, IP Cores

Maumboni

Buku Logwiritsa Ntchito

FPGA Integer Arithmetic IP Cores

Zolemba / Zothandizira

Maumboni

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