infineon CYW30739B2-P5TAI051 Airoctm Bluetooth and Bluetooth LE Module Instruction Manual

Instruction Manual for infineon models including: 739I05, WAP739I05, CYW30739B2-P5TAI051 Airoctm Bluetooth and Bluetooth LE Module, CYW30739B2-P5TAI051, CYW30739B2-P5TAI051 Module, Airoctm Bluetooth and Bluetooth LE Module, Airoctm Bluetooth Module, Airoctm Bluetooth LE Module, Bluetooth LE Module, Bluetooth Module, Module

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CYW30739B2-P5TAI051
AIROCTM Bluetooth® & Bluetooth® LE module
General description
The CYW30739B2-P5TAI051 module is a multi-protocol solution wireless module solution with an integrated 2.4 GHz transceiver that is Matter 1.2, Thread 1.3, and Bluetooth® 5.3-compliant. The CYW30739B2-P5TAI051 includes onboard crystal oscillators, 2 MB flash, passive components, and the CYW30739 silicon device. The CYW30739B2-P5TAI051 supports a number of peripheral functions (ADC, PWM), as well as multiple serial communication protocols (UART, SPI, I2C, I2S/PCM). The device is intended for use in smart home applications such as thermostats, sensors, smart lighting and smart door locks. The CYW30739B2-P5TAI051 is the optimal solution for applications in smart home, industrial and Internet of Things (IoT) devices, with the flexibility to address the increasing size of protocol stacks and applications. The CYW30739B2-P5TAI051 includes a royaltyfree stack compatible with Bluetooth® core specification v5.1 with Bluetooth® LE 2 Mbps and IEEE 802.15.4-2015 in a small module form-factor. The CYW30739B2-P5TAI051 has 2MB external flash memory and qualified by Bluetooth® SIG and Matter v1.3, and includes regulatory certification approval for FCC, ISED, and CE.
Module description
· Module size: 13.47 mm × 15.83 mm × 1.95 mm
· Complies with Bluetooth® Core specification version 5.3 supporting BR, EDR 2/3 Mbps, eSCO, Bluetooth® LE, and LE 2 Mbps. - QDID: D068835 - Declaration ID: 243084
· Certified for FCC ISED and CE
· Up to 13 GPIOs
· External 2048-KB flash memory. And Internal 1024-KB flash memory, 512-KB SRAM memory · Industrial temperature range: 30 °C to +85 °C
· Integrated Arm® Cortex®-M4 microprocessor core with floating point unit (FPU)
RF characteristics
· Maximum TX output power: +5.0 dBm · Bluetooth® LE RX receive sensitivity: 92.0 dBm
· Received signal strength indicator (RSSI) with 1-dB resolution
Power consumption
· TX current consumption - Bluetooth® LE silicon: 5.6 mA (MCU + radio only, 0 dBm)
· RX current consumption - Bluetooth® silicon: 5.9 mA (MCU + radio only)
· CYW30739 silicon low power mode support - PDS: 6.1 µA with 512 KB SRAM retention - SDS: 1.6 µA - HIDOFF (external interrupt): 400 nA

Preliminary Datasheet www.infineon.com

Please read the Important Notice and Warnings at the end of this document page 1

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Functional capabilities
Functional capabilities
· 1x ADC with (12-bit ENoB for DC measurement and 13-bit ENoB for Audio measurement) with 10 channels · 1x HCI UART for programming and HCI · 1x peripheral UART (PUART) · 1x SPI (master or slave) blocks (SPI, Quad SPI, MIPI DBI-C) · 1x I2C master/slave and 1x I2C master only · I2S/PCM audio interfaces · Up to 6 16-bit PWMs · Watchdog timer (WDT) · Bluetooth® Basic Rate (BR) and Enhanced Data Rate (EDR) Support · Bluetooth® LE protocol stack supporting generic access profile (GAP) central, peripheral, or broadcaster roles · Features are subject to support in the Bluetooth® SDK. · Matter-ready SDK and Bluetooth® LE SDK: Check the latest version of the Bluetooth® SDK technical brief for
supported features · Hardware security engine

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Table of contents
General description ....................................................................................................................................1
Module description .....................................................................................................................................1
RF characteristics .......................................................................................................................................1
Power consumption....................................................................................................................................1
Functional capabilities................................................................................................................................2
Table of contents ........................................................................................................................................3
1 Benefits ...................................................................................................................................................5
2 More information .....................................................................................................................................6 2.1 References .......................................................................................................................................................................6 2.2 Technical support ...........................................................................................................................................................6 3 Overview .................................................................................................................................................7
Functional block diagram............................................................................................................................7 3.1 Module description .........................................................................................................................................................7 3.1.1 Module dimensions and drawing ................................................................................................................................7 4 Pad connection interface ..........................................................................................................................9
5 Recommended host PCB layout...............................................................................................................11
6 Module connections ...............................................................................................................................13 6.1 Connections and optional external components ........................................................................................................14 6.2 Power connections (VDD) .............................................................................................................................................14 6.2.1 Considerations and optional components for brownout (BO) conditions ..............................................................15 6.3 External reset (XRES).....................................................................................................................................................16 6.4 HCI UART connections ..................................................................................................................................................16 6.5 External component recommendation........................................................................................................................16 6.5.1 Power supply input options and circuitry .................................................................................................................16 6.6 Critical components list ................................................................................................................................................18 6.7 Antenna design..............................................................................................................................................................18 7 Bluetooth® Baseband Core ......................................................................................................................19 7.1 BQB and regulatory testing support.............................................................................................................................19 8 Power management unit ........................................................................................................................20
9 Integrated radio transceiver ...................................................................................................................21 9.1 Transmitter path ...........................................................................................................................................................21 9.1.1 Digital modulator .......................................................................................................................................................21 9.2 Receiver path ................................................................................................................................................................21 9.2.1 Digital demodulator and bit synchronizer ................................................................................................................21 9.2.2 Receiver signal strength indicator.............................................................................................................................21 9.3 Local oscillator ..............................................................................................................................................................21 10 Microcontroller unit .............................................................................................................................22 10.1 External reset ..............................................................................................................................................................22 11 Peripheral and communication interfaces..............................................................................................23 11.1 I2C ................................................................................................................................................................................23 11.2 HCI UART interface ......................................................................................................................................................23 11.3 Peripheral UART interface...........................................................................................................................................23 11.4 Serial peripheral interface ..........................................................................................................................................23 11.4.1 MIPI interface............................................................................................................................................................23 11.5 32-kHz crystal oscillator..............................................................................................................................................24 11.6 ADC port.......................................................................................................................................................................24 11.7 GPIO ports ...................................................................................................................................................................25 11.8 PWM .............................................................................................................................................................................25 11.9 PDM microphone.........................................................................................................................................................26 11.10 I2S interface...............................................................................................................................................................26 11.11 PCM interface ............................................................................................................................................................27

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11.11.1 Slot mapping............................................................................................................................................... 27 11.11.2 Frame synchronization ............................................................................................................................... 27 11.11.3 Data formatting........................................................................................................................................... 27 11.11.4 Burst PCM mode.......................................................................................................................................... 27 11.12 Security engine .............................................................................................................................................. 28 11.12.1 Random number generator........................................................................................................................ 28 12 Power modes .....................................................................................................................................29 13 Firmware ...........................................................................................................................................30 14 Electrical characteristics ....................................................................................................................31 14.1 Core buck regulator ......................................................................................................................................... 33 14.2 Digital LDO ....................................................................................................................................................... 34 14.3 Digital I/O characteristics ................................................................................................................................ 34 14.4 ADC electrical characteristics .......................................................................................................................... 34 15 Chipset RF specifications ....................................................................................................................36 16 Timing and AC characteristics .............................................................................................................39 16.1 UART timing ..................................................................................................................................................... 39 16.2 SPI timing ......................................................................................................................................................... 39 16.3 I2C compatible interface timing...................................................................................................................... 41 16.4 I2S interface timing.......................................................................................................................................... 42 17 Environmental specifications ..............................................................................................................44 17.1 Environmental compliance ............................................................................................................................. 44 17.2 RF certification ................................................................................................................................................. 44 17.3 Safety certification........................................................................................................................................... 44 17.4 Environmental conditions ............................................................................................................................... 44 17.5 ESD and EMI protection ................................................................................................................................... 44 18 Regulatory information ......................................................................................................................45 18.1 FCC.................................................................................................................................................................... 45 18.2 ISED .................................................................................................................................................................. 46 18.3 European Declaration of Conformity .............................................................................................................. 47 19 Packaging ..........................................................................................................................................48 20 Ordering information..........................................................................................................................50 21 Acronyms...........................................................................................................................................51 22 Document conventions .......................................................................................................................52 22.1 Units of measure .............................................................................................................................................. 52 Revision history......................................................................................................................................53

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Table of contents

Benefits

CYW30739B2-P5TAI051 is fully integrated and certified solution that provides all necessary components required to operate Bluetooth® and Matter communication standards. · Proven hardware design ready to use · Ultra-flexible supermux I/O design allows maximum flexibility for GPIO function assignment · Large nonvolatile memory (1MB Internal + 2MB External) for complex application development · Over-the-Air (OTA) update capable for development or field updates · Bluetooth® SIG qualified with QDID and declaration ID

IEEE 802.15.4 architecture
· CYW30739 has 2 MB ROM, where stable software that requires little or no ongoing updates can be stored, thus freeing up much of the 1 MB internal flash on the part for application usage. The ROM currently includes the Bluetooth® LE software stack as well as support for hardware peripherals and the lower layers of the IEEE 802.15.4 MAC. Any updates to software in ROM can be implemented via patch code stored in flash and executed from RAM.
· CYW30739 supports the Thread networking standard for wireless mesh networking, which runs on top of the IEEE 802.15.4 MAC layer. It also supports the Matter protocol for interoperable device to device communications running on top of Thread. The Thread and Matter software stacks are maintained in flash currently, and executed from RAM.

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Table of contents

More information

Infineon provides a wealth of data at www.infineon.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design.

2.1

References

· Overview: EZ-BLE/EZ-BT Module Portfolio, Module Roadmap
· Development kits: - CYW30739B2-P5TAI051 CYW30739 Base Module w/ 2 MB external flash - CYW30739B2-P5-EVK, Evaluation Kit for CYW30739 silicon device
· Test and debug tools: - CYSmart, Bluetooth® LE Test and Debug Tool (Windows) - CYSmart Mobile, Bluetooth® LE Test and Debug Tool (Android/iOS Mobile App)
· Knowledge base article - KBA97095 - EZ-BLETM Module Placement - KBA224516 - RF Regulatory Certifications for CYBT-483039-02 EZ-BTTM WICED Modules - KBA213976 - FAQ for Bluetooth® LE and Regulatory
Certifications with EZ-BLE modules - KBA210802 - Queries on Bluetooth® LE Qualification and
Declaration Processes - KBA218122 - 3D Model Files for EZ-BLE/EZ-BT Modules - KBA223428 - Programming an EZ-BT WICED Module - KBA225450 - Putting 2073x, 2070x, and 20719 based devices or modules in HCI Mode

2.2

Technical support

· Infineon Community: Whether you're a customer, partner or a developer interested in the latest Infineon innovations, the Infineon Developer Community offers you a place to learn, share and engage with both Infineon experts and other embedded engineers around the world.

· Frequently Asked Questions (FAQs): Learn more about our Bluetooth® ecosystem.

· Visit our support page and create a technical support case or contact a local sales representatives.

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Overview

Overview

Functional block diagram
Figure 1 Figure 1 illustrates the CYW30739B2-P5TAI051 functional block diagram.

Figure 1

Functional block diagram

Note General purpose input/output pins shown in Figure 1 are configurable to any specified input or output function in the SuperMux table detailed in Table 4 in the Module connections section.
Note Connections shown in the above block diagram are maximum number of connections per function. The total number of GPIOs available on the CYW30739B2-P5TAI051 is 13.

3.1

Module description

The CYW30739B2-P5TAI051 module is a complete module designed to be soldered to the applications main board.

3.1.1

Module dimensions and drawing

Infineon reserves the right to select components from various vendors to achieve the Bluetooth® module functionality. Such selections will still guarantee that all mechanical specifications and module certifications are maintained. Any changes to the current BOM for the CYW30739B2-P5TAI051 will not be made until approval is provided by the end customer for this product. The CYW30739B2-P5TAI051 will be held within the physical dimensions shown in the mechanical drawings in Figure 2. All dimensions are in millimeters (mm).

Table 1. Module design dimensions

Dimension item

Unit

Specification

Module dimensions

Length (X) 13.47 ± 0.15 mm Width (Y) 15.83 ± 0.15 mm

Antenna location dimensions

Length (X) 13.47 mm Width (Y) 4.60 mm

PCB thickness

Height (H) 0.50 ± 0.10 mm

Shield height

Height (H) 1.45 mm

Maximum component height

Height (H) 0.95 mm typical (inductor)

Total module thickness (bottom of module to top of shield) Height (H) 1.95 mm typical

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Overview
See Figure 2 for the mechanical reference drawing for CYW30739B2-P5TAI051.

Top view (Seen from top)

Side View

Figure 2

Bottom view (Seen from bottom) Module mechanical drawing[1]

Note 1. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area.
For more information on recommended host PCB layout, see Recommended host PCB layout.

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Pad connection interface

Pad connection interface

As shown in the bottom view of Figure 2, the CYW30739B2-P5TAI051 has 31 connections to a host board via solder pads (SP). Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYW30739B2-P5TAI051 module.

Table 2

Connection description

Name SP

Connections 31

Connection type

Pad length dimension

Solder pad

1.02 mm

Pad width dimension
0.71 mm

Pad pitch 1.00 mm

Figure 3

Solder pad dimensions (seen from bottom)

To maximize RF performance, the host layout should follow these recommendations:
1. Antenna area keepout: The host board directly below the antenna area of the module (see Figure 2) must contain no ground or signal traces. This keep out area requirement applies to all layers of the host board.
2. Module placement: The ideal placement of the Bluetooth® module is in a corner of the host board with the trace antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 3 below. Refer to AN96841 for module placement best practices.
3. Optional keepout: To maximize RF performance, the area immediately around the Bluetooth® module trace antenna may contain an additional keep out area, where there are no grounding or signal traces. The keep out area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm).

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Pad connection interface

Figure 4

Optional additional host PCB keep out area around the CYW30739B2-P5TAI051 trace antenna

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Recommended host PCB layout

Recommended host PCB layout

Figure 5, Figure 6, provide details that can be used for the recommended host PCB layout pattern for the CYW30739B2-P5TAI051. Dimensions are in millimeters unless otherwise noted. Pad length of 1.02 mm (0.51 mm from center of the pad on either side) is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure5, Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern.

Figure 5

CYW30739B2-P5TAI051 host layout (dimensioned)

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Recommended host PCB layout

Figure 6

CYW30739B2-P5TAI051 host layout (relative to origin)

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Module connections

Module connections

Table 3 details the solder pad connection definitions and available functions for each connection pad. The GPIO connections available on the CYW30739B2-P5TAI051 can be configured to any of the input or output functions listed in Table 4. Table 3 specifies any function that is required to be used on a specific solder pad, and also identifies GPIOs that can be configured using the SuperMux.

Table 3

CYW30739B2-P5TAI051 solder pad connection definitions

Pad

Pad name

GND

HOST_WAKE

GND

Silicon pin name GND GND BT_HOST_WAKE GND

XTAL I/O

ADC

GPIO

SuperMux capable[4]

Ground

A signal from the CYW30739B2-P5TAI051 module to the host indicating that the Bluetooth® device requires attention.

Ground

GND

Ground

GND

Ground

HCI_RXD

BT_UART_RXD

UART serial input. Serial data input for the HCI UART interface.

HCI_TXD

BT_UART_TXD

UART serial output. Serial data output for the HCI UART interface

HCI_RTS

BT_UART_RTS_N Request to send (RTS) for HCI UART interface. Leave unconnected if not used

HCI_CTS

BT_UART_CTS_N Clear to send (CTS) for HCI UART interface. Leave unconnected if not used.

GND

Ground

XTALO_32K

Low-power oscillator output.

XTALI_32K

GND

BTN

DEBUG_TXD

P_TXD

P_RXD

P_CTS

P_RTS_LED

P16

XTALI_32K/P15
GND P2 P4 P6 P7 P17 P10 P28 P16

Low-power oscillator input.

IN20

Ground

IN18 IN25 IN11 IN19

V(P15)
V(P2) V(P4) V(P6) V(P7) V(P17) V(P10) V(P28) V(P16)

Vsee Table 4
Vsee Table 4 Vsee Table 4 Vsee Table 4 Vsee Table 4 Vsee Table 4 Vsee Table 4 Vsee Table 4 Vsee Table 4

GND

DRDY_INT

SCL

SDA

P33

XRST_N

GND

GND P29 P26 P25 P33 RST_N GND

Ground

IN10

V(P29)

V(P26)

V(P25)

IN6

V(P33)

Active-low system reset with internal pull-up resistor. Ground

Vsee Table 4 Vsee Table 4 Vsee Table 4 Vsee Table 4

VDD

SR_VDDBAT3V/ BT_VDDO/ VDDO

Power(1.76V~3.63V)

GND

Ground

Notes
1. The CYW30739B2-P5TAI051 can configure GPIO connections to any input/output function described in Table 4.
2. P15 should not be driven high externally while the part is held in reset (it can be floating or driven low). Failure to do so may cause some current to flow through P15 until the device comes out of reset.

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Module connections

Table 4 details the available Input and output functions configurable to any solder pad in Table 3 that are marked as SuperMux capable.

Table 4
Function
SPI
PUART I2C PCM In PCM Out I2S In I2S Out PDM

GPIO SuperMux input and output functions

Input/output

Function type

GPIOs required

Input/output

Serial communication (Master or Slave)

4 ~ 8

Output Input Output Input/Output

Serial communication input 4
Serial communication output

Serial communication (Master or Slave)

Input

Audio input communication 3

Output

Audio output communication 3

Input

Audio input communication 3

Output Input

Audio output communication 3

Microphone

1 ~ 2

Function connection description SPI clock SPI chip select SPI MOSI SPI MISO SPI I/O 2 (Quad SPI) SPI I/O 3 (Quad SPI) SPI interrupt SPI DCX (DBI-C DCX 8-bit mode) Peripheral UART RX Peripheral UART CTS Peripheral UART TX Peripheral UART RTS I2C clock I2C data PCM input PCM clock PCM sync PCM output PCM clock PCM sync I2S DI, data input I2S WS, word select I2S clock I2S DO, data output I2S WS, word select I2S clock PDM input channel 1 PDM input channel 2

6.1

Connections and optional external components

6.2

Power connections (VDD)

The CYW30739B2-P5TAI051 contains one power supply connections, VDD.

VDD is the power supply connection for the CYW30739 silicon device. VDD accepts a supply input of 1.76 V to 3.63 V. Table 11 provides this specification. The maximum power supply ripple for this power connection is 100 mV,
as shown in Table 11.

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Module connections

6.2.1

Considerations and optional components for brownout (BO) conditions

Power supply design must be completed to ensure that the CYW30739B2-P5TAI051 module does not encounter a brownout condition, which can lead to unexpected functionality, or module lock up. A brownout condition may
be met if power supply provided to the module during power up or reset is in the range shown below: V IL VDD
VIH.
Refer to Table 17 for the VIL and VIH specifications.
System design should ensure that the condition above is not encountered when power is removed from the system. In the event that this cannot be guaranteed (i.e. battery installation, high value power capacitors with slow discharge), it is recommended that an external voltage detection device be used to prevent the brownout voltage range from occurring during power removal.

Figure 7 shows the recommended circuit design when using an external voltage detection IC.

Figure 7

Reference circuit block diagram for external voltage detection IC

In the event that the module does encounter a brownout condition, and is operating erratically or not responsive, power cycling the module will correct this issue and once reset, the module should operate correctly. Brownout conditions can potentially cause issues that cannot be corrected, but in general, a power-on-reset operation will correct a brownout condition.

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6.3

External reset (XRES)

The CYW30739B2-P5TAI051 has an integrated power-on reset circuit which completely resets all circuits to a known power on state. This action can also be invoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal, which is an input to the CYW30739B2-P5TAI051 module (solder pad 28). The CYW30739B2-P5TAI051 module does not require an external pull-up resistor on the XRES input.

During power on operation, the XRES connection to the CYW30739B2-P5TAI051 is required to be held low 50 ms after the VDD power supply input to the module is stable. This can be accomplished in the following ways:

· The host device can connect a GPIO to the XRES of CYW30739B2-P5TAI051 module and pull XRES low until VDD is stable. XRES is recommended to be released 50 ms after VDD is stable.

· If the XRES connection of the CYW30739B2-P5TAI051 module is not used in the application, a 0.33 µF capacitor may be connected to the XRES solder pad of the CYW30739B2-P5TAI051 in order to delay the XRES release. The capacitor value for this recommended implementation is approximate, and the exact value may differ depending on the VDD power supply ramp time of the system. The capacitor value should result in an XRES release timing of at least 50 ms after VDD stability.

· The XRES release timing may be controlled by a external voltage detection IC. XRES should be released 50 ms after VDD is stable.
Refer to Figure 10 for XRES operating and timing requirements during power-on events.

6.4

HCI UART connections

The recommendations in this section apply to the HCI UART (Solder pads 7, 8, 9, and 10). For full UART functionality, all UART signals must be connected to the Host device (CTS must be pulled high when poweron/reset). If full UART functionality is not being used, and only UART RXD and TXD are desired or capable, then the following connection considerations should be followed for UART RTS and CTS:

· ·UART RTS: Must be left floating.

· ·UART CTS: Must be pulled high when power-on/reset and be pulled low after application startup to bypass flow control and ensure that continuous data transfers are made from the host to the module.

6.5

External component recommendation

6.5.1

Power supply input options and circuitry

It is recommended to place an external ferrite bead between the supply and the module connection. The ferrite bead should be positioned as close as possible to the module pad connection.
The recommended ferrite bead value is 330, 100 MHz (Murata BLM21PG331SN1D).

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Module connections
Figure 8 illustrates the CYW30739B2-P5TAI051 schematic.

Figure 8

CYW30739B2-P5TAI051 schematic diagram

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Module connections

6.6

Critical components list

Table 5 details the critical components used in the CYW30739B2-P5TAI051 module.

Table 5. Critical component list

Component Silicon

Reference designator Description

40-pin QFN Bluetooth® silicon device CYW30739

Crystal

24 MHz, 12 pF

6.7

Antenna design

Table 6 details the trace antenna used in the CYW30739B2-P5TAI051 module.

Table 6. Trace antenna specifications

Item Frequency range Peak gain Return loss

Description 2400 2500 MHz 0.9 dBi typical 10.0 dB typical

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Bluetooth® Baseband Core

Bluetooth® Baseband Core

The Bluetooth® Baseband Core (BBC) implements all time-critical functions required for high-performance Bluetooth® operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It prioritizes and schedules all RX/TX activities including adv, paging, scanning, and servicing of connections. In addition to these functions, it independently handles the host controller interface (HCI) including all commands, events, and data flowing over HCI. The core also handles symbol timing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), authentication, data encryption/decryption, and data whitening/dewhitening.

Table 7

Bluetooth® features

Bluetooth® 1.0 Basic rate SCO Paging and inquiry Page and inquiry scan Sniff

Bluetooth® 1.2 Interlaced scans Adaptive frequency hopping eSCO

Bluetooth® 2.0
EDR 2 Mbps and 3 Mbps

Bluetooth® 2.1 Secure simple pairing Enhanced inquiry response Sniff subrating

Bluetooth® 3.0 Unicast connectionless data Enhanced power control eSCO

Bluetooth® 4.0 Bluetooth® Low Energy

Bluetooth® 4.1 Low duty cycle advertising Dual mode LE link layer topology

Bluetooth® 4.2 Data packet length extension LE secure connection Link layer privacy

Bluetooth® 5.0 LE 2 Mbps Slot availability mask High duty cycle advertising

7.1

BQB and regulatory testing support

CYW30739B2-P5TAI051 fully supports Bluetooth® Test mode as described in Part I:1 of the specification of the Bluetooth® system version 3.0. This includes the transmitter tests, normal and delayed loop back tests, and reduced hopping sequence.
In addition to the standard Bluetooth® Test mode, CYW30739B2-P5TAI051 also supports enhanced testing features to simplify RF debugging and qualification and type-approval testing. These features include:

· Fixed frequency carrier wave (unmodulated) transmission - Simplifies some type-approval measurements (Japan) - Aids in transmitter performance analysis

· Fixed frequency constant receiver mode - Receiver output directed to I/O pin - Allows for direct BER measurements using standard RF test equipment - Facilitates spurious emissions testing for receive mode

· Fixed frequency constant transmission - 8-bit fixed pattern or PRBS-9 - Enables modulated signal measurements with standard RF test equipment

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Power management unit

Power management unit

Figure 9 shows the CYW30739 power management unit (PMU) block diagram. The CYW30739 includes an integrated buck regulator, a bypass LDO, a capless LDO for digital circuits and a separate LDO for RF. The bypass LDO automatically takes over from the buck once VBAT supply falls below 2.1 V.
The voltage levels shown in this figure are the default settings; the firmware may change voltage levels based on operating conditions.

Figure 9

Default usage mode

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Integrated radio transceiver

Integrated radio transceiver

The CYW30739B2-P5TAI051 has an integrated radio transceiver that has been designed to provide low power operation in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with Bluetooth® Radio specification 3.0 and meets or exceeds the requirements to provide the highest communication link quality of service.

9.1

Transmitter path

CYW30739B2-P5TAI051 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band.

9.1.1

Digital modulator

The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal.

9.2

Receiver path

The receiver path uses a low IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, and an extended dynamic range to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the CYW30739B2-P5TAI051 to be used in most applications without off-chip filtering.

9.2.1

Digital demodulator and bit synchronizer

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm.

9.2.2

Receiver signal strength indicator

The radio portion of the CYW30739B2-P5TAI051 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller to take part in a Bluetooth® power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power.

9.3

Local oscillator

The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The CYW30739B2-P5TAI051 uses an internal loop filter.

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Microcontroller unit

Microcontroller unit

The CYW30739B2-P5TAI051 includes a Arm® Cortex®-M4 processor with 2 MB of ROM, 448 KB of data RAM, 64 KB of patch RAM, and 1 MB of on-chip flash. The CM4 has a maximum speed of 96 MHz. CYW30739B2-P5TAI051 supports execution from on-chip flash (OCF).
The CM4 also includes a single precision IEEE 754 compliant floating point unit (FPU).
The CM4 runs all the BT layers as well as application code. The ROM includes LM, HCI, L2CAP, GATT, as well as other stack layers freeing up the flash for application usage. A standard serial wire debug (SWD) interface provides debugging support.

10.1

External reset

An external active-low reset signal, XRES, can be used to put the CYW30739B2-P5TAI051 in the reset state. An external voltage detector reset IC with 50 ms delay is recommended on the XRES connection. The XRES must only be released after the VDDO supply voltage level has been stabilized for 50 ms.

Figure 10

Reset timing

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Peripheral and communication interfaces

Peripheral and communication interfaces

11.1

I2C

The CYW30739B2-P5TAI051 provides a 2-pin I2C compatible master interface to communicate with I2C compatible peripherals. The following transfer clock rates are supported are:

· 100 kHz

· 400 kHz

· 800 kHz (Not a standard I2C-compatible speed)

· 1 MHz (Compatibility with high-speed I2C-compatible devices is not guaranteed)
SCL and SDA lines can be routed to any of the P0-P39 GPIOs allowing for flexible system configuration. When used as SCL/SDA the GPIOs go into open drain mode and require an external pull-up for proper operation. I2C block does not support multi master capability by either master or slave devices.
I2C is master only.

11.2

HCI UART interface

The CYW30739B2-P5TAI051 includes a UART interface for factory programming as well as when operating as a BT HCI device in a system with an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 115200 bps to 1.5 Mbps. Typical rates are 115200, 921600, 1500000 bps although intermediate speeds are also available. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command. The CYW30739B2-P5TAI051 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%. The UART interface has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth® UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud.

The CYW30739B2-P5TAI051 can wake up the host as needed or allow the host to sleep via the HOST_WAKE signal (solder pad 2). The signal allows the CYW30739B2-P5TAI051 to optimize system power consumption by allowing a host device to remain in low power modes as long as possible. The HOST_WAKE signal can be enabled via a vendorspecific command.

11.3

Peripheral UART interface

The CYW30739B2-P5TAI051 has a second UART that may be used to interface to peripherals. This peripheral UART is accessed through the optional I/O ports, which can be configured individually and separately for each functional pin. The CYW30739B2-P5TAI051 can map the peripheral UART to any GPIO. The Peripheral UART functionality is the same as the HCI UART, but with a 256-byte transmit and receive FIFO.

11.4

Serial peripheral interface

The CYW30739B2-P5TAI051 has two independent SPI interfaces. Both interfaces support Single, Dual, and Quad mode SPI operations as well as MIPI DBI-C Interface. Either of the interface can be a master or a slave. SPI2 can support only 1 slave. SPI1 has a 1024 byte transmit and receive buffers which is sh ared with the host UART interface. SPI2 has a dedicated 256-byte transmit and receive buffers. To support more flexibility for user applications, the CYW30739B2-P5TAI051 has optional I/O ports that can be configured individually and separately for each functional pin. SPI IO voltage depends on VDDO.

11.4.1 MIPI interface
There are three options in DBI type-C corresponding to 9-bit, 16-bit, and 8-bit modes. The CYW30739B2-P5TAI051 plays the role of host, and only the 9-bit and 8-bit modes (option 1 and option 3 in DBI-C spec) are supported. In the 9-bit mode, the SCL, CS, MOSI, and MISO pins are used. In the 8-bit mode, an additional pin (DCX) is required. The DCX pin indicates if the current outgoing bit stream is a command or data byte.

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11.5

32-kHz crystal oscillator

The CYW30739B2-P5TAI051 utilizes the built-in local oscillator (LO) on the CYW30739 silicon device for 32-kHz timing. The accuracy of the LO is +/- 500 ppm. The use of an external XTAL oscillator is optional. CYW30739B2P5TAI051 includes external XTAL oscillator connections for applications requiring higher timing accuracy. Figure 11 shows an external 32-kHz XTAL oscillator with external components and Table 8 lists the recommended external oscillator's characteristics. This oscillator input can be operated with a 32-kHz or 32.768-kHz crystal oscillator or be driven with a clock input at similar frequency. The default component values are: R1 = 10 M and C1 = C2 = ~6 pF. The values of C1 and C2 are used to fine-tune the oscillator.

Figure 11 32-kHz oscillator block diagram

Table 8

XTAL oscillator characteristics

Parameter
Output frequency Frequency tolerance Start-up time XTAL drive level XTAL series resistance XTAL shunt capacitance External AC input amplitude

Symbol
Foscout Tstartup Pdrv Rseries Cshunt
VIN (AC)

Conditions Crystal-dependent For crystal selection For crystal selection For crystal selection
Ccouple = 100 pF; Rbias = 10 M

Min

Typ Max Unit

32.76

kHz

100

ppm

500

0.5

µW

2.2

400

mVpp

11.6

ADC port

The ADC is a - ADC core designed for audio (13 bits) and DC (12 bits) measurement. It operates at 12 MHz and has 10 solder pad connections that can act as input channels. The internal bandgap reference has ±5% accuracy without calibration. Calibration and digital correction schemes can be applied to reduce ADC absolute error and improve measurement accuracy in DC mode.
The following CYW30739B2-P5TAI051 module solder pads can be used as ADC inputs:

· Pad 13: P15, ADC input channel 20 NoteP15 should not be driven high externally while the part is held in reset (it can be floating or driven low). Failure to do so may cause some current to flow through P15 until the device comes out of reset.

· Pad 19: P17, ADC input channel 18

· Pad 20: P10, ADC input channel 25

· Pad 21: P28, ADC input channel 11

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· Pad 22: P16, ADC input channel 19 · Pad 24: P29, ADC input channel 10 · Pad 27: P33, ADC input channel 6

11.7

GPIO ports

The CYW30739B2-P5TAI051 has a maximum of 13 general-purpose I/Os (GPIOs). All GPIOs support the following:

· Programmable pull-up/down of approximately 45 k.

· Input disable, allowing pins to be left floating or analog signals connected without risk of leakage.

· Source/sink 8 mA at 3.3 V and 4 mA at 1.8 V.

· P15 is Bonded to the same pin as XTALI_32K (Pad 13). If an external 32.768 kHz crystal is not used, then this pin can be used as GPIO P15.

· P26/P28/P29 can sink/source 16 mA at 3.3V and 8 mA at 1.8V. Most peripheral functions can be assigned to any GPIO. For details, refer to Table 4. For more details on SuperMux configuration and control, refer to "Supermux Wizard for CYW30739" user guide. The list below details the GPIOs that are available on the CYW30739B2-P5TAI051 module:

· P2, P4, P6, P7, P10, P16, P17, P25, P26, P28, P29, and P33

· P15/XTALI_32K (double bonded pin on the CYW30739B2-P5TAI051 module, only one of two is available)
For GPIOs highlighted as double bonded connections, only one of the connections can be used at a given time. When a certain GPIO is selected, the other GPIOs bonded to the same connection must be configured to input with output disable.

11.8

PWM

The CYW30739B2-P5TAI051 has six internal PWMs, labeled PWM0-5. The PWM module consists of the following:

· Each of the six PWM channels contains the following registers: - 16-bit initial value register (read/write) - 16-bit toggle register (read/write) - 16-bit PWM counter value register (read)

· PWM configuration register shared among PWM05 (read/write). This 18-bit register is used: - To configure each PWM channel - To select the clock of each PWM channel - To change the phase of each PWM channel

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The application can access the PWM module through the FW driver. Figure 12 shows the structure of one PWM channel.

Figure 12 PWM block diagram

11.9

PDM microphone

The CYW30739B2-P5TAI051 accepts a L\-based one-bit pulse density modulation (PDM) input stream and outputs filtered samples at either 8 kHz or 16 kHz sampling rates. The PDM signal derives from an external kit that can process analog microphone signals and generate digital signals. The PDM input shares the filter path with the auxADC. Two types of data rates can be supported:

· 8 kHz

· 16 kHz
The external digital microphone takes in a 2.4 MHz clock generated by the CYW30739B2-P5TAI051 and outputs a PDM signal which is registered by the PDM interface with either the rising or falling edge of the 2.4 MHz clock selectable through a programmable control bit. The design can accommodate two simultaneous PDM input channels, so stereo voice is possible.
Note Subject to the driver support in WICED Studio.

11.10

I2S interface

The CYW30739B2-P5TAI051 supports a single I2S digital audio port with both master and slave modes. The I2S signals are:

· I2S clock: I2S SCK

· I2S word select: I2S WS

· I2S data out: I2S DO

· I2S data in: I2S DI

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I2S SCK and I2S WS become outputs in master mode and inputs in slave mode, while I2S DO always stays as an output. The channel word length is 16 bits and the data is justified so that the MSN of the left -channel data is aligned with the MSB of the I2S bus, per I2S Specifications. The MSB of each data word is transmitted one bit clock cycle after the I2S WS transition, synchronous with the falling edge of bit clock. Left channel data is transmitted when I2S WS is low, and right-channel data is transmitted when I2S WS is high. Data bits sent by the CYW30739B2-P5TAI051 are synchronized with the falling edge of I2S SCK and should be sampled by the receiver on the rising edge of the I2S SCK.
Note The PCM interface shares HW with the I2S interface and only one can be used at a given time.

11.11

PCM interface

The CYW30739B2-P5TAI051 includes a PCM interface that can connect to linear PCM codec devices in master or slave mode. In master mode, the CYW30739B2-P5TAI051 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYW30739B2P5TAI051.The configuration of the PCM interface may be adjusted by the host using vendor -specific HCI commands.

Note The PCM interface shares HW with the I2S interface and only one can be used at a given time.

11.11.1 Slot mapping
The CYW30739B2-P5TAI051 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM Interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or 1024 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot.

11.11.2 Frame synchronization
The CYW30739B2-P5TAI051 supports both short- and long-frame synchronization in both master and slave modes. In short frame synchronization mode, the frame synchronization signal is an active -high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCGM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot.

11.11.3 Data formatting
The CYW30739B2-P5TAI051 may be configured to generate and accept several different data formats. For conventional narrow band speech mode, the CYW30739B2-P5TAI051 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2's complement data, left justified, and clocked MSB first.

11.11.4 Burst PCM mode
In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with an HCI command from the host.

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11.12

Security engine

The CYW30739B2-P5TAI051 includes a hardware security accelerator which greatly decreases the time required to perform typical security operations. Access to the hardware block is provided via a firmware interface.
This security engine includes:

· Public key acceleration (PKA) cryptography

· AES-CTR/CBC-MAC/CCM acceleration

· SHA2 message hash and HMAC acceleration

· RSA encryption and decryption of modulus sizes up to 2048 bits

· Elliptic curve Diffie-Hellman in prime field GF(p)
Note Security engine is used only by the Bluetooth® stack to reduce CPU overhead. It is not available for application use.

11.12.1 Random number generator
This hardware block is used for key generation for Bluetooth®.
Note Availability for use by the application is subject to the support in WICED Studio. Note The random number generator block must be warmed up prior to use. A delay of 500 ms from cold boot is necessary prior to using the random number generator.

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Power modes

Power modes

The CYW30739B2-P5TAI051 support the following HW power modes are supported:
· Active mode - Normal operating mode in which all peripherals are available and the CPU is active.
· Idle mode - In this mode, the CPU is in "Wait for Interrupt" (WFI) and the HCLK, which is the high frequency clock derived from the main crystal oscillator is running at a lower clock speed. Other clocks are active and the state of the entire chip is retained.
· Sleep mode - In this mode, CPU is in WFI and the HCLK is not running. The PMU determines if the other clocks can be turned off and does accordingly. State of the entire chip is retained, the internal LDOs run at a lower voltage (voltage is managed by the PMU), and SRAM is retained.
· PDS mode - This mode is an extension of the PMU Sleep wherein most of the peripherals such as UART and SPI are turned off. The entire memory is retained, and on wakeup the execution resumes from where it paused.
· Shut Down Sleep (SDS) - Everything is turned off except the IO power domain, RTC, and LPO. The device can come out of this mode either due to BT activity or by an external interrupt. Before going into this mode, the application can store some bytes of data into "Always On RAM" (AON). When the device comes out of this mode, the data from AON is restored. After waking from SDS, the application will start from the beginning (warmboot) and has to restore its state based on information stored in AON. In the SDS mode, a single BT task with no data activity, such as an ACL connection, Bluetooth® LE connection, or Bluetooth® LE advertisement can be performed.
· HIDOFF (Timed-Wake) mode - The device can enter this mode asynchronously, that is, the application can force the device into this mode at any time. IO power domain, RTC, and LPO are the only active blocks. A timer that runs off the LPO is used to wake the device up after a predetermined fixed time.
· HIDOFF (External Interrupt-Waked) mode - This mode is similar to Timed-Wake, but in HID-off mode even the LPO and RTC are turned off. So, the only wakeup source is an external interrupt.
Transition between power modes is handled by the on-chip firmware with host/application involvement. Refer to the Firmware section for details.

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Firmware

Firmware

The CYW30739B2-P5TAI051 ROM firmware runs on a real time operating system and handles the programming and configuration of all on-chip hardware functions as well as the BT/LE baseband, LM, HCI, GATT, ATT, L2CAP and SDP layers. The ROM also includes drivers for on-chip peripherals as well as handling on-chip power management functions including transitions between different power modes.

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Electrical characteristics

Electrical characteristics

The absolute maximum ratings in the following table indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.

Table 9

Silicon absolute maximum ratings

Requirement parameter
Maximum junction temperature VDDIO VDDRF VDDBAT3V DIGLDO_VDDIN1P5 RFLDO_VDDIN1P5 PALDO_VDDIN_5V MIC_AVDD

Specification
Min
0.5 0.5 0.5 0.5 0.5 0.5 0.5

Nom

Max 125 3.795 1.38 3.795 1.65 1.65 3.795 3.795

Unit
°C V V V V V V V

Table 10

ESD/latchup

Requirement parameter
ESD tolerance HBM (Silicon) ESD tolerance CDM (Silicon) Latchup

Specification

Unit

Min

Nom

Max

2000

500

200

Table 11

Power supply specifications

Parameter

Conditions

Min

Typ

Max

Unit

VDD input

Module chipset input

1.76

3.0

3.63

VDDPA input VDD ripple

Module PA/LNA input

2.0

3.0

3.60

Module input ripple (VDDPA, VDD)

100

VBAT input

Internal to module (not accessible)

1.90

3.0

3.6

PMU turn-on time

VBAT is ready

300

µs

The CYW30739B2-P5TAI051 uses an onboard low voltage detector to shut down the part when supply voltage (VDD) drops below operating range.

Table 12

Power supply shut down specifications

Parameter VSHUT

Min

Typ

Max

Unit

1.625

1.7

1.76

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Electrical characteristics

Table 13

Bluetooth®, Bluetooth® LE, BR and EDR current consumption

Parameter

Description

Silicon or mod-

ule

Typ

Unit

parameter

HCI

48 MHz with pause

Silicon

1.1

HCI

48 MHz without pause

Silicon

2.2

Continuous RX

Silicon

5.9

Continuous TX - 0 dBm

Silicon

5.6

PDS

Silicon

6.1

HID-Off (SDS)

32 kHz XTAL and 16 KB retention RAM on

Silicon

1.6

Advertising

Unconnectable - 1 second

Silicon

Advertising

Connectable undirected - 1 second

Silicon

Page Scan - PDS

Interlaced - R1

Silicon

122

Sniff - PDS

500 ms Sniff, 1 attempt, 0 timeout - Master Silicon

132

Sniff - PDS

500 ms Sniff, 1 attempt, 0 timeout - Slave

Silicon

138

Bidirectional data Continuous DM5 or DH5 packets - Master

exchange

or slave

Silicon

6.9

Bluetooth® Low Energy (20 dBm)

RX peak

Peak RX current

Module

8.8

TX peak

Peak TX current

Module

PDS

Module

13.9

HID-Off (SDS)

Module

14.9

Advertising - SDS Connectable undirected - 1 second

Module

LE connection - SDS Slave - 1 second

Module

Bluetooth® Classic (BR, EDR, 20 dBm)

IDLE

Module is idle, non-discoverable and non-connectable

Module

8.3

Iscan

Inquiry scan (1.28 seconds)

Module

160

Pscan

Page scan (1.28 seconds)

Module

160

IScan + Pscan

Inquiry scan + page scan (1.28 seconds)

Module

10.4

Connected

Connected with no data transfer

Module

12.7

Connected + Pscan

Connected with no data transfer + page scan (1.28 seconds)

Module

12.75

Connected + IScan + Pscan

Connected with no data transfer + inquiry scan (1.28 seconds) + page scan (1.28 seconds)

Module

12.9

Connected + SNIFF

Connected with no data transfer + SNIFF (500 ms)

Module

Connected + SNIFF + IScan + Pscan

Connected with no data transfer + SNIFF (500 ms) + inquiry scan and page scan 1.28 seconds

Module

10.5

TX_BR

Data transfer @115200 baud rate

Module

21.5

TX + SNIFF_BR

Data transfer @115200 baud rate + SNIFF (500 ms)

Module

14.5

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Electrical characteristics

Table 14. Power amplifier/low noise amplifier current consumption specifications

Parameter

Test condition

TX high power current Pout = +20dBm

TX quiescent current No RF applied

RX quiescent current No RF applied

Min

Typ

Max

Unit

100

14.1

Core buck regulator

Table 15

Silicon core buck regulator

Parameter

Conditions

Input supply voltage DC, VBAT

DC voltage range inclusive of distur-bances

CBUCK output current

LPOM only

Output voltage range

Programmable, 30 mV/step default = 1.2V (bits = 0000)

Output voltage DC accuracy Includes load and line regulation

LPOM efficiency (high load)

LPOM efficiency (low load)

Input supply voltage ramp-up time

0 to 3.3V

Min Typ Max Unit

1.90

3.0 3.63

1.2 1.26

1.5

µs

· Minimum capacitor value refers to residual capacitor value after taking into account part-to-part tolerance, DC-bias, temperature, and aging.
· Maximum capacitor value refers to the total capacitance seen at a node where the capacitor is connected. This also includes any decoupling capacitors connected at the load side, if any.

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14.2
Table 16 Parameter

Digital LDO
Digital LDO

Input supply voltage, Vin

Nominal output voltage, Vo Dropout voltage

Conditions Minimum Vin = Vo + 0.12V requirement must be met under maximum load.
Internal default setting
At maximum load

Min Typ Max Unit

1.2 1.2 1.6

1.1

120 mV

14.3

Digital I/O characteristics

Table 17

Digital I/O characteristics

Characteristics

Symbol

Input low voltage (VDD = 3 V)

VIL

Input high voltage (VDD = 3 V)

VIH

Input low voltage (VDD = 1.8 V)

VIL

Input high voltage (VDD = 1.8 V)

VIH

Output low voltage

VOL

Output high voltage

VOH

Input low current

IIL

Input high current

IIH

Output low current (VDD = 3 V, VOL = 0.5 V) IOL

Output low current (VDD = 1.8 V, VOL = 0.5 V) IOL

Output high current (VDD = 3 V, VOH = 2.55 V) IOH

Output high current (VDD = 1.8 V, VOH = 1.35 V) IOH

Input capacitance

CIN

Min

Typ

2.4

1.4

VDDO 0.45V

Max 0.8
0.4
0.45
1.0 1.0 8.0 4.0 8.0
4.0 0.4

14.4

ADC electrical characteristics

Table 18. Electrical characteristics

Parameter

Symbol Conditions/Comments

Min

Typ

Max

Current consumption ITOT Power down current

At room temperature

ADC core specification

ADC reference voltage VREF

From BG with ±3% accuracy

0.85

ADC sampling clock

Absolute error

Includes gain error, offset and

distortion. Without factory

calibration.

Includes gain error, offset and

distortion. After factory

calibration.

ENOB

For audio application For static measurement

Unit V V V V V V
µA µA mA mA mA mA pF
Unit mA µA
V MHz
%
%
Bit

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Electrical characteristics

Table 18. Electrical characteristics (continued)

Parameter ADC input full scale

Symbol FS

Conditions/Comments For audio application For static measurement

Min

Typ

Max

Unit

1.6

1.8

3.6

Conversion rate

For audio application For static measurement

100

kHz

Signal bandwidth

For audio application For static measurement

Input impedance

RIN

For audio application For static measurement

500

Startup time

For audio application For static measurement

µs

MIC PGA specifications

MIC PGA gain range

MIC PGA gain step

MIC PGA gain error

Includes part-to-part gain variation

PGA input referred noise

At 42 dB PGA gain A-weighted

µV

Passband gain flatness

PGA and ADC, 100 Hz4 kHz 0.5

0.5

MIC bias specifications

MIC bias output voltage

At 2.5V supply

2.1

MIC bias loading current

MIC bias noise

Refers to PGA input 20 Hz to 8 kHz, A-weighted

µV

MIC bias PSRR

at 1 kHz

ADC SNR

A-weighted 0 dB PGA gain

ADC THD + N

3 dB FS input 0 dB PGA gain

GPIO input voltage GPIO source impedance[4]

Always lower than VDDBAT

Resistance

Capacitance

3.6

Note 4. Conditional requirement for the measurement time of 10 ms. Relaxed with longer measurement time for each GPIO input channel.

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Chipset RF specifications

Chipset RF specifications

Table 19 and Table 20 apply to single-ended industrial temperatures. Unused inputs are left open. Table 19 Chipset receiver RF specifications

Parameter Frequency range

Mode and conditions

RX sensitivity[5]

GFSK, 0.1% BER, 1 Mbps 7t/4-DQPSK, 0.01% BER, 2 Mbps

8-DPSK, 0.01% BER, 3 Mbps

Maximum input

All data rates

GFSK modulation C/I cochannel

GFSK, 0.1% BER[5]

C/I 1 MHz adjacent channel

GFSK, 0.1% BER[6]

C/I 2 MHz adjacent channel

GFSK, 0.1% BER[7]

C/I 3 MHz adjacent channel C/I image channel

GFSK, 0.1% BER[5] GFSK, 0.1% BER[7]

C/I 1 MHz adjacent to image channel GFSK, 0.1% BER[7]

QPSK modulation

C/I cochannel

7t/4-DQPSK, 0.1% BER[7]

C/I 1 MHz adjacent channel

7t/4-DQPSK, 0.1% BER[8]

C/I 2 MHz adjacent channel

7t/4-DQPSK, 0.1% BER[7]

C/I 3 MHz adjacent channel

7t/4-DQPSK, 0.1% BER[9]

C/I image channel

7t/4-DQPSK, 0.1% BER[7]

C/I 1 MHz adjacent to image channel

7t/4-DQPSK, 0.1% BER[7]

8PSK modulation C/I cochannel

8-DPSK, 0.1% BER[7]

C/I 1 MHz adjacent channel

8-DPSK, 0.1% BER[7]

C/I 2 MHz adjacent channel

8-DPSK, 0.1% BER[7]

C/I 3 MHz adjacent channel C/I image channel

8-DPSK, 0.1% BER[9] 8-DPSK, 0.1% BER[7]

C/I 1 MHz adjacent to image channel

8-DPSK, 0.1% BER[7]

Out-of-band blocking performance (CW)[8]

30 MHz to 2000 MHz

BDR GFSK 0.1% BER

2000 MHz to 2399 MHz

BDR GFSK 0.1% BER

2498 MHz to 3000 MHz 3000 MHz to 12.75 GHz

BDR GFSK 0.1% BER BDR GFSK 0.1% BER

Inter-modulation performance[5] BT, interferer signal level

BDR GFSK 0.1% BER

Spurious emissions

Min 2402

Typ
92.0[5] 94.0[6] 88.0[6]

10.0 27.0 27.0 10.0

Max

Unit

2480

MHz

dBm

11.0

30.0

40.0

9.0

20.0

13.0

30.0

40.0

9.0

20.0

21.0

5.0

25.0

33.0

dBm

39.0

dBm

30 MHz to 1 GHz

57.0

dBm

1 GHz to 12.75 GHz

55.0

dBm

Notes 5. Dirty TX is Off. 6. Up to 1 dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations. 7. The receiver sensitivity is measured at BER of 0.1% on the device interface. 8. Desired signal is 10 dB above the reference sensitivity level (defined as 70 dBm). 9. Desired signal is 3 dB above the reference sensitivity level (defined as 70 dBm). 10.Desired signal is -64 dBm Bluetooth®-modulated signal, interferer 1 is 39 dBm sine wave at frequency f1, interferer 2 is 39 dBm
Bluetooth® modulated signal at frequency f2, f0 = 2 * f1 f2, and |f2 f1| = n * 1 MHz, where n is 3, 4, or 5. For the typical case, n = 4.

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Chipset RF specifications

Table 20

Chipset transmitter RF specifications

Parameter Transmitter section Frequency range Class 2: GFSK TX power Class 2: EDR TX Power 20 dB bandwidth Adjacent channel power |M N| = 2 |M N| 3 Out-of-band spurious emission 30 MHz to 1 GHz 1 GHz to 12.75 GHz 1.8 GHz to 1.9 GHz 5.15 GHz to 5.3 GHz LO performance Initial carrier frequency tolerance
Frequency drift DH1 packet DH3 packet DH5 packet Drift rate
Frequency deviation Average deviation in payload (sequence used is 00001111) Maximum deviation in payload (sequence used is 10101010) Channel spacing Modulation accuracy
/4-DQPSK frequency stability /4-DQPSK RMS DEVM /4-QPSK Peak DEVM /4-DQPSK 99% DEVM 8-DPSK frequency stability 8-DPSK RMS DEVM 8-DPSK Peak DEVM
8-DPSK 99% DEVM In-band spurious emissions 1.0 MHz < |M N| < 1.5 MHz 1.5 MHz < |M N| < 2.5 MHz |M N| > 2.5 MHz

Min
2402

75
25 40 40 20
140 115

10
10

Typ

Max

Unit

2480

MHz

4.0

dBm

930

1000

kHz

36.0

30.0

47.0

dBm dBm
dBm dBm dBm dBm

+75 kHz

+25 kHz

+40 kHz

20 kHz/50 µs

175

kHz

MHz

kHz

dBm

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Chipset RF specifications

Table 21

Bluetooth® LE RF specifications

Parameter Frequency range RX sensitivity (QFN)[111
TX power
Mod Char: Delta F1 average Mod Char: Delta F2 max[131 Mod Char: Ratio

Conditions N/A LE GFSK, 0.1% BER, 1 Mbps Bluetooth® LE silicon device CYW30739 Only
N/A
N/A
N/A

Min 2402

225
99.9 0.8

Typ 95.0[121
4.0

Max 2480

255

275

0.95

Unit MHz dBm dBm
kHz
% %

Table 22

CYW30739B2-P5TAI051 GPS and GLONASS band spurious emission

Parameter 1570-1580 MHz 1592-1610 MHz

Condition GPS GLONASS

Min

Typ

160

159

Max Unit dBm/Hz dBm/Hz

Notes 11.Dirty TX is Off. 12.Up to 1 dB of variation may potentially be seen from typical sensitivity specs due to the chip, board and associated variations. 13.At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz

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Timing and AC characteristics

Timing and AC characteristics

In this section, use the numbers listed in the Reference column of each table to interpret the following timing diagrams.

16.1

UART timing

Table 23

UART timing specifications

Reference Characteristics

Min

Delay time, UART_CTS_N low to UART_TXD valid.

Setup time, UART_CTS_N high before midpoint of stop bit.

Delay time, midpoint of stop bit to UART_RTS_N high.

Typ Max Unit 1.50 Bit periods 0.67 Bit periods 1.33 Bit periods

Figure 13 UART timing

16.2

SPI timing

The SPI interface can be clocked up to 24 MHz.

Table 24 and Figure 14 show the timing requirements when operating in SPI mode 0 and 2.

Table 24

SPI mode 0 and 2

Reference Characteristics

Time from master assert SPI_CSN to first clock edge

Hold time for MOSI data lines

Time from last sample on MOSI/MISO to slave deassert SPI_INT

Time from slave deassert SPI_INT to master deassert SPI_CSN

Idle time between subsequent SPI transactions

Min 45 12 0 0
1 SCK

Max Unit

1/2 SCK

100

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Timing and AC characteristics

Figure 14 SPI timing, Mode 0 and 2

Table 25 and Figure 15 show the timing requirements when operating in SPI mode 1 and 3.

Table 25

SPI mode 1 and 3

Reference Characteristics

Min Max

Unit

Time from master assert SPI_CSN to first clock edge

Hold time for MOSI data lines

1/2 SCK

Time from last sample on MOSI/MISO to slave deassert SPI_INT

0 100

Time from slave deassert SPI_INT to master deassert SPI_CSN

Idle time between subsequent SPI transactions

1 SCK

Figure 15 SPI timing, Mode 1 and 3

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Timing and AC characteristics

16.3

I2C compatible interface timing

The specifications in Table 26 references Figure 16.

Table 26

I2C compatible interface timing specifications (up to 1 MHz)

Reference Characteristics

Min

Max

Unit

100

Clock frequency

400

kHz

800

START condition setup time

START condition hold time

Clock low time

Clock high time

Data input hold time[14]

Data input setup time

STOP condition setup time

Output valid from clock

Bus free time[15]

1000

650

280

650

280

100

280

400

650

Figure 16

I2C interface timing diagram

Notes 14.As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation
of START or STOP conditions. 15.Time that the CBUS must be free before a new transaction can start.

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Timing and AC characteristics

16.4

I2S interface timing

I2S timing is shown below in Table 27, Figure 17, and Figure 18.

Table 27

Timing for I2S transmitters and receivers

Transmitter

Parameter

Lower limit

Upper limit

Min

Max Min

Max

Clock period T

Ttr

Master mode: Clock generated by transmitter or receiver

HIGH tHC LOWtLC

0.35Ttr

Slave mode: Clock accepted by transmitter or receiver

HIGH tHC LOW tLC Rise time tRC

0.35Ttr

0.15Ttr

Transmitter

Delay tdtr

0.8T

Hold time thtr

Receiver Setup time tsr Hold time thr

Receiver

Lower limit

Min

Max

0.35Ttr

0.35Ttr 0.35Ttr

0.2Ttr

Upper limit

Min

Max

Notes
Note 16
Note 17 Note 17
Note 18 Note 18 Note 19
Note 20 Note 19
Note 21 Note 21

Figure 17 I2S transmitter timing
Notes 16.The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data
transfer rate. 17.At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and
tLC are specified with respect to T. 18.In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal.
So long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used. 19.Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can
result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr. 20.To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time. 21.The data setup and hold time must not be less than the specified receiver setup and hold time.

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Timing and AC characteristics

Figure 18

I2S receiver timing

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Environmental specifications

Environmental specifications

17.1

Environmental compliance

This Bluetooth® LE module is produced in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen-Free (HF) directives. The module and components used to produce this module are RoHS and HF compliant.

17.2

RF certification

The CYW30739B2-P5TAI051 module is certified under the following RF certification standards:

· FCC: WAP739I05

· IC: 7922A-739I05

· MIC:

· CE

17.3

Safety certification

The CYW30739B2-P5TAI051 module complies with the following safety regulations:

· Underwriters Laboratories, Inc. (UL): Filing E331901

· CSA

· TUV

17.4

Environmental conditions

Table 28 describes the operating and storage conditions for the Bluetooth® LE module.

Table 28. Environmental conditions for CYW30739B2-P5TAI051

Description Operating temperature Operating humidity (relative, non-condensation) Thermal ramp rate Storage temperature Storage temperature and humidity

Minimum specification
-30 °C
5% 40 °C

ESD: Module integrated into system components[22]

Maximum specification 85 °C 85% 10 °C/minute 85 °C 85 °C at 85% 15 kV air 2.0 kV contact

17.5

ESD and EMI protection

Exposed components require special attention to ESD and electromagnetic interference (EMI).

A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground.

Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.

Note 22.This does not apply to the RF pins (ANT).

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18 Regulatory information

18.1

FCC

FCC notice:

The device CYW30739B2-P5TAI051 complies with Part 15 of the FCC Rules. The device meets the requirements
for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.

Caution:
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Infineon may void the user's authority to operate the equipment.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
· Reorient or relocate the receiving antenna.
· Increase the separation between the equipment and receiver.
· Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
· Consult the dealer or an experienced radio/TV technician for help

Labeling requirements: The original equipment manufacturer (OEM) must ensure that FCC labeling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Infineon FCC identifier for this product as well as the FCC notice above. The FCC identifier is FCC ID: WAP739I05.
In any case the end product must be labeled exterior with "Contains FCC ID: WAP739I05".
Antenna warning:
This device is tested with a standard SMA connector and with the antenna listed in Table 6. When integrated in the OEMs product, this fixed antenna requires installation preventing end-users from replacing them with nonapproved antennas. Any antenna not in Table 6 must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions.

RF exposure:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous.
The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas in Table 6, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed.
The radiated output power of CYW30739B2-P5TAI051 with the integrated trace antenna (FCC ID: WAP739I05) is far below the FCC radio frequency exposure limits. Nevertheless, use CYW30739B2-P5TAI051 in such a manner that minimizes the potential for human contact during normal operation.
End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance.
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 8 mm between the radiator and your body.

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Regulatory information

18.2

ISED

Innovation, Science and Economic Development (ISED) Canada Certification

CYW30739B2-P5TAI051 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development (ISED) Canada.

License: IC: 7922A-739I05

Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca.

This device has been designed to operate with the antennas listed in Table 6, having a maximum gain of -0.5 dBi. Antennas not included in Table 6 or having a gain greater than -0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 . The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter.

ISED notice:
The device CYW30739B2-P5TAI051 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation.

L'appareil CYW30739B2-P5TAI051, y compris l'antenne intégrée, est conforme aux Règles RSS-GEN de Canada. L'appareil répond aux exigences d'approbation de l'émetteur modulaire tel que décrit dans RSS-GEN. L'opération est soumise aux deux conditions suivantes: (1) Cet appareil ne doit pas causer d'interférences nuisibles, et (2) Cet appareil doit accepter toute interférence reçue, y compris les interférences pouvant entraîner un fonctionnement indésirable.

ISED interference statement for Canada
This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device.

Cet appareil est conforme à la norme sur l'innovation, la science et le développement économique (ISED) norme RSS exempte de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

ISED radiation exposure statement for Canada This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment.

Cet équipement est conforme aux limites d'exposition aux radiations ISED prévues pour un environnement incontrôlé.

Labeling requirements:
The original equipment manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Infineon IC identifier for this product as well as the ISED Notices above. The IC identifier is 7922A-739I05. In any case, the end product must be labeled in its exterior with "Contains IC: 7922A-739I05".

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Regulatory information

Le fabricant d'équipement d'origine (OEM) doit s'assurer que les exigences d'étiquetage ISED sont respectées. Cela
comprend une étiquette clairement visible à l'extérieur de l'enceinte OEM spécifiant l'identifiant Infineon IC approprié pour ce produit ainsi que l'avis ISED ci-dessus. L'identificateur IC est 7922A-739I05. En tout cas, le produit final doit être étiqueté dans son extérieur avec "Contient IC: 7922A-739I05".

This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with a minimum distance of 10 mm between the radiator and your body.
Cet équipement est conforme aux limites d'exposition aux radiations ISED prévues pour un environnement incontrôlé. Cet équipement doit être installé et utilisé avec un minimum de 10 mm de distance entre la source de rayonnement et votre corps.

18.3

European Declaration of Conformity

Hereby, Infineon declares that the Bluetooth® module CYW30739B2-P5TAI051 complies with the essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows:

All versions of the CYW30739B2-P5TAI051 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway.

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Packaging

Packaging

Table 29

Solder reflow peak temperature

Module part number

Package

Maximum peak temperature

CYW30739B2-P5TAI051 31-pad SMT 260 °C

Maximum time at peak temperature
30 seconds

No. of cycles 2

Table 30

Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-2

Module part number

Package

MSL

CYW30739B2-P5TAI051

34-pad SMT

MSL 3

The CYW30739B2-P5TAI051 is offered in tape and reel packaging. Figure 19 details the tape dimensions used for the CYW30739B2-P5TAI051.

Figure 19 CYW30739B2-P5TAI051 tape dimensions Figure 20 details the orientation of the CYW30739B2-P5TAI051 in the tape as well as the direction for unreeling.

Figure 20 Component orientation in tape and unreeling direction

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Packaging
Figure 21 details reel dimensions used for the CYW30739B2-P5TAI051.

Figure 21 Reel dimensions

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Ordering information

Ordering information

Table 31 lists the CYW30739B2-P5TAI051 part number and features. Table 31 also lists the target program for the respective module ordering codes. Table 32 lists the reel shipment quantities for the CYW30739B2-P5TAI051.

Table 31

Ordering information

Ordering part number

Max CPU speed (MHz)

Flash size
(KB)

RAM size (KB)

UART

I2C

SPI

I2S

PCM

PWM

ADC inputs

CYW30739B2-P5TAI05 1

1024 512 Yes Yes Yes Yes Yes 6

GPIOs Package 13 31-SMT

Packaging Tape and reel

Table 32

Tape and reel package quantity and minimum order amount

Description
Reel quantity Minimum order quantity (MOQ) Order increment (OI)

Minimum reel quantity
500
500
500

Maximum reel quantity
500

Comments
Ships in 500 unit reel quantities.

The CYW30739B2-P5TAI051 is offered in tape and reel packaging. The CYW30739B2-P5TAI051 ships in a reel size of 500 units.

For additional information and a complete list of Infineon's Bluetooth® products, contact your local Infineon sales representative. To locate the nearest Infineon office, visit our website.

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Acronyms

Acronyms

Table 33

Acronyms used in this document

Acronym Bluetooth® LE Bluetooth® SIG CE CSA EMI ESD FCC GPIO ISED IDE KC MIC OTA PCB RX

Description Bluetooth® Low Energy Bluetooth® Special Interest Group European Conformity Canadian Standards Association electromagnetic interference electrostatic discharge Federal Communications Commission general-purpose input/output Innovation, Science and Economic Development (Canada) integrated design environment Korea Certification Ministry of Internal Affairs and Communications (Japan) Over-the-Air printed circuit board receive

QDID
SMT
TCPWM TUV TX

qualification design ID surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of PCBs timer, counter, pulse width modulator (PWM) Germany: Technischer Überwachungs-Verein (Technical Inspection Association) transmit

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Document conventions

22
22.1
Table 34
Symbol °C kV mA mm mV µA µm MHz GHz V

Document conventions
Units of measure
Units of measure
Unit of measure degree Celsius kilovolt milliamperes millimeters millivolt microamperes micrometers megahertz gigahertz volt

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Document conventions

Revision history

Document version
**

Date of release Description of changes

2024-06-21

Initial release

Preliminary Datasheet

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Trademarks
All referenced product or service names and trademarks are the property of their respective owners. The Bluetooth® word mark and logos are registered trademarks owned by Bluetooth SIG, Inc., and any use of such marks by Infineon is under license.

Edition 2024-06-21 Published by Infineon Technologies AG 81726 Munich, Germany
© 2024 Infineon Technologies AG. All Rights Reserved.
Do you have a question about this document? Go to www.infineon.com/support
Document reference 002-40069 Rev. **

IMPORTANT NOTICE

The information given in this document shall in no event For further information on the product, technology,

be regarded as a guarantee of conditions or delivery terms and conditions and prices please contact

characteristics ("Beschaffenheitsgarantie").

your nearest Infineon Technologies office

(www.infineon.com).

With respect to any examples, hints or any typical

values stated herein and/or any information WARNINGS

regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party.

Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office.

In addition, any information given in this document is subject to customer's compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer's products and any use of the product of Infineon Technologies in customer's applications.

Except as otherwise explicitly approved by Infineon

Technologies in a written document signed by

authorized

representatives

Infineon

Technologies, Infineon Technologies' products may not

be used in any applications where a failure of the

product or any consequences of the use thereof can

reasonably be expected to result in personal injury.

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer's technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application.

References

Microsoft Word for Microsoft 365