ALINX 芯驿电子科技（上海）有限公司
User Manual for ALINX models including: AC7A200 ARTIX-7 FPGA Development Board, AC7A200, ARTIX-7 FPGA Development Board, FPGA Development Board, Development Board, Board
ARTIX-7FPGADevelopmentBoardAC7A200UserManual 11/31 www.alinx.com Part4:DDR3DRAM The FPGA core board AC7A200 is equipped with two Micron 4Gbit (512MB) DDR3 chips ...
File Info : application/pdf, 31 Pages, 1.53MB
DocumentDocumentARTIX-7 FPGA Core Board AC7A200 System on Module ARTIX-7 FPGA Development Board AC7A200 User Manual Version Record Version Rev 1.0 Date 2020-06-28 Release By Rachel Zhou Description First Release 2 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Table of Contents Version Record...................................................................................................... 2 Part 1: AC7A200 Core Board Introduction........................................................4 Part 2: FPGA Chip.................................................................................................6 Part 3: Active Differential Crystal........................................................................ 8 Part 3.1: 200Mhz Active Differential clock................................................. 8 Part 3.2: 125MHz Active Differential Crystal............................................. 9 Part 4: DDR3 DRAM........................................................................................... 11 Part 5: QSPI Flash.............................................................................................. 15 Part 6: LED Light on Core Board......................................................................17 Part 7: JTAG Interface.........................................................................................19 Part 8: Power Interface on the Core Board.................................................... 20 Part 9: Board to Board Connectors pin assignment..................................... 21 Part 10: Power Supply........................................................................................29 Part 11: Size Dimension.....................................................................................31 3 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Part 1: AC7A200 Core Board Introduction AC7A200 (core board model, the same below) FPGA core board, it is based on XILINX's ARTIX-7 series 100T XC7A200T-2FBG484I. It is a high-performance core board with high speed, high bandwidth and high capacity. It is suitable for high-speed data communication, video image processing, high-speed data acquisition etc. This AC7A200 core board uses two pieces of MICRON's MT41J256M16HA-125 DDR3 chip, each DDR has a capacity of 4Gbit; two DDR chips are combined into a 32-bit data bus width, and the read/write data bandwidth between FPGA and DDR3 is up to 25Gb; such a configuration can meet the needs of high bandwidth data processing. The AC7A200 core board expands 180 standard IO ports of 3.3V level, 15 standard IO ports of 1.5V level, and 4 pairs of GTP high speed RX/TX differential signals. For users who need a lot of IO, this core board will be a good choice. Moreover, the routing between the FPGA chip and the interface is equal length and differential processing, and the core board size is only 2.36 inch *2.36 inch, which is very suitable for secondary development. 4 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Figure 1-1: AC7A200 Core Board (Front View) Figure 1-2: AC7A200 Core Board (Rear View) 5 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Part 2: FPGA Chip As mentioned above, the FPGA model we use is XC7A200T-2FBG484I, which belongs to Xilinx's Artix-7 series. The speed grade is 2, and the temperature grade is industry grade. This model is a FGG484 package with 484 pins. Xilinx ARTIX-7 FPGA chip naming rules as below Figure 2-1: The Specific Chip Model Definition of ARTIX-7 Series Figure 2-2: FPGA chip on board The main parameters of the FPGA chip XC7A200T are as follows Name Specific parameters Logic Cells 215360 Slices 33650 CLB flip-flops 269200 6 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Block RAMkb DSP Slices PCIe Gen2 XADC GTP Transceiver Speed Grade Temperature Grade 13140 740 1 1 XADC, 12bit, 1Mbps AD 4 GTP, 6.6Gb/s max -2 Industrial FPGA power supply system Artix-7 FPGA power supplies are V , CCINT V , CCBRAM V , CCAUX VCCO, VMGTAVCC and V . MGTAVTT VCCINT is the FPGA core power supply pin, which needs to be connected to 1.0V; VCCBRAM is the power supply pin of FPGA Block RAM, connect to 1.0V; VCCAUX is FPGA auxiliary power supply pin, connect 1.8V; VCCO is the voltage of each BANK of FPGA, including BANK0, BANK13~16, BANK34~35. On AC7A200 FPGA core board, BANK34 and BANK35 need to be connected to DDR3, the voltage connection of BANK is 1.5V, and the voltage of other BANK is 3.3V. The VCCO of BANK15 and BANK16 is powered by the LDO, and can be changed by replacing the LDO chip. VMGTAVCC is the supply voltage of the FPGA internal GTP transceiver, connected to 1.0V; VMGTAVTT is the termination voltage of the GTP transceiver, connected to 1.2V. The Artix-7 FPGA system requires that the power-up sequence be power by V , CCINT then V , CCBRAM then V , CCAUX and finally VCCO. If VCCINT and VCCBRAM have the same voltage, they can be powered up at the same time. The order of power outages is reversed. The power-up sequence of the GTP transceiver is V , CCINT then V , MGTAVCC then V . MGTAVTT If VCCINT and VMGTAVCC have the same voltage, they can be powered up at the same time. The power-off sequence is just the opposite of the power-on sequence. 7 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Part 3: Active Differential Crystal The AC7A200 core board is equipped with two Sitime active differential crystals, one is 200MHz, the model is SiT9102-200.00MHz, the system main clock for FPGA and used to generate DDR3 control clock; the other is 125MHz, model is SiT9102 -125MHz, reference clock input for GTP transceivers. Part 3.1: 200Mhz Active Differential clock G1 in Figure 3-1 is the 200M active differential crystal that provides the development board system clock source. The crystal output is connected to the BANK34 global clock pin MRCC (R4 and T4) of the FPGA. This 200Mhz differential clock can be used to drive the user logic in the FPGA. Users can configure the PLLs and DCMs inside the FPGA to generate clocks of different frequencies. Figure 3-1: 200Mhz Active Differential Crystal Schematic Figure 3-2: 200Mhz Active Differential Crystal on the Core Board 8 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual 200Mhz Differential Clock Pin Assignment Signal Name SYS_CLK_P SYS_CLK_N FPGA PIN R4 T4 Part 3.2: 125MHz Active Differential Crystal G2 in Figure 3-3 is the 125MHz active differential crystal, which is the reference input clock provided to the GTP module inside the FPGA. The crystal output is connected to the GTP BANK216 clock pins MGTREFCLK0P (F6) and MGTREFCLK0N (E6) of the FPGA. Figure 3-3: 125MHz Active Differential Crystal Schematic Figure 3-4: 125MHz Active Differential Crystal on the Core Board 9 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual 125MHz Differential Clock Pin Assignment Net Name MGT_CLK0_P MGT_CLK0_N FPGA PIN F6 E6 10 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Part 4: DDR3 DRAM The FPGA core board AC7A200 is equipped with two Micron 4Gbit (512MB) DDR3 chips (8Gbit in totally), model is MT41J256M16HA-125 (compatible with MT41K256M16HA-125). The DDR3 SDRAM has a maximum operating speed of 400MHz (data rate 800Mbps). The DDR3 memory system is directly connected to the memory interface of the BANK 34 and BANK35 of the FPGA. The specific configuration of DDR3 SDRAM is shown in Table 4-1. Bit Number U5,U6 Chip Model MT41J256M16HA-125 Capacity 256M x 16bit Factory Micron Table 4-1: DDR3 SDRAM Configuration The hardware design of DDR3 requires strict consideration of signal integrity. We have fully considered the matching resistor/terminal resistance, trace impedance control, and trace length control in circuit design and PCB design to ensure high-speed and stable operation of DDR3. Figure 4-1 details the hardware connection of DDR3 DRAM Figure 4-1: The DDR3 DRAM Schematic 11 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Figure 4-2: The DDR3 on the Core Board DDR3 DRAM pin assignment: Net Name FPGA PIN Name DDR3_DQS0_P IO_L3P_T0_DQS_AD5P_35 DDR3_DQS0_N DDR3_DQS1_P DDR3_DQS1_N DDR3_DQS2_P DDR3_DQS2_N DDR3_DQS3_P DDR3_DQS3_N DDR3_DQ[0] DDR3_DQ [1] DDR3_DQ [2] DDR3_DQ [3] DDR3_DQ [4] DDR3_DQ [5] DDR3_DQ [6] DDR3_DQ [7] DDR3_DQ [8] DDR3_DQ [9] DDR3_DQ [10] IO_L3N_T0_DQS_AD5N_35 IO_L9P_T1_DQS_AD7P_35 IO_L9N_T1_DQS_AD7N_35 IO_L15P_T2_DQS_35 IO_L15N_T2_DQS_35 IO_L21P_T3_DQS_35 IO_L21N_T3_DQS_35 IO_L2P_T0_AD12P_35 IO_L5P_T0_AD13P_35 IO_L1N_T0_AD4N_35 IO_L6P_T0_35 IO_L2N_T0_AD12N_35 IO_L5N_T0_AD13N_35 IO_L1P_T0_AD4P_35 IO_L4P_T0_35 IO_L11P_T1_SRCC_35 IO_L11N_T1_SRCC_35 IO_L8P_T1_AD14P_35 12 / 31 FPGA P/N E1 D1 K2 J2 M1 L1 P5 P4 C2 G1 A1 F3 B2 F1 B1 E2 H3 G3 H2 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual DDR3_DQ [11] IO_L10N_T1_AD15N_35 H5 DDR3_DQ [12] IO_L7N_T1_AD6N_35 J1 DDR3_DQ [13] IO_L10P_T1_AD15P_35 J5 DDR3_DQ [14] IO_L7P_T1_AD6P_35 K1 DDR3_DQ [15] IO_L12P_T1_MRCC_35 H4 DDR3_DQ [16] IO_L18N_T2_35 L4 DDR3_DQ [17] IO_L16P_T2_35 M3 DDR3_DQ [18] IO_L14P_T2_SRCC_35 L3 DDR3_DQ [19] IO_L17N_T2_35 J6 DDR3_DQ [20] IO_L14N_T2_SRCC_35 K3 DDR3_DQ [21] IO_L17P_T2_35 K6 DDR3_DQ [22] IO_L13N_T2_MRCC_35 J4 DDR3_DQ [23] IO_L18P_T2_35 L5 DDR3_DQ [24] IO_L20N_T3_35 P1 DDR3_DQ [25] IO_L19P_T3_35 N4 DDR3_DQ [26] IO_L20P_T3_35 R1 DDR3_DQ [27] IO_L22N_T3_35 N2 DDR3_DQ [28] IO_L23P_T3_35 M6 DDR3_DQ [29] IO_L24N_T3_35 N5 DDR3_DQ [30] IO_L24P_T3_35 P6 DDR3_DQ [31] IO_L22P_T3_35 P2 DDR3_DM0 IO_L4N_T0_35 D2 DDR3_DM1 IO_L8N_T1_AD14N_35 G2 DDR3_DM2 IO_L16N_T2_35 M2 DDR3_DM3 IO_L23N_T3_35 M5 DDR3_A[0] IO_L11N_T1_SRCC_34 AA4 DDR3_A[1] IO_L8N_T1_34 AB2 DDR3_A[2] IO_L10P_T1_34 AA5 DDR3_A[3] IO_L10N_T1_34 AB5 DDR3_A[4] IO_L7N_T1_34 AB1 DDR3_A[5] IO_L6P_T0_34 U3 DDR3_A[6] IO_L5P_T0_34 W1 DDR3_A[7] IO_L1P_T0_34 T1 DDR3_A[8] IO_L2N_T0_34 V2 DDR3_A[9] IO_L2P_T0_34 U2 DDR3_A[10] IO_L5N_T0_34 Y1 13 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual DDR3_A[11] IO_L4P_T0_34 W2 DDR3_A[12] IO_L4N_T0_34 Y2 DDR3_A[13] IO_L1N_T0_34 U1 DDR3_A[14] IO_L6N_T0_VREF_34 V3 DDR3_BA[0] IO_L9N_T1_DQS_34 AA3 DDR3_BA[1] IO_L9P_T1_DQS_34 Y3 DDR3_BA[2] IO_L11P_T1_SRCC_34 Y4 DDR3_S0 IO_L8P_T1_34 AB3 DDR3_RAS IO_L12P_T1_MRCC_34 V4 DDR3_CAS IO_L12N_T1_MRCC_34 W4 DDR3_WE IO_L7P_T1_34 AA1 DDR3_ODT IO_L14N_T2_SRCC_34 U5 DDR3_RESET IO_L15P_T2_DQS_34 W6 DDR3_CLK_P IO_L3P_T0_DQS_34 R3 DDR3_CLK_N IO_L3N_T0_DQS_34 R2 DDR3_CKE IO_L14P_T2_SRCC_34 T5 14 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Part 5: QSPI Flash The FPGA core board AC7A200 is equipped with one 128Mbit QSPI FLASH, and the model is N25Q128, which uses the 3.3V CMOS voltage standard. Due to the non-volatile nature of QSPI FLASH, it can be used as a boot device for the system to store the boot image of the system. These images mainly include FPGA bit files, ARM application code, soft core application code and other user data files. The specific models and related parameters of SPI FLASH are shown in Table 5-1. Position U8 Model N25Q128 Capacity 128M Bit Factory Numonyx Table 5-1: QSPI FLASH Specification QSPI FLASH is connected to the dedicated pins of BANK0 and BANK14 of the FPGA chip. The clock pin is connected to CCLK0 of BANK0, and other data and chip select signals are connected to D00~D03 and FCS pins of BANK14 respectively. Figure 5-1 shows the hardware connection of QSPI Flash. 15 / 31 Figure 5-1: QSPI Flash Schematic www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual QSPI Flash pin assignments: Net Name FPGA PIN Name QSPI_CLK CCLK_0 QSPI_CS QSPI_DQ0 IO_L6P_T0_FCS_B_14 IO_L1P_T0_D00_MOSI_14 QSPI_DQ1 QSPI_DQ2 IO_L1N_T0_D01_DIN_14 IO_L2P_T0_D02_14 QSPI_DQ3 IO_L2N_T0_D03_14 FPGA P/N L12 T19 P22 R22 P21 R21 Figure 5-2: QSPI FLASH on the Core Board 16 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Part 6: LED Light on Core Board There are 3 red LED lights on the AC7A200 FPGA core board, one of which is the power indicator light (PWR), one is the configuration LED light (DONE), and one is the user LED light. When the core board is powered, the power indicator will illuminate; when the FPGA is configured, the configuration LED will illuminate. The user LED light is connected to the IO of the BANK34, the user can control the light on and off by the program. When the IO voltage connected to the user LED is high, the user LED is illuminate. When the connection IO voltage is low, the user LED will be extinguished. The schematic diagram of the LED light hardware connection is shown in Figure 6-1: Figure 6-1: LED lights on the Core Board Schematic 17 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Figure 6-2: LED lights on the Core Board User LEDs Pin Assignment Signal Name LED1 FPGA Pin Name IO_L15N_T2_DQS_34 FPGA Pin Number W5 Description User LED 18 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Part 7: JTAG Interface The JTAG test socket J1 is reserved on the AC7A200 core board for JTAG download and debugging when the core board is used alone. Figure 7-1 is the schematic part of the JTAG port, which involves TMS, TDI, TDO, TCK. , GND, +3.3V these six signals. Figure 7-1: JTAG Interface Schematic The JTAG interface J1 on AC7A200 FPGA core board uses a 6-pin 2.54mm pitch single-row test hole. If you need to use the JTAG connector to debug on the core board, you need to solder a 6-pin single-row pin header. Figure 7-2 shows the JTAG interface J1 on the AC7A200 FPGA core board. Figure 7-2 JTAG Interface on Core Board 19 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Part 8: Power Interface on the Core Board In order to make the AC7A200 FPGA core board work alone, the core board is reserved 2-pin power supply interface J2. If the user wants to debug the function of the core board separately (without the carrier board), the external device needs to provide +5V to supply power to the core board. Figure 8-1Power Interface schematic on the Core Board Figure 8-2Power interface on the Core Board 20 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Part 9: Board to Board Connectors pin assignment The core board has a total of four high-speed board to board connectors. The core board uses four 80-pin inter-board connectors to connect to the carrier board. The IO port of the FPGA is connected to the four connectors by differential routing. The pin spacing of the connectors is 0.5mm, insert to the board to board connectors on the carrier board for high-speed data communication. Board to Board Connectors CON1 The 80-pin board to board connectors CON1, which are used to connect with the VCCIN power supply (+5V) and ground on the carrier board, extend the normal IOs of the FPGA. It should be noted here that 15 pins of CON1 are connected to the IO port of BANK34, because the BANK34 connection is connected to DDR3. Therefore, the voltage standard of all IOs of this BANK34 is 1.5V. Pin Assignment of Board to Board Connectors CON1 CON1 PIN Net Name FPGA PIN Voltage Level CON1 PIN Net Name PIN1 PIN3 PIN5 PIN7 PIN9 PIN11 PIN13 PIN15 PIN17 PIN19 PIN21 VCCIN VCCIN VCCIN VCCIN GND NC NC NC NC GND B13_L5_P - +5V PIN2 - +5V PIN4 - +5V PIN6 - +5V PIN8 - Ground PIN10 - NC PIN12 - NC PIN14 - NC PIN16 - NC PIN18 - Ground PIN20 Y13 3.3V PIN22 VCCIN VCCIN VCCIN VCCIN GND NC NC B13_L4_P B13_L4_N GND B13_L1_P FPGA PIN Voltage Level AA15 AB15 Y16 +5V +5V +5V +5V Ground NC NC 3.3V 3.3V Ground 3.3V 21 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual PIN23 PIN25 PIN27 PIN29 PIN31 PIN33 PIN35 PIN37 PIN39 PIN41 PIN43 PIN45 PIN47 PIN49 PIN51 PIN53 PIN55 PIN57 PIN59 PIN61 PIN63 PIN65 PIN67 PIN69 PIN71 PIN73 PIN75 PIN77 PIN79 B13_L5_N B13_L7_P B13_L7_P GND B13_L3_P B13_L3_N B34_L23_P B34_L23_N GND B34_L18_N B34_L18_P B34_L19_P B34_L19_N GND XADC_VN XADC_VP NC NC GND B16_L1_N B16_L1_P B16_L4_N B16_L4_P GND B16_L6_N B16_L6_P B16_L8_P B16_L8_N NC AA14 AB11 AB12 AA13 AB13 Y8 Y7 AA6 Y6 V7 W7 M9 L10 F14 F13 E14 E13 D15 D14 C13 B13 - 3.3V 3.3V 3.3V Ground 3.3V 3.3V 1.5V 1.5V Ground 1.5V 1.5V 1.5V 1.5V Ground Analog Analog NC NC Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V NC PIN24 PIN26 PIN28 PIN30 PIN32 PIN34 PIN36 PIN38 PIN40 PIN42 PIN44 PIN46 PIN48 PIN50 PIN52 PIN54 PIN56 PIN58 PIN60 PIN62 PIN64 PIN66 PIN68 PIN70 PIN72 PIN74 PIN76 PIN78 PIN80 B13_L1_N B13_L2_P B13_L2_N GND B13_L6_P B13_L6_N B34_L20_P B34_L20_N GND B34_L21_N B34_L21_P B34_L22_P B34_L22_N GND NC B34_L25 B34_L24_P B34_L24_N GND NC NC NC NC GND NC NC NC NC NC AA16 AB16 AB17 W14 Y14 AB7 AB6 V8 V9 AA8 AB8 - 3.3V 3.3V 3.3V Ground 3.3V 3.3V 1.5V 1.5V Ground 1.5V 1.5V 1.5V 1.5V Ground U7 1.5V W9 1.5V Y9 1.5V - Ground - NC - NC - NC - NC - Ground - NC - NC - NC - NC - NC 22 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Figure 9-1: Board to Board Connectors CON1 on the Core Board Board to Board Connectors CON2 The 80-pin female connection header CON2 is used to extend the normal IO of the BANK13 and BANK14 of the FPGA. The voltage standards of both BANKs are 3.3V. Pin Assignment of Board to Board Connectors CON2 CON2 PIN Net Name FPGA PIN Voltage Level CON2 PIN Net Name FPGA PIN Voltage Level PIN1 PIN3 PIN5 PIN7 PIN9 PIN11 PIN13 PIN15 PIN17 PIN19 PIN21 PIN23 PIN25 PIN27 PIN29 PIN31 B13_L16_P B13_L16_N B13_L15_P B13_L15_N GND B13_L13_P B13_L13_N B13_L12_P B13_L12_N GND B13_L11_P B13_L11_N B13_L10_P B13_L10_N GND B13_L9_N W15 W16 T14 T15 V13 V14 W11 W12 Y11 Y12 V10 W10 AA11 3.3V PIN2 3.3V PIN4 3.3V PIN6 3.3V PIN8 Ground PIN10 3.3V PIN12 3.3V PIN14 3.3V PIN16 3.3V PIN18 Ground PIN20 3.3V PIN22 3.3V PIN24 3.3V PIN26 3.3V PIN28 Ground PIN30 3.3V PIN32 B14_L16_P B14_L16_N B13_L14_P B13_L14_N GND B14_L10_P B14_L10_N B14_L8_N B14_L8_P GND B14_L15_N B14_L15_P B14_L17_P B14_L17_N GND B14_L6_N V17 W17 U15 V15 AB21 AB22 AA21 AA20 AB20 AA19 AA18 AB18 T20 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 23 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual PIN33 PIN35 PIN37 PIN39 PIN41 PIN43 PIN45 PIN47 PIN49 PIN51 PIN53 PIN55 PIN57 PIN59 PIN61 PIN63 PIN65 PIN67 PIN69 PIN71 PIN73 PIN75 PIN77 PIN79 B13_L9_P B13_L8_N B13_L8_P GND B14_L11_N B14_L11_P B14_L14_N B14_L14_P GND B14_L5_N B14_L5_P B14_L18_N B14_L18_P GND B13_L17_P B13_L17_N B14_L21_N B14_L21_P GND B14_L22_P B14_L22_N B14_L24_N B14_L24_P B14_IO0 AA10 AB10 AA9 V20 U20 V19 V18 R19 P19 U18 U17 T16 U16 P17 N17 P15 R16 R17 P16 P20 3.3V PIN34 3.3V PIN36 3.3V PIN38 Ground PIN40 3.3V PIN42 3.3V PIN44 3.3V PIN46 3.3V PIN48 Ground PIN50 3.3V PIN52 3.3V PIN54 3.3V PIN56 3.3V PIN58 Ground PIN60 3.3V PIN62 3.3V PIN64 3.3V PIN66 3.3V PIN68 Ground 3.3V 3.3V 3.3V 3.3V PIN70 PIN72 PIN74 PIN76 PIN78 3.3V PIN80 B13_IO0 B14_L7_N B14_L7_P GND B14_L4_P B14_L4_N B14_L9_P B14_L9_N GND B14_L12_N B14_L12_P B14_L13_N B14_L13_P GND B14_L3_N B14_L3_P B14_L20_N B14_L20_P GND B14_L19_N B14_L19_P B14_L23_P B14_L23_N B14_IO25 Y17 W22 W21 T21 U21 Y21 Y22 W20 W19 Y19 Y18 V22 U22 T18 R18 R14 P14 N13 N14 N15 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V 3.3V Figure 9-2: Board to Board Connectors CON2 on the Core Board 24 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Board to Board Connectors CON3 The 80-pin connector CON3 is used to extend the normal IO of the BANK15 and BANK16 of the FPGA. In addition, four JTAG signals are also connected to the carrier board via the CON3 connector. The voltage standards of BANK15 and BANK16 can be adjusted by an LDO chip. The default installed LDO is 3.3V. If you want to output other standard levels, you can replace it with a suitable LDO. Pin Assignment of Board to Board Connectors CON3 CON3 PIN Net Name FPGA PIN Voltage Level CON3 PIN Net Name FPGA Voltage PIN Level PIN1 PIN3 PIN5 PIN7 PIN9 PIN11 PIN13 PIN15 PIN17 PIN19 PIN21 PIN23 PIN25 PIN27 PIN29 PIN31 PIN33 PIN35 PIN37 PIN39 PIN41 B15_IO0 B16_IO0 B15_L4_P B15_L4_N GND B15_L2_P B15_L2_N B15_L12_P B15_L12_N GND B15_L11_P B15_L11_N B15_L1_N B15_L1_P GND B15_L5_P B15_L5_N B15_L3_N B15_L3_P GND B15_L19_P J16 F15 G17 G18 G15 G16 J19 H19 J20 J21 G13 H13 J15 H15 H14 J14 K13 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V PIN2 PIN4 PIN6 PIN8 PIN10 PIN12 PIN14 PIN16 PIN18 PIN20 PIN22 PIN24 PIN26 PIN28 PIN30 PIN32 PIN34 PIN36 PIN38 PIN40 PIN42 B15_IO25 B16_IO25 B16_L21_N B16_L21_P GND B16_L23_P B16_L23_N B16_L22_P B16_L22_N GND B16_L24_P B16_L24_N B15_L8_N B15_L8_P GND B15_L7_N B15_L7_P B15_L9_P B15_L9_N GND B15_L15_N M17 F21 A21 B21 E21 D21 E22 D22 G21 G22 G20 H20 H22 J22 K21 K22 M22 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 25 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual PIN43 PIN45 PIN47 PIN49 PIN51 PIN53 PIN55 PIN57 PIN59 PIN61 PIN63 PIN65 PIN67 PIN69 PIN71 PIN73 PIN75 PIN77 PIN79 B15_L19_N B15_L20_P B15_L20_N GND B15_L14_P B15_L14_N B15_L21_P B15_L21_N GND B15_L23_P B15_L23_N B15_L22_P B15_L22_N GND B15_L24_P B15_L24_N NC FPGA_TCK FPGA_TDO K14 M13 L13 L19 L20 K17 J17 L16 K16 L14 L15 M15 M16 V12 U13 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V PIN44 PIN46 PIN48 PIN50 PIN52 PIN54 PIN56 PIN58 PIN60 PIN62 PIN64 PIN66 PIN68 PIN70 PIN72 PIN74 PIN76 PIN78 PIN80 B15_L15_P B15_L6_N B15_L6_P GND B15_L13_N B15_L13_P B15_L10_P B15_L10_N GND B15_L18_P B15_L18_N B15_L17_N B15_L17_P GND B15_L16_P B15_L16_N NC FPGA_TDI FPGA_TMS N22 H18 H17 K19 K18 M21 L21 N20 M20 N19 N18 M18 L18 R13 T13 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Figure 9-3: Board to Board Connectors CON3 on the Core Board Board to Board Connectors CON4 The 80-Pin connector CON4 is used to extend the normal IO and GTP high-speed data and clock signals of the FPGA BANK16. The voltage standard 26 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual of the IO port of BANK16 can be adjusted by an LDO chip. The default installed LDO is 3.3V. If the user wants to output other standard levels, it can be replaced by a suitable LDO. The high-speed data and clock signals of the GTP are strictly differential routed on the core board. The data lines are equal in length and kept at a certain interval to prevent signal interference. Pin Assignment of Board to Board Connectors CON4 CON4 PIN Net Name FPGA PIN Voltage Level CON4 PIN Net Name PIN1 NC - PIN3 NC - PIN5 NC - PIN7 NC - PIN9 GND - PIN11 NC - PIN13 NC - PIN15 GND - PIN17 MGT_TX3_P D7 PIN19 MGT_TX3_N C7 PIN21 GND - PIN23 MGT_RX3_P D9 PIN25 MGT_RX3_N C9 PIN27 GND - PIN29 MGT_TX1_P D5 PIN31 MGT_TX1_N C5 PIN33 GND - PIN35 MGT_RX1_P D11 PIN37 MGT_RX1_N C11 PIN39 GND - PIN41 B16_L5_P E16 PIN43 B16_L5_N D16 PIN45 B16_L7_P B15 PIN47 B16_L7_N B16 Ground Ground Diff Diff Ground Diff Diff Ground Diff Diff Ground Diff Diff Ground 3.3V 3.3V 3.3V 3.3V PIN2 PIN4 PIN6 PIN8 PIN10 PIN12 PIN14 PIN16 PIN18 PIN20 PIN22 PIN24 PIN26 PIN28 PIN30 PIN32 PIN34 PIN36 PIN38 PIN40 PIN42 PIN44 PIN46 PIN48 GND MGT_TX2_P MGT_TX2_N GND MGT_RX2_P MGT_RX2_N GND MGT_TX0_P MGT_TX0_N GND MGT_RX0_P MGT_RX0_N GND MGT_CLK1_P MGT_CLK1_N GND B16_L2_P B16_L2_N B16_L3_P B16_L3_N FPGA PIN B6 A6 B10 A10 B4 A4 B8 A8 F10 E10 F16 E17 C14 C15 Voltage Level Ground Diff Diff Ground Diff Diff Ground Diff Diff Ground Diff Diff Ground Diff Diff Ground 3.3V 3.3V 3.3V 3.3V 27 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual PIN49 PIN51 PIN53 PIN55 PIN57 PIN59 PIN61 PIN63 PIN65 PIN67 PIN69 PIN71 PIN73 PIN75 PIN77 PIN79 GND B16_L9_P B16_L9_N B16_L11_P B16_L11_N GND B16_L13_P B16_L13_N B16_L15_P B16_L15_N GND B16_L17_P B16_L17_N B16_L19_P B16_L19_N NC A15 A16 B17 B18 C18 C19 F18 E18 A18 A19 D20 C20 - Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V Ground 3.3V 3.3V 3.3V 3.3V PIN50 PIN52 PIN54 PIN56 PIN58 PIN60 PIN62 PIN64 PIN66 PIN68 PIN70 PIN72 PIN74 PIN76 PIN78 PIN80 GND B16_L10_P B16_L10_N B16_L12_P B16_L12_N GND B16_L14_P B16_L14_N B16_L16_P B16_L16_N GND B16_L18_P B16_L18_N B16_L20_P B16_L20_N NC - Ground A13 3.3V A14 3.3V D17 3.3V C17 3.3V - Ground E19 3.3V D19 3.3V B20 3.3V A20 3.3V - Ground F19 3.3V F20 3.3V C22 3.3V B22 3.3V - Figure 9-4: Board to Board Connectors CON4 on the Core Board 28 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Part 10: Power Supply The AC7A200 FPGA core board is powered by DC5V via carrier board, and it is powered by the Mini USB interface when it is used alone. Please be careful not to supply power by the Mini USB and the carrier board at the same time to avoid damage. The power supply design diagram on the board is shown in Figure 10-1. Figure 10-1Power Supply on core board schematic The core board is powered by +5V and converted to +3.3V, +1.5V, +1.8V, +1.0V four-way power supply through three DC/DC power supply chip TLV62130RGT. The current of +1.0V can be up to 6A, and the other three output currents can be up to 3A. The VCCIO is generated by one LDOSPX3819M5-3-3. VCCIO mainly supplies power to BANK15 and BANK16 of FPGA. Users can change the IO of BANK15,16 to different voltage standards by replacing their LDO chip. The 1.5V generates the VTT and VREF voltages required by DDR3 via TI's TPS51200. The 1.8V power supply of MGTAVTT and MGTAVCC for the GTP transceiver is generated by TI's TPS74801 chip. The functions of each power distribution are shown in the 29 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual following table: Power Supply Function +1.0V FPGA Core Voltage +1.8V FPGA auxiliary voltage, TPS74801 power supply +3.3V VCCIO of Bank0,Bank13 and Bank14 of FPGA,QSIP FLASH, Clock Crystal +1.5V DDR3, Bank34 and Bank35 of FPGA VREF,VTT(+0.75V) DDR3 CCIP(+3.3V) FPGA Bank15, Bank16 MGTAVTT(+1.2V) GTP Transceiver Bank216 of FPGA MGTVCC(+1.0V) GTP Transceiver Bank216 of FPGA Because the power supply of Artix-7 FPGA has the power-on sequence requirement, in the circuit design, we have designed according to the power requirements of the chip, and the power-on is 1.0V->1.8V->(1.5 V, 3.3V, VCCIO) and 1.0V-> MGTAVCC -> MGTAVTT, the circuit design to ensure the normal operation of the chip. The power circuit on the AC7A200 FPGA core board is shown in Figure 10-2: Figure 10-2: Power Supply on the AC7A200 FPGA Core Board 30 / 31 www.alinx.com ARTIX-7 FPGA Development Board AC7A200 User Manual Part 11: Size Dimension Figure 11-1: AC7A200 FPGA Core board (Top View) Figure 11-2: AC7A200 FPGA Core board (Bottom View) 31 / 31 www.alinx.com