User Guide for THine models including: THCS Series I2C GPIOHigh Speed Bus Signal Transceiver, THCS Series I2C, GPIOHigh Speed Bus Signal Transceiver, Speed Bus Signal Transceiver, Signal Transceiver, Transceiver
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DocumentDocumentTHCS253_Design_Guideline_Rev.1.00_E
THCS253
I2C/GPIO High Speed Bus Signal Transceiver System Design Guidelines
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Contents
Contents.................................................................................................................................................................. 2 Example 1. I/O extension, Up/Down Stream synchronous mode ...................................................................... 3 Example 2. I/O & I2C extension, Up/Down Stream asynchronous mode ........................................................ 5 Example 3. I/O expansion with I2C ..................................................................................................................... 7 Design Guidelines for Power Supply ................................................................................................................... 9 Design Guideline for High-Speed Signal ........................................................................................................... 10 Notices and Requests........................................................................................................................................... 11
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Example 1. I/O extension, Up/Down Stream synchronous mode
The primary chip performs parallel/serial conversion of input data using either the clock signal input to the REFIN pin or the built-in oscillator clock signal, whichever is selected, and outputs it from the TXP/N pin as a clock embedded serial signal. Secondary chip set to synchronous mode (SYNCEN pin = High) operate with clock signals regenerated from clock-embedded serial signals input to both the serial/parallel conversion circuit and the parallel/serial conversion circuit on the RXP/N pin. The Up/Down Stream will therefore have the same transmission bit rate.
Example 1 is an example of transmitting 16-bit GPIO data sampled asynchronously by the 20 MHz built-in oscillator clock on the Primary chip to the Secondary chip, and transmitting 16-bit GPIO data sampled asynchronously by the 20 MHz clock regenerated on the Secondary chip set to synchronous mode. This is an example of transmitting 16-bit GPIO data sampled asynchronously by a 20 MHz clock regenerated by the Secondary chip set to synchronous mode to the Primary chip.
When I2C is not used, all THCS253 settings are made at the setting terminals.
LVCMOS Driver
THCS253 Primary chip
16bit
D0/D31/SDA1
D15/D16 REFIN
THCS253 Secondary chip
D31/D0
D16/D15 REFOUT
16bit
*2-2 VDDx
VDDx
LVCMOS Receiver
LVCMOS Receiver
VDD1 0
RESETN
NC
16bit
REFOUT D16/D15 D31/D0
VDD1
10k
INTN
READY
TP
0.1uF TXN
TXP
RESETN RESETN
0.1uF RXN
RXP
*2-1OE VDD1
OE
PSSEL REFEN RF_IN/OSCSEL0 RF_OUT/OSCSEL1
VDD1 *1
VDD
0.1uF
SYNCEN DATA_WIDTH SSEN ENI2C0 IDSEL0 IDSEL1
CAPOUT CAPINA CAPINP
10uF 0.1uF 0.1uF
CTSEL_I2C/FILTSEL1
SCL0/FILTSEL0
SDA0/OBUF
TEST1
TEST2
VDD2
10k
INTN
TP
READY
Cable Cable
*3 Cable Cable
0.1uF RXN RXP
0.1uF TXN TXP
REFIN D15/D16
D1/D30/SCL1
16bit
RESETN RESETN
*2-2 OE
PSSEL
*1 VDD2
0.1uF
VDD
REFEN RF_IN/OSCSEL0 RF_OUT/OSCSEL1
10uF 0.1uF 0.1uF
CAPOUT CAPINA CAPINP
SYNCEN DATA_WIDTH
SSEN ENI2C0 IDSEL0 IDSEL1
CTSEL_I2C/FILTSEL1
SCL0/FILTSEL0 *2-2 SDA0/OBUF
TEST1
TEST2
VDD2
LVCMOS Driver
VDD2 0
RESETN
NC
Power supply*1 The Primary chip (VDD1) and Secondary chip (VDD2) can be used with different supply voltages.
Data output control in start-up sequences If I2C is not used, there are two options. - Output enable control by OE pin*2-1
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- Set to open drain output and pull-up with receive side power supply*2-2
Disposal of unused terminals Unused inputs should be fixed Low and outputs should be open.
Cable for connection between Primary chip and Secondary chip*3 Use twisted pair cables with a differential impedance of 100 . Impedance error should be within ±10%, but
this is not a limitation if the signal waveform observed near the RXP/RXN terminals meets the Eye opening described in the datasheet.
When unshielded twisted pair cables are bundled with other signal lines or power lines, data errors may occur due to crosstalk between the lines, resulting in malfunctions. Twisted pair cables must be shielded for each pair.
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Example 2. I/O & I2C extension, Up/Down Stream asynchronous mode
The primary chip and secondary chip perform parallel/serial conversion with the REFIN pin input clock signal or the internal oscillator clock signal selected by each chip, and output from the TXP/N pin as clock embedded serial signals. Therefore, the bit rate of the Up/Down stream signal is based on the clock signal frequency selected for each chip.
Example 2 shows an example of transmitting I2C data in addition to GPIO data sampled at the falling edge of the clock signal input to each REFIN pin.
When using I2C, some settings (input/output direction, output buffer type, and digital filter settings) are set in registers.
LVCMOS Driver
THCS253 Primary chip
16bit
D0/D31/SDA1
D15/D16 REFIN
THCS253 Secondary chip
D31/D0
D16/D15 REFOUT
16bit
LVCMOS Receiver
LVCMOS Receiver 8bit
Sensor data
VDD1 0
RESETN
NC
*4 RESETN VDD1
VDDx
10k
I2C Controller
REFOUT D16/D15 D23/D8 D24/D7 D30/D1 D31/D0*3
RESETN OE*2
VDD1 10k
INTN
READY
TP
0.1uF TXN
TXP
0.1uF RXN
RXP
PSSEL REFEN RF_IN/OSCSEL0 RF_OUT/OSCSEL1
VDD1 *1
VDD
0.1uF
SYNCEN DATA_WIDTH SSEN ENI2C0 IDSEL0
ID:34h IDSEL1
CAPOUT CAPINA CAPINP
10uF 0.1uF 0.1uF
CTSEL_I2C/FILTSEL1
SCL0/FILTSEL0
SDA0/OBUF
TEST1
TEST2
Cable Cable
*5
Cable Cable
VDD2
10k
INTN
TP
READY
0.1uF RXN
RXP
REFIN D15/D16
D8/D23 D7/D24 D1/D30/SCL1
0.1uF TXN
TXP
*3 D0/D31/SDA1 RESETN
*2 OE
PSSEL
*1 VDD2
0.1uF
VDD
REFEN RF_IN/OSCSEL0 RF_OUT/OSCSEL1
10uF 0.1uF 0.1uF
CAPOUT CAPINA CAPINP
SYNCEN DATA_WIDTH
SSEN ENI2C0 IDSEL0 IDSEL1
CTSEL_I2C/FILTSEL1
SCL0/FILTSEL0
SDA0/OBUF
TEST1
TEST2
8bit *4
RESETN VDD2
LVCMOS Driver
5V*3 Sensor
VDD2 0
RESETN
NC
VDDx
10k
I2C Target
Power supply*1 The Primary chip (VDD1) and Secondary chip (VDD2) can be used with different supply voltages.
Data output control in start-up sequences*2 By fixing the OE pin to Low, all GPIO pins are disabled (Hi-Z) in the initial state immediately after power-
on, avoiding unnecessary voltage application to the connected devices. From this state, set the input/output polarity and output buffer type of each GPIO pin using the GPIO_OEN and GPIO_OBUF registers, and then set the OVERRIDE_OE register to "1" to enable GPIO, overriding the register setting over the OE pin setting.
Step 1All outputs disabled by OE pin = Low Hi-Z
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Step 2GPIO_OENGPIO_OBUF, Set GPIO_I_FILTEN register as needed Step 3OVERRIDE_OE register is set to "1"
5V Tolerant I/OVoltage Level Conversion*3 There are up to four-5V input and output pins each. In the above example, a signal output from a 5V driven
sensor is input to the 5V input terminal on the secondary chip side and output from the primary chip side at VDD1 voltage for 5V to VDD1 level conversion.
To use the 5V tolerant output pin as a 5V signal output, set the corresponding pin as an open drain and pull up to 5V externally.
Disposal of unused terminals*4 Unused inputs should be fixed Low and outputs should be open.
Cable for connection between Primary chip and Secondary chip*5 Use twisted pair cables with a differential impedance of 100 . Impedance error should be within ±10%, but
this is not a limitation if the signal waveform observed near the RXP/RXN terminals meets the Eye opening described in the datasheet.
When unshielded twisted pair cables are bundled with other signal lines or power lines, data errors may occur due to crosstalk between the lines, resulting in malfunctions. Twisted pair cables must be shielded for each pair.
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Example 3. I/O expansion with I2C
This mode uses I2C to control the state of each GPIO pin individually.
LVCMOS Driver / Receiver
THCS253 Primary chip
D0/D31/SDA1
D15/D16 REFIN
REFOUT D16/D15
VDD1 10k
INTN
READY
TP
D31/D0
0.1uF TXN
TXP
VDD1
0
RESETN
NC
RESETN VDD1
VDDx
10k
I2C Controller
RESETN OE*2
0.1uF RXN
RXP
PSSEL REFEN RF_IN/OSCSEL0 RF_OUT/OSCSEL1
VDD1 *1
VDD
0.1uF
SYNCEN DATA_WIDTH SSEN ENI2C0 IDSEL0
ID:34h IDSEL1
CAPOUT CAPINA CAPINP
10uF 0.1uF 0.1uF
CTSEL_I2C/FILTSEL1
SCL0/FILTSEL0
SDA0/OBUF
TEST1
TEST2
THCS253 Secondary chip
D31/D0
16bit
LVCMOS Receiver
Cable Cable
*5 Cable Cable
D16/D15 REFOUT
VDD2
10k
INTN
TP
READY
0.1uF RXN
RXP
REFIN D15/D16
D8/D23 D7/D24 D2/D29
D1/D30/SCL1 *3
D0/D31/SDA1
0.1uF TXN
TXP
RESETN *2 OE
PSSEL
*1 VDD2
0.1uF
VDD
REFEN RF_IN/OSCSEL0 RF_OUT/OSCSEL1
10uF 0.1uF 0.1uF
CAPOUT CAPINA CAPINP
SYNCEN DATA_WIDTH
SSEN ENI2C0 IDSEL0 IDSEL1
CTSEL_I2C/FILTSEL1
SCL0/FILTSEL0
SDA0/OBUF
TEST1
TEST2
8bit *4
LVCMOS Driver
5V*3 Sensor
RESETN VDD2
VDD2 0
RESETN
NC
VDDx
10k
I2C Target
Power supply*1 The Primary chip (VDD1) and Secondary chip (VDD2) can be used with different supply voltages.
Data output control in start-up sequences*2 By fixing the OE pin to Low, all GPIO pins are disabled (Hi-Z) in the initial state immediately after power-
on, avoiding unnecessary voltage application to the connected devices. From this state, set the input/output polarity and output buffer type of each GPIO pin using the GPIO_OEN and GPIO_OBUF registers, and then set the OVERRIDE_OE register to "1" to enable GPIO, overriding the register setting over the OE pin setting.
Step 1All outputs disabled by OE pin = Low Hi-Z Step 2I2C_EXPAND register is set to "1" Step 3GPIO_OENGPIO_OBUF, Set GPIO_I_FILTEN register as needed Step 4OVERRIDE_OE register is set to "1"
5V Tolerant I/OVoltage Level Conversion*3 There are up to four-5V input and output pins each. In the above example, a signal output from a 5V driven
sensor is input to the 5V input terminal on the secondary chip side and output from the primary chip side at
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VDD1 voltage for 5V to VDD1 level conversion. To use the 5V tolerant output pin as a 5V signal output, set the corresponding pin as an open drain and pull
up to 5V externally.
Disposal of unused terminals*4 Unused inputs should be fixed Low and outputs should be open.
Cable for connection between Primary chip and Secondary chip*5 Use twisted pair cables with a differential impedance of 100 . Impedance error should be within ±10%, but
this is not a limitation if the signal waveform observed near the RXP/RXN terminals meets the Eye opening described in the datasheet.
When unshielded twisted pair cables are bundled with other signal lines or power lines, data errors may occur due to crosstalk between the lines, resulting in malfunctions. Twisted pair cables must be shielded for each pair.
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Design Guidelines for Power Supply
Insert filters (Ferrite Beads and Capacitors) in the Power Supply (VDD and AVDD). And insert Bypass Capacitor (0.1uF) in the Power Supply pins. This device is equipped with a 1.2V built-in regulator. Insert Bypass Capacitors (CAPOUT: 10uF and CAPINA/CAPINP: 0.1uF) also for this regulator. Bypass Capacitors should be attached just near the device. Insert the GND-Via to the Exposed-Pad to strengthen.
Power Supply
Ferrite Beads
Ferrite Beads
0.1uF
0.1uF 10uF 0.1uF 0.1uF
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD
49
32
50
31
51
30
52 AVDD
29
53 CAPOUT
28
54
27
55
26
56 CAPINA 57
Exposed-Pad
VDD 25 24
58
23
59 CAPINP
22
60
21
61
20
62
19
63
18
VDD
64
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0.1uF
0.1uF
Top Layer
0.1uF
AVDD CAPOUT
CAPINA
Grand Via
CAPINP
ExposedPad
VDD
0.1uF
Bottom Layer
10uF
0.1uF VDD
CAPOUT CAPINA CAPINP
0.1uF 0.1uF
VDD
0.1uF
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Design Guideline for High-Speed Signal
TXP/TXN and RXP/RXN are differential pairs of high-speed serial signals. Differential pairs should be closely spaced and coupled to eliminate common mode noise. Also, differential should be designed as 100 differential characteristic impedance (Zdiff).
The following is an example of microstrip line design. The high-speed signal lines trace in only single layer. The AC coupled capacitors should be attached just near the device.
Connector
AC Couple capacitor
0.1uF 0.1uF
0.1uF 0.1uF
48 47 46 45 44 43 42 49 50 51 52 53 54 RXP 55 RXN 56 57 TXN 58 TXP 59 60 61 62 63 64
1234567
Connector
Top Layer
AC Couple Capacitor
RXN/RXP TXP/TXN
Connector
Differential signal traces (Microstrip Lines) > 3 x S1 S1 > 3 x S1
Layer1: Signals
GND
GND
Layer2: Ground
Layer3: Power
Layer4: Signals
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Notices and Requests
1. The product specifications described in this material are subject to change without prior notice.
2. The circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. THine Electronics, Inc. ("THine") is not responsible for possible errors and omissions in this material. Please note even if errors or omissions should be found in this material, THine may not be able to correct them immediately.
3. This material contains THine's copyright, know-how or other proprietary. Copying or disclosing to third parties the contents of this material without THine's prior permission is prohibited.
4. Note that even if infringement of any third party's industrial ownership should occur by using this product, THine will be exempted from the responsibility unless it directly relates to the production process or functions of the product.
5. Product Application
5.1 Application of this product is intended for and limited to the following applications: audio-video device, office automation device, communication device, consumer electronics, smartphone, feature phone, and amusement machine device. This product must not be used for applications that require extremely highreliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device.
5.2 This product is not intended to be used as an automotive part, unless the product is specified as a product conforming to the demands and specifications of IATF16949 ("the Specified Product") in this data sheet. THine accepts no liability whatsoever for any product other than the Specified Product for it not conforming to the aforementioned demands and specifications. 5.3 THine accepts liability for demands and specifications of the Specified Product only to the extent that the user and THine have been previously and explicitly agreed to each other.
6. Despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conductor product. Therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage.
7. Please note that this product is not designed to be radiation-proof.
8. Testing and other quality control techniques are used to this product to the extent THine deems necessary to support warranty for performance of this product. Except where mandated by applicable law or deemed necessary by THine based on the user's request, testing of all functions and performance of the product is not necessarily performed.
9. Customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the Foreign Exchange and Foreign Trade Act.
10. The product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the product are shorted by such as foreign substance. The damages may cause a smoking and ignition. Therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses.
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