ESP32-C3 Family Datasheet

Product Overview

The ESP32-C3 family is an ultra-low-power and highly-integrated MCU-based SoC solution that supports 2.4 GHz Wi-Fi and Bluetooth® Low Energy (Bluetooth LE). It offers:

• A complete Wi-Fi subsystem compliant with IEEE 802.11b/g/n protocol, supporting Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode.
• A Bluetooth LE subsystem supporting features of Bluetooth 5 and Bluetooth mesh.
• State-of-the-art power and RF performance.
• A 32-bit RISC-V single-core processor with a four-stage pipeline operating at up to 160 MHz.
• 400 KB of SRAM (16 KB for cache) and 384 KB of ROM on the chip.
• SPI, Dual SPI, Quad SPI, and QPI interfaces for connection to external flash.
• Reliable security features including cryptographic hardware accelerators (AES-128/256, Hash, RSA, HMAC, digital signature, secure boot), a random number generator, permission control for memory access, and external memory encryption/decryption.
• A rich set of peripheral interfaces and GPIOs suitable for various scenarios and complex applications.

Features

Wi-Fi

• IEEE 802.11 b/g/n-compliant.
• Supports 20 MHz, 40 MHz bandwidth in the 2.4 GHz band.
• 1T1R mode with data rate up to 150 Mbps.
• Wi-Fi Multimedia (WMM).
• TX/RX A-MPDU, TX/RX A-MSDU.
• Immediate Block ACK.
• Fragmentation and defragmentation.
• Transmit opportunity (TXOP).
• Automatic Beacon monitoring (hardware TSF).
• 4 x virtual Wi-Fi interfaces.
• Simultaneous support for Infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode. (Note: SoftAP channel changes with Station channel when scanning).
• Antenna diversity.
• 802.11mc FTM.

Bluetooth

• Bluetooth LE: Bluetooth 5, Bluetooth mesh.
• Speed: 125 Kbps, 500 Kbps, 1 Mbps, 2 Mbps.
• Advertising extensions.
• Multiple advertisement sets.
• Channel selection algorithm #2.

CPU and Memory

• 32-bit RISC-V single-core processor, up to 160 MHz.
• 384 KB ROM.
• 400 KB SRAM (16 KB for cache).
• 8 KB SRAM in RTC.
• Embedded flash (details in Chapter 1: Family Member Comparison).

External Flash Interface

• SPI, Dual SPI, Quad SPI, and QPI interfaces for connection to multiple external flash.

Advanced Peripheral Interfaces

• 22 x programmable GPIOs.
• 2 x 12-bit SAR ADCs, up to 6 channels.
• 1 x temperature sensor.
• 3 x SPI.
• 2 x UART.
• 1 x I2C.
• 1 x I2S.
• Remote control peripheral, with 2 transmit channels and 2 receive channels.
• LED PWM controller, up to 6 channels.
• Full-speed USB Serial/JTAG controller.
• General DMA controller, with 3 transmit channels and 3 receive channels.
• 1 x TWAI® controller (compatible with ISO 11898-1).

Low Power Management

• Power Management Unit with five power modes.

Security

• Secure boot.
• Flash encryption.
• 4096-bit OTP, up to 1792 bits for users.
• Cryptographic hardware acceleration: AES-128/256 (FIPS PUB 197), SHA Accelerator (FIPS PUB 180-4), RSA Accelerator, Random Number Generator (RNG), HMAC, Digital signature.
• Permission Control.

Applications (A Non-exhaustive List)

With ultra-low power consumption, the ESP32-C3 family is an ideal choice for IoT devices in the following areas:

• Smart Home: Light control, Smart button, Smart plug, Indoor positioning.
• Industrial Automation: Industrial robot, Mesh network, Human machine interface (HMI), Industrial field bus.
• Health Care: Health monitor, Baby monitor.
• Consumer Electronics: Smart watch and bracelet, Over-the-top (OTT) devices.
• Connectivity Devices: Wi-Fi and Bluetooth speaker, Logger toys and proximity sensing toys.
• Smart Agriculture: Smart greenhouse, Smart irrigation, Agriculture robot.
• Retail and Catering: POS machines, Service robot.
• Audio Device: Internet music players, Live streaming devices, Internet radio players.
• IoT Infrastructure: Generic Low-power IoT Sensor Hubs, Generic Low-power IoT Data Loggers.

1 Family Member Comparison

1.1 Family Nomenclature

1.2 Comparison

2 Pin Definition

2.1 Pin Layout

2.2 Pin Description

Notes:

• PA: analog power supply; PD: power supply for RTC IO; I: input; O: output; T: high impedance.
• Ports of embedded flash correspond to pins of ESP32-C3FN4 and ESP32-C3FH4: CS# = SPICS0, IO0/DI = SPID, IO1/DO = SPIQ, CLK = SPICLK, IO2/WP# = SPIWP, IO3/HOLD# = SPIHD. These pins are not recommended for other uses.
• For data port connection between ESP32-C3 family and external flash, refer to Section 3.4.2 Serial Peripheral Interface (SPI).
• Pin function refers to fixed settings and does not cover all GPIO matrix cases. Refer to ESP32-C3 Technical Reference Manual for GPIO matrix details.

2.3 Power Scheme

Digital pins are divided into four power domains: VDD3P3_CPU, VDD_SPI, VDD3P3_RTC. VDD3P3_CPU is the input power supply for the CPU. VDD_SPI can be an input or output power supply. VDD3P3_RTC is the input power supply for the RTC analog domain and CPU.

When VDD_SPI acts as an output, it can be powered by VDD3P3_CPU. VDD_SPI can be powered off via software to minimize current leakage in Deep-sleep mode.

2.4 Strapping Pins

The ESP32-C3 family has three strapping pins: GPIO2, GPIO8, GPIO9, and GPIO10. Their values are sampled during system reset to determine boot mode and other configurations. These pins function as normal pins after reset.

Types of system reset include: power-on-reset, RTC watchdog reset, brownout reset, analog super watchdog reset, and crystal clock glitch detection reset.

GPIO9 has internal pull-up resistors by default. If unconnected, internal pull-up/pull-down determines its input level.

The strapping combination of GPIO8 = 0 and GPIO9 = 0 is invalid and will trigger unexpected behavior.

3 Functional Description

3.1 CPU and Memory

3.1.1 CPU

The ESP32-C3 family features a low-power 32-bit RISC-V single-core microprocessor with a four-stage pipeline, supporting clock frequencies up to 160 MHz. It includes RV32IMC ISA, 32-bit multiplier/divider, up to 32 vectored interrupts, 8 hardware breakpoints/watchpoints, up to 16 PMP regions, and JTAG for debugging.

3.1.2 Internal Memory

Internal memory includes:

• 384 KB of ROM for booting and core functions.
• 400 KB of on-chip SRAM for data and instructions (16 KB configured for cache).
• 8 KB of RTC memory (SRAM) accessible by the main CPU, retaining data in Deep-sleep mode.
• 4 Kbit of eFuse (1792 bits reserved for user data, encryption keys, and device ID).
• Embedded flash (details in Chapter 1: Family Member Comparison).

3.1.3 External Flash

The ESP32-C3 family supports SPI, Dual SPI, Quad SPI, and QPI interfaces for connecting to external flash memory up to 16 MB. It features hardware encryption/decryption based on XTS-AES. High-speed caches support up to 8 MB of instruction memory space and 8 MB of data memory space, mappable from flash in 64 KB blocks with 8/16/32-bit reads.

After initialization, software can customize external flash mapping into the CPU address space.

3.1.4 Address Mapping Structure

3.1.5 Cache

The ESP32-C3 has an eight-way set associative, read-only cache with the following features: size of 16 KB, block size of 32 bytes, pre-load function, lock function, and critical word first and early restart.

3.2 System Clocks

3.2.1 CPU Clock

The CPU clock sources are: external main crystal clock, internal 20 MHz oscillator, and PLL clock. The application can select the clock source for the CPU clock.

3.2.2 RTC Clock

The RTC slow clock is used for RTC counter, watchdog, and low-power controller. Sources include: external low-speed (32 kHz) crystal, internal RC oscillator (~150 kHz), and internal 78.125 kHz clock. The RTC fast clock, used for RTC peripherals and sensor controllers, has two sources: external main crystal clock divided by 2, and internal 20 MHz oscillator.

3.3 Analog Peripherals

3.3.1 Analog-to-Digital Converter (ADC)

The ESP32-C3 integrates two 12-bit SAR ADCs supporting measurements on 6 channels. ADC characteristics are detailed in Table 14.

3.3.2 Temperature Sensor

A temperature sensor generates a voltage proportional to temperature, converted to a digital value by an ADC. It operates in the range of -40 °C to 125 °C and primarily senses internal chip temperature changes, which may be higher than ambient temperature.

3.4 Digital Peripherals

3.4.1 General Purpose Input / Output Interface (GPIO)

The ESP32-C3 has 22 GPIO pins, configurable for digital or analog functions (like ADC). GPIOs support selectable internal pull-up/pull-down resistors or high impedance. They can trigger CPU interrupts and are bi-directional with tristate control. Pins can be multiplexed with other functions (UART, SPI, etc.) and can be set to a holding state for low-power operations.

3.4.2 Serial Peripheral Interface (SPI)

The ESP32-C3 family features three SPI interfaces (SPI0, SPI1, and SPI2). SPI0 and SPI1 are for SPI memory mode, while SPI2 supports both SPI memory and general-purpose SPI modes (master/slave). SPI memory mode supports up to 120 MHz clock frequency in STR mode. General-purpose SPI2 supports two-line full-duplex and single-/two-/four-line half-duplex communication, with configurable clock polarity and phase. It can connect to GDMA.

3.4.3 Universal Asynchronous Receiver Transmitter (UART)

Two UART interfaces (UART0, UART1) support IrDA and asynchronous communication (RS232, RS485) up to 5 Mbps. They provide hardware flow control (CTS/RTS) and software flow control (XON/XOFF), connecting to GDMA via UHCI0.

3.4.4 I2C Interface

The I2C interface supports master or slave mode, with standard mode (100 Kbit/s), fast mode (400 Kbit/s), and up to 800 Kbit/s. It supports 7-bit and 10-bit addressing, double addressing, and 7-bit broadcast address.

3.4.5 I2S Interface

A standard I2S interface operates as master or slave in full-duplex or half-duplex mode, configurable for 8/16/24/32-bit serial communication. BCK clock frequency ranges from 10 kHz to 40 MHz. It supports TDM PCM, TDM MSB alignment, TDM standard, and PDM TX, connecting to GDMA.

3.4.6 Remote Control Peripheral

The RMT supports two channels for infrared remote transmission and two for reception, using pulse waveform control. It shares a 192 × 32-bit memory block for waveform storage.

3.4.7 LED PWM Controller

The LED PWM controller generates independent digital waveforms on six channels with configurable periods and duty cycles (up to 18 bits). It uses multiple clock sources and can operate in Light-sleep mode, supporting gradual duty cycle changes for effects like RGB color gradients.

3.4.8 General DMA Controller

A general DMA controller (GDMA) has six independent channels (3 transmit, 3 receive), shared by peripherals with DMA features. It implements a fixed-priority scheme and uses linked lists for high-speed peripheral-to-memory and memory-to-memory data transfers. Peripherals with DMA include SPI2, UHCI0, I2S, AES, SHA, and ADC.

3.4.9 USB Serial/JTAG Controller

The integrated USB Serial/JTAG controller is USB 2.0 full speed compliant (12 Mbit/s), offering CDC-ACM virtual serial port, JTAG adapter functionality, flash programming, and CPU debugging. It includes a full-speed USB PHY.

3.4.10 TWAI® Controller

The TWAI® controller is compatible with ISO 11898-1, supporting standard (11-bit ID) and extended (29-bit ID) frames. Bit rates range from 1 Kbit/s to 1 Mbit/s. It operates in Normal, Listen Only, and Self-Test modes, features a 64-byte receive FIFO, acceptance filters, and error detection/handling.

3.5 Radio and Wi-Fi

The ESP32-C3 radio consists of a 2.4 GHz receiver, 2.4 GHz transmitter, bias and regulators, balun, transmit-receive switch, and clock generator.

3.5.1 2.4 GHz Receiver

The receiver demodulates 2.4 GHz RF signals to quadrature baseband signals using high-resolution ADCs. It integrates RF filters, Automatic Gain Control (AGC), DC offset cancelation, and baseband filters.

3.5.2 2.4 GHz Transmitter

The transmitter modulates baseband signals to 2.4 GHz RF, driving an antenna with a high-powered CMOS amplifier. Digital calibration improves linearity and cancels imperfections like carrier leakage, I/Q amplitude/phase mismatch, baseband/RF nonlinearities, and antenna matching.

3.5.3 Clock Generator

The clock generator produces quadrature clock signals for the receiver and transmitter. It integrates inductors, varactors, filters, regulators, and dividers. Built-in calibration and self-test circuits optimize quadrature clock phases and phase noise.

3.5.4 Wi-Fi Radio and Baseband

Supports 802.11b/g/n, 20/40 MHz bandwidth, MCS0-7, MCS32, 0.4 µs guard interval, data rates up to 150 Mbps, RX STBC, adjustable transmit power, and antenna diversity via an external RF switch controlled by GPIOs.

3.5.5 Wi-Fi MAC

Implements the 802.11 b/g/n MAC protocol, supporting BSS STA and SoftAP operations. Features include 4 virtual Wi-Fi interfaces, infrastructure BSS modes, RTS/CTS protection, Block ACK, fragmentation, TX/RX A-MPDU/A-MSDU, TXOP, WMM, various security protocols (GCMP, CCMP, WPA2/3), hardware TSF, and 802.11mc FTM.

3.5.6 Networking Features

Espressif provides libraries for TCP/IP networking, ESP-WIFI-MESH, and other Wi-Fi protocols. TLS 1.0, 1.1, and 1.2 are supported.

3.6 Bluetooth LE

The Bluetooth Low Energy subsystem integrates a hardware link layer controller, RF/modem block, and software protocol stack, supporting Bluetooth 5 and mesh features.

3.6.1 Bluetooth LE Radio and PHY

Supports 1 Mbps PHY, 2 Mbps PHY for high throughput, and coded PHY (125/500 Kbps) for sensitivity and range. Includes Listen Before Talk (LBT) and antenna diversity.

3.6.2 Bluetooth LE Link Layer Controller

Supports LE advertising extensions, multiple advertisement sets, simultaneous advertising/scanning, multiple connections, adaptive frequency hopping, LE channel selection algorithm #2, connection parameter update, high duty cycle non-connectable advertising, LE privacy 1.2, LE data packet length extension, link layer extended scanner filter policies, low duty cycle directed advertising, link layer encryption, and LE Ping.

3.7 Low Power Management

The ESP32-C3 family supports multiple power modes:

• Active mode: CPU and radio are powered on for receive, transmit, or listen operations.
• Modem-sleep mode: CPU is operational at reduced speed; Wi-Fi/Bluetooth baseband and radio are disabled, but connections can remain active.
• Light-sleep mode: CPU is paused; wake-up events (MAC, host, RTC, external interrupts) reactivate the chip. Wi-Fi/Bluetooth connections can remain active.
• Deep-sleep mode: CPU and most peripherals are powered down; only RTC memory is powered. Wi-Fi connection data is stored in RTC memory.
• Hibernation mode: Internal 20 MHz oscillator is disabled; only an RTC timer on the slow clock is active. RTC timer or RTC GPIOs can wake the chip.

For power consumption details in different modes, refer to Table 16.

3.8 Timers

3.8.1 General Purpose Timers

Two 54-bit general-purpose timers are embedded, based on 16-bit prescalers and 54-bit auto-reload up/down timers. Features include a 16-bit clock prescaler (1 to 65536), a 54-bit time-base counter (programmable increment/decrement), real-time value reading, halting/resuming, programmable alarm generation, and level interrupt generation.

3.8.2 System Timer

A 52-bit system timer integrates two 52-bit counters and three comparators. It operates with a fixed 16 MHz clock and supports three types of interrupts. Alarm modes include target and period modes, with 52-bit target alarm and 26-bit periodic alarm values. Counters auto-reload and can stall if the CPU stalls or is in OCD mode.

3.8.3 Watchdog Timers

Three watchdog timers exist: two Main System Watchdog Timers (MWDT) in timer groups and one RTC Watchdog Timer (RWDT). They are enabled during flash boot to detect and recover from errors. Watchdog timers have four stages, each configurable for timeout, enabled/disabled status, and interrupt/reset actions. They feature a 32-bit expiry counter, write protection, and flash boot protection.

3.9 Cryptographic Hardware Accelerators

The ESP32-C3 is equipped with hardware accelerators for AES-128/256, SHA1/224/256, RSA3072, and ECC. It supports Big Integer Multiplication and Big Integer Modular Multiplication (up to 3072 bits).

3.10 Physical Security Features

• Transparent external flash encryption (AES-XTS) with software-inaccessible keys prevents unauthorized readout.
• Secure boot uses a hardware root of trust for signed firmware verification (RSA-PSS signature).
• HMAC module generates MAC signatures using software-inaccessible keys.
• Digital Signature module generates RSA signatures using software-inaccessible secure keys.
• World Controller provides two secure and general environments for software, establishing a security boundary.

4 Electrical Characteristics

4.1 Absolute Maximum Ratings

Stresses beyond these ratings may cause permanent damage. These are stress ratings only.

4.2 Recommended Operating Conditions

¹ For more information, refer to Section 2.3 Power Scheme. ² When VDD_SPI drives peripherals, VDD3P3_CPU must comply with peripheral specifications. ³ If using a single power supply, recommended output current is 500 mA or more.

4.3 VDD_SPI Output Characteristics

In 3.3 V output mode, VDD3P3_CPU may be affected by RSPI. Specification: VDD3P3_CPU > VDD_flash_min + I_flash_max*RSPI. For more information, refer to Section 2.3 Power Scheme.

4.4 DC Characteristics (3.3 V, 25 °C)

¹ VDD is the I/O voltage for a particular power domain. ² VOH and VOL are measured using high-impedance load.

4.5 ADC Characteristics

¹ To get better DNL results, sample multiple times and apply a filter, or calculate the average value.

4.6 Current Consumption

Current consumption is measured with a 3.3 V supply at 25 °C ambient temperature at the RF port. All transmitters' measurements are based on a 100% duty cycle.

¹ Current consumption in Modem-sleep mode assumes CPU is powered on and cache is idle. ² When Wi-Fi is enabled, the chip switches between Active and Modem-sleep modes. ³ In Modem-sleep mode, CPU frequency changes based on load and peripherals used.

4.7 Reliability

¹ JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. ² JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

4.8 Wi-Fi Radio

4.8.1 Wi-Fi RF Transmitter (TX) Specifications

¹ SL stands for standard limit value.

4.8.2 Wi-Fi RF Receiver (RX) Specifications

4.9 Bluetooth LE Radio

4.9.1 Bluetooth LE RF Transmitter (TX) Specifications

4.9.2 Bluetooth LE RF Receiver (RX) Specifications

¹ Refer to the value of Adjacent channel to image frequency when F = Fimage – 1 MHz.

¹ Refer to the value of Image frequency. ² Refer to the value of Adjacent channel selectivity C/I when F = F0 + 2 MHz.

¹ Refer to the value of Adjacent channel to image frequency when F = Fimage – 1 MHz.

5 Package Information

For information about tape, reel, and product marking, please refer to Espressif Chip-Packing Information.

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