Richtek RTQ2820AGQWF Evaluation Board
20A, 17V, ACOT® High-Efficiency Synchronous Step-Down Converter Evaluation Board
General Description
This user guide contains information for the RTQ2820AGQWF DC-DC converter. It includes performance specifications, the schematic, and the list of materials for the RTQ2820AGQWF.
Performance Specification Summary
A summary of the RTQ2820AGQWF Evaluation Board performance specification is provided in Table 1. The ambient temperature is 25°C.
| Specification | Test Conditions | Min | Typ | Max | Unit |
|---|---|---|---|---|---|
| Input Voltage Range | 3.5 | 12 | 17 | V | |
| Output Current | 0 | -- | 20 | A | |
| Default Output Voltage | -- | 1.2 | -- | V | |
| Operation Frequency | -- | 800 | -- | kHz | |
| Output Ripple Voltage | IOUT = 20A | -- | 10 | -- | mVp-p |
| Line Regulation | IOUT = 10A, VIN = 3.5V to 17V | -- | ±0.5 | -- | % |
| Load Regulation | VIN = 12V, IOUT = 0.001A to 20A | -- | ±0.5 | -- | % |
| Load Transient Response | IOUT = 10mA to 20A | -- | ±5 | -- | % |
| Maximum Efficiency | VIN = 12V, VOUT = 1.2V, IOUT = 20A | -- | 85.8 | -- | % |
Power-up Procedure
Suggested Required Equipments
- RTQ2820AGQWF Evaluation Board
- DC power supply capable of at least 17V and 7A
- Electronic load capable of 20A
- Function Generator
- Oscilloscope
Quick Start Procedures
The Evaluation Board is fully assembled and tested. Follow the steps below to verify board operation. Do not turn on supplies until all connections are made. When measuring the output voltage ripple, care must be taken to avoid a long ground lead on the oscilloscope probe. Measure the output voltage ripple by touching the probe tip and ground ring directly across the last output capacitor.
Proper measurement equipment setup and follow the procedure below.
- With power off, connect the input power supply to the VIN and GND pins.
- With power off, connect the electronic load between the VOUT and nearest GND pins.
- Turn on the power supply at the input. Make sure that the input voltage does not exceed 17V on the Evaluation Board.
- Check for the proper output voltage using a voltmeter.
- Once the proper output voltage is established, adjust the load within the operating ranges and observe the output voltage regulation, ripple voltage, efficiency, and other performance.
Detailed Description of Hardware
Headers Description and Placement
The evaluation board features various headers and test points for configuration and measurement. Key connectors include J1 for VIN input, J2 for input PGND, J3 for VOUT output, and J4 for output PGND. Sensing pins JP1 (VIN SNS) and JP2 (VOUT SNS) are provided for accurate measurements. JP3 is for VOUT waveform measurement. JP4 connects EN to VIN to enable the device. JP5 connects PGOOD to VCC through a 100kΩ resistor. JP6 is for mode selection.
The board also includes test points such as EN, SS/TR, VCC, PGOOD, MODE, RLIM, and SW for monitoring and debugging.
A visual inspection of all components is recommended. Ensure all components are undamaged and correctly installed. If any component is missing or damaged, contact distributors or email evb_service@richtek.com.
The board is populated with components including the RTQ2820AGQWF main IC (U1), an inductor (L1), various ceramic capacitors (C1-C19), a solid capacitor (EC1), and resistors (R1-R14). The PCB itself is a four-layer design with 2 oz. Cu outer and inner layers.
Test Points
The EVB is provided with the test points and pin names listed in the table below:
| Test Point/ Pin Name | Function |
|---|---|
| J1 | VIN input voltage connector |
| J2 | PGND connection for input |
| J3 | VOUT output voltage connector |
| J4 | PGND connection for output |
| JP1 | VIN voltage sensing for efficiency test points |
| JP2 | VOUT voltage sensing for efficiency test points |
| JP3 | VOUT voltage measuring for waveform test points |
| JP4 | Connects EN to VIN to enable the device. |
| JP5 | Connects PGOOD to VCC through a 100kΩ. |
| JP6 | Mode selection |
| EN | EN test point |
| SS/TR | Can be used to monitor the reference voltage. |
| VCC | VCC test point |
| PGOOD | PGOOD output test point |
| MODE | Mode selection test point |
| RLIM | Can be used to monitor the voltage level of the valley current limit. |
| SW | Switch node test point |
Bill of Materials
The Bill of Materials lists the components used on the evaluation board for operation at VIN = 12V, VOUT = 1.2V, IOUT = 20A, fSW = 800kHz.
| Reference | Count | Part Number | Value | Description | Package | Manufacturer |
|---|---|---|---|---|---|---|
| U1 | 1 | RTQ2820AGQWF | -- | Step-Down Converter | WQFN-21TL 3x4 (FC) | RICHTEK |
| L1 | 1 | VLBU1007090T-R33L | 0.33µH | Inductor, Isat = 39A, 180Ω | -- | TDK |
| C1, C2, C3 | 3 | GRM31CR71E106KA12L | 10µF | Capacitor, Ceramic, 25V, X7R | 1206 | MURATA |
| C4, C5 | 2 | GRM155C81E105KE11D | 1µF | Capacitor, Ceramic, 25V, X6S | 0402 | MURATA |
| C6 | 1 | GRM188R60J105KA01D | 1µF | Capacitor, Ceramic, 6.3V, X5R | 0603 | MURATA |
| C7 | 1 | GRM188R71H471KA01D | 470pF | Capacitor, Ceramic, 50V, X7R | 0603 | MURATA |
| C8, C10, C18, C19 | 4 | GRM188R71H104KA93D | 0.1µF | Capacitor, Ceramic, 50V, X7R | 0603 | MURATA |
| C9 | 1 | GRM188R71H223KA01D | 22nF | Capacitor, Ceramic, 50V, X7R | 0603 | MURATA |
| C11, C12, C13, C14, C15, C16 | 6 | GRM31CR60J476ME19 | 47µF | Capacitor, Ceramic, 6.3V, X5R | 1206 | MURATA |
| EC1 | 1 | 250ARHA221M08A2 | 220µF | Capacitor, Solid, 25V, 105°C | -- | APAQ |
| R1, R2 | 2 | WR06X1002FTL | 10k | Resistor, Chip, 1/10W, 1% | 0603 | WALSIN |
| R3, R4, R7 | 3 | WR04X000 PTL | 0 | Resistor, Chip, 1/10W, 1% | 0402 | WALSIN |
| R5 | 1 | WR06X4991FTL | 4.99k | Resistor, Chip, 1/10W, 1% | 0603 | WALSIN |
| R6 | 1 | WR06X000 PTL | 0 | Resistor, Chip, 1/10W, 1% | 0603 | WALSIN |
| R8, R9, R10 | 3 | WR06X1003FTL | 100k | Resistor, Chip, 1/10W, 1% | 0603 | WALSIN |
| R11 | 1 | WR06X2433FTL | 243k | Resistor, Chip, 1/10W, 1% | 0603 | WALSIN |
| R12 | 1 | RTT031213FTP | 121k | Resistor, Chip, 1/10W, 1% | 0603 | RALEC |
| R13 | 1 | RTT033012FTP | 30.1k | Resistor, Chip, 1/10W, 1% | 0603 | RALEC |
| R14 | 1 | CR0603F60K4P05Z | 60.4k | Resistor, Chip, 1/10W, 1% | 0603 | EVER OHMS |
Typical Applications
EVB Schematic Diagram
The schematic diagram illustrates the connections and components of the RTQ2820AGQWF evaluation board. Key sections include power input (VIN, GND), output (VOUT, PGND), enable (EN), power good (PGOOD), mode selection, and feedback sensing (VIN_SNS, VOUT_SNS). The main IC, RTQ2820AGQWF, is shown with its associated passive components like inductors (L1), capacitors (C1-C19, EC1), and resistors (R1-R14). The diagram also details specific configurations for PGOOD & EN pins pull-up selection, test points, and mode selections (PSM/FCCM at various frequencies). The input and output capacitors significantly influence voltage ripple, and MLCC capacitors can degrade in capacitance under DC bias.
PGOOD & EN Pins Pull-Up Selection: This section shows how to configure pull-up resistors for the PGOOD and EN pins, typically connecting them to VCC or AGND.
Golden Pins & Test Pins: Identifies specific test points for monitoring signals like EN, SS/TR, PGOOD, MODE, RLIM, SW, and BST.
Mode Selections: This part of the schematic details how to set the operating mode (PSM or FCCM) and switching frequency (600kHz, 800kHz, 1000kHz) using jumpers or resistors connected to specific pins.
Notes:
- The capacitance values of the input and output capacitors will influence the input and output voltage ripple.
- MLCC capacitors have degrading capacitance at DC bias voltage, and especially smaller size MLCC capacitors will have much lower capacitance.
Measure Results
The following graphs present various performance measurements of the RTQ2820AGQWF evaluation board under different conditions.
Output Ripple Measurement
Condition: IOUT = 10mA, Mode = PSM
Description: This graph shows the output voltage (VOUT) ripple and the switch node voltage (VSW). The VOUT ripple is approximately 10mV/DIV, and VSW is 5V/DIV. The time base is 100µs/Div. This indicates low output ripple under light load in PSM mode.
Condition: IOUT = 20A, Mode = FCCM
Description: This graph shows the output voltage (VOUT) ripple and the switch node voltage (VSW) under full load in FCCM mode. The VOUT ripple is approximately 10mV/DIV, and VSW is 5V/DIV. The time base is 1µs/Div. This demonstrates tight output voltage control and low ripple even at maximum load in FCCM mode.
Load Transient Response
Condition: IOUT = 10mA to 20A, TR = TF = 10µs, Mode = PSM
Description: This graph illustrates the output voltage (VOUT) response to a load transient from 10mA to 20A. The VOUT deviation is approximately 20mV/DIV, and the load current (IOUT) is 10A/Div. The time base is 100µs/Div. This shows the board's ability to maintain stable output voltage during rapid load changes in PSM mode.
Condition: IOUT = 10mA to 20A, TR = TF = 10µs, Mode = FCCM
Description: This graph shows the output voltage (VOUT) response to a load transient from 10mA to 20A in FCCM mode. The VOUT deviation is approximately 20mV/DIV, and the load current (IOUT) is 10A/Div. The time base is 100µs/Div. This demonstrates excellent transient response and voltage regulation in FCCM mode.
Power On from EN
Condition: IOUT = 50mA, Mode = PSM
Description: This graph shows the power-on sequence when the EN pin is enabled. It displays the output voltage (VOUT) rising to its set point (500mV/Div), the PG (Power Good) signal (2V/Div), and the EN pin voltage (2V/Div). The switch node voltage (VSW) is also shown (10V/Div). The time base is 1ms/Div. This illustrates a controlled and smooth power-up.
Condition: IOUT = 20A, Mode = FCCM
Description: This graph shows the power-on sequence at a high load (20A) in FCCM mode. It displays VOUT (500mV/Div), PG (2V/Div), EN (2V/Div), and VSW (10V/Div). The time base is 1ms/Div. This demonstrates a stable power-up even under heavy load conditions.
Power Off from EN
Condition: IOUT = 50mA, Mode = PSM
Description: This graph shows the power-off sequence when the EN pin is disabled. It displays VOUT (500mV/Div), PG (2V/Div), EN (2V/Div), and VSW (10V/Div). The time base is 10ms/Div. This illustrates a controlled shutdown.
Condition: IOUT = 20A, Mode = FCCM
Description: This graph shows the power-off sequence at a high load (20A) in FCCM mode. It displays VOUT (500mV/Div), PG (2V/Div), EN (2V/Div), and VSW (10V/Div). The time base is 40µs/Div. This demonstrates a rapid and controlled shutdown.
Overcurrent Protection
Description: This graph shows the response to an overcurrent condition. It displays VOUT (500mV/Div), PG (5V/Div), and ISW (Switching Current, 10A/Div). The time base is 50µs/Div. The graph indicates that the output voltage drops and the current is limited when an overcurrent condition is detected.
Short-Circuit Protection and Recovery
Description: This graph illustrates the behavior during a short-circuit event and subsequent recovery. It shows VOUT (500mV/Div), VSW (5V/Div), and ISW (10A/Div). The time base is 20ms/Div. The graph indicates that the device enters a protection mode when a short is applied and recovers when the short is removed.
Overvoltage Protection
Description: This graph shows the response to an overvoltage condition, triggered by an applied external bias of 3V on VOUT. It displays VOUT (1V/Div), VPG (4V/Div), and ISW (10A/Div). The time base is 200µs/Div. This demonstrates the overvoltage protection mechanism.
Efficiency vs. Output Current
Condition: VIN = 12V, Mode = PSM
Description: This graph plots Efficiency (%) against Output Current (A). The efficiency reaches a peak of approximately 85-90% at around 1A to 10A output current and slightly decreases at very low and high currents. This is typical for DC-DC converters.
Output Voltage Characteristics
Output Voltage vs. Output Current
Condition: fsw = 800kHz
Description: This graph shows the output voltage (V) versus output current (A). The output voltage remains very stable, around 1.205V, across the entire output current range from 0A to 20A. This indicates excellent load regulation.
Output Voltage vs. Input Voltage
Condition: IOUT = 10A, Mode = FCCM, fsw = 800kHz
Description: This graph shows the output voltage (V) versus input voltage (V). The output voltage is consistently around 1.205V across the input voltage range from 3.5V to 17V. This demonstrates excellent line regulation.
Thermal Image
Condition: VIN = 12V, VOUT = 1.2V, IOUT = 20A
Description: The thermal image shows the temperature distribution on the evaluation board under full load conditions. It highlights hot spots, indicating areas of highest power dissipation. The image shows a concentrated heat signature around the main converter IC and the inductor.
Note: Care must be taken to avoid a long ground lead on the oscilloscope probe when measuring the input or output voltage ripple. Measure the output voltage ripple by touching the probe tip directly across the output capacitor.
Evaluation Board Layout
Figures 1 to 4 illustrate the RTQ2820AGQWF Evaluation Board layout. The board dimensions are 85mm x 80mm and it is constructed on a four-layer PCB. The outer layers and inner layers utilize 2 oz. Copper (Cu).
Figure 1. Top View (1st layer)
The top layer shows the placement of major components: VIN and VOUT connectors (J1, J3), GND and PGND connections (J2, J4), headers (JP1-JP6), the main IC (RTQ2820AGQWF), inductor (L1), capacitors (C1-C19, EC1), and resistors (R1-R14). It also displays silkscreen markings for pin names, component designators, and board information like the model number and manufacturing date (Jul. 16, 2024). The PCB also indicates RoHS compliance.
Figure 2. PCB Layout—Inner Side (2nd Layer)
The second layer of the PCB is primarily a ground plane, with some signal routing and vias connecting to other layers. It shows the internal copper traces and planes.
Figure 3. PCB Layout—Inner Side (3rd Layer)
The third layer of the PCB also functions as a ground or power plane, with internal copper traces and vias. It complements the other layers in providing connectivity and signal integrity.
Figure 4. Bottom View (4th Layer)
The bottom layer of the PCB contains additional copper traces and component placements, if any, and vias connecting to the top and inner layers. It completes the four-layer structure of the board.
More Information
For more information, please find the related datasheet or application notes from the Richtek website: http://www.richtek.com.
Important Notice for Richtek Evaluation Board
THIS DOCUMENT IS FOR REFERENCE ONLY. NOTHING CONTAINED IN THIS DOCUMENT SHALL BE CONSTRUED AS RICHTEK'S WARRANTY, EXPRESS OR IMPLIED, UNDER CONTRACT, TORT OR STATUTORY, WITH RESPECT TO THE PRESENTATION HEREIN. IN NO EVENT SHALL RICHTEK BE LIABLE TO BUYER OR USER FOR ANY AND ALL DAMAGES INCLUDING WITHOUT LIMITATION TO DIRECT, INDIRECT, SPECIAL, PUNITIVE OR CONSEQUENTIAL DAMAGES.
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